JP7208511B2 - PHASE MODULATION DEVICE AND PHASE MODULATION METHOD - Google Patents

Description

The present invention relates to a phase modulation device and a phase modulation method.

Conventionally, a phase modulation device using LCOS (Liquid Crystal On Silicon) has been proposed as disclosed in Patent Document 1, for example. Paragraph [0015] of Patent Document 1 and the like disclose controlling the voltage applied to each pixel of the LCOS element to phase-modulate the incident light.

JP 2014-56004 A

Devices that handle infrared light must sufficiently modulate long-wavelength light. Therefore, as a means to secure a high modulation factor, it is basically possible to use a liquid crystal material having a high refractive index anisotropy. For example, the applied voltage of is increased. The method of increasing the thickness of the liquid crystal layer has the disadvantage that the orientation of the liquid crystal tends to be disturbed.

On the other hand, in the technique disclosed in the above-mentioned Patent Document 1, since the voltage supplied to each pixel from the drive circuit is limited, the amount of modulation when modulating the phase cannot be increased. If the voltage output from the drive circuit is increased, it is necessary to increase the withstand voltage of the circuit elements, which causes a problem of increased power consumption.

SUMMARY OF THE INVENTION The present invention has been made in order to solve such conventional problems. An object of the present invention is to provide a phase modulation device and a phase modulation method capable of securing a sufficient phase modulation amount even for infrared light by increasing the voltage applied to the liquid crystal without increasing the voltage.

In order to achieve the above object, a phase modulation device according to the present invention is a phase modulation device for reflecting incident light at a desired angle, wherein a plurality of column data lines and a plurality of row scanning lines orthogonal to each other intersect each other. a plurality of pixel circuits and a plurality of reflective pixels provided at positions where the a control circuit for controlling driving of the pixel circuit, the control circuit comprising a counter circuit for counting up to a predetermined maximum value of digital gradation, and a gradation value corresponding to each pixel circuit and output from the counter circuit. A comparator circuit is provided for comparing the count values and outputting a switching control signal when they match, and a ramp-shaped reference voltage that changes up to a predetermined maximum voltage is applied to a wiring connected to the column data line via a switch circuit. is applied, and a control voltage is determined and held in each pixel circuit by turning off the switch at the timing of the switching control signal, the pixel circuit has a charge pump that amplifies the control voltage, and further the control When the drive voltage supplied to the liquid crystal is equal to or less than the maximum voltage, the circuit outputs the control voltage to the liquid crystal without amplifying it, and the drive voltage supplied to the liquid crystal exceeds the maximum voltage. and a charge pump control section for controlling the control voltage to be amplified by the charge pump and output to the liquid crystal.

A phase modulation method according to the present invention is a phase modulation method for reflecting incident light at a desired angle, wherein the gradation value corresponding to each pixel circuit and the count value in the counter circuit coincide with each other. determining a control voltage from a ramp-shaped reference voltage that varies up to a predetermined maximum voltage by switching control of; and outputting the control voltage to the liquid crystal when the drive voltage supplied to the liquid crystal provided for each of the pixel circuits is equal to or less than the maximum voltage. and a step of amplifying the control voltage by a charge pump and outputting it to the liquid crystal when the drive voltage supplied to the liquid crystal exceeds the maximum voltage.

According to the present invention, it is possible to set a large amount of phase modulation of reflected light without increasing the control voltage supplied from the column data line to the pixel circuit. As a result, it is possible to suppress the thickening of the liquid crystal layer for securing the phase modulation amount and the disturbance of the liquid crystal alignment due to the thickening of the liquid crystal layer.

FIG. 1 is a plan view showing the configuration of a phase modulation device according to an embodiment of the invention. FIG. 2 is a side sectional view showing the configuration of the phase modulation device according to the embodiment of the present invention. FIG. 3 is a circuit diagram of a phase modulation device according to an embodiment of the invention. FIG. 4 is a circuit diagram showing the configuration of each pixel circuit provided in the phase modulation device according to the embodiment of the invention. FIG. 5 is an explanatory diagram showing the direction of reflected light reflected by the pixel circuit, where sa1 indicates the case when the charge pump is off and sb1 indicates the case when the charge pump is on. FIG. 6(a) shows pixel circuits arranged in a matrix, and FIG. 6(b) is a graph showing drive voltages supplied from each pixel circuit to the liquid crystal. FIG. 7 is a graph showing the relationship between the gradation set to the liquid crystal, the ramp waveform voltage, and the drive voltage supplied to the liquid crystal. FIG. 8A is a graph showing the relationship between the gradation set to the liquid crystal, the control voltage supplied to the pixel circuit, and the drive voltage supplied to the liquid crystal. FIG. 8B is a graph showing the relationship between the gradation set to the liquid crystal, the control voltage supplied to the pixel circuit, and the drive voltage supplied to the liquid crystal. FIG. 9 is an explanatory diagram showing a first modification of the pixel circuit provided in the phase modulation circuit according to this embodiment. FIG. 10A shows an example of supplying a monotonically increasing ramp voltage to a pixel circuit according to a second modification of the phase modulation device according to the present embodiment. FIG. 10B shows an example of supplying a monotonically decreasing ramp voltage to a pixel circuit, according to a second modification of the phase modulation device according to the present embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a phase modulation device according to an embodiment of the present invention, and FIG. 2 is a side cross-sectional view. As shown in FIGS. 1 and 2, a phase modulation device 101 according to this embodiment has an LCOS panel structure including a reflective substrate 11, a liquid crystal layer 12, and a counter substrate 13. FIG. Then, the light incident from the counter substrate 13 side (the direction of the arrow Y1 in FIG. 2) is reflected and separated into a plurality of reflected lights having different phases. In the following, the surfaces of the reflecting substrate 11 and the opposing substrate 13 on which light is incident are referred to as "light incident surfaces".

A plurality of reflective pixels made of a metal (for example, aluminum) that reflects light is provided on the light incident surface of the reflective substrate 11, and each reflective pixel is provided with a pixel circuit. A plurality of pixel circuits 21 are arranged in the horizontal direction and the vertical direction, respectively, as will be described later with reference to FIG. Each pixel circuit 21 operates under the control of the control circuit 22 .

The opposing substrate 13 is arranged parallel to the light incident surface side of the reflecting substrate 11 at a constant interval, and is made of a transparent member (for example, a transparent glass material). That is, the counter substrate 13 has a function as a transparent substrate. Furthermore, the counter substrate 13 is provided with a transparent electrode. Therefore, the light incident from the light incident surface side of the opposing substrate 13 passes through the transparent member and the transparent electrode and enters the liquid crystal layer 12 .

The liquid crystal layer 12 is arranged in a space sandwiched between the reflective substrate 11 and the opposing substrate 13, and the periphery thereof is sealed with a sealing material 14. As shown in FIG. For the convenience of the following explanation, the liquid crystal layer 12 is considered as a liquid crystal 42 (see FIG. 4 described later) divided on each reflective pixel (that is, each pixel circuit 21). The liquid crystal 42 includes a pixel electrode having light reflectivity (q1 shown in FIG. 4 to be described later, i.e., reflective pixel) and a common electrode (q2 shown in FIG. 4 to be described later, i.e., transparent electrode ) and are filled and sealed. A voltage output from the pixel circuit 21 (hereinafter referred to as "driving voltage") is supplied to the pixel electrode q1, and a preset common electrode voltage is supplied to the common electrode q2.

Therefore, the potential difference between the driving voltage applied by each pixel circuit 21 and the common electrode voltage applied to the common electrode q2 changes the refractive index of the liquid crystal 42 on each reflective pixel with respect to the incident light to the individual liquid crystal. By changing every 42 or every predetermined number of groups, the incident light incident from the light incident surface side of the counter substrate 13 can be reflected in a desired direction.

By changing the refractive index of the liquid crystal 42 on a plurality of continuous reflective pixels stepwise from large to small (or from small to large), the speed of the incident light (advance or delay in phase) will change. Because of the difference, the incident light travels in a curved manner, and reflected light with a certain angle can be obtained.

Next, the configuration of each pixel circuit 21 and the control circuit 22 that controls each pixel circuit 21 will be described with reference to the block diagram shown in FIG. 3 and the circuit diagram shown in FIG. 3, the control circuit 22 includes a plurality of pixel circuits 21 (m columns, n rows) arranged in a matrix, a horizontal scanning circuit 23, a vertical scanning circuit 24, and a charge pump control section 25. ing. Then, the control circuit 22 outputs an electric signal to each pixel circuit 21 to drive each pixel circuit 21 , and a driving voltage is applied from each pixel circuit 21 . The refractive index for incident light of the liquid crystal 42 on each reflective pixel is controlled to a desired value.

A plurality of pixel circuits 21 (m ×n) are arranged. The plurality of pixel circuits 21 are all configured identically. Further, drive lines (L1 to Ln) and control lines (K1 to Kn) are provided in parallel with the row scanning lines (G1 to Gn). The drive lines (L1-Ln) and the control lines (K1-Kn) are connected to the charge pump controller 25. FIG.

As will be described later, the driving lines (L1 to Ln) are electric wires for transmitting control signals for switching ON/OFF of the transistor Q2 (short-circuit switch; see FIG. 4) provided in each pixel circuit 21. FIG. The control lines (K1 to Kn) are wirings for transmitting control signals for switching ON/OFF of the switches S1 to S4 (see FIG. 4) provided in each pixel circuit . As shown in FIG. 4, a plurality of control lines (K1-Kn) are provided (three lines K1-1, K1-2, and K1-3 in the figure), but only one line is shown in FIG. is simplified by a control line K1.
The column data lines (D1 to Dm) are wirings for supplying each pixel circuit 21 with a ramp-shaped voltage (ramp-shaped reference voltage) output from the voltage supply line X1.

FIG. 4 is a circuit diagram showing a detailed configuration of the pixel circuit 21. As shown in FIG. Here, the configuration of the pixel circuit 21 (referred to as pixel circuit 21a) arranged at the intersection of the column data line D1 and the row scanning line G1 shown in FIG. 3 will be described. As shown in FIG. 4, the pixel circuit 21a includes a capacitor Cd for storing the control voltage supplied from the column data line D1, and a series connection circuit of a source follower Q4 and a load transistor Q5. The pixel circuit 21a further comprises transistors Q1 and Q2, a charge pump 31 and an output capacitor C2.

Capacitor Cd accumulates the control voltage supplied from column data line D1 and outputs it to the gate of source follower Q4. The output of the source follower Q4 is connected to the input terminal p1 of the charge pump 31.

The transistor Q1 is a switching transistor, and is composed of, for example, an N-channel MOSFET (field effect transistor). One terminal (eg, drain) of the transistor Q1 is connected to the column data line D1, and the other terminal (eg, source) is connected to the input terminal p1 of the charge pump 31. FIG. A control terminal (for example, gate) of the transistor Q1 is connected to the row scanning line G1. Therefore, when the row scanning line G1 is selected and the control voltage is input from the column data line D1, this control voltage is supplied to the input terminal p1 of the charge pump 31. FIG.

Similar to the transistor Q1, the transistor Q2 is also a switching transistor, and is composed of, for example, an N-channel MOSFET (field effect transistor). One terminal (eg, drain) of the transistor Q2 is connected to the input terminal p1 of the charge pump 31, and the other terminal (eg, source) is connected to the output terminal p2 of the charge pump 31. FIG.

A control terminal (for example, a gate) is connected to the drive line L1. Therefore, when a voltage of "H" level is supplied to the drive line L1, the transistor Q2 is turned on and the input terminal p1 and the output terminal p2 of the charge pump 31 are short-circuited. That is, the function of the charge pump 31 can be stopped. On the contrary, when drive line L1 is supplied with a voltage of "L" level, transistor Q2 is turned off. Therefore, the input terminal p1 and the output terminal p2 of the charge pump 31 are opened, and the charge pump 31 can be operated.

That is, the transistor Q2 functions as a short-circuit switch for short-circuiting the input terminal p1 for supplying the control voltage to the charge pump 31 and the output terminal p2 for outputting the voltage (driving voltage) from the charge pump 31 to the liquid crystal 42. ing.

When the drive voltage for setting the liquid crystal 42 to a desired refractive index is equal to or lower than the maximum voltage VCL, which is the maximum voltage supplied from the column data line D1, the charge pump controller 25 (see FIG. 3 ), the transistor Q2 is short-circuited. Also, when the drive voltage exceeds the maximum voltage VCL, the transistor Q2 is opened to make the charge pump 31 drivable.

The charge pump 31 is provided with four switches S1 to S4 and a capacitor C1 (first capacitor) for accumulating charges. The control voltage supplied via Q4 is amplified and output to the output terminal p2.

In the charge pump 31, a switch S1 (first switch) and a switch S3 (third switch) are connected in series, the end on the switch S1 side is connected to the input terminal p1, and the end on the switch S3 side is connected to the output terminal p2. It is connected to the. Also, the switch S2 (second switch) and the switch S4 (fourth switch) are connected in series with each other, the end on the switch S2 side is connected to the input terminal p1, and the end on the switch S4 side is connected to the ground. .

Furthermore, a capacitor C1 (first capacitor) is provided between the connection point of the switches S1 and S3 and the connection point of the switches S2 and S4. The output terminal p2 is connected to the ground via the output capacitor C2 and further connected to the pixel electrode q1 of the liquid crystal 42. FIG. That is, one end of the capacitor C1 is connected to the switches S1 and S3, and the other end of the capacitor C1 is connected to the switches S2 and S4. Further, as described above, the common electrode q2 of the liquid crystal 42 is a transparent electrode provided on transparent glass. A common electrode voltage is applied to the transparent electrode.

The liquid crystal 42 is driven according to the potential difference between the drive voltage applied to the pixel electrode q1 from the pixel circuit 21 and the common electrode applied to the common electrode q2. Therefore, the incident light incident on the liquid crystal 42 is phase-modulated according to the potential difference and reflected.

[Description of Reflected Light by Reflective Substrate]
FIG. 5 is an explanatory diagram schematically showing the angles of incident light incident on the pixel circuit 21 and reflected light transmitted through the liquid crystal 42 corresponding to the pixel circuit 21 and reflected by the reflective pixel 20 . In FIG. 5, symbol st indicates incident light incident from a direction orthogonal to the reflective pixel 20 corresponding to each pixel circuit 21, symbol sa1 indicates reflected light reflected at the angle θa by the reflective pixel 20, and symbol sb1. indicates reflected light reflected at an angle θb. The same phase plane of the incident light st (a plane normal to the direction of the incident light st) is r1, the phase plane of the reflected light sa1 is ra1, and the same phase plane of the reflected light sb1 is rb1.

As shown in FIG. 5, incident light st is irradiated from a direction substantially perpendicular to the reflective pixel 20 and enters the liquid crystal 42 . Further, the refractive index of the liquid crystal 42 changes according to the drive voltage applied to the liquid crystal 42 by the pixel circuit 21 . For example, when the maximum drive voltage in the conventional art is the voltage Va, the reflection angle of the reflected light sa1 obtained when the voltage is changed stepwise from the minimum voltage Vmin to the voltage Va in the continuous pixel circuits 21 is θa On the other hand, when the charge pump 31 is driven, the maximum driving voltage becomes Vb (Vb>Va), and reflected light sb1 reflected at a larger reflection angle θb is obtained.

At this time, although Vmin is applied, the liquid crystal on the pixel has a large refractive index nmax, and the liquid crystal on the pixel to which the maximum voltage Va is applied changes to a small refractive index na. Since the light incident on the liquid crystal with the refractive index na travels faster than the light incident on the liquid crystal with the refractive index nmax, the reflected light is emitted at an angle θa. On the other hand, since the liquid crystal on the pixel to which the voltage Vb is applied has a refractive index nb smaller than na, the incident light travels even faster. Therefore, the reflected light is emitted at a larger angle θb.

Returning to FIG. 3, the horizontal scanning circuit 23 provided in the control circuit 22 includes a shift register circuit 26, a comparator circuit 28, a counter circuit 29, and a switch circuit 27 including switches SW1 to SWm.

The shift register circuit 26 inputs a horizontal synchronization signal (HST) and horizontal scanning clock signals (HCK1, HCK2). The shift register circuit 26 sequentially shifts the clock signal based on the horizontal synchronizing signal and the clock signal for horizontal scanning, thereby generating, for example, a q-bit digital signal to be output to the comparator circuit 28 at a cycle of one horizontal scanning period. do.

The shift register circuit 26 inputs q-bit digital signals 2 to q (where 2 to q represent 2 to the qth power), and further digital signals corresponding to the respective pixel circuits 21 . is latched and output to the comparator circuit 28 . For example, when the liquid crystal 42 is controlled by supplying drive voltages corresponding to five levels of gradation from 1 to 5, (1/5)*2 to q, (2/5)* Digital signals of 2 to q, (3/5)*2 to q, (4/5)*2 to q, and 2 to q are latched and output to the comparator circuit 28 .
That is, the shift register circuit 26 has a function of outputting digital signals of a plurality of preset stages among digital signals that change corresponding to voltages within a range up to a predetermined maximum voltage (VLC).

The counter circuit 29 counts the above q-bit digital signal within one horizontal scanning period and outputs a count value. That is, the counter circuit 29 has a function of counting up to the maximum value of a predetermined digital gradation and outputting the count value.

The switch circuit 27 includes m switches SW1 to SWm for switching ON/OFF of each column data line (D1 to Dm). Each of the switches SW1 to SWm is controlled to be on or off based on a switching control signal output from the comparator circuit . When each switch SW1 to SWm is turned on, the voltage value of the ramp waveform voltage at that timing is supplied to each column data line (D1 to Dm) as a control voltage (details will be described later).

The comparator circuit 28 has a comparison circuit (not shown) for each column data line (D1 to Dm), and controls supply of a control voltage to each column data line (D1 to Dm). That is, each of the switches SW1 to SWm provided in the switch circuit 27 is provided with a comparison circuit that generates a switching control signal for switching the on state and off state of each of the switches SW1 to SWm. A digital signal corresponding to one of the gradations (gradation 1 to 5) supplied from the shift register circuit 26 and the count value output from the counter circuit 29 are input to each comparison circuit. be done. Then, when both inputs match, a switching control signal is output.
That is, the comparator circuit 28 has a function of comparing the gradation value corresponding to each pixel circuit 21 and the count value output from the counter circuit 29 and outputting a switching control signal when they match.

Therefore, when controlling the liquid crystal 42 to five levels of gradation from gradation 1 to 5, for example, five comparator circuits or five grouped comparator circuits each have (1/5 )*2~q, (2/5)*2~q, (3/5)*2~q, (4/5)*2~q, and 2~q, respectively, are supplied, the counter circuit When the count value output from 29 matches the above digital signal, each comparison circuit outputs a switching control signal.

That is, the comparator circuit 28 acquires a ramp waveform voltage corresponding to the change in the count value of the counter circuit 29, and the digital signal output from the shift register circuit 26 matches the count value output from the counter circuit 29. It has a function of supplying a ramp waveform voltage to the column data line as a control voltage.

[Description of Ramp Waveform and Driving Voltage to be Supplied to Liquid Crystal 42]
The ramp waveform voltage will be described below with reference to FIG. FIG. 7(a) shows gradations (gradation 1 to 5) corresponding to digital signals of 0 to 2 to q, and FIG. 4 shows a ramp waveform voltage output in a scanning cycle; (c) shows the drive voltage output to the liquid crystal 42 corresponding to each gradation.

The ramp waveform voltage is an analog voltage having two ramp waveforms in the period (one horizontal scanning period) in which the shift register circuit 26 outputs the q-bit digital signal. Specifically, as shown in FIGS. 7A and 7B, the minimum The voltage monotonically increases from the voltage “0” to the maximum voltage “VLC”, and then monotonically increases from the intermediate voltage “VLC/2” to the maximum voltage “VLC” in the period from time t1 to t2, which is the half period (second half). is a voltage that varies as

In this embodiment, a double voltage (2*VLC), which is twice the maximum voltage VLC of the ramp waveform voltage, is set. A voltage of k gradations (where k is an integer of 3 or more) is set (k=5 in the case of FIG. 7). By switching between driving and stopping the charge pump 31, the ramp waveform voltage (voltage in the range of 0 to VLC) supplied from the column data line is changed to the voltage of k gradation (voltage in the range of 0 to 2*VLC). voltage).

For example, when supplying the voltage of gradation 1 to the liquid crystal 42 shown in FIG. 4, voltage (2/5)*VLC is output. When supplying the voltage of gradation 2, the voltage (4/5)*VLC is output.

Furthermore, when supplying a voltage of gradation 3, it is necessary to output voltage (6/5)*VLC. However, since it exceeds the maximum voltage "VLC", the half voltage (3/5)*VLC is input as the control voltage, amplified twice by the charge pump 31 and supplied to the liquid crystal 42 . For the voltage "8/5*VLC" and the voltage "2*VLC" which are the gradation 4, half the voltage (4/5)*VLC and VLC are similarly inputted as control voltages and doubled by the charge pump 31. , and supplied to the liquid crystal 42 . Therefore, the slope of the graph between times t1 and t2 in FIG. 7B is half the slope of the graph between times t0 and t1.

As a result, driving voltages corresponding to gradations 1 to 5 can be generated and supplied to the liquid crystal 42, as shown in FIG. 7(c).
That is, when the driving voltage supplied to the liquid crystal 42 to obtain the desired gradation is equal to or lower than the maximum voltage VLC, which is the maximum value of the ramp waveform voltage (in the case of gradations 1 and 2 in the above example), As shown in the graph between times t0 and t1 in FIG. 7B, this control voltage is output to the liquid crystal 42 as a drive voltage without being amplified. On the other hand, when the drive voltage is higher than the maximum voltage VLC (in the above example, for gradations 3, 4, and 5), as shown in the graph between times t1 and t2 in FIG. A control voltage that is half the voltage is amplified by a factor of two to produce the desired drive voltage.

That is, the charge pump control unit 25 selects an arbitrary gradation among a plurality of gradations preset in a range up to a voltage higher than the maximum voltage (VLC) (for example, a voltage twice as high as the maximum voltage VLC). If the corresponding voltage is less than the maximum voltage (VLC), the control voltage is output to the liquid crystal without being amplified. On the other hand, when the voltage corresponding to an arbitrary grayscale out of a plurality of grayscales exceeds the maximum voltage (VLC), the charge pump 31 controls to amplify the control voltage and output it to the liquid crystal 42 .

In this way, by controlling the on/off of each of the switches SW1 to SWm provided in the switch circuit 27 and controlling the driving of the charge pump 31, the pixel circuit 21 has k gradations (5 gradations in the above example). It is possible to generate a drive signal corresponding to the gradation) and supply it to the liquid crystal 42 . That is, as shown in the graph of FIG. 7C, driving voltages of gradations 1 to 5 obtained by dividing the voltage (2*VLC) twice the maximum voltage VCL into 5 equal parts are applied to the liquid crystal 42. can be output.

Returning to FIG. 3, the vertical scanning circuit 24 is connected to row scanning lines (G1 to Gn). The vertical scanning circuit 24 inputs a vertical synchronization signal (VST) and vertical scanning clock signals (VCK1, VCK2). The vertical scanning circuit 24 sequentially supplies row selection signals (scanning signals), for example, from the row scanning line G1 to the row scanning line Gn at a cycle of one horizontal scanning period based on the vertical synchronization signal and the clock signal for vertical scanning. .

The charge pump control unit 25 outputs a drive signal to each drive line (L1 to Ln) shown in FIG. Specifically, among a plurality of gradations set in advance in a range up to a voltage higher than the maximum voltage (VLC) (for example, a voltage twice the maximum voltage), the voltage corresponding to an arbitrary gradation is the maximum voltage. (VLC) In the following cases, an "H" level signal is output to the drive line. As a result, transistor Q2 is turned on.

Further, when the voltage corresponding to an arbitrary grayscale out of a plurality of grayscales exceeds the maximum voltage (VLC), an "L" level signal is output to the drive line. As a result, the transistor Q2 shown in FIG. 4 is turned off.

Further, the charge pump control unit 25 does not drive the charge pump 31 when a signal of "H" level is supplied to the drive line, and does not drive the charge pump 31 when a signal of "L" level is supplied to the drive line. 31 is driven.

[Description of Charge Pump 31]
Next, operation of the charge pump 31 will be described. When the charge pump control unit 25 drives the charge pump 31, the control signal for controlling the ON/OFF of each of the switches S1 to S4 shown in FIG. output to Specifically, when the charge pump 31 is driven, the switches S1 and S4 are first turned on and the switches S2 and S3 are turned off when the control voltage is input from the column data line D1.

Therefore, the control voltage is stored on capacitor C1. After a predetermined time has elapsed, the switches S1 and S4 are turned off and the switches S2 and S3 are turned on. As a result, the control voltage supplied from the column data line D1 and the voltage accumulated in the capacitor C1 are added, and the added voltage is accumulated in the output capacitor C2. Therefore, a voltage that is twice the control voltage supplied from the column data line D1 is accumulated in the output capacitor C2 and output to the pixel electrode q1.

Then, in the phase modulation device 101 according to the present embodiment, blocks made up of some of the (n×m) pixel circuits 21 shown in FIG. 3 are set. For example, as shown in FIG. 6A, a block composed of (5 rows×6 columns) pixel circuits 21 is set. In FIG. 6A, the suffix "-nm" is added to specify the row (n) and column (m) of each pixel circuit 21, respectively. Accordingly, the pixel circuit of row 1 and column 1 shown in FIG. 6A is 21-11, and the pixel circuit of row 5 and column 6 is 21-56.

In FIG. 6A, the same voltage is supplied to the six pixel circuits 21-11 to 21-16 in the same row. For example, the pixel circuits 21-11 to 21-16 are supplied with control voltages corresponding to gradation 1 among gradations 1 to 5. FIG. Also, the gradation is set so that the gradation gradually increases from top to bottom in the vertical direction, and a control voltage corresponding to gradation 5 is supplied to the pixel circuits 21-51 to 21-56 in the bottom row.

Specifically, as shown in FIG. 6B, in each pixel circuit 21-11 to 21-51 arranged in the vertical direction, the driving voltage supplied to each liquid crystal 42 corresponds to the gradation 1 to gradation 5. Set to change step by step. Accordingly, six pixel circuits 21 are grouped into one group, and the reflectance can be changed in five ways, and thus it is possible to obtain reflected light phase-modulated in five ways.

[Explanation of operation of the present embodiment]
Next, the operation of the phase modulation device 101 according to this embodiment configured as described above will be described. Here, as shown in FIG. 6A, an example of setting the refractive index of each liquid crystal by controlling the pixel circuits 21 of 5 rows and 6 columns will be described.

The comparator circuit 28 shown in FIG. 3 controls the on/off of each of the switches SW1 to SWm (here, m=6) provided in the switch circuit 27 to control the ramp waveform voltage supplied from the voltage supply line X1. A desired voltage is extracted from the , and supplied to a desired column data line as a control voltage.

Further, by driving the vertical scanning circuit 24, the scanning line corresponding to the desired pixel circuit 21 is selected from the row scanning lines (G1 to Gn) (here, n=5). As a result, the desired pixel circuit 21 can be supplied with the control voltage.

For example, the comparator circuit 28 sets the q-bit digital signal (0 to 2 to q) output from the shift register circuit 26 to five levels of gradation (gradation 1 to gradation 5). When the shift register circuit 26 outputs a digital signal corresponding to each of gradations 1 to 5, the switch circuit 27 outputs a desired value at the time when the count value output from the counter circuit 29 matches this digital signal. Outputs a switching control signal to the switch. Therefore, the ramp waveform voltage at this time can be supplied to the pixel circuit 21 as the control voltage.

For example, as shown in FIG. 7, when a digital signal corresponding to gradation 1 is output, the ramp waveform voltage is (2/5)*VLC, and a digital signal corresponding to gradation 2 is output. then the ramp waveform voltage is (4/5)*VLC. Further, when a digital signal corresponding to gradation 3 is output, the ramp waveform voltage is (3/5)*VLC, and when a digital signal corresponding to gradation 4 is output, the ramp waveform is The voltage is (4/5)*VLC, and when a digital signal corresponding to gradation 5 is output, the ramp waveform voltage is VLC. A voltage corresponding to each ramp waveform voltage is supplied to the pixel circuit 21 as a control voltage.

At this time, as described above, when the digital signal is less than half the numerical value of 2 to q (time t0 to t1 in FIG. 7), the control voltage is not amplified, and when it is more than half (time t1 to t2) case), the control voltage is amplified by the charge pump 31 and used as the drive voltage to be output to the liquid crystal 42 .

A control voltage supplied from the column data line is stored in the capacitor Cd via the transistor Q1 shown in FIG. 4, and further supplied to the input terminal p1 of the charge pump 31 via the source follower Q4.

The operation of the charge pump 31 will be described below with reference to the timing charts shown in FIGS. 8A and 8B. FIG. 8A is a timing chart showing, as an example, changes in each signal when a drive voltage of gradation 2 is output to the liquid crystal 42 . FIG. 8B is a timing chart showing changes in each signal when the driving voltage of gradation 4 is output.

As shown in FIG. 8A(a), q-bit digital signals 2 to q are output from the shift register circuit 26 (see FIG. 3). At this time, the q-bit digital signal is equally divided into five, and gradations 1 to 5 (indicated as "1" to "5" in the figure) are assigned to the respective digital signals.

When the count value output from the counter circuit 29 matches the digital signal, the comparator circuit 28 outputs a switching control signal to a desired switch among the plurality of switches SW1 to SWm provided in the switch circuit 27. The switch is turned on and a ramp waveform voltage is supplied to the column data line as a control voltage. Also, as described above, the ramp waveform voltage outputs two waveforms (two sawtooth waveforms) within one horizontal scanning period, as shown in FIG. 8A(b).

When setting the liquid crystal 42 to gradation 2, a ramp waveform voltage of (4/5)*VLC is supplied to the column data line as a control voltage at time ta when a digital signal corresponding to gradation 2 is output. will be This control voltage is accumulated in the capacitor Cd and held until time t12.

Further, as shown in FIG. 8A (d), the transistor Q2 is kept on even after time t12, and as shown in (e) and (f), the switches S1 to S4 are turned on even after time t12 All are kept off. Therefore, the charge pump 31 is not driven and the ramp waveform voltage supplied to the pixel circuit 21 is not amplified. Then, as shown in FIG. 8A(c), the row selection signal G in the vertical scanning circuit 24 is turned on at time t12. (4/5)*VLC is output. Therefore, the driving voltage (4/5)*VLC of the second gradation can be supplied to the liquid crystal 42 .
In the case of the gradation 1, the liquid crystal 42 can be supplied with the driving voltage (2/5)*VLC of the gradation 1 in the same manner as described above.

On the other hand, when setting the liquid crystal 42 to gradation 4, as shown in FIG. The waveform voltage will be applied to the column data line as the control voltage. This control voltage is accumulated in the capacitor Cd and held until time t22.

Further, as shown in FIG. 8A(d), the transistor Q2 is turned off at time t22. Furthermore, as shown in (e), during the period from time t22 to t23, the switches S1 and S4 are turned on and the voltage (4/5)*VLC is held in the capacitor C1. After that, at time t24 as shown in (f), the switches S2 and S3 are turned on, so that the voltage (4/5)*VLC is applied to the output capacitor C2 shown in FIG. 4 as shown in (g). A voltage doubled (8/5)*VLC will be obtained. Therefore, the voltage of gradation 4 can be supplied to the liquid crystal 42 .
In the case of gradations 3 and 5, the driving voltage (6/5)*VLC for gradation 3 and the driving voltage VLC for gradation 5 can be supplied to the liquid crystal 42 in the same manner as described above.

By controlling the driving voltage supplied from each pixel circuit 21 to the liquid crystal 42 as described above, each liquid crystal 42 can be set to a desired gradation. can be set to a desired refractive index.

[Description of effects of the present embodiment]
Thus, in the phase modulation device 101 according to this embodiment, each pixel circuit 21 is provided with the charge pump 31 . When the liquid crystal 42 is set to an arbitrary gradation among a plurality of preset gradations ranging from "0" to a voltage (2*VLC) that is twice the maximum voltage, the arbitrary When the voltage corresponding to the gradation of is equal to or lower than the maximum voltage (VLC), the control voltage (voltage obtained from the ramp waveform voltage) supplied from the column data line to the pixel circuit 21 is applied to the liquid crystal 42 without being amplified. Output.

Further, when the voltage corresponding to an arbitrary grayscale out of a plurality of grayscales exceeds the maximum voltage (VLC), the charge pump 31 amplifies the control voltage supplied to the pixel circuit 21 from the column data line. to output to the liquid crystal 42.

Therefore, when the maximum control voltage supplied to the pixel circuit 21 from the column data line is the maximum voltage (VLC), the voltage for driving the liquid crystal 42 is within the range of the voltage (2*VLC) which is twice the maximum voltage (VLC). It becomes possible to set the drive voltage. Therefore, the magnitude of the refractive index of the liquid crystal 42 can be changed in a wider range, an increase in the thickness of the liquid crystal layer 12 can be suppressed, and the precision of phase modulation can be improved.

Furthermore, since the gradation can be set in a wide range of voltage without increasing the control voltage VLC supplied to the pixel circuit 21, there is no need to increase the withstand voltage of each component constituting the control circuit 22, and the size and weight of the device can be reduced. It becomes possible to plan

Further, since the voltage, which is the voltage range for setting the driving voltage of the liquid crystal 42, is set to a voltage twice as high as the predetermined maximum voltage (VLC), it is possible to simply amplify the control voltage by a factor of two. A desired drive voltage can be obtained by processing, and the circuit configuration can be simplified.

In this embodiment, an example in which the voltage range for setting the driving voltage of the liquid crystal 42 is set to twice the predetermined maximum voltage (VLC) has been described, but the present invention is not limited to this. Instead, the drive voltage should be set higher than the maximum voltage VLC.

[Description of the first modification]
Next, a modified example of this embodiment will be described. FIG. 9 is a circuit diagram showing the configuration of a pixel circuit 21' according to the first modified example. As shown in FIG. 9, in the pixel circuit 21' according to the modification, the drive lines L1 are arranged in the vertical direction. Therefore, the same voltage can be output to the liquid crystal 42 in the vertical direction of each pixel circuit 21' arranged in a matrix. Therefore, the direction in which the refractive index changes is the vertical direction.

That is, in the examples shown in FIGS. 6A and 6B, the refractive index of the liquid crystal 42 changes in the vertical direction, whereas in the modified example shown in FIG. , the refractive index of the liquid crystal 42 is set to change.

[Description of Second Modification]
Next, the 2nd modification of this embodiment is demonstrated. 10A and 10B are explanatory diagrams showing temporal changes in the ramp waveform voltage according to the second modification of the present embodiment. In the second modification, two pixel circuits are connected to the intersections of the column data lines D1 to Dm and the row scanning lines G1 to Gn shown in FIG. These pixel circuits are referred to as 21A and 21B.

Then, one pixel circuit 21A is of positive polarity and the other pixel circuit 21B is of negative polarity, and ramp waveform voltages in which the directions of voltage change are opposite to each other are applied to the pixel circuits 21A and 21B.
That is, as shown in FIG. 10A(a), a monotonically increasing ramp waveform voltage is applied to the pixel circuit 21A, and as shown in FIG. 10B(a), a monotonically decreasing ramp waveform voltage is applied to the pixel circuit 21B. Then, at the gradation i, a control voltage VpixH (see FIG. 10A) and a control voltage VpixL (see FIG. 10B) can be obtained. Therefore, as shown in FIG. 10A(b), voltages CceL to VpixH with respect to the counter electrode voltage CceL, and as shown in FIG. 10B(b), with respect to the counter electrode voltage CceH, VpixL ˜CceH can be output to the liquid crystal 42, and the gradation of the liquid crystal 42 can be changed in a time shorter than one horizontal scanning period. Therefore, it is possible to further improve the accuracy of phase modulation.

Although embodiments of the present invention have been described above, the statements and drawings forming part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art from this disclosure.

Reference Signs List 11 reflective substrate 12 liquid crystal layer 13 counter substrate 14 sealing material 21, 21′, 21-11 to 21-56 pixel circuits 21a, 21A, 21B pixel circuit 22 control circuit 23 horizontal scanning circuit 24 vertical scanning circuit 25 charge pump controller 26 Shift register circuit 27 Switch circuit 28 Comparator circuit 29 Counter circuit 31 Charge pump 42 Liquid crystal 101 Phase modulator Q4 Source follower Q5 Load transistor C1 Capacitor (first capacitor)
C2 Output capacitor Cd Capacitor X1 Voltage supply line

Claims (6)

A phase modulation device that reflects incident light at a desired angle,
a plurality of pixel circuits provided at positions where a plurality of column data lines and a plurality of row scanning lines that are orthogonal to each other intersect, and a plurality of reflective pixels;
a liquid crystal provided corresponding to the reflective pixel and having a refractive index with respect to incident light that changes according to a driving voltage supplied from the pixel circuit;
a control circuit that controls driving of the pixel circuit;
The control circuit is
A counter circuit that counts up to the maximum value of a predetermined digital gradation, and a comparator circuit that compares the gradation value corresponding to each pixel circuit with the count value output from the counter circuit and outputs a switching control signal when they match. a ramp-shaped reference voltage that changes up to a predetermined maximum voltage and then changes from an intermediate voltage to the maximum voltage is applied to a wiring connected to the column data line via a switch circuit; The switch is turned off at the timing of the switching control signal to determine the control voltage and hold it in each pixel circuit.
The pixel circuit has a charge pump that amplifies the control voltage,
Furthermore, the control circuit
When the drive voltage supplied to the liquid crystal is equal to or less than the maximum voltage, the control voltage is output to the liquid crystal without being amplified, and when the drive voltage supplied to the liquid crystal exceeds the maximum voltage, a charge pump control unit for controlling the control voltage to be amplified by the charge pump and output to the liquid crystal;
A phase modulation device comprising: setting the refractive index of the liquid crystal to change in one of the directions orthogonal to each other, and arranging a driving line for switching on and off of the charge pump in the other direction; The phase modulation device according to claim 1, characterized by: the pixel circuit includes a short-circuit switch that short-circuits an input terminal for supplying the control voltage to the charge pump and an output terminal for outputting a voltage from the charge pump to the liquid crystal;
The charge pump controller short-circuits the short-circuit switch when the drive voltage supplied to the liquid crystal is equal to or less than the maximum voltage, and closes the short-circuit switch when the drive voltage supplied to the liquid crystal exceeds the maximum voltage. 3. The phase modulation device according to claim 1, wherein the phase modulation device is open. The pixel circuit includes an output capacitor that stores a voltage supplied to the liquid crystal,
The charge pump is
a first capacitor that stores electric charge;
a first switch provided between one end of the first capacitor and an input terminal to which the control voltage is supplied;
a second switch provided between the other end of the first capacitor and the input terminal;
a third switch provided between the one end of the first capacitor and one end of the output capacitor;
a fourth switch provided between the other end of the first capacitor and the other end of the output capacitor;
The phase modulation device according to any one of claims 1 to 3, characterized by comprising: 5. The phase modulation device according to any one of claims 1 to 4, wherein the maximum voltage of the driving voltage supplied to the liquid crystal is set to twice the maximum voltage. A phase modulation method that reflects incident light at a desired angle, in which the gradation value corresponding to each pixel circuit and the count value in the counter circuit are controlled at the same timing, and the voltage is controlled up to a predetermined maximum voltage. varying and then determining a control voltage from a ramped reference voltage varying from an intermediate voltage to said maximum voltage ;
supplying the control voltage to a plurality of pixel circuits provided at intersections of a plurality of column data lines and a plurality of row scanning lines that are orthogonal to each other;
outputting the control voltage to the liquid crystal when the drive voltage supplied to the liquid crystal provided for each pixel circuit is equal to or less than the maximum voltage;
a step of amplifying the control voltage by a charge pump and outputting it to the liquid crystal when the drive voltage supplied to the liquid crystal exceeds the maximum voltage;
A phase modulation method, comprising:

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