JP7208513B2 - PHASE MODULATION DEVICE AND PHASE MODULATION METHOD - Google Patents

Description

The present invention relates to a phase modulation device and a phase modulation method.

Conventionally, a phase modulation device using LCOS (Liquid Crystal On Silicon) has been proposed as disclosed in Patent Document 1, for example. Paragraph [0015] of Patent Document 1 and the like disclose controlling the voltage applied to each pixel of the LCOS element to phase-modulate the incident light.

JP 2014-56004 A

Devices that handle infrared light must sufficiently modulate long-wavelength light. Therefore, as a means to secure a high modulation factor, it is basically possible to use a liquid crystal material having a high refractive index anisotropy. For example, the applied voltage of is increased. The method of increasing the thickness of the liquid crystal layer has the disadvantage that the orientation of the liquid crystal tends to be disturbed.

On the other hand, in the technique disclosed in the above-mentioned Patent Document 1, since the voltage supplied to each pixel from the drive circuit is limited, the amount of modulation when modulating the phase cannot be increased. If the voltage output from the drive circuit is increased, it is necessary to increase the withstand voltage of the circuit elements, which causes a problem of increased power consumption.

SUMMARY OF THE INVENTION The present invention has been made in order to solve such conventional problems. An object of the present invention is to provide a phase modulation device and a phase modulation method capable of securing a sufficient phase modulation amount even for infrared light by increasing the voltage applied to the liquid crystal without increasing the voltage.

In order to achieve the above object, a phase modulation device according to the present invention is a phase modulation device for reflecting incident light at a desired angle, wherein a plurality of column data lines and a plurality of row scanning lines orthogonal to each other intersect each other. a plurality of pixel circuits and a plurality of reflective pixels provided at positions where the a control circuit for controlling driving of the pixel circuit, wherein the pixel circuit includes a digital signal holding unit that holds a digital signal having a predetermined pulse width or number of pulses when the digital signal is supplied; a charge pump that amplifies the digital signal output from the digital signal holding unit; The digital signal is output to the liquid crystal without being amplified, and when the drive voltage supplied to the liquid crystal exceeds the maximum amplitude, the digital signal is amplified by the charge pump and output to the liquid crystal. and a charge pump control unit for performing the charging.

Further, the phase modulation method according to the present invention is a phase modulation method for reflecting incident light at a desired angle, and is provided at positions where a plurality of mutually orthogonal column data lines and a plurality of row scanning lines intersect each other. a step of outputting a digital signal having a predetermined pulse width or a predetermined number of pulses to a plurality of pixel circuits; a step of holding the digital signal; outputting the digital signal to the liquid crystal without amplification when a driving voltage supplied to the liquid crystal whose refractive index changes with respect to incident light is equal to or less than the maximum amplitude of the digital signal; a step of amplifying the digital signal with a charge pump and outputting it to the liquid crystal when the voltage exceeds the maximum amplitude.

According to the present invention, it is possible to set a large amount of phase modulation of reflected light without increasing the control voltage supplied from the column data line to the pixel circuit. As a result, it is possible to suppress the thickening of the liquid crystal layer for securing the phase modulation amount and the disturbance of the liquid crystal alignment due to the thickening of the liquid crystal layer.

FIG. 1 is a plan view showing the configuration of a phase modulation device according to an embodiment of the invention. FIG. 2 is a side sectional view showing the configuration of the phase modulation device according to the embodiment of the present invention. FIG. 3 is a circuit diagram of a phase modulation device according to an embodiment of the invention. FIG. 4 is a circuit diagram showing the configuration of each pixel circuit provided in the phase modulation device according to the embodiment of the invention. FIG. 5 is an explanatory diagram showing the direction of reflected light reflected by the pixel circuit, where sa1 indicates the case when the charge pump is off and sb1 indicates the case when the charge pump is on. FIG. 6(a) shows pixel circuits arranged in a matrix, and FIG. 6(b) is a graph showing drive voltages supplied from each pixel circuit to the liquid crystal. FIG. 7 is a graph showing the relationship between the number of data bits of a digital signal and the number/width of pulses. FIG. 8 is a timing chart showing operations of the transistor Q2 and the switches S1 to S4 provided in each pixel circuit of the phase modulation device according to the embodiment of the present invention. FIG. 9 is an explanatory diagram showing a modification of the pixel circuit provided in the phase modulation circuit according to this embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a phase modulation device according to an embodiment of the present invention, and FIG. 2 is a side cross-sectional view. As shown in FIGS. 1 and 2, a phase modulation device 101 according to this embodiment has an LCOS panel structure including a reflective substrate 11, a liquid crystal layer 12, and a counter substrate 13. FIG. Then, the light incident from the counter substrate 13 side (the direction of the arrow Y1 in FIG. 2) is reflected and separated into a plurality of reflected lights having different phases. In the following, the surfaces of the reflecting substrate 11 and the opposing substrate 13 on which light is incident are referred to as "light incident surfaces".

A plurality of reflective pixels made of a metal that reflects light (for example, aluminum) is provided on the light incident surface of the reflective substrate 11, and a pixel circuit is provided for each reflective pixel. A plurality of pixel circuits 21 are arranged in the horizontal direction and the vertical direction, respectively, as will be described later with reference to FIG. Each pixel circuit 21 operates under the control of the control circuit 22 .

The opposing substrate 13 is arranged parallel to the light incident surface side of the reflecting substrate 11 at a constant interval, and is made of a transparent member (for example, a transparent glass material). That is, the counter substrate 13 has a function as a transparent substrate. Furthermore, the counter substrate 13 is provided with a transparent electrode. Therefore, the light incident from the light incident surface side of the opposing substrate 13 passes through the transparent member and the transparent electrode and enters the liquid crystal layer 12 .

The liquid crystal layer 12 is arranged in a space sandwiched between the reflective substrate 11 and the opposing substrate 13, and the periphery thereof is sealed with a sealing material 14. As shown in FIG. For the convenience of the following explanation, the liquid crystal layer 12 is considered as a liquid crystal 42 (see FIG. 4 described later) divided on each reflective pixel (that is, each pixel circuit 21). The liquid crystal 42 includes a pixel electrode having light reflectivity (q1 shown in FIG. 4 to be described later, i.e., reflective pixel) and a common electrode (q2 shown in FIG. 4 to be described later, i.e., transparent electrode ) and are filled and sealed. A voltage output from the pixel circuit 21 (hereinafter referred to as "driving voltage") is supplied to the pixel electrode q1, and a preset common electrode voltage is supplied to the common electrode q2.

Therefore, by the potential difference between the drive voltage applied by each pixel circuit 21 and the common electrode voltage applied to the common electrode q2, the refractive index of the liquid crystal 42 on each reflective pixel with respect to the incident light is changed by the individual liquid crystal 42 The light incident on the light incident surface side of the counter substrate 13 can be reflected in a desired direction by changing the light intensity for each group or for each predetermined number of groups.
By changing the refractive index of the liquid crystal 42 on a plurality of continuous reflective pixels stepwise from large to small (or from small to large), the speed of the incident light (advance or delay in phase) will change. Because of the difference, the incident light travels in a curved manner, and reflected light with a certain angle can be obtained.

Next, the configuration of each pixel circuit 21 and the control circuit 22 that controls each pixel circuit 21 will be described with reference to the block diagram shown in FIG. 3 and the circuit diagram shown in FIG. 3, the control circuit 22 includes a plurality of pixel circuits 21 (m columns, n rows) arranged in a matrix, a horizontal scanning circuit 23, a vertical scanning circuit 24, and a charge pump control section 25. ing. Then, the control circuit 22 outputs an electric signal to each pixel circuit 21 to drive each pixel circuit 21 , and a driving voltage is applied from each pixel circuit 21 . The refractive index for incident light of the liquid crystal 42 on each reflective pixel is controlled to a desired value.

A plurality of pixel circuits 21 (m ×n) are arranged. The plurality of pixel circuits 21 are all configured identically. Further, drive lines (L1 to Ln) and control lines (K1 to Kn) are provided in parallel with the row scanning lines (G1 to Gn). The drive lines (L1-Ln) and the control lines (K1-Kn) are connected to the charge pump controller 25. FIG.

The drive lines (L1 to Ln) are wires for transmitting control signals for switching on and off of the transistor Q2 (short-circuit switch; see FIG. 4) provided in each pixel circuit 21. FIG. The control lines (K1 to Kn) are wirings for transmitting control signals for switching ON/OFF of the switches S1 to S4 (see FIG. 4) provided in each pixel circuit . As shown in FIG. 4, a plurality of control lines (K1-Kn) are provided (two lines K1-1 and K1-2 in FIG. 3). are shown in abbreviated form.
The column data lines (D1 to Dm) are wirings for supplying each pixel circuit 21 with a digital signal output from the digital signal line X1.

[Description of Pixel Circuit 21]
FIG. 4 is a circuit diagram showing a detailed configuration of the pixel circuit 21. As shown in FIG. Here, the configuration of the pixel circuit 21 (referred to as pixel circuit 21a) arranged at the intersection of the column data line D1 and the row scanning line G1 shown in FIG. 3 will be described. As shown in FIG. 4, the pixel circuit 21a includes an SRAM (Static RAM; digital signal holding unit) 32, transistors Q1 and Q2, a charge pump 31, and an output capacitor C2.

The SRAM 32 holds a digital signal consisting of a pulse pattern corresponding to each bit supplied from the column data line D1, and outputs a digital signal of voltage VLC with maximum amplitude. As will be described later, the SRAM 32 outputs a digital signal of voltage "0" or "VLC". Specifically, when the pulse does not rise, the voltage "VLC" is output, and when the pulse rises, the pulse pattern with the amplitude "VLC" is output. Further, by driving the charge pump 31 which will be described later, the voltage VLC can be amplified to a voltage "2*VLC" which is doubled and supplied to the liquid crystal 42. FIG.

That is, the SRAM 32 has a function of outputting a digital signal corresponding to the pulse number or pulse width of the digital signal supplied to the column data line.

The transistor Q1 is a switching transistor, and is composed of, for example, an N-channel MOSFET (field effect transistor). One terminal (eg, drain) of the transistor Q1 is connected to the column data line D1, and the other terminal (eg, source) is connected to the input of the SRAM32. A control terminal (for example, gate) of the transistor Q1 is connected to the row scanning line G1. Therefore, when the row scanning line G1 is selected and a digital signal is input from the column data line D1, this digital signal is supplied to the SRAM32.

Similar to the transistor Q1, the transistor Q2 is also a switching transistor, and is composed of, for example, an N-channel MOSFET (field effect transistor). One terminal (eg, drain) of the transistor Q2 is connected to the input terminal p1 of the charge pump 31, and the other terminal (eg, source) is connected to the output terminal p2 of the charge pump 31. FIG.

A control terminal (for example, a gate) is connected to the drive line L1. Therefore, when a voltage of "H" level is supplied to the drive line L1, the transistor Q2 is turned on and the input terminal p1 and the output terminal p2 of the charge pump 31 are short-circuited. That is, the voltage supplied to the input terminal p1 can be directly output to the output terminal p2. In other words, the function of the charge pump 31 can be stopped. On the contrary, when drive line L1 is supplied with a voltage of "L" level, transistor Q2 is turned off. Therefore, the input terminal p1 and the output terminal p2 of the charge pump 31 are opened, and the charge pump 31 can be operated.

That is, the transistor Q2 functions as a short-circuit switch that short-circuits the input terminal p1, through which the charge pump 31 is supplied with the output voltage of the SRAM 32, and the output terminal p2, through which the charge pump 31 outputs the voltage (driving voltage) to the liquid crystal 42. It has

As will be described later, when the number of data bits of the digital signal supplied from the column data line D1 is in the range of "0 to m/2" (where m is the maximum number of bits), the charge pump control unit 25 (see FIG. 3) short-circuits the transistor Q2 to stop the charge pump 31 from driving. Further, when the number of data bits of the digital signal is in the range of "m/2 to m", the transistor Q2 is opened and the charge pump 31 is made drivable.

The charge pump 31 includes four switches S1 to S4 and a capacitor C1 (first capacitor) for storing charges, and amplifies the voltage supplied to the input terminal p1 (the output voltage of the SRAM 32) and outputs it to the output terminal p2. output to

In the charge pump 31, a switch S1 (first switch) and a switch S3 (third switch) are connected in series, the end on the switch S1 side is connected to the input terminal p1, and the end on the switch S3 side is connected to the output terminal p2. It is connected to the. Also, the switch S2 (second switch) and the switch S4 (fourth switch) are connected in series with each other, the end on the switch S2 side is connected to the input terminal p1, and the end on the switch S4 side is connected to the ground. .

Furthermore, a capacitor C1 is provided between the connection point of the switches S1 and S3 and the connection point of the switches S2 and S4. The output terminal p2 is connected to the ground via the output capacitor C2 and further connected to the pixel electrode q1 of the liquid crystal 42. FIG. That is, one end of the capacitor C1 is connected to the switches S1 and S3, and the other end of the capacitor C1 is connected to the switches S2 and S4. Further, as described above, the common electrode q2 of the liquid crystal 42 is a transparent electrode provided on transparent glass. A common electrode voltage is applied to the transparent electrode.

The liquid crystal 42 is driven according to the potential difference between the drive voltage applied to the pixel electrode q1 from the pixel circuit 21 and the common electrode applied to the common electrode q2. Therefore, the incident light incident on the liquid crystal 42 is phase-modulated according to the potential difference and reflected.

[Description of Reflected Light by Reflective Substrate]
FIG. 5 is an explanatory diagram schematically showing angles of incident light incident on the pixel circuit 21 and reflected light reflected by the reflective pixel 20 corresponding to the pixel circuit 21 . In FIG. 5, symbol st indicates incident light incident from a direction orthogonal to the reflective pixel 20 corresponding to each pixel circuit 21, symbol sa1 indicates reflected light reflected at the angle θa by the reflective pixel 20, and symbol sb1. indicates reflected light reflected at an angle θb. The same phase plane of the incident light st (a plane normal to the direction of the incident light st) is r1, the phase plane of the reflected light sa1 is ra1, and the same phase plane of the reflected light sb1 is rb1.

As shown in FIG. 5, incident light st is applied from a direction substantially orthogonal to the reflective pixel 20 and enters the liquid crystal 42 . Further, the refractive index of the liquid crystal 42 changes according to the drive voltage applied to the liquid crystal 42 by the pixel circuit 21 . For example, when the maximum drive voltage in the conventional art is the voltage Va, the reflection angle of the reflected light sa1 obtained when the voltage is changed stepwise from the minimum voltage Vmin to the voltage Va in the continuous pixel circuits 21 is θa On the other hand, when the charge pump 31 is driven, the maximum driving voltage becomes Vb (Vb>Va), and reflected light sb1 reflected at a larger reflection angle θb is obtained.

At this time, although Vmin is applied, the liquid crystal on the pixel has a large refractive index nmax, and the liquid crystal on the pixel to which the maximum voltage Va is applied changes to a small refractive index na. Since the light incident on the liquid crystal with the refractive index na travels faster than the light incident on the liquid crystal with the refractive index nmax, the reflected light is emitted at an angle θa. On the other hand, since the liquid crystal on the pixel to which the voltage Vb is applied has a refractive index nb smaller than na, the incident light travels even faster. Therefore, the reflected light is emitted at a larger angle θb.
Although the change in the refractive index of the liquid crystal due to the voltage value is explained here, even when a high-frequency pulse signal is applied to the liquid crystal, the refractive index can be changed by the pulse number/width and pattern. In the case of a pulse pattern, for example, the greater the number of pulses, the greater the amount of change in the refractive index.

Returning to FIG. 3, the horizontal scanning circuit 23 provided in the control circuit 22 includes a shift register circuit 26 and a switch circuit 27 including switches SW1 to SWm.

The shift register circuit 26 inputs a horizontal synchronization signal (HST) and horizontal scanning clock signals (HCK1, HCK2). The shift register circuit 26 sequentially shifts the clock signal based on the horizontal synchronizing signal and the clock signal for horizontal scanning, thereby outputting switching signals (which are referred to as "SD1 to SDm") to the switch circuit 27. It is generated in a cycle of one horizontal scanning period.

The switch circuit 27 includes m switches SW1 to SWm for switching ON/OFF of each column data line (D1 to Dm). The switches SW1 to SWm are controlled to be on or off based on switching signals (SD1 to SDm) output from the shift register circuit . The switches SW1 to SWm are provided corresponding to the column data lines (D1 to Dm), and sequentially input the digital signal "d" corresponding to each column data line.

The switches SW1 to SWm selectively apply digital signals corresponding to the respective column data lines (D1 to Dm) to the column data lines. For example, the switch SW1 is turned on when the switching signal SD1 is at high level, selects a digital signal corresponding to the column data line D1, and outputs the selected digital signal to the column data line D1. A digital signal is supplied from the digital signal line X1.

[Description of the number of pulses of the digital signal and the output voltage of the SRAM 32]
FIG. 7 is a graph showing the relationship between the number of data bits of a digital signal and the number of pulses. In FIG. 7, the horizontal axis indicates the number of data bits (maximum value m) of the digital signal supplied from the column data line D1, and the vertical axis indicates the number of pulses. Although it is also possible to use the pulse width instead of the number of pulses, the number of pulses will be explained below.

As shown in FIG. 7, when the number of data bits ranges from 0 to (m/2), the number of pulses varies from 0 to the maximum value Wmax, as shown in graph R1. Further, when the number of data bits is in the range of (m/2) to m, the number of pulses varies in the range of (Wmax/2) to Wmax as shown in graph R2. Then, the charge pump 31 is turned off when the number of data bits is in the range of 0 to (m/2), and turned on in the range of (m/2) to m. That is, the charge pump control unit 25 shown in FIG. 3 turns off the charge pump 31 when the number of data bits of the digital signal is in the range of 0 to (m/2), and turns off the charge pump in the range of (m/2) to m. 31 is turned on.

In FIG. 7, when the pulse of the digital signal does not rise, the voltage supplied from the column data line is "0". At this time, the output voltage of the SRAM 32 is "VLC". When the pulse is standing and the number of data bits is in the range of 0 to (m/2), the SRAM 32 outputs a pulse pattern corresponding to each bit with a voltage VCL that is the maximum amplitude of the digital signal. . At this time, the charge pump 31 is turned off. Therefore, the voltage VLC output from the SRAM 32 is supplied to the liquid crystal 42 as a driving voltage without being amplified by the charge pump 31 .

When the pulse is on and the number of data bits is in the range of (m/2) to m, the SRAM 32 outputs a pulse pattern corresponding to each bit at the voltage VCL that provides the maximum amplitude of the digital signal. be done. At this time, the charge pump 31 is turned on. Therefore, the voltage VLC output from the SRAM 32 is amplified to double the voltage (2*VLC) by the charge pump 31, and the pulse pattern of this voltage (2*VLC) is supplied to the liquid crystal 42 as the drive voltage.

Therefore, when the pulse does not rise, the voltage output from the SRAM 32 can be set to "VLC", and the drive voltage supplied to the liquid crystal 42 can be set to "VLC". By outputting the voltage VLC from the SRAM 32 and stopping the charge pump 31, the drive voltage supplied to the liquid crystal 42 can be set to "VLC". Further, by outputting a pulse pattern of the voltage VLC from the SRAM 32 and driving the charge pump 31, the voltage VCL can be doubled, so that the amplitude of the driving voltage supplied to the liquid crystal 42 is set to "2*VLC". can do.

Although the graphs R1 and R2 shown in FIG. 7 are linear, the relationship of the phase change to the voltage in the liquid crystal 42 is not necessarily linear, so the number of pulses is not necessarily linear. Also, since the voltage output from the SRAM 32 is inverted in polarity, the pixel electrode q1 is supplied with a voltage with the inverted polarity. A desired voltage can be applied to the liquid crystal 42 by inverting the voltage supplied to the common electrode q2 corresponding to this.

In this manner, the operation of the charge pump 31 makes it possible to set the amplitude of the drive voltage of the pulse pattern supplied to the liquid crystal 42 in three ways: "0", "VLC", and "2*VLC". Then, it becomes possible to set the liquid crystal 42 to a plurality of gradations according to the pulse pattern (pulse width or number of pulses) of each amplitude.

Therefore, by controlling the ON/OFF of each of the switches SW1 to SWm provided in the switch circuit 27 and controlling the driving of the charge pump 31, the pixel circuit 21 generates driving signals of a plurality of gradations. It can be supplied to the liquid crystal 42 .

Returning to FIG. 3, the vertical scanning circuit 24 is connected to row scanning lines (G1 to Gn). The vertical scanning circuit 24 inputs a vertical synchronization signal (VST) and vertical scanning clock signals (VCK1, VCK2). The vertical scanning circuit 24 sequentially supplies row selection signals (scanning signals), for example, from the row scanning line G1 to the row scanning line Gn at a cycle of one horizontal scanning period based on the vertical synchronization signal and the clock signal for vertical scanning. .

The charge pump control unit 25 outputs a drive signal to each drive line (L1 to Ln) shown in FIG. Specifically, when the number of data bits of the digital signal supplied from the column data line is in the range of 0 to (m/2), an "H" level signal is output to the drive line. Also, when the number of data bits of the digital signal is in the range of (m/2) to m, it outputs an "L" level signal to the drive line.

Further, the charge pump control unit 25 does not drive the charge pump 31 when a signal of "H" level is supplied to the drive line, and does not charge the charge pump 31 when a signal of "L" level is supplied to the drive line. It controls to drive the pump 31 . The operation of the charge pump 31 will be described below.

When the charge pump control unit 25 drives the charge pump 31, the control signal for controlling the ON/OFF of each of the switches S1 to S4 shown in FIG. Output. Specifically, when a pulse pattern is output from the SRAM 32, the switches S1 and S4 are first turned on, and the switches S2 and S3 are turned off.

Therefore, the voltage of the pulse pattern with the amplitude VLC output from the SRAM 32 is stored in the capacitor C1. After a predetermined time has passed, the switches S1 and S4 are turned off, and the switches S2 and S3 are turned on. As a result, the voltage of the pulse pattern output from the SRAM 32 and the voltage VLC accumulated in the capacitor C1 are added, and the voltage after the addition is accumulated in the output capacitor C2. Therefore, the voltage accumulated in the output capacitor C2 is output to the pixel electrode q1.

Then, in the phase modulation device 101 according to the present embodiment, blocks made up of some of the (n×m) pixel circuits 21 shown in FIG. 3 are set. For example, as shown in FIG. 6A, a block composed of (5 rows×6 columns) pixel circuits 21 is set. In FIG. 6A, the suffix "-nm" is added to specify the row (n) and column (m) of each pixel circuit 21, respectively. Accordingly, the pixel circuit of row 1 and column 1 shown in FIG. 6A is 21-11, and the pixel circuit of row 5 and column 6 is 21-56.

In FIG. 6A, six pixel circuits 21-11 to 21-16 in the same row are set to have the same refractive index. For example, the pixel circuits 21-11 to 21-16 in the first row are set to have the first refractive index, and the pixel circuits 21-21 to 21-26 in the second row are set to have the second refractive index. The third row pixel circuits 21-31 to 21-36 are set to have a third refractive index, the fourth row pixel circuits 21-41 to 21-46 are set to have a fourth refractive index, and the fifth row pixel circuits 21-31 to 21-46 are set to have a fourth refractive index. The pixel circuits 21-51 to 21-56 are set to have a fifth refractive index.

Specifically, as shown in FIG. 6B, in each pixel circuit 21-11 to 21-51 arranged in the vertical direction, the refractive index of each liquid crystal 42 is set to change in five steps. Therefore, it is possible to group six pixel circuits 21 arranged in the horizontal direction into one group, change the refractive index in five gradations, and obtain reflected light phase-modulated in five ways. . Note that the vertical direction and the horizontal direction may be interchanged.

[Explanation of operation of the present embodiment]
Next, the operation of the phase modulation device 101 according to this embodiment configured as described above will be described with reference to the graph shown in FIG. 7 and the timing chart shown in FIG. In the following, as shown in FIG. 6A, an example in which pixel circuits 21 are arranged in a matrix of 5 rows and 6 columns and reflective pixels corresponding to the pixel circuits 21 are provided will be described. .

The horizontal scanning circuit 23 shown in FIG. 3 controls the ON/OFF of each switch SW1 to SWm (here, m=6) provided in the switch circuit 27, thereby controlling the digital signal supplied from the digital signal line X1. to the desired column data lines.

Further, by driving the vertical scanning circuit 24, the scanning line corresponding to the desired pixel circuit 21 is selected from the row scanning lines (G1 to Gn) (here, n=5). As a result, a digital signal can be supplied to the SRAM 32 of the desired pixel circuit 21 .

Specifically, when the pulse of the digital signal does not rise, the SRAM 32 outputs the voltage "VLC". As shown in graph R1 in FIG. 7, when the number of data bits is in the range of 0 to (m/2) and the pulse is on, the SRAM 32 outputs a pulse pattern with amplitude "VLC". At this time, the transistor Q2 is turned on and the switches S1 to S4 are all turned off, as shown at times t0 to t1 in FIG. Therefore, the charge pump 31 is not driven. A pulse pattern with an amplitude "VLC" is supplied to the pixel electrode q1 and the liquid crystal 42 via the transistor Q2.

On the other hand, as shown in the graph R2 in FIG. 7, when the number of data bits is in the range of (m/2) to m and the pulse stands, the SRAM 32 outputs a pulse pattern with an amplitude of "VLC". At this time, the transistor Q2 is turned off as shown at times t1 to t4 in FIG. Further, the switches S1 and S4 are turned on and the switches S2 and S3 are turned off from time t1 to t2, and the switches S2 and S3 are turned on and the switches S1 and S4 are turned off from time t3 to t4. The pulse pattern is amplified twice and supplied to the pixel electrode q1 and the liquid crystal 42.

[Description of effects of the present embodiment]
Thus, in the phase modulation device 101 according to the present embodiment, digital signals output from the column data lines (D1 to Dm) are input to the SRAM 32 provided in each pixel circuit 21. FIG. By controlling the driving and stopping of the charge pump 31, the liquid crystal 42 can be switched to a plurality of gradations within the range of "0" to "2*VLC".

Therefore, when the maximum value of the digital signal output from the SRAM 32 is the voltage VLC, it is possible to set the drive voltage for driving the liquid crystal 42 within the range of the voltage (2*VLC) which is twice the voltage VLC. becomes. Therefore, the refractive index of the liquid crystal 42 can be changed in a wider range, and the precision of phase modulation can be improved.

Furthermore, since the gradation can be set in a wide voltage range without increasing the maximum voltage VLC of the voltage supplied to the pixel circuit 21, there is no need to increase the breakdown voltage of each component constituting the control circuit 22, and the size of the device can be reduced. It becomes possible to achieve weight reduction.

In addition, since the voltage range for setting the gradation of the liquid crystal 42 is set to twice the predetermined maximum voltage (VLC), the voltage output from the SRAM 32 can be simply amplified by a factor of two. A desired driving voltage can be obtained by simple processing, and the circuit configuration can be simplified.
Further, in this embodiment, the refractive index of the liquid crystal 42 is set to change in one of the directions orthogonal to each other, ie, the column direction and the row direction shown in FIG. 3, and changes in the other direction. , drive lines (L1 to Ln) for switching the charge pump on and off. Therefore, it is possible to prevent the alignment of the liquid crystal from being disturbed due to the change in the refractive index.

Furthermore, since the SRAM 32 is used as the digital signal holding unit, it is possible to hold the digital signal with a simple configuration and output it to the charge pump 31 . Furthermore, since digital signals are used in this embodiment, it is possible to perform the operation of switching the gradation at a higher speed.

In this embodiment, the maximum value of the driving voltage for driving the liquid crystal 42 is set to a voltage (2*VLC) that is twice the maximum voltage VLC, but the present invention is not limited to this. It is sufficient if the maximum value of the drive voltage is greater than a predetermined maximum voltage (VLC).

[Description of modification of the present embodiment]
Next, a modified example of this embodiment will be described. FIG. 9 is a circuit diagram showing the configuration of a pixel circuit 21' according to a modification. As shown in FIG. 9, in the pixel circuit 21' according to the modification, the drive lines L1 are arranged in the vertical direction. Therefore, the charge pump circuit can be turned on or off in the vertical direction of each pixel circuit 21' arranged in a matrix. Therefore, the direction in which the refractive index changes is the lateral direction.

That is, in the examples shown in FIGS. 6A and 6B, the refractive index of the liquid crystal 42 changes in the vertical direction, whereas in the modified example shown in FIG. , the refractive index of the liquid crystal 42 is set to change. In this case, the digital signal supplied to the pixel circuit 21' is set so that the number of pulses or the pulse width changes in one vertical scanning period.

Although embodiments of the present invention have been described above, the statements and drawings forming part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art from this disclosure.

11 reflective substrate 12 liquid crystal layer 13 counter substrate 14 sealing material 21, 21a, 21' pixel circuit 22 control circuit 23 horizontal scanning circuit 24 vertical scanning circuit 25 charge pump control unit 26 shift register circuit 27 switch circuit 31 charge pump 32 SRAM (digital signal holding part)
42 liquid crystal 101 phase modulation device C1 capacitor C2 output capacitor D1 to Dm column data line G1 to Gn row scanning line K1 to Kn control line L1 to Ln drive line Q1, Q2 transistor

Claims (7)

A phase modulation device that reflects incident light at a desired angle,
a plurality of pixel circuits provided at positions where a plurality of column data lines and a plurality of row scanning lines that are orthogonal to each other intersect, and a plurality of reflective pixels;
a liquid crystal provided corresponding to the reflective pixel and having a refractive index with respect to incident light that changes according to a drive voltage supplied from the pixel circuit;
a control circuit that controls driving of the pixel circuit;
The pixel circuit is
a digital signal holding unit that holds a digital signal having a predetermined pulse width or number of pulses when the digital signal is supplied;
a charge pump that amplifies the digital signal output from the digital signal holding unit;
Furthermore, the control circuit
When the driving voltage supplied to the liquid crystal is equal to or less than the maximum amplitude of the digital signal, the digital signal is output to the liquid crystal without being amplified, and the driving voltage supplied to the liquid crystal exceeds the maximum amplitude. a charge pump control unit for controlling the digital signal to be amplified by the charge pump and output to the liquid crystal;
A phase modulation device comprising: setting the refractive index of the liquid crystal to change in one of the directions orthogonal to each other, and arranging a driving line for switching on and off of the charge pump in the other direction; The phase modulation device according to claim 1, characterized by: The pixel circuit includes a short-circuit switch that short-circuits an input terminal for supplying the voltage output from the digital signal holding unit to the charge pump and an output terminal for outputting the voltage from the charge pump to the liquid crystal,
The charge pump controller short-circuits the short-circuit switch when the drive voltage output to the liquid crystal is equal to or less than the maximum amplitude, and closes the short-circuit switch when the drive voltage output to the liquid crystal exceeds the maximum amplitude. 3. The phase modulation device according to claim 1, wherein the phase modulation device is open. The pixel circuit includes an output capacitor that stores a voltage supplied to the liquid crystal,
The charge pump is
a first capacitor that stores electric charge;
a first switch provided between one end of the first capacitor and an input terminal to which the digital signal is supplied;
a second switch provided between the other end of the first capacitor and the input terminal;
a third switch provided between the one end of the first capacitor and one end of the output capacitor;
a fourth switch provided between the other end of the first capacitor and the other end of the output capacitor;
The phase modulation device according to any one of claims 1 to 3, characterized by comprising: 5. The phase modulation device according to claim 1, wherein a maximum driving voltage supplied to said liquid crystal is set to twice said maximum amplitude. 6. The phase modulation device according to claim 1, wherein said digital signal holding unit comprises an SRAM. A phase modulation method for reflecting incident light at a desired angle,
outputting a digital signal with a predetermined pulse width or number of pulses to a plurality of pixel circuits provided at positions where a plurality of column data lines and a plurality of row scanning lines which are orthogonal to each other intersect;
holding the digital signal;
In each of the pixel circuits , when the drive voltage supplied to the liquid crystal whose refractive index for incident light changes according to the input drive voltage is equal to or less than the maximum amplitude of the digital signal, the digital signal is not amplified. a step of outputting to a liquid crystal;
a step of amplifying the digital signal with a charge pump and outputting it to the liquid crystal when the driving voltage supplied to the liquid crystal exceeds the maximum amplitude;
A phase modulation method, comprising:

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