JP7192757B2 - Epitaxial silicon wafer, manufacturing method thereof, and X-ray detection sensor - Google Patents

Description

The present invention relates to an epitaxial silicon wafer, its manufacturing method, and an X-ray detection sensor.

X-rays are used in various fields such as baggage inspection, food foreign substance inspection, medical care, and astronomical observation. In the past, it was common to detect X-rays using a photosensitive film, but with the expansion of its use, semiconductor wafers such as silicon are used to measure X-rays at high speed and with high sensitivity. In recent years, attention has been paid to an X-ray detection sensor composed of photoelectric conversion elements.

For example, in the X-ray detection sensor disclosed in Patent Document 1, an SOI (Silicon I) layer is formed by stacking a buried oxide layer made of a silicon oxide film and a p-type semiconductor layer on an n-type semiconductor layer made of a silicon single crystal that also serves as a support substrate. on Insulator) substrate is used. For example, in an X-ray detection sensor manufactured using this SOI substrate, the support substrate is used as an X-ray sensor section (X-ray light receiving section). This is because the X-ray sensor must have a sufficient thickness in consideration of the X-ray absorption rate of the silicon single crystal. A device such as a CMOS circuit for processing signals transmitted from the X-ray detection sensor is formed in the p-type semiconductor layer.

WO2011/111754

By the way, since the buried insulating layer (also called BOX layer) of the SOI wafer is made of silicon oxide as described above, its thermal conductivity is low. Therefore, in the X-ray detection sensor manufactured using the SOI wafer described in Patent Document 1, etc., the CMOS circuit formed in the p-type semiconductor layer self-heats during use, causing the device to malfunction. There is a risk that

Accordingly, the present inventor has conceived of using epitaxial silicon wafers instead of SOI wafers as semiconductor wafers for fabricating X-ray detection sensors. This is because an epitaxial silicon wafer does not contain silicon oxide, and thus has a higher thermal conductivity than an SOI wafer and is excellent in heat dissipation. Therefore, by forming a silicon epitaxial layer having a two-layer structure on a silicon wafer serving as a supporting substrate and making the silicon epitaxial layer directly above the supporting substrate function as a substantial insulating layer, an epitaxial silicon wafer substituting for an SOI wafer can be obtained. I remembered making it. If an epitaxial silicon wafer has such an insulating function, it can be used as an X-ray detection sensor. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an epitaxial silicon wafer and a method for manufacturing the same, which are applicable to X-ray detection sensors. A further object of the present invention is to provide an X-ray detection sensor using this epitaxial silicon wafer.

The present inventor has made studies to solve the above problems. Then, by optimizing the relationship between the conductivity type, carrier concentration, and thickness of the silicon wafer serving as the supporting substrate and the first and second silicon epitaxial layers formed thereon, the first silicon epitaxial layer is converted into an insulating layer. I came up with the idea to function as In this case, a p-type substrate with high resistance is used as the silicon wafer, and the silicon wafer is used as a sensor section for detecting X-rays. The inventors of the present invention have found that the use of this silicon wafer may cause resistance fluctuations due to heat treatment when fabricating the device structure, and that it is necessary to deal with high sensitivity when used as a sensor section. was also recognized as a further issue. Accordingly, the present inventors have further studied silicon wafers to be used, and have completed the present invention. That is, the gist and configuration of the present invention are as follows.

<1> a silicon wafer;
a silicon epitaxial layer provided on the surface of the silicon wafer;
An epitaxial silicon wafer comprising
The silicon epitaxial layer comprises a first silicon epitaxial layer provided on the surface of the silicon wafer and a second silicon epitaxial layer provided on the surface thereof,
The silicon wafer is p-type, the first silicon epitaxial layer is n-type, the second silicon epitaxial layer is p-type, and the silicon wafer and the first and second silicon epitaxial layers are Each thickness and each carrier concentration of the following formulas (1) to (3):
d1>d3>d2 (1)
C3>C2>C1 (2)
C3·(d3/10)≧C2·d2 (3)
(In the above formulas (1) to (3), d1, d2 and d3 represent the thicknesses of the silicon wafer, the first silicon epitaxial layer and the second silicon epitaxial layer, respectively; C1, C2 and C3 are represents the carrier concentrations of the silicon wafer, the first silicon epitaxial layer and the second silicon epitaxial layer, respectively)
satisfies the
The silicon wafer has a resistivity of 100 Ω·cm or more and an oxygen concentration of 5.0 × 10 ¹⁷ atoms/cm ³ or less.
An epitaxial silicon wafer characterized by:

<2> The epitaxial silicon wafer according to <1>, wherein the first silicon epitaxial layer is a depletion layer.

<3> The epitaxial silicon wafer according to <1> or <2>, wherein the silicon wafer has a thickness d1 of 100 μm or more.

<4> The epitaxial silicon wafer according to any one of <1> to <3>, wherein the silicon wafer is an FZ wafer or an MCZ wafer.

<5> The epitaxial silicon wafer according to any one of <1> to <4>, wherein the silicon wafer does not contain COPs.

<6> The method for producing an epitaxial silicon wafer according to any one of <1> to <5>,
forming the first silicon epitaxial layer on the surface of the silicon wafer;
forming the second silicon epitaxial layer on the surface of the first silicon epitaxial layer;
A method for producing an epitaxial silicon wafer, comprising:

<7> An X-ray detection sensor formed using the epitaxial silicon wafer according to any one of <1> to <5>,
An X-ray detection unit is provided on the silicon wafer,
An X-ray detection sensor, wherein a MOS transistor section is provided in the second silicon epitaxial layer.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide an epitaxial silicon wafer suitable for an X-ray detection sensor and a method for producing the same. Furthermore, according to the present invention, an X-ray detection sensor using this epitaxial silicon wafer can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic cross section explaining the epitaxial silicon wafer by one Embodiment of this invention. It is a schematic diagram showing the relationship between the thickness of the silicon wafer and silicon epitaxial layer and the carrier concentration in the epitaxial silicon wafer according to one embodiment of the present invention. It is a schematic cross section explaining the manufacturing method of the epitaxial silicon wafer by one Embodiment of this invention. 1 is a schematic cross-sectional view illustrating an X-ray detection sensor according to one embodiment of the present invention; FIG. FIG. 4 is a schematic cross-sectional view for explaining a TEG for withstand voltage measurement used for TZDB measurement;

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In principle, the same constituent elements are given the same reference numerals, and the description thereof is omitted. In FIGS. 1 and 3 to 5, the thicknesses of the silicon wafer and the silicon epitaxial layer are exaggerated in order to simplify the drawings.

(epitaxial silicon wafer)
Please refer to FIG. An epitaxial silicon wafer 100 according to one embodiment of the present invention comprises a silicon wafer 110 and a silicon epitaxial layer 120 provided on the surface of the silicon wafer 110 . This silicon epitaxial layer 120 consists of a first silicon epitaxial layer 121 provided on the surface of the silicon wafer 110 and a second silicon epitaxial layer 122 provided on that surface. Here, the silicon wafer 110 is p-type, the first silicon epitaxial layer 121 is n-type, and the second silicon epitaxial layer 122 is p-type. Then, each thickness and each carrier concentration of the silicon wafer 110 and the first silicon epitaxial layer 121 and the second silicon epitaxial layer 122 are calculated by the following formulas (1) to (3):
d1>d3>d2 (1)
C3>C2>C1 (2)
C3·(d3/10)≧C2·d2 (3)
(In the above formulas (1) to (3), d1, d2 and d3 represent the thicknesses of the silicon wafer 110, the first silicon epitaxial layer 121 and the second silicon epitaxial layer 122, respectively; C1, C2 and C3 are represent the carrier concentrations of the silicon wafer 110, the first silicon epitaxial layer 121 and the second silicon epitaxial layer 122). Furthermore, the silicon wafer 110 has a resistivity of 100 Ω·cm or more and an oxygen concentration of 5.0×10 ¹⁷ atoms/cm ³ or less. Details of each configuration will be described below.

<Silicon wafer>
Silicon wafer 110 is a support substrate that supports silicon epitaxial layer 120 . As the silicon wafer 110, a so-called bulk silicon single crystal wafer without a separate epitaxial layer is used. When the epitaxial silicon wafer 100 is used to fabricate an X-ray detection sensor, a sensor portion is formed on the silicon wafer 110 .

<Silicon epitaxial layer>
The silicon epitaxial layer 120 consists of a first silicon epitaxial layer 121 and a second silicon epitaxial layer 122 . As shown in FIG. 1 , a first silicon epitaxial layer 121 is provided on the surface of the silicon wafer 110 and a second silicon epitaxial layer 122 is provided on the surface of the first silicon epitaxial layer 121 . It should be noted that the silicon epitaxial layer 120 does not have other structures except for impurities that are unavoidable in the manufacturing process.

The first and second silicon epitaxial layers 121 and 122 are two-layer structure silicon epitaxial layers having different conductivity types and different carrier densities. The carrier concentrations of the first and second silicon epitaxial layers 121 and 122 referred to here are substantially uniform in the thickness direction of each layer, except for inevitable manufacturing errors. For example, when layers having the same conductivity type but having a carrier concentration that changes twice or more in the thickness direction are provided, such as the so-called n+ layer/n- layer, the n+ layer and the n- layer Each n-layer is considered a separate layer.

<<Conductivity type, carrier concentration and thickness of each configuration>>
As described above, the conductivity types of the silicon wafer 110, the first silicon epitaxial layer 121, and the second silicon epitaxial layer 122 are p-type, n-type, and p-type, respectively. The reason why the conductivity types are arranged in this order is that the first silicon epitaxial layer 121 is depleted to have a high resistance. Then, the thickness and carrier concentration of each component of the epitaxial silicon wafer 100 are set to the above formula (1 ) to (3) are satisfied. Hereinafter, the reasons for defining each formula will be described with reference to the schematic diagram of FIG.

- Thickness relationship: formula (1) -
As described above, d1, d2 and d3 represent the thicknesses of the silicon wafer 110, the first silicon epitaxial layer 121 and the second silicon epitaxial layer 122, respectively, and each of these thicknesses satisfies d1>d3 according to the above equation (1). >d2 is satisfied. Since the silicon wafer 110 supports the silicon epitaxial layer 120 and epitaxially grows the silicon epitaxial layer 120, the thickness d1 of the silicon wafer 110 is equal to the thickness d2 of the first and second silicon epitaxial layers 121, 122, greater than d3. Further, when the epitaxial silicon wafer 100 is applied to an X-ray detection sensor, the silicon wafer 110 is provided with a sensor portion, so the thickness d1 needs to be sufficiently large in consideration of the X-ray absorption efficiency of the silicon single crystal. be. Further, the thickness d2 of the first silicon epitaxial layer is made smaller than the thickness d3 of the second silicon epitaxial layer in order to deplete the entire first silicon epitaxial layer 121 to function as an insulating layer.

-Relationship between carrier concentrations: Equation (2)-
As described above, C1, C2 and C3 represent the carrier concentrations of the silicon wafer 110, the first silicon epitaxial layer 121 and the second silicon epitaxial layer 122, respectively, and each of these carrier concentrations satisfies C3>C2 according to equation (2) above. > satisfies the relationship of C1. When the epitaxial silicon wafer 100 is applied to an X-ray detection sensor, the sensor portion is provided on the silicon wafer 110 as described above, so the carrier concentration C1 must be sufficiently reduced to increase the resistivity. Further, in this case, since the second silicon epitaxial layer 122 is provided with a MOS transistor portion, it is necessary to increase the carrier concentration to lower the resistivity. Then, in order to deplete the entire first silicon epitaxial layer 121 to function as an insulating layer, the carrier concentration C2 is set to be smaller than C3 and smaller than C1 in combination with the above conductivity type and the above formula (3). also increase.

-Relationship between thickness and carrier concentration: Equation (3)-
The relationship between the thickness d2 and carrier concentration C2 of the first silicon epitaxial layer 121 and the thickness d3 and carrier concentration C3 of the second silicon epitaxial layer is C3·(d3/10) according to the above equation (3). It satisfies the relationship ≧C2·d2. Here, the reason why the value of 1/10 of the product of C3 and d3 is made equal to or greater than the value of the product of C2 and d2 is to deplete the first silicon epitaxial layer 121 and increase the resistance. . This allows the first silicon epitaxial layer 121 to function as an insulating layer.

<<Silicon wafer conditions>>
As described above, since the silicon wafer 110 satisfies the relationships of the above formulas (1) to (3), a p-type substrate having a resistivity of 100 Ω·cm or more is used. Any dopant may be used to make the silicon wafer 110 p-type, and for example, boron (B) may be used. Note that the resistivity of 100 Ω·cm is 1.3×10 ¹⁴ atoms/cm ³ when converted to the carrier concentration C1. The carrier concentration C1 is more preferably 1.3×10 ¹⁴ atoms/cm ³ or less, even more preferably 1.3×10 ¹³ atoms/cm ³ or less. In addition, since a substrate with a high resistance is used because the resistivity is 100 Ω·cm or more, device elements such as a sensor section and a MOS transistor section are affected by oxygen that is inevitably mixed when growing a silicon single crystal ingot. There is concern about resistance fluctuations due to heat treatment when fabricating the structure. Therefore, the oxygen concentration of the silicon wafer 110 is limited to 5.0×10 ¹⁷ atoms/cm ³ or less. For this purpose ^, it is preferable that the oxygen ^{concentration} of the silicon ^{wafer 110} is as low as possible. more preferred. Although the lower limit of the oxygen concentration is not limited, one example of the lower limit is 1.0×10 ¹⁵ atoms/cm ³ in consideration of industrial productivity. Silicon wafers 110 satisfying such oxygen concentration conditions are preferably MCZ wafers obtained from single-crystal silicon ingots grown by the MCZ (Magnetic field applied Czochralski) method. For the same reason regarding the oxygen concentration, the silicon wafer 110 is also preferably an FZ wafer obtained from a single crystal silicon ingot grown by the FZ (Floating Zone) method. The oxygen concentration of the silicon wafer conforms to ASTM F121-1979 and employs a value measured using a Fourier Transform Infrared Spectrometer (FTIR).

As described above, the epitaxial silicon wafer 100 according to one embodiment of the present invention satisfies the relationships of the above formulas (1) to (3) in terms of the conductivity type, carrier concentration and thickness of each component, so that the first silicon epitaxial Layer 121 functions as an insulating layer. Furthermore, since the silicon wafer 110 has limited resistivity and oxygen concentration, it can be applied to the sensor portion of the X-ray detection sensor. Although it is particularly preferable to use the epitaxial silicon wafer 100 for manufacturing an X-ray detection sensor, its use is not limited as long as the first silicon epitaxial layer 121 is used as an insulating layer.

Specific aspects of the epitaxial silicon wafer 100 suitable for application to the present invention will be described below.

The silicon wafer 110 is preferably a silicon wafer containing no COPs in order to apply it to the sensor portion of the X-ray sensor. In this specification, the term "silicon wafer containing no COPs" means a silicon wafer in which COPs are not detected by observation and evaluation described below. That is, first, a silicon wafer cut out from a single crystal silicon ingot grown by the CZ method is subjected to SC-1 cleaning (that is, ammonia water, hydrogen peroxide water, and ultrapure water at 1:1:15 ), and the surface of the silicon wafer after cleaning is observed and evaluated using Surfscan SP-2 manufactured by KLA-Tenchor as a surface defect inspection device, and a bright spot defect presumed to be a surface pit (LPD: Light Point Defect). At that time, the observation mode shall be the oblique mode (oblique incidence mode), and the surface pits shall be estimated based on the detection size ratio of the Wide Narrow channel. An atomic force microscope (AFM) is used to evaluate whether or not the LPD identified in this manner is COP. Note that COPs are not formed on the silicon wafer 110 when grown by the FZ method. Also, the thickness d1 of the silicon wafer 110 is preferably 100 μm or more, more preferably 300 μm or more. Although the upper limit of the thickness d1 is not particularly limited, for a wafer with a diameter of 300 mm, the thickness 775 μm±25 μm is an example of the upper limit of the thickness d1.

The first silicon epitaxial layer 121 preferably serves as a depletion layer. Also, the thickness d2 and the carrier concentration C2 are not particularly limited as long as the above formulas (1) to (3) are satisfied. For example, the thickness d2 is preferably 1 μm or more and 10 μm or less. Further, the carrier concentration C2 is preferably 2.0×10 ¹³ atoms/cm ³ or more and 5.0×10 ¹⁵ atoms/cm ³ or less, more preferably 4.3×10 ¹³ atoms/cm ³ or more. It is 3×10 ¹⁴ atoms/cm ³ or less (10 Ω·cm or more and 100 Ω·cm or less in terms of resistivity). Any dopant may be used to make the first silicon epitaxial layer 121 n-type, and phosphorus (P), arsenic (As), or the like may be used.

The thickness d3 and carrier concentration C3 of the second silicon epitaxial layer 122 are also not particularly limited as long as the above equations (1) to (3) are satisfied. For example, the thickness d3 is preferably 1 μm or more and 15 μm or less. Further, the carrier concentration C3 is preferably 1.0×10 ¹⁵ atoms/cm ³ or more and 5.0×10 ¹⁶ atoms/cm ³ or less, more preferably 1.3×10 ¹⁵ atoms/cm ³ or more. It is 6×10 ¹⁶ atoms/cm ³ or less (1 Ω·cm or more and 10 Ω·cm or less in terms of resistivity). Any dopant may be used to make the second silicon epitaxial layer 122 p-type, and boron or the like may be used as the dopant for the silicon wafer 100 .

(Method for manufacturing epitaxial silicon wafer)
Next, one embodiment of the method for manufacturing the epitaxial silicon wafer 100 of the present invention described so far will be described with reference to FIG. A method for manufacturing an epitaxial silicon wafer 100 according to an embodiment of the present invention includes steps of forming a first silicon epitaxial layer 121 on the surface of a silicon wafer 110 (see S110 and S120), and and forming a second silicon epitaxial layer 122 (see S130). As described above, the silicon epitaxial layer 120 is composed of the first and second silicon epitaxial layers 121 and 122, and the conductivity type of each component of the silicon wafer 110 and the first and second silicon epitaxial layers 121 and 122 And the carrier concentration and thickness also satisfy the conditions described above.

Each layer of the silicon epitaxial layer 120 may be formed under general conditions. For example, using hydrogen (H) as a carrier gas, a source gas such as dichlorosilane (SiH ₂ Cl ₂ ) or trichlorosilane (SiHCl ₃ ) is introduced into the chamber. Each silicon epitaxial layer may be epitaxially grown by a CVD (Chemical Vapor Deposition) method at a temperature in the range of 1000 to 1200.degree. Also, the dopant used for forming each layer is as described above.

(X-ray detection sensor)
An X-ray detection sensor can be formed using the epitaxial silicon wafer 100 described so far. This X-ray detection sensor has an X-ray detection section provided on the silicon wafer 100 and a MOS transistor section provided on the second silicon epitaxial layer 122 . Since the first silicon epitaxial layer 121 functioning as an insulating layer is made of single crystal silicon, its thermal conductivity is superior to that of silicon oxide. Therefore, the X-ray detection sensor according to the present invention is superior in heat dissipation to the X-ray detection sensor formed using the SOI wafer disclosed in Patent Document 1 and the like.

A specific example of an X-ray detection sensor formed using the epitaxial silicon wafer 100 will be described with reference to FIG. The X-ray detection sensor 200 shown in FIG. 4 includes a p-type silicon layer 210 derived from the silicon wafer 100 and having a high-concentration n-type diffusion region 214 provided on the surface thereof, and a first epitaxial layer derived from the p-type silicon layer 210 and functioning as an insulating layer. and a p-type silicon layer 222 derived from the second silicon epitaxial layer 122 and provided with an n-type diffusion region 224 and a p-type diffusion region 225 in this order. An insulating region is formed between the n-type diffusion region 224 and the p-type diffusion region 225 . A conductor 250 made of Al, Cu, or the like connects the rear surface of the p-type silicon layer 210 to the high-concentration n-type diffusion region 214, the n-type diffusion region 224, and the p-type diffusion region 225. FIG. The p-type silicon layer 210 corresponds to the X-ray detection section, and the p-type silicon layer 222 corresponds to the MOS transistor section. In this X-ray detection sensor 200, the rear surface of the p-type silicon layer 210 (the side on which the conductor 250 is provided) is used as the X-ray incident surface. In order to increase the X-ray detection efficiency, as shown in FIG. 4, an opening 290 may be provided in the conductor 250 so that the back surface of the p-type silicon layer 210 is exposed under the high-concentration n-type diffusion region 214. preferable.

EXAMPLES The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples.

[Experimental example 1]
(Invention Example 1-1)
A p-type silicon wafer obtained from FZ single crystal as a support substrate (thickness: 750 μm, dopant type: boron, carrier concentration: 1.3×10 ¹⁴ atoms/cm ³ , resistivity: 100 Ω·cm, oxygen concentration: 2× 10 ¹⁶ atoms/cm ³ ) were prepared. Next, this silicon wafer was transported into a single-wafer epitaxial growth apparatus (manufactured by Applied Materials), and a 5.0 μm thick film was formed on the silicon wafer by CVD at 1150° C. using hydrogen as a carrier gas and trichlorosilane as a source gas. was grown (hereinafter abbreviated as n-type Si layer) (dopant: phosphorus, carrier concentration: 4.3×10 ¹⁴ atoms/cm ³ _, resistivity: 10 Ω·cm). Next, a 10.0 μm thick p-type silicon epitaxial layer (dopant: boron, carrier concentration: 1.4×10 ¹⁶ atoms/cm ³ _, resistivity: 1 Ω·cm) was grown on the surface of this n-type layer. (hereinafter abbreviated as p-type Si layer), an epitaxial silicon wafer according to Invention Example 1-1 was produced.

(Invention Example 1-2)
In Invention Example 1-1, the carrier concentration of the n-type Si layer was set to 4.3×10 ¹⁴ atoms/cm ³ (resistivity: 10 Ω·cm), but this was changed to 2.0×10 ¹⁵ atoms/cm ³ (resistance An epitaxial silicon wafer according to Invention Example 1-2 was produced in the same manner as in Invention Example 1-1, except that the ratio was changed to 2.3 Ω·cm.

(Invention Example 1-3)
In Invention Example 1-1, the thickness of the n-type Si layer is 5.0 μm, the carrier concentration is 4.3×10 ¹⁴ atoms/cm ³ (resistivity: 10 Ω·cm), and the thickness of the p-type Si layer is 10 μm. 0 μm and a carrier concentration of 1.4×10 ¹⁶ atoms/cm ³ (resistivity: 1 Ω·cm), the n-type Si layer has a thickness of 2.3 μm and a carrier concentration of 8.0×10 ¹⁴ . atoms/cm ³ (resistivity: 1 Ω·cm), the thickness of the p-type Si layer is 3.0 μm, and the carrier concentration is 1.0×10 ¹⁶ atoms/cm ³ (resistivity: 0.77 Ω·cm). An epitaxial silicon wafer according to Invention Example 1-3 was produced in the same manner as in Invention Example 1-1, except that it was changed.

(Invention Example 1-4)
In Invention Example 1-1, the thickness of the n-type Si layer is 5.0 μm, the carrier concentration is 4.3×10 ¹⁴ atoms/cm ³ (resistivity: 10 Ω·cm), and the thickness of the p-type Si layer is 10 μm. 0 μm and a carrier concentration of 1.4×10 ¹⁶ atoms/cm ³ (resistivity: 1 Ω·cm), the n-type Si layer has a thickness of 3.0 μm and a carrier concentration of 3.0×10 ¹⁴ . The thickness of the p-type Si layer is 12.0 μm, and the carrier concentration is 1.0×10 ¹⁵ atoms/cm ^{3 (} resistivity: 13.3 Ω·cm). cm), an epitaxial silicon wafer according to Invention Example 1-4 was produced in the same manner as in Invention Example 1-1.

(Comparative Example 1-1)
In Invention Example 1-1, the carrier concentration of the n-type Si layer was set to 4.3×10 ¹⁴ atoms/cm ³ (resistivity: 10 Ω·cm), but this was changed to 5.0×10 ¹⁵ atoms/cm ³ (resistance An epitaxial silicon wafer according to Comparative Example 1-1 was produced in the same manner as in Invention Example 1-1, except that the ratio was changed to 1.0 Ω·cm.

(Comparative Example 1-2)
An epitaxial silicon wafer according to Comparative Example 1-2 was produced in the same manner as in Invention Example 1-1 except that the thickness of the n-type Si layer was changed to 40 μm instead of 5.0 μm in Invention Example 1-1. did.

(Comparative Example 1-3)
In Invention Example 1-1, the thickness of the n-type Si layer is 5.0 μm, the carrier concentration is 4.3×10 ¹⁴ atoms/cm ³ (resistivity: 10 Ω·cm), and the thickness of the p-type Si layer is 10 μm. 0 μm and a carrier concentration of 1.4×10 ¹⁶ atoms/cm ³ (resistivity: 1 Ω·cm), the n-type Si layer has a thickness of 2.0 μm and a carrier concentration of 7.5×10 ¹⁵ . atoms/cm ³ (resistivity: 0.7Ω·cm), the thickness of the p-type Si layer is 5.0 μm, and the carrier concentration is 2.0×10 ¹⁶ atoms/cm ³ (resistivity: 0.77Ω·cm). cm), an epitaxial silicon wafer according to Comparative Example 1-3 was produced in the same manner as in Invention Example 1-1.

(Comparative Example 1-4)
In Invention Example 1-1, the thickness of the n-type Si layer is 5.0 μm, the carrier concentration is 4.3×10 ¹⁴ atoms/cm ³ (resistivity: 10 Ω·cm), and the thickness of the p-type Si layer is 10 μm. 0 μm and a carrier concentration of 1.4×10 ¹⁶ atoms/cm ³ (resistivity: 1 Ω·cm), the n-type Si layer has a thickness of 10.0 μm and a carrier concentration of 5.5×10 ¹⁵ . atoms/cm ³ (resistivity: 0.9 Ω·cm), the thickness of the p-type Si layer is 10.0 μm, and the carrier concentration is 3.0×10 ¹⁵ atoms/cm ³ (resistivity: 4.5 Ω·cm). cm), an epitaxial silicon wafer according to Comparative Example 1-4 was produced in the same manner as in Invention Example 1-1.

(Evaluation 1: Insulation of n-type Si layer)
In order to confirm that the n-type Si layer functions as an insulating layer, TZDB (Time Zero Dielectric Breakdown) measurement was performed. A TEG (Test Element Group) 300 for withstand voltage measurement used for the TZDB measurement will be described with reference to FIG. A groove 370 was formed by etching the p-type Si layer 322 and the n-type Si layer 321 to produce an island-shaped isolated element. Next, a wiring 350 was formed on the back surface of the support substrate 350 and the surface of the p-type layer 321 of the isolated element. Using this TEG 300, the insulating property of the n-type Si layer 321 was measured by applying a voltage from 0 V to 10 V to the front electrode with the back electrode set to 0 V (grounded) and measuring the value of the current flowing at that time. evaluated. Note that the lower limit of measurement is 1×10 ⁻¹⁰ (A/cm ² ) in the experimental apparatus used this time. The results are listed in Table 1 below. From this evaluation result, it was confirmed that the n-type Si layer functions as an insulating layer in Invention Examples 1-1 to 1-4, while the n-type Si layer in Comparative Examples 1-1 to 1-4 was found to be insufficient to function as an insulating layer.

[Experimental example 2]
(Invention Example 2-1)
An epitaxial silicon wafer according to Invention Example 2-1 was produced in the same manner as Invention Example 1-1 in Experimental Example 1.

(Invention Example 2-2)
While the FZ wafer was used in Invention Example 2-1, this was a p-type silicon wafer (thickness: 750 μm, dopant type: boron, carrier concentration: 1.3×10 ¹⁴ atoms/cm ³ ) obtained from MCZ single crystal. , resistivity: 100 Ω·cm, oxygen concentration: 3.0×10 ¹⁷ atoms/cm ³ ). .

(Invention Example 2-3)
Although the oxygen concentration of the p-type silicon wafer of Invention Example 2-2 was 3.0×10 ¹⁷ atoms/cm ³ , Invention Example 2- was changed to 5.0×10 ¹⁷ atoms/cm ³ . An epitaxial silicon wafer according to Invention Example 2-2 was produced under the same conditions as in Example 2.

(Comparative Example 2-1)
Although the oxygen concentration of the p-type silicon wafer of Invention Example 2-2 was 3.0×10 ¹⁷ atoms/cm ³ , Invention Example 2- was changed to 7.0×10 ¹⁷ atoms/cm ³ . An epitaxial silicon wafer according to Comparative Example 2-1 was produced under the same conditions as in 2.

(Comparative Example 2-2)
A silicon oxide film having a thickness of 5.0 μm was formed on the same FZ silicon wafer as used in Invention Example 2-1. Next, this was bonded to a p-type silicon wafer (dopant: boron, carrier concentration: 1.4×10 ¹⁶ atoms/cm ³ _, resistivity: 1 Ω·cm) through the silicon oxide film. Then, the p-type silicon wafer is ground and polished to form a p-type silicon single crystal layer having a thickness of 10.0 μm (for convenience of explanation, referred to as a p-type Si layer according to Invention Example 1-1, etc.). did. Thus, an SOI wafer according to Comparative Example 2-2 was produced.

(Evaluation 2-1: IV measurement test)
patterning an Al electrode on the p-type Si layer of each of the epitaxial silicon wafers according to Invention Examples 2-1, 2-2, 2-3 and Comparative Example 2-1 and the SOI wafer according to Comparative Example 2-2; A current flowing from the front surface (p-type Si layer) of the epitaxial silicon wafer to the back surface (back surface of the silicon wafer) was evaluated by IV measurement. Specifically, a voltage ranging from 0 V to 10 V was applied to the Al electrode while the back surface of the wafer was grounded, and the current flowing at that time was measured. The current that flows is the leakage current. Table 2 shows the measurement results.

(Evaluation 2-2: Resistance fluctuation evaluation)
Further, assuming a device manufacturing process, the epitaxial silicon wafers according to Invention Examples 2-1, 2-2, 2-3 and Comparative Example 2-1 and the SOI wafer according to Comparative Example 2-2 were heated to 450 ° C. , 10 hours of heat treatment was carried out under a nitrogen atmosphere. The resistivity of the back side of the silicon wafer before and after the heat treatment was evaluated by the 4-point needle method. The results are listed in Table 2.

※１：支持基板は発明例２－１と同様のＦＺウェーハである。比較例２－２はＳＯＩウェーハである。

*1: The support substrate is an FZ wafer similar to Invention Example 2-1. Comparative Example 2-2 is an SOI wafer.

From Evaluation 2-1 and Evaluation 2-2, the epitaxial silicon wafers according to Invention Examples 2-1, 2-2, 2-3 and Comparative Example 2-1 are all the same as the SOI wafer according to Comparative Example 2-2. It was confirmed that the leakage current was about the same. However, in Comparative Example 2-1 with a high oxygen concentration, it was confirmed that the resistance varied with the heat treatment.

[Experimental example 3]
In order to confirm the difference in thermal conductivity between the epitaxial wafer and the SOI wafer, the following experiment was conducted.

(Sample 1)
An n-type Si layer was formed on the surface of the FZ wafer under the same conditions as in Invention Example 2-1. No p-type Si layer was formed on the surface of the n-type Si layer.

(Sample 2)
A silicon oxide film was formed on the surface of the FZ wafer under the same conditions as in Comparative Example 2-2. No p-type Si layer was formed on the surface of the silicon oxide film.

(Evaluation 3: thermal conductivity)
The thermal conductivities of the wafers of Samples 1 and 2 were evaluated using a C-Thermtechnology TCi using a modified transient plane source method. The thermal conductivity of sample 2 is 40% of the thermal conductivity of sample 1, and it is confirmed that the silicon oxide film deteriorates the heat dissipation.

From Experimental Examples 1 to 3 above, it was confirmed that in the epitaxial silicon wafers satisfying the conditions of the present invention, the n-type Si layer functions as an insulating layer, and that the resistance does not change even after the heat treatment associated with the device fabrication process. rice field. Therefore, the epitaxial silicon wafer according to the present invention is suitable for X-ray detection sensors.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide an epitaxial silicon wafer suitable for an X-ray detection sensor and a method for producing the same. Furthermore, according to the present invention, an X-ray detection sensor using this epitaxial silicon wafer can be provided.

100 epitaxial silicon wafer 110 silicon wafer 120 silicon epitaxial layer 121 first silicon epitaxial layer 122 second silicon epitaxial layer 200 X-ray detection sensor 210 p-type silicon layer 214 high concentration n-type diffusion region 221 n-type silicon layer 222 p-type Silicon layer 224 n-type diffusion region 225 p-type diffusion region 250 conductor 300 TEG for withstand voltage measurement

Claims (7)

a silicon wafer;
a silicon epitaxial layer provided on the surface of the silicon wafer;
An epitaxial silicon wafer comprising
The silicon epitaxial layer comprises a first silicon epitaxial layer provided on the surface of the silicon wafer and a second silicon epitaxial layer provided on the surface thereof,
The silicon wafer is p-type, the first silicon epitaxial layer is n-type, the second silicon epitaxial layer is p-type, and the silicon wafer and the first and second silicon epitaxial layers are Each thickness and each carrier concentration of the following formulas (1) to (3):
d1>d3>d2 (1)
C3>C2>C1 (2)
C3·(d3/10)≧C2·d2 (3)
(In the above formulas (1) to (3), d1, d2 and d3 represent the thicknesses of the silicon wafer, the first silicon epitaxial layer and the second silicon epitaxial layer, respectively; C1, C2 and C3 are represents the carrier concentrations of the silicon wafer, the first silicon epitaxial layer and the second silicon epitaxial layer, respectively)
satisfies the
The silicon wafer has a resistivity of 100 Ω·cm or more and an oxygen concentration of 5.0 × 10 ¹⁷ atoms/cm ³ or less.
An epitaxial silicon wafer characterized by: 2. The epitaxial silicon wafer of claim 1, wherein said first silicon epitaxial layer is a depletion layer. 3. The epitaxial silicon wafer according to claim 1, wherein the thickness d1 of said silicon wafer is 100 [mu]m or more. The epitaxial silicon wafer according to any one of claims 1 to 3, wherein said silicon wafer is an FZ wafer or an MCZ wafer. The epitaxial silicon wafer according to any one of claims 1 to 4, wherein said silicon wafer does not contain COPs. The method for producing an epitaxial silicon wafer according to any one of claims 1 to 5,
forming the first silicon epitaxial layer on the surface of the silicon wafer;
forming the second silicon epitaxial layer on the surface of the first silicon epitaxial layer;
A method for producing an epitaxial silicon wafer, comprising: An X-ray detection sensor formed using the epitaxial silicon wafer according to any one of claims 1 to 5,
An X-ray detection unit is provided on the silicon wafer,
An X-ray detection sensor, wherein a MOS transistor section is provided in the second silicon epitaxial layer.

Images