JP2014130920A - Double-well structure soi radiation sensor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a double-well structure SOI radiation sensor in which a photo diode and a transistor are formed on the same semiconductor substrate via an insulating film and having small parasitic capacitance, and to provide a method of manufacturing the same.SOLUTION: A double-well structure SOI radiation sensor includes: a photo diode 30 having a semiconductor layer 11 of one conductivity type and a semiconductor region 232 of an opposite conductivity type provided in the semiconductor layer 11; a semiconductor layer 9 provided on the semiconductor layer and in which a transistor element 40 is formed; an insulating layer 10 between the semiconductor layer 9 and the semiconductor layer 11; a semiconductor region 114 of the one conductivity type provided in the semiconductor layer 11, having higher impurity concentration than the semiconductor layer 11, and to which a first fixed potential is provided; a semiconductor region 116 of the opposite conductivity type surrounding the semiconductor region 114, provided spaced apart from the semiconductor region 114, and to which a second fixed potential is provided; and a fourth semiconductor region 11 of the one conductivity type having lower impurity concentration than the semiconductor region 114 and located between the semiconductor region 114 and the third semiconductor region 116.

Description

  The present invention relates to a double well structure SOI radiation sensor and a method for manufacturing the same, and in particular, an X-ray (radiation) sensor in which a photodiode and a transistor for X-ray detection are mixed on the same SOI (Slicon On Insulator) substrate. And a manufacturing method thereof.

  Patent Documents 1 and 2 disclose a semiconductor device having a structure in which a sensor and a peripheral circuit are formed on the same semiconductor substrate via an insulating film.

JP 2009-170615 A JP 2008-130795 A

  In a semiconductor device having a structure in which a sensor and a peripheral circuit are formed on the same semiconductor substrate, an X-ray sensor having a structure in which a photodiode for X-ray detection and a transistor are formed on the same semiconductor substrate Uses a low-concentration, high-resistance semiconductor substrate on the semiconductor substrate on which an X-ray detection photodiode is formed, or a bias of several hundred volts is applied to the back surface of the semiconductor substrate in order to increase the detection sensitivity upon radiation incidence. The whole semiconductor substrate may be depleted by a method such as application.

  At this time, by using an SOI (Silicon On Insulator) substrate in which a buried oxide film is buried between the upper first semiconductor layer and the lower second semiconductor layer, the first semiconductor on the upper side of the buried oxide film is used. One layer is a high-concentration low-resistance substrate for forming an element such as a MOS transistor for circuit operation, and the second semiconductor layer under the buried oxide film is a low-concentration high-resistance substrate for forming a photodiode. An X-ray sensor including peripheral circuits can be configured on the wafer.

  However, the voltage applied to the back surface of the second semiconductor layer to deplete the second semiconductor layer is also transmitted to the first semiconductor layer formed on the buried oxide film via the buried oxide film. In the MOS transistor formed in the semiconductor layer, the channel region on the buried oxide film side operates as a current path due to the voltage transmitted from the second semiconductor layer separately from the current path controlled by the original gate electrode In addition, there is a problem that the channel region on the buried oxide film side operates as a current path because the buried oxide film is positively charged by X-ray irradiation.

  In order to solve these problems, as shown in FIG. 11, a P-type semiconductor region 232 serving as an anode electrode is provided on the surface (main surface) 151 of the high-resistance N-type second semiconductor layer 11, On the surface (main surface) 151 of the N-type second semiconductor layer 11 in a region 61 different from the region 51 in which the photodiode 30 is formed by the N-type second semiconductor layer 11 and the P-type semiconductor region 232, A P well 101 is provided, an N well 102 is provided in the P well 101, an active region 91 of the first semiconductor layer 9 is provided on the N well 102 via a buried oxide film 10, and a MOS is provided in the active region 91. The transistor 40 is provided, the P well 101 is connected to the GND 90 through a high concentration P type extraction region 111, and the N well 102 is high concentration N type extraction region 112. It is conceivable to connect structures to GND90 through. A high-concentration N-type extraction region 242 is provided on the surface (main surface) 151 of the high-resistance N-type second semiconductor layer 11, and this N-type extraction region 242 is provided on the positive electrode side of the power supply 28. The back surface (main surface) 152 of the high-resistance N-type second semiconductor layer 11 is also connected to the positive electrode side of the power supply 28. The P-type semiconductor region 232 is connected to the negative electrode side of the power supply 28 and to the GND 90.

  In this structure, an N well 102 is formed in the high-resistance N-type second semiconductor layer 11, so that the vicinity of the interface between the buried oxide film 10 and the N-type second semiconductor layer 11 by X-ray irradiation. Even when charges are accumulated in the surface, electrons which are majority carriers are accumulated on the surface of the N well 102, so that the depletion layer does not expand. The N well 102 is formed in the P well 101. That is, a P well 101 is formed so as to cover the N well 102, and a depletion layer is also formed between the N well 102 and the P type well 101 in order to fix the N well diffusion layer 102 and the P well 101 to the ground potential. Does not spread. Thus, when a high bias voltage is applied to the back surface 152 of the N-type second semiconductor layer 11 to deplete the N-type second semiconductor layer 11, the P-well 101 and the N-type second semiconductor layer 11 are depleted. Among the depletion layers extending to the PN junction surface between the two semiconductor layers 11, the depletion layer extending to the P well 101 side does not reach the junction surface with the N well 102. Regardless, the potential in the vicinity of the surface of the P well 101 is maintained at the ground potential. Accordingly, the voltage applied from the power supply 28 to the back surface 152 of the N-type first semiconductor layer 11 is not transmitted to the interface of the active region 91 of the first semiconductor layer 9 on the buried oxide film 10 side. Therefore, even when charges are accumulated near the interface between the buried oxide film 10 and the N-type second semiconductor layer 11 by X-ray irradiation, the charge is formed in the active region 91 of the first semiconductor layer 9. Since the channel region on the buried oxide film 10 side of the MOS transistor 40 does not operate, it is possible to suppress the occurrence of leakage current unrelated to the control by the gate electrode 20.

  However, this structure has a problem that the parasitic capacitance between the N well 102 and the P well 101 becomes large. This is because the N well 102 must have a higher concentration than the P well 101, and the P well 101 also has a certain concentration in order to keep the N well 102 / N type substrate 11 at different potentials. Therefore, it is necessary to maintain the breakdown voltage between the N well 102 and the N-type substrate 11, and it is difficult to reduce the concentration of both the N well 102 / P well 101. This is because the depletion layer width between them does not increase.

  A main object of the present invention is to provide a double well structure SOI radiation sensor in which a photodiode and a transistor are formed on the same semiconductor substrate through an insulating film and have a small parasitic capacitance, and a method for manufacturing the same.

According to the present invention,
A second semiconductor layer of one conductivity type and a first of an opposite conductivity type provided on one main surface of the first region of the second semiconductor layer and having a conductivity type opposite to the one conductivity type; A photodiode comprising a semiconductor region;
A first semiconductor layer provided on the one main surface of a second region different from the first region of the second semiconductor layer and having a transistor element formed thereon;
An insulating layer provided between the first semiconductor layer and the second semiconductor layer;
The second semiconductor layer is provided on the one main surface of the second region of the second semiconductor layer, is of the one conductivity type, has a higher impurity concentration than the second semiconductor layer, and is supplied with a first fixed potential. A semiconductor region of
A third semiconductor region that surrounds the second semiconductor region and is provided in the second semiconductor layer apart from the second semiconductor region, is of the opposite conductivity type, and is supplied with a second fixed potential When,
A fourth semiconductor region between the second semiconductor region and the third semiconductor region, the first conductivity type having a lower impurity concentration than the second semiconductor region;
A double well structure SOI radiation sensor is provided.

Moreover, according to the present invention,
A second semiconductor layer of one conductivity type, an insulating layer on one main surface of the second semiconductor layer, and an active region having a first semiconductor layer selectively provided on the insulating layer, Preparing a laminate comprising:
Forming a transistor element in the active region;
Forming a first semiconductor region having a conductivity type opposite to the one conductivity type on the one main surface of the second semiconductor layer;
Alignment is performed using the active region, and a second semiconductor region of the one conductivity type and having a higher impurity concentration than the second semiconductor layer is formed on the one main surface of the second semiconductor layer. Introducing a first impurity for performing,
Alignment is performed using the active region, and the second semiconductor layer surrounds the second semiconductor region and is spaced apart from the second semiconductor region. Introducing a second impurity for forming a semiconductor region;
A method of manufacturing a double well structure SOI radiation sensor comprising:

  According to the present invention, there are provided a double well structure SOI radiation sensor in which a photodiode and a transistor are formed on the same semiconductor substrate through an insulating film and have a small parasitic capacitance, and a method for manufacturing the same.

FIG. 1 is a schematic longitudinal sectional view for explaining a double well structure SOI radiation sensor according to a preferred embodiment of the present invention. FIG. 2 is a schematic longitudinal sectional view for explaining a method for manufacturing a double well structure SOI radiation sensor according to a preferred embodiment of the present invention. FIG. 3 is a schematic longitudinal sectional view for explaining a method of manufacturing a double well structure SOI radiation sensor according to a preferred embodiment of the present invention. FIG. 4 is a schematic longitudinal sectional view for explaining a method for manufacturing a double well structure SOI radiation sensor according to a preferred embodiment of the present invention. FIG. 5 is a schematic longitudinal sectional view for explaining a method for manufacturing a double well structure SOI radiation sensor according to a preferred embodiment of the present invention. FIG. 6 is a schematic longitudinal sectional view for explaining the method for manufacturing the double well structure SOI radiation sensor according to the preferred embodiment of the present invention. FIG. 7 is a schematic longitudinal sectional view for explaining a method for manufacturing a double well structure SOI radiation sensor according to a preferred embodiment of the present invention. FIG. 8 is a schematic longitudinal sectional view for explaining the method for manufacturing the double well structure SOI radiation sensor according to the preferred embodiment of the present invention. FIG. 9 is a schematic longitudinal sectional view for explaining a method for manufacturing a double well structure SOI radiation sensor according to a preferred embodiment of the present invention. FIG. 10 is a schematic longitudinal sectional view for explaining the method for manufacturing the double well structure SOI radiation sensor according to the preferred embodiment of the present invention. FIG. 11 is a schematic longitudinal sectional view for explaining a related semiconductor device.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  Referring to FIG. 1, a double well structure SOI radiation sensor 100 according to a preferred embodiment of the present invention includes a first semiconductor layer 9 in which a peripheral circuit MOS transistor 40 is formed, and a second semiconductor layer 11. And a semiconductor region 232, and a buried oxide film 10 between the first semiconductor layer 9 and the second semiconductor layer 11.

  The first semiconductor layer 9 is a P-type semiconductor substrate, and the second semiconductor layer 11 is an N-type semiconductor substrate. A P-type semiconductor region 232 is provided on the main surface 151 of the region 51 of the second semiconductor layer 11. An X-ray photodiode 30 is formed by the P-type semiconductor region 232 and the N-type second semiconductor layer 11. Note that a high-concentration N-type extraction region 242 is provided in the region 51 of the main surface 151 of the second semiconductor layer 11. An electrode 280 is provided on the main surface 152 opposite to the main surface 151 of the second semiconductor layer 15. The active region 91 of the first semiconductor layer 9 in which the MOS transistor 40 is formed is provided on the main surface 151 of the region 61 different from the region 51 of the second semiconductor layer 11.

  An N well 114 is provided on the main surface 151 side of the region 61 of the second semiconductor layer 11. The N well 114 has a higher impurity concentration than the N-type second semiconductor layer 11. A high concentration N-type extraction region 241 is provided on the main surface 151 side of the N well 114.

  P wells 116, 118, and 119 are provided in the second semiconductor layer 11 so as to surround the N well 114 and be separated from the N well 114. The P wells 118 and 119 are provided by connecting the P well 116 and the surface (main surface 151) of the second semiconductor layer 11. The P well 119 is provided on the P well 116 side, and the P well 118 is provided on the surface (main surface 151) side of the second semiconductor layer 11. Note that a high concentration P-type extraction region 231 is provided on the main surface 151 side of the P well 118. The second semiconductor layer 11 exists between the N well 114 and the P wells 116, 118, and 119.

  An interlayer film 25 is provided on the active region 91 of the first semiconductor layer 9 in which the MOS transistor 40 is formed. Via the buried oxide film 10 and the interlayer film 25, the extraction electrode 261 connected to the P-type extraction region 231, the extraction electrode 264 connected to the N-type extraction region 241, and the P-type semiconductor region 232 are connected. An extraction electrode 265 connected to the extraction electrode 265 and the N-type extraction region 231 is provided. Extraction electrodes 262 and 263 connected to the source and drain of the MOS transistor 40 via the interlayer film 25 are provided.

  The N-type second semiconductor layer 11 includes an electrode 280 provided on the main surface 152 of the second semiconductor layer 11 and a high-concentration N-type extraction region provided on the main surface 151 of the second semiconductor layer 11. It is connected to the positive electrode side of the power supply 28 through a take-out electrode 266 connected to 242. The P-type semiconductor region 232 provided on the main surface 151 of the second semiconductor layer 11 is connected to the negative electrode side of the power supply 28 and the GND 90 via the extraction electrode 265.

  In order to deplete the N-type second semiconductor layer 11 constituting the photodiode 30 for X-rays, the back surface (main surface 152) of the second semiconductor layer 11 and the high-concentration N-type extraction region 242 (cathode) A positive high voltage of about 100 to 300 V is applied to the electrode) from the power source 28. At this time, the P well 116 is grounded to the GND 90 via the extraction electrode 261. Further, the N well 114 is grounded to the GND 90 via the extraction electrode 264. Alternatively, a positive voltage up to 5V may be applied to the N well 114. In this embodiment, for example, 1.5 V is applied.

  Since the N-type second semiconductor layer 11 with a low impurity concentration exists between the N well 114 and the P well 116, a depletion layer to some extent spreads. When a high voltage is applied to the back surface (main surface 152) of the second semiconductor layer 11 to deplete the second semiconductor layer 11, the P well 116, the P wells 118 and 119, and the second semiconductor layer 11 are depleted. Of the depletion layers spreading to the PN junction between the layers 11, if the depletion layer spreading to the P well 116, P well 118, 119 side does not reach the junction with the N well 114, the amount of charge accumulated by X-ray irradiation is increased. Regardless, the potential in the vicinity of the surface of the N well 114 is kept at GND or a potential up to 5 V, and the second semiconductor layer 11 is also present at the interface of the active region 91 of the first semiconductor layer 9 on the buried oxide film 10 side. The voltage applied to the back side of is not transmitted.

  As described above, according to the present embodiment, the breakdown voltage between the N well 114 and the N-type second semiconductor layer 11 is kept sufficiently high, and between the P wells 116, 118, and 119 and the N well 114. Since the depletion layer width can be increased, the parasitic capacitance can be reduced.

  In the present embodiment, the N-type low impurity concentration second semiconductor layer 11 exists between the N well 114 and the P wells 116, 118, and 119, but the second semiconductor layer 11 If the semiconductor region is N-type and has a lower impurity concentration than the N-well 114, the depletion layer width of the N-well 114 and the P-wells 116, 118, and 119 can be increased, thereby reducing the parasitic capacitance. Can do. Further, the semiconductor region existing between the N well 114 and the P wells 116, 118, and 119 extends to the PN junction between the P well 116, the P wells 118 and 119, and the second semiconductor layer 11 depending on the concentration. Of the depletion layers, if the depletion layer extending to the P well 116, P well 118, 119 side has a thickness that does not reach the junction with the N well 114, N The potential in the vicinity of the surface of the well 114 is kept at a predetermined potential of GND or 5 V, and the second semiconductor layer 11 is also present at the interface of the active region 91 of the first semiconductor layer 9 on the buried oxide film 10 side. The voltage applied to the back side is not transmitted.

  Next, a manufacturing method of the double well structure SOI radiation sensor 100 according to a preferred embodiment of the present invention will be described.

  First, as shown in FIG. 2, a first semiconductor layer 9 having a thickness of about 880 mm on the upper side with a buried oxide film 10 having a thickness of about 2000 mm and a second semiconductor having a thickness of about 700 μm on the lower side. An SOI (Silicon On Insulator) substrate having the layer 11 is used. At this time, for example, the first semiconductor layer 9 is a P-type substrate having a specific resistance of 10 Ω · cm, and the second semiconductor layer 11 is an SOI substrate formed of an N-type substrate having a specific resistance of 10 kΩ · cm.

  A pad oxide film (not shown) and a nitride film (not shown) are formed on this surface, and after removing the nitride film in the region where the field oxide film is to be formed, the field oxide film is formed by the LOCOS formation method. As shown in FIG. 3, all nitride films and pad oxide films are removed. As a result, active regions 91 and 92 are formed in the first semiconductor layer 9.

Further, a gate oxide film 12 is formed on the surfaces of the active regions 91 and 92 of the first semiconductor layer 9, and as shown in FIG. 4, an N well 114 to be formed in the second semiconductor layer 11 (see FIG. 1). A region other than the region where the first semiconductor layer 9 is formed is covered with a photoresist 13 which is aligned with the active region 91 formed in the first semiconductor layer 9. For example, the implantation energy is 300 keV and the dose is 1.0 × 10 ¹² to 1. 31P ⁺ impurities 14 of about 0 × 10 ¹³ cm ⁻² are implanted at a tilt angle of 0 degree.

Thereafter, after removing the photoresist 13, a place other than the formation region of the P well 116 (see FIG. 1) set larger than the region into which the impurity 14 has been implanted is disposed in the first semiconductor layer 9 as shown in FIG. The active region 91 formed in (1) is covered with a photoresist 15 that has been aligned. In the implantation of the impurity 16 for forming the P well 116 (see FIG. 1), for example, the implantation energy is 500 keV and the dose amount is 1.0 × so as to be deeper than the impurity 14 for forming the N well 114 (see FIG. 1). An 11B ⁺ impurity 16 of about 10 ^{12 to} 1.0 × 10 ¹³ cm ⁻² is implanted at a tilt angle of 0 degree.

Further, after the photoresist 15 is removed, the formation region of the N well 114 (see FIG. 1) is surrounded, and from the formation region of the P well 116 (see FIG. 1) to the surface (main surface) 151 of the second semiconductor layer 11. As shown in FIG. 6, a photo of alignment of the active region 91 formed in the first semiconductor layer 9 with a place other than the P wells 118 and 119 (see FIG. 1) is connected. Covered with a resist 17, for example, an implantation energy of 100 keV, a dose amount of about 1.0 × 10 ^{12 to} 1.0E × 10 ¹³ cm ⁻² of 11B ⁺ impurities 18, an implantation energy of 220 keV, and a dose amount of 1.0 × 10 ¹² to An 11B ⁺ impurity 19 of about 1.0 × 10 ¹³ cm ⁻² is implanted at a tilt angle of 0 degree.

  After removing the photoresist 17, a polysilicon film is deposited, and the polysilicon film patterned with the photoresist (not shown) is dry-etched to form the gate electrode 20 as shown in FIG. . In this polysilicon film deposition process or the like, the impurities 14, 16, 18, and 19 are activated to become an N well 114, a P well 116, and a P well 118, 119, respectively.

  Thereafter, after the photoresist is removed, LDD (not shown) is ion-implanted into the active region 91 of the first semiconductor layer 9 to form sidewall spacers 22 as shown in FIG. A source / drain 21 ion implantation step is performed and activated to form the MOS transistor 40.

Thereafter, the portions other than the N-type / P-type extraction regions to be formed in the second semiconductor layer 11 are covered with a photoresist, and the photoresist is removed after the buried oxide film 10 is etched as shown in FIG. For the formation of the N-type extraction region 241 that also serves as the cathode of the diode and the N-type extraction region 242 of the N-well, for example, an impurity with an implantation energy of 60 keV and a dose of about 5.0 × 10 ¹⁵ cm ⁻² 31P ⁺ is used for forming a P-type semiconductor region 232 that also serves as an anode of a diode and a P-type extraction region 241 of the P-well 118, for example, an implantation energy of 40 keV and a dose of 5.0 × 10 ¹⁵ cm ^−2. Impurity 11B ⁺ is implanted.

  Thereafter, an interlayer film 25 is formed by deposition of a CVD film as shown in FIG.

  Thereafter, as shown in FIG. 10, contact holes are formed by etching the locations where the extraction electrodes of the first semiconductor layer 91 and the second semiconductor layer 11 are to be formed. Thereafter, portions of the metal layer formed by sputtering other than the electrode formation region are etched to form extraction electrodes 261, 262, 263, 264, 265, and 266.

  In this embodiment, the N well 114, the P well 116, and the P wells 118 and 119 are formed after forming the active region 91 in the first semiconductor layer 9, so that before the impurity implantation for forming each well. In the photolithography process, the alignment of the photolithography can be performed using the active region 91. Also, a polysilicon film deposition process for forming the gate electrode of the MOS transistor 40 by forming the MOS transistor 40 in the active region 91 of the first semiconductor layer 9 after impurity implantation for forming each well, etc. In this case, a sufficient heat treatment can be applied to each well.

  As described above, according to the present embodiment, the N well 114, the P well 116, and the P wells 118 and 119 are formed in the active region 91 formed in the first semiconductor layer 9 with a minimum photolithography misalignment amount. The N well 114, the P well 116, and the P wells 118 and 119 can be formed to a deeper position by forming and further applying a lot of heat treatment after each well implantation.

  In the above embodiment, the case where the second semiconductor layer 11 is an N-type substrate has been described. However, the second semiconductor layer 11 can also be applied to a P-type double well structure SOI radiation sensor. In this case, for other regions, the P type is the N type, and the P type is the N type.

  While various typical embodiments of the present invention have been described above, the present invention is not limited to these embodiments. Accordingly, the scope of the invention is limited only by the following claims.

9 First semiconductor layer 10 Buried oxide film 11 Second semiconductor layer 25 Interlayer film 28 Power supply 30 Photodiode 40 MOS transistors 51 and 61 Region 90 GND
91 Active region 100 Double well structure SOI radiation sensor 114 N well 116, 118, 119 P well 151, 152 Main surface 231, 241, 242 Extraction region 232 Semiconductor region 261, 262, 263, 264, 265, 266 Extraction electrode 280 electrode

Claims (7)

A second semiconductor layer of one conductivity type and a first of an opposite conductivity type provided on one main surface of the first region of the second semiconductor layer and having a conductivity type opposite to the one conductivity type; A photodiode comprising a semiconductor region;
A first semiconductor layer provided on the one main surface of a second region different from the first region of the second semiconductor layer and having a transistor element formed thereon;
An insulating layer provided between the first semiconductor layer and the second semiconductor layer;
The second semiconductor layer is provided on the one main surface of the second region of the second semiconductor layer, is of the one conductivity type, has a higher impurity concentration than the second semiconductor layer, and is supplied with a first fixed potential. A semiconductor region of
A third semiconductor region that surrounds the second semiconductor region and is provided in the second semiconductor layer apart from the second semiconductor region, is of the opposite conductivity type, and is supplied with a second fixed potential When,
A fourth semiconductor region between the second semiconductor region and the third semiconductor region, the first conductivity type having a lower impurity concentration than the second semiconductor region;
A double well structure SOI radiation sensor.   2. The double well structure SOI radiation sensor according to claim 1, wherein the first fixed potential is a predetermined potential between a ground potential and 5 V, and the second fixed potential is a ground potential.   3. The double well structure SOI radiation sensor according to claim 2, wherein the one conductivity type is an N type and the opposite conductivity type is a P type.   The distance between the second semiconductor region and the third semiconductor region is such that a reverse voltage for operating the photodiode is applied between the second semiconductor layer and the first semiconductor region. In this case, a depletion layer extending to the third semiconductor region among the depletion layers extending to the PN junction between the third semiconductor region and the second semiconductor layer does not reach the second semiconductor region. The double well structure SOI radiation sensor according to any one of claims 1 to 3, which is a distance.   The double well structure SOI radiation sensor according to any one of claims 1 to 4, wherein the photodiode is a photodiode for X-ray detection. A second semiconductor layer of one conductivity type, an insulating layer on one main surface of the second semiconductor layer, and an active region having a first semiconductor layer selectively provided on the insulating layer, Preparing a laminate comprising:
Forming a transistor element in the active region;
Forming a first semiconductor region having a conductivity type opposite to the one conductivity type on the one main surface of the second semiconductor layer;
Alignment is performed using the active region, and a second semiconductor region of the one conductivity type and having a higher impurity concentration than the second semiconductor layer is formed on the one main surface of the second semiconductor layer. Introducing a first impurity for performing,
Alignment is performed using the active region, and the second semiconductor layer surrounds the second semiconductor region and is spaced apart from the second semiconductor region. Introducing a second impurity for forming a semiconductor region;
A manufacturing method of a double well structure SOI radiation sensor comprising:   7. The method of manufacturing a double well structure SOI radiation sensor according to claim 6, wherein the step of forming a transistor element in the active region is performed after the step of introducing the first impurity and the step of introducing the second impurity. .

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