JP7192683B2 - Method for sorting silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a method for sorting silicon carbide semiconductor devices.

Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. There are multiple types of power semiconductor devices, including bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). It is

For example, bipolar transistors and IGBTs have higher current densities than MOSFETs and can handle large currents, but cannot be switched at high speed. Specifically, bipolar transistors are limited to use at a switching frequency of about several kHz, and IGBTs are limited to use at a switching frequency of about several tens of kHz. On the other hand, a power MOSFET has a lower current density than a bipolar transistor or an IGBT, making it difficult to increase the current, but it is capable of high-speed switching operation up to several MHz.

However, there is a strong demand in the market for power semiconductor devices that combine large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs. . From the viewpoint of power semiconductor devices, semiconductor materials that can replace silicon are being investigated, and silicon carbide (SiC) is a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. is attracting attention.

The background is as follows. SiC is a chemically very stable material, has a wide bandgap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Also, the maximum electric field strength is one order of magnitude higher than that of silicon. Since SiC has a high possibility of exceeding the material limit of silicon, future growth is greatly expected for power semiconductor applications, especially for MOSFETs. In particular, its on-resistance is expected to be small, and a vertical SiC-MOSFET having even lower on-resistance while maintaining high breakdown voltage characteristics can be expected.

The structure of a conventional silicon carbide semiconductor device will be described using a vertical MOSFET as an example. FIG. 14 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 14, n type silicon carbide epitaxial layer 102 is deposited on the front surface of n ⁺ type silicon carbide substrate 101 , and p ⁺ type base region 103 is formed on the surface of n type silicon carbide epitaxial layer 102 . A p-type base layer 104 is selectively provided in the surface of n-type silicon carbide epitaxial layer 102 . Also, an n ⁺ -type source region 105 , a p ⁺ -type contact region 106 and an n-type well region 107 are selectively provided in the surface of the p-type base layer 104 .

A gate electrode 109 is provided on the surface of p-type base layer 104 and n ⁺ -type source region 105 with gate insulating film 108 interposed therebetween. A source electrode 110 is provided on the surfaces of the p ⁺ -type contact region 106 and the n ⁺ -type source region 105 . A drain electrode 111 is provided on the back surface of the n ⁺ -type silicon carbide substrate 101 .

A vertical MOSFET having such a structure incorporates a parasitic pn diode formed by p ⁺ -type base region 103 and n-type silicon carbide epitaxial layer 102 as a body diode between source and drain. This parasitic pn diode can be operated by applying a high potential to the source electrode 110, and current flows in the direction indicated by arrow A in FIG. Thus, unlike IGBTs, MOSFETs incorporate a parasitic pn diode, so a free wheeling diode (FWD) used in an inverter can be omitted, contributing to cost reduction and miniaturization. Hereinafter, the parasitic pn diode of the MOSFET will be referred to as the built-in diode.

A method of sorting silicon carbide MOSFETs using this built-in diode is known. For example, the temperature of the silicon carbide semiconductor device is set to 235° C. or more and 300° C. or less, a forward current with a frequency of 10 kHz or more and 100 kHz or less is passed, and silicon carbide semiconductor devices having a forward voltage change rate of less than 3% are selected. (See, for example, Patent Document 1). Thereby, it is possible to screen a silicon carbide semiconductor device that does not deteriorate in reliability even when it is used in an inverter circuit at high temperature for a long time.

JP 2018-205251 A

However, the conventional silicon carbide MOSFET selection method does not select silicon carbide semiconductor devices that can be driven at a specific frequency. Since silicon carbide semiconductor devices are sorted by passing a forward current of a predetermined frequency, silicon carbide semiconductor devices that normally operate at a frequency higher than the predetermined frequency are not sorted out. Further, even a silicon carbide semiconductor device that has been screened as a non-conforming product at a predetermined frequency may operate normally at a frequency lower than the predetermined frequency. not selected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for selecting silicon carbide semiconductor devices capable of selecting silicon carbide semiconductor devices that can be driven at a specific frequency, in order to solve the above-described problems of the prior art.

In order to solve the above problems and achieve the object of the present invention, a method for sorting silicon carbide semiconductor devices according to the present invention has the following features. A selection method for silicon carbide semiconductor devices having built-in diodes. First, a first step of passing a forward current of a predetermined frequency through the built-in diode of the silicon carbide semiconductor device is performed. Next, for a period of time shorter than the time during which the forward current is in the on state during one cycle of the predetermined frequency, the carbonization is performed such that a maximum value occurs in the curve of time vs. voltage when the forward current increases. A second step of sorting silicon semiconductor devices is performed.

Further, a method for selecting a silicon carbide semiconductor device according to the present invention is, in the invention described above, a third step of increasing the predetermined frequency; and a fourth step of selecting the silicon carbide semiconductor device in which the curve of time versus voltage has a maximum value during the short period of time when the forward current increases.

Further, in the method for selecting a silicon carbide semiconductor device according to the present invention, in the invention described above, the silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a silicon carbide semiconductor substrate. , a second semiconductor layer of a second conductivity type provided on the side opposite to the silicon carbide semiconductor substrate side of the first semiconductor layer, and selectively provided on a surface layer of the second semiconductor layer, a first conductivity type first semiconductor region having an impurity concentration higher than that of the silicon carbide semiconductor substrate; a gate insulating film in contact with the second semiconductor layer; and a surface of the gate insulating film in contact with the second semiconductor layer. a gate electrode provided on the opposite surface, a first electrode provided on the surfaces of the first semiconductor region and the second semiconductor layer, and a second electrode provided on the back surface of the silicon carbide semiconductor substrate; characterized by comprising

Further, in the method for selecting a silicon carbide semiconductor device according to the present invention, in the above-described invention, the silicon carbide semiconductor device further includes a trench penetrating the second semiconductor layer and reaching the first semiconductor layer, A gate electrode is provided inside the trench via the gate insulating film.

Further, according to the method for selecting a silicon carbide semiconductor device according to the present invention, in the invention described above, the silicon carbide semiconductor device has a withstand voltage of 3300 V or higher.

According to the above-described invention, a current of a predetermined frequency is applied to the silicon carbide semiconductor device, and the silicon carbide semiconductor device determines whether or not a maximum value occurs in the time-voltage curve during a short period of time when the current increases. Selecting equipment. Thereby, silicon carbide semiconductor devices that can be driven at a specific switching frequency can be selected, and silicon carbide semiconductor devices that can be driven at a high frequency can be selected.

According to the method for selecting silicon carbide semiconductor devices according to the present invention, it is possible to select silicon carbide semiconductor devices that can be driven at a specific frequency.

4 is a flow chart showing a method for sorting silicon carbide semiconductor devices according to an embodiment. 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment; FIG. 4 is a graph showing frequency dependence of forward voltage of a built-in diode of the silicon carbide semiconductor device according to the embodiment; 5 is a graph showing the relationship between time, current, and voltage when a current with a frequency of 1 kHz is applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment; 5 is a graph showing the relationship between time, current, and voltage when a current with a frequency of 100 kHz is applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment; 5 is a graph showing the relationship between time and current when currents of multiple frequencies are applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment. 5 is a graph showing the relationship between time and voltage when currents of a plurality of frequencies are applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment; 1 is a cross-sectional view showing a state in the middle of manufacturing a silicon carbide semiconductor device according to an embodiment (No. 1); FIG. It is a sectional view showing a state in the middle of manufacture of a silicon carbide semiconductor device concerning an embodiment (part 2). 3 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 3); FIG. FIG. 13 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 4); FIG. 11 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 5); FIG. 11 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 6); It is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

Preferred embodiments of a method for sorting silicon carbide semiconductor devices according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.

(Embodiment)
FIG. 1 is a flowchart showing a method for sorting silicon carbide semiconductor devices according to an embodiment. Although a MOSFET will be described below as an example of a silicon carbide semiconductor device, the same applies to other silicon carbide semiconductor devices having a MOS gate structure. First, a silicon carbide semiconductor device according to an embodiment will be described. FIG. 2 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment.

The semiconductor device 20 is a vertical MOSFET provided with a MOS gate (insulated gate having a three-layer structure of metal-oxide film-semiconductor) on the front surface side of the semiconductor substrate 10 . Here, a case where the semiconductor device 20 has the same wiring structure using pin-shaped wiring members (terminal pins 48a to be described later) will be described as an example, but wires are used instead of the pin-shaped wiring members. It may have a wiring structure.

Semiconductor substrate 10 includes n ⁻ -type drift region (first conductivity type first semiconductor layer) 32 and p-type base region (second conductivity type) formed on n ⁺ -type starting substrate (silicon carbide semiconductor substrate) 31 made of silicon carbide. (second semiconductor layer) 34a in which silicon carbide layers 71 and 72 are sequentially epitaxially grown. The semiconductor device 20 includes a p-type base region 34a provided on the front surface side of the semiconductor substrate 10, an n ⁺ -type source region (first conductivity type first semiconductor region) 35a, a p ⁺⁺ -type contact region 36a, It has a general MOS gate composed of a trench 37a, a gate insulating film 38a and a gate electrode 39a.

Trench 37 a penetrates p-type silicon carbide layer 72 in depth direction Z from the front surface of semiconductor substrate 10 (the surface of p-type silicon carbide layer 72 ) and reaches n ⁻ -type silicon carbide layer 71 . The trenches 37 a are arranged, for example, in stripes extending in a direction parallel to the front surface of the semiconductor substrate 10 .

A gate electrode 39a is provided inside the trench 37a via a gate insulating film 38a. A p-type base region 34a, an n ⁺ -type source region 35a and a p ⁺⁺ -type contact region 36a are selected in the front surface region of the semiconductor substrate 10 between two trenches 37a (mesa regions) adjacent to each other. is provided The n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 36a are provided between the front surface of the semiconductor substrate 10 and the p-type base region 34a.

The n ⁺ -type source region 35a is provided closer to the trench 37a than the p ⁺⁺ -type contact region 36a. The p ⁺⁺ type contact region 36a may not be provided. If the p ⁺⁺ -type contact region 36a is not provided, the p-type base region 34a reaches the front surface of the semiconductor substrate 10 at a location farther from the trench 37a than the n ⁺ -type source region 35a. exposed on the front of the

Inside the semiconductor substrate 10, an n ⁻ -type drift region 32 is provided in contact with the p-type base region 34a at a position closer to the n ⁺ -type drain region (n ⁺ -type starting substrate 31) than the p-type base region 34a. ing. An n-type current diffusion region 33a may be provided between the p-type base region 34a and the n ⁻ -type drift region 32 and in contact with these regions. The n-type current spreading region 33a is a so-called current spreading layer (CSL) that reduces spreading resistance of carriers.

Further, inside the semiconductor substrate 10, a second p ⁺ -type region 61a and a first p ⁺ -type region 62a are provided at positions closer to the n ⁺ -type drain region than the p-type base region 34a. The second p ⁺ -type region 61a is provided apart from the p-type base region 34a and faces the bottom surface of the trench 37a in the depth direction Z. As shown in FIG. A portion of the second p ⁺ -type region 61a is connected to the first p ⁺ -type region 62a.

The first p ⁺ -type region 62a is provided in the mesa region apart from the second p ⁺ -type region 61a and the trench 37a, and is in contact with the p-type base region 34a. The first and second p ⁺ -type regions 62a and 61a are fixed to the source potential of the semiconductor device 20 via the p-type base region 34a. The first and second p ⁺ -type regions 62a and 61a have the function of relaxing the electric field applied to the bottom surface of the trench 37a.

The interlayer insulating film 40 is provided over the entire front surface of the semiconductor substrate 10 and covers the gate electrode 39a. All the gate electrodes 39a of the semiconductor device 20 are electrically connected to gate pads (not shown) via gate runners (not shown) at portions not shown. The gate runner is provided on the front surface of the semiconductor substrate 10 via a field insulating film (not shown) in the edge termination region that surrounds the active region through which current flows when ON and maintains the breakdown voltage. It is a gate polysilicon layer surrounding the periphery in a substantially rectangular shape. The withstand voltage is the limit voltage at which the element does not malfunction or break down.

The n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 36a of the semiconductor device 20 are exposed in the first contact hole 40a that penetrates the interlayer insulating film 40 in the depth direction Z and reaches the semiconductor substrate 10 . A nickel silicide (NiSi, Ni ₂ Si or thermally stable NiSi ₂ : hereinafter collectively referred to as NiSi) film 41a is provided on the front surface of the semiconductor substrate 10 inside the first contact hole 40a. ing.

The NiSi film 41a is in ohmic contact with the semiconductor substrate 10 inside the first contact hole 40a and is electrically connected to the n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 36a. If the p ⁺⁺ -type contact region 36a is not provided, instead of the p ⁺⁺ -type contact region 36a, the p-type base region 34a is exposed through the first contact hole 40a and electrically connected to the NiSi film 41a. be done.

A barrier metal 46a is provided over the entire surfaces of the interlayer insulating film 40 and the NiSi film 41a. The barrier metal 46a has a function of preventing mutual reaction between respective metal films of the barrier metal 46a or between opposing regions with the barrier metal 46a interposed therebetween. The barrier metal 46a may have a laminated structure in which, for example, a first titanium nitride (TiN) film 42a, a first titanium (Ti) film 43a, a second TiN film 44a and a second Ti film 45a are laminated in this order.

The first TiN film 42 a is provided only on the surface of the interlayer insulating film 40 and covers the entire surface of the interlayer insulating film 40 . The first Ti film 43a is provided on the surfaces of the first TiN film 42a and the NiSi film 41a. The second TiN film 44a is provided on the surface of the first Ti film 43a. The second Ti film 45a is provided on the surface of the second TiN film 44a.

The source pad 21a is embedded in the first contact hole 40a and provided over the entire surface of the second Ti film 45a. Source pad 21 a is electrically connected to n ⁺ -type source region 35 a and p-type base region 34 a through barrier metal 46 a and NiSi film 41 a and functions as a source electrode of semiconductor device 20 . The source pad 21a is, for example, an aluminum (Al) film or Al alloy film having a thickness of approximately 5 μm.

Specifically, when the source pad 21a is an Al alloy film, the source pad 21a may be, for example, an aluminum-silicon (Al--Si) film containing about 5% or less of silicon in its entirety. It may be an aluminum-silicon-copper (Al-Si-Cu) film containing about 5% or less of the whole and copper (Cu) of about 5% or less of the whole, or an aluminum-silicon containing about 5% or less of the whole copper (Cu). A copper (Al—Cu) film may be used.

One end of a terminal pin 48a is joined onto the source pad 21a via a plating film 47a and a solder layer (not shown). The other end of the terminal pin 48 a is joined to a metal bar (not shown) arranged to face the front surface of the semiconductor substrate 10 . The other end of the terminal pin 48a is exposed outside the case (not shown) in which the semiconductor substrate 10 is mounted, and is electrically connected to an external device (not shown). The terminal pin 48a is a rod-shaped (cylindrical) wiring member having a predetermined diameter.

The terminal pin 48a is soldered to the plated film 47a while standing substantially perpendicular to the front surface of the semiconductor substrate 10. As shown in FIG. The terminal pin 48a is an external connection terminal for extracting the potential of the source pad 21a to the outside, and is connected to an external ground potential (lowest potential). A portion of the surface of the source pad 21a other than the plated film 47a is covered with a first protective film 49a, and the boundary between the plated film 47a and the first protective film 49a is covered with a second protective film 50a. The first and second protective films 49a and 50a are polyimide films, for example.

The drain electrode 51 is in ohmic contact with the entire back surface of the semiconductor substrate 10 (the back surface of the n ⁺ -type starting substrate 31). A drain pad (electrode pad: not shown) is provided on the drain electrode 51 with a laminated structure in which, for example, a Ti film, a nickel (Ni) film and a gold (Au) film are laminated in this order. The drain pad is soldered to a metal base plate (not shown) and at least partially contacts the base portion of the cooling fin (not shown) through the metal base plate.

Returning to FIG. 1, in the method for selecting silicon carbide semiconductor devices, first, the frequency of the current to be applied to the silicon carbide semiconductor devices is set (step S1). For example, the lowest switching frequency at which the silicon carbide semiconductor device is used is set as the frequency of the current to be applied. Moreover, the current applied to the silicon carbide semiconductor device may be a triangular wave in which the current gradually rises or a rectangular wave in which the current rises abruptly.

Next, a forward current is applied to the built-in diode of the MOSFET (step S2). Specifically, the gate electrode 39a and the source electrode (source pad 21a) of the MOSFET are short-circuited, a positive voltage is applied to the source electrode, and the potential of the drain electrode 51 is set to 0, so that the built-in diode 16a (FIG. 2 ) is energized.

Here, FIG. 3 is a graph showing frequency dependence of the forward voltage of the built-in diode of the silicon carbide semiconductor device according to the embodiment. In FIG. 3, the horizontal axis represents the thickness of the n ⁻ -type silicon carbide layer 71, which is n-type epitaxial, in units of μm. The vertical axis represents the forward voltage Vf of the built-in diode 16a in units of V. As shown in FIG.

The forward voltage Vf of the built-in diode 16a of the silicon carbide semiconductor device is about 3 V, but as shown in FIG. 3, the thicker the n ⁻ -type silicon carbide layer 71, that is, the higher the breakdown voltage, the higher the forward voltage Vf. Become. Further, the higher the frequency of the forward current flowing through the built-in diode, the higher the forward voltage Vf.

When the frequency of the forward current increases, a time delay occurs in the conductivity modulation inside the n ⁻ -type silicon carbide layer 71, and the conductivity modulation tends to become non-uniform. Therefore, the higher the frequency of the forward current, the higher the forward voltage Vf. In addition, the thicker the n ^{− -type} silicon carbide layer 71, the more likely it is that crystal defects will occur latently inside the layer. The thicker the silicon layer 71, the higher the forward voltage Vf.

FIG. 3 shows the measurement result of the forward voltage Vf after applying the forward current for a long time. After applying the forward current for a long time, the forward voltage Vf increases, but the built-in diode 16a does not operate normally. However, the silicon carbide semiconductor device cannot be sorted out. Here, a long time is a time longer than one period of the frequency of the forward current. For example, if the frequency is 1 kHz, one period is 1 ms and the long time is longer than 1 ms.

Therefore, in the embodiment, the silicon carbide semiconductor device is selected based on the relationship between the current and voltage of built-in diode 16a in a short period of time. Here, the short time is a time shorter than the time during which the forward current is in the ON state during one cycle of the frequency of the forward current. The ON state is a state in which the current value of the forward current is greater than zero, and the OFF state is a state in which the current value of the forward current is zero. For example, when the duty ratio (the ratio of the ON state time to the total time that is the sum of the ON state time and the OFF state time) is 50% at a frequency of 1 kHz, the forward current is in the ON state in one cycle. One time is 500 μs. Therefore, in the embodiment, it is determined whether or not there is a hump (maximum value) in the time-voltage curve during an increase in current for a short period of time (step S3).

FIG. 4 is a graph showing the relationship between time, current, and voltage when a current with a frequency of 1 kHz is applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment. In FIG. 4, the horizontal axis indicates time, and the unit is μs. The vertical axis indicates the voltage and current of the built-in diode 16a. FIG. 4 shows current and voltage from 0 μs to 500 μs when a current with a duty ratio of 50% is flowed at a frequency of 1 kHz. Current is the I line and voltage is the V line. The voltage is when the n ⁻ type silicon carbide layer 71 is 5 μm to 60 μm, the lowest voltage is 5 μm, the next lowest voltage is 10 μm, 15 μm, 30 μm in order, and the highest voltage is 60 μm. is the case. As shown in FIG. 4, at a low frequency of about 1 kHz, the voltage increases in proportion to the current increase.

FIG. 5 is a graph showing the relationship between time, current, and voltage when a current with a frequency of 100 kHz is applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment. In FIG. 5, the horizontal axis indicates time, and the unit is μs. The vertical axis indicates the voltage and current of the built-in diode 16a. FIG. 5 shows current and voltage from 0 μs to 5 μs when a current with a duty ratio of 50% is passed at a frequency of 100 kHz. The current is the I line and the voltage is the multiple V curve. The voltage is when the n ⁻ -type silicon carbide layer 71 is 5 μm to 60 μm. As in FIG. 4, the lowest voltage is 5 μm, the next lowest voltage is 10 μm, and the voltages are 15 μm and 30 μm in order. The highest voltage is for 60 μm.

As shown in FIG. 5, at a high frequency of about 100 kHz, when the current increases, the voltage may decrease instead of increasing at the same time. That is, a hump (maximum value) P occurs in the time-voltage curve. In FIG. 5, when the thickness of the n ⁻ -type silicon carbide layer 71 is 30 μm or more, no bumps are generated, and when the thickness is less than 30 μm, no bumps are generated.

When a negative voltage is applied to the drain electrode and a positive voltage is applied to the source electrode, conductivity modulation occurs in the n ⁻ -type silicon carbide layer 71 and current begins to flow. As the n ⁻ -type silicon carbide layer 71 becomes thicker and the frequency becomes higher, that is, as the on-state time becomes shorter, the conductivity modulation does not keep up with changes in the current from the outside, and the conductivity modulation tends to become non-uniform. Become. In particular, it tends to be uneven in the depth direction.

Therefore, when a current is forcibly supplied from the outside and di/dt increases as the frequency increases, the n ⁻ -type drift region 32 and the first p ⁺ -type region 62a are formed inside the device to maintain this current. In the vicinity of the pn junction layer such as the interface with the element itself, it is necessary to increase the electric field so that the current flows due to the drift current. Therefore, the voltage suddenly increases at a low current value. In particular, when the thickness of the n ⁻ -type silicon carbide layer 71 is 20 μm or more, and many crystal defects exist in the n ⁻ -type silicon carbide layer 71, the conductivity modulation becomes non-uniform, and the voltage responds to the rapid current rise. It becomes a non-stable device and produces a hump in the time-voltage curve. Such a semiconductor device is not suitable for high-frequency driving because the voltage cannot follow a sudden rise in current.

On the other hand, even if n ⁻ -type silicon carbide layer 71 has a thickness of 20 μm or more, if there are not many crystal defects in n ⁻ -type silicon carbide layer 71, even if di/dt increases, that is, the current frequency increases. However, the voltage can follow the sudden rise of the current, and there is no hump in the time-voltage curve. Such semiconductor devices can be driven at high frequencies.

Therefore, in the embodiment, if there is no bump (maximum value) in the time-voltage curve when the current increases for a short time (step S3: No), the semiconductor device is operated at a higher frequency than the recorded frequency. It is selected as being drivable at a low frequency or unusable (step S8). If there is a recorded frequency in step S4, it is selected to be drivable at a frequency lower than the recorded frequency, and if there is no recorded frequency in step S4, that is, even the lowest frequency is for a short time. If there is a local maximum in the time-voltage curve during the increase, it is sorted out as unusable. Here, the selection criterion does not necessarily have to be the presence or absence of a hump (maximum value), and the size of the hump (maximum value) may be used.

Also, if there is a hump (maximum value) in the time-voltage curve when the current increases for a short period of time (step S3: Yes), it is recorded that it can be driven at the set frequency (step S4). For example, when this flowchart is executed by a computer, it is recorded in a recording device of the computer. Next, the set frequency is increased (step S5). For example, the constant frequency may be increased, or the silicon carbide semiconductor device may be increased for each switching frequency used. For example, when switching frequencies of 1 kHz, 10 kHz, 20 kHz, 50 kHz and 100 kHz are used in the silicon carbide semiconductor device, the frequencies may be increased in order of 1 kHz, 10 kHz, 20 kHz, 50 kHz and 100 kHz.

Next, it is determined whether or not the frequency has reached the upper limit frequency (step S6). The upper limit frequency is the maximum switching frequency at which the silicon carbide semiconductor device is used. Since there is no need to test at the upper limit frequency or higher, if the frequency reaches the upper limit frequency (step S6: Yes), the semiconductor device is selected as drivable at the upper limit frequency (step S7).

On the other hand, if the frequency has not reached the upper limit frequency (step S6: No), the process returns to step S2, and the test is performed again with the increased frequency. In addition, the thicker the n ^{− -type} silicon carbide layer 71, the more easily a hump occurs in the time-voltage curve. Effective for silicon semiconductor devices. The thickness of the n ⁻ -type silicon carbide layer 71 is, for example, about 5 μm, 10 μm, 15 μm, 30 μm, and 60 μm for breakdown voltages of 600 V, 1200 V, 1700 V, 3300 V, and 6500 V classes, respectively. This is effective for a silicon carbide semiconductor device in which n ⁻ -type silicon carbide layer 71 has a thickness of 30 μm or more and a breakdown voltage of 3300 V class or more.

Here, FIGS. 6 and 7 show the results of multiple tests between steps S2 to S5. FIG. 6 is a graph showing the relationship between time and current when currents of a plurality of frequencies are applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment. FIG. 7 is a graph showing the relationship between time and voltage when currents of a plurality of frequencies are applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment.

In FIG. 6, the horizontal axis indicates time, and the unit is μs. The vertical axis indicates the current of the built-in diode 16a. In FIG. 7, the horizontal axis indicates time, and the unit is μs. The vertical axis indicates the voltage of the built-in diode 16a.

First, a current of low frequency (1) in FIG. 6, for example, 10 kHz is passed. In this case, as shown in (1) of FIG. 7, no bump occurs. Next, a current of frequency (2) in FIG. 6, for example, 20 kHz is applied. In this case, as shown in (2) of FIG. 7, no bump is generated. Next, a current of frequency (3) in FIG. 6, for example, 50 kHz is applied. In this case, as shown in (3) of FIG. 7, a bump occurs. Therefore, the silicon carbide semiconductor device here is used at the frequency of (2) in FIG. 6, for example, at a frequency of 20 kHz or less. Moreover, in FIGS. 6 and 7, the frequency (4) in FIG. 6, for example, the case where the current of 100 kHz is applied. In this case, as shown in FIG. 7(4), the bump is larger than in FIG. 7(3).

As a result, the series of processes according to this flowchart ends. By executing this flowchart, silicon carbide semiconductor devices that can be driven at a specific switching frequency can be selected, and silicon carbide semiconductor devices that can be driven at a high frequency can be selected.

Next, a method for manufacturing the semiconductor device according to the embodiment will be described. 8 to 13 are cross-sectional views showing states in the middle of manufacturing the semiconductor device according to the embodiment.

First, as shown in FIG. 8, an n ⁺ -type starting substrate (semiconductor wafer) 31 made of silicon carbide is prepared. The n ⁺ -type starting substrate 31 may be, for example, a nitrogen (N)-doped silicon carbide single crystal substrate. Next, on the front surface of n ⁺ -type starting substrate 31, n ⁻ -type silicon carbide layer 71 doped with nitrogen at a concentration lower than that of n ⁺ -type starting substrate 31 is epitaxially grown. When semiconductor device 20 has a withstand voltage of 3300V class, thickness t11 of n ⁻ -type silicon carbide layer 71 may be, for example, about 30 μm.

Next, as shown in FIG. 9, a second p ⁺ -type region 61a and a p ⁺ -type region 81 are formed in the surface region of the n ⁻ -type silicon carbide layer 71 by photolithography and ion implantation of a p-type impurity such as Al. Each is selectively formed. This p ⁺ -type region 81 is part of the first p ⁺ -type region 62a. The second p ⁺ -type regions 61a and the p ⁺ -type regions 81 are alternately and repeatedly arranged in the first direction X in FIG. 2, for example.

A distance d2 between the second p ⁺ -type region 61a and the p ⁺ -type region 81 adjacent to each other may be, for example, about 1.5 μm. The depth d1 and impurity concentration of the second p ⁺ -type region 61a and p ⁺ -type region 81 may be, for example, about 0.5 μm and about 5.0×10 ¹⁸ /cm ³ , respectively. Then, the ion implantation mask (not shown) used for forming the second p ⁺ -type region 61a and the p ⁺ -type region 81 is removed.

Next, an n-type region 82 is formed in the surface region of the n ⁻ -type silicon carbide layer 71 by photolithography and ion implantation of an n-type impurity such as nitrogen. The n-type region 82 is formed, for example, between the second p ⁺ -type region 61a and the p ⁺ -type region 81 and in contact with these regions. The depth d3 and impurity concentration of the n-type region 82 may be, for example, approximately 0.4 μm and approximately 1.0×10 ¹⁷ /cm ³ , respectively.

This n-type region 82 is part of the n-type current diffusion region 33a. A portion of n ⁻ -type silicon carbide layer 71 sandwiched between n-type region 82 , second p ⁺ -type region 61 a and p ⁺ -type region 81 , and n ⁺ -type starting substrate 31 serves as n ⁻ -type drift region 32 . . Then, the ion implantation mask (not shown) used for forming the n-type region 82 is removed. The formation order of the n-type region 82, the second p ⁺ -type region 61a and the p ⁺ -type region 81 may be changed.

Next, as shown in FIG. 10, an n − -type silicon carbide layer doped with an n ^- type impurity such as nitrogen is epitaxially grown on the n ⁻ -type silicon carbide layer 71 to a thickness t12 of 0.5 μm, for example. The thickness of n ⁻ -type silicon carbide layer 71 is increased.

Next, by photolithography and ion implantation of a p-type impurity such as Al, a p ⁺ -type region 83 is formed at a depth reaching the p ⁺ -type region 81 in the thickened portion 71a of the n ^- -type silicon carbide layer 71. Form selectively. The p ⁺ -type regions 81 and 83 adjacent to each other in the depth direction Z are connected to form the first p ⁺ -type region 62a. The width and impurity concentration of the p ⁺ -type region 83 are substantially the same as those of the p ⁺ -type region 81, for example. Then, the ion implantation mask (not shown) used for forming the p ⁺ -type region 83 is removed.

Next, an n-type region 84 is selected in the thickened portion 71a of the n ⁻ -type silicon carbide layer 71 with a depth reaching the n-type region 82 by photolithography and ion implantation of an n-type impurity such as nitrogen. to form The impurity concentration of the n-type region 84 is substantially the same as that of the n-type region 82, for example. The n-type regions 82 and 84 adjacent to each other in the depth direction Z are connected to form the n-type current diffusion region 33a. The formation order of the p ⁺ -type region 83 and the n-type region 84 may be exchanged. Then, the ion implantation mask (not shown) used for forming the n-type region 84 is removed.

Next, as shown in FIG. 11, a p-type silicon carbide layer 72 doped with a p-type impurity such as Al is epitaxially grown on the n ⁻ -type silicon carbide layer 71 . The thickness t13 and impurity concentration of p-type silicon carbide layer 72 may be, for example, approximately 1.3 μm and approximately 4.0×10 ¹⁷ /cm ³ , respectively. Thus, a semiconductor substrate (semiconductor wafer) 10 is formed by epitaxially growing an n ⁻ -type silicon carbide layer 71 and a p-type silicon carbide layer 72 in this order on the n ⁺ -type starting substrate 31 .

Next, a set of steps of photolithography, ion implantation, and removal of the ion implantation mask is repeated under different conditions to form an n ⁺ -type source region of semiconductor device 20 in p-type silicon carbide layer 72 in main effective region 1a. 35a and p ⁺⁺ type contact regions 36a are selectively formed.

The formation order of the n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 36a may be changed. A portion sandwiched between n ⁺ -type source region 35a and p ⁺⁺ -type contact region 36a and n ⁻ -type silicon carbide layer 71 serves as p-type base region 34a. In each ion implantation described above, for example, a resist film or an oxide film may be used as an ion implantation mask.

Next, the diffusion regions formed by ion implantation (first and second p ⁺ -type regions 62a and 61a, n-type current diffusion region 33a, n ⁺ -type source region 35a and p ⁺⁺ -type contact region 36a) are subjected to impurity activation. For this purpose, for example, heat treatment (activation annealing) is performed at a temperature of about 1700° C. for about 2 minutes. Activation annealing may be performed once after all diffusion regions are formed, or may be performed each time a diffusion region is formed by ion implantation.

Next, as shown in FIG. 12, trenches 37a are formed through the n ⁺ -type source region 35a and the p-type base region 34a by photolithography and, for example, dry etching. The trench 37a has a depth reaching, for example, the second p ⁺ -type region 61a inside the n-type current diffusion region 33a. For example, a resist film or an oxide film may be used as an etching mask for forming the trench 37a. Then, the etching mask is removed.

Next, as shown in FIG. 13, a gate insulating film 38a is formed along the surface of semiconductor substrate 10 and the inner wall of trench 37a. The gate insulating film 38a may be, for example, a thermal oxide film formed at a temperature of about 1000° C. in an oxygen (O ₂ ) atmosphere, or a film deposited by high temperature oxidation (HTO). good. Next, a phosphorus-doped polysilicon layer, for example, is formed as a gate electrode 39a on the gate insulating film 38a inside the trench 37a.

Next, an interlayer insulating film 40 is formed over the entire front surface of the semiconductor substrate 10 . The interlayer insulating film 40 may be PSG (Phospho Silicate Glass), for example. The thickness of the interlayer insulating film 40 may be, for example, about 1 μm. Next, the interlayer insulating film 40 and the gate insulating film 38a are selectively removed by photolithography and etching to form the first contact holes 40a.

At this time, a first contact hole 40a is formed to expose the n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 36a. Next, the interlayer insulating film 40 is flattened (reflowed) by heat treatment.

Next, a first TiN film 42a is formed on the entire front surface of the semiconductor substrate 10 by sputtering, for example. The first TiN film 42a covers the entire surface of the interlayer insulating film 40, and the portions of the front surface of the semiconductor substrate 10 exposed to the first contact holes 40a (the n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 35a). Cover area 36a).

Next, by photolithography and etching, the portion of the first TiN film 42a inside the first contact hole 40a covering the semiconductor substrate 10 is removed to expose the n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 36a again. Let As a result, the first TiN film 42a is left on the entire surface of the interlayer insulating film 40 as a barrier metal 46a.

Next, a Ni film (not shown) is formed on the semiconductor portion (the front surface of the semiconductor substrate 10) exposed in the first contact hole 40a by, for example, sputtering. At this time, a Ni film is also formed on the first TiN film 42a. Next, a heat treatment at, for example, about 970° C. is performed to silicidize the contact portion of the Ni film with the semiconductor portion, thereby forming the NiSi film 41a in ohmic contact with the semiconductor portion.

During the heat treatment for silicidation of nickel, the first TiN film 42a is arranged between the interlayer insulating film 40 and the Ni film, so that nickel atoms in the Ni film are prevented from diffusing into the interlayer insulating film 40. can be prevented. A portion of the Ni film on the interlayer insulating film 40 is not silicided because it is not in contact with the semiconductor portion. After that, the portion of the Ni film on the interlayer insulating film 40 is removed to expose the interlayer insulating film 40 .

Next, a Ni film, for example, is formed on the back surface of the semiconductor substrate 10 . Next, the Ni film is silicided by heat treatment at about 970° C., for example, and a NiSi film is formed as the drain electrode 51 in ohmic contact with the semiconductor portion (back surface of the semiconductor substrate 10). The heat treatment for silicidation when forming the NiSi film to be the drain electrode 51 may be performed simultaneously with the heat treatment for forming the NiSi film 41 a on the front surface of the semiconductor substrate 10 .

Next, by sputtering, on the front surface of the semiconductor substrate 10, a first Ti film 43a, a second TiN film 44a, and a second Ti film 45a, which serve as the barrier metal 46a, and an Al film (or an Al alloy film, which serves as the source pad 21a) are formed. ) and are stacked in order. The thickness of the Al film is, for example, about 5 μm or less.

Next, by photolithography and etching, the metal film deposited on the front surface of the semiconductor substrate 10 is patterned to leave a portion that will become the barrier metal 46a.

Next, for example, a Ti film, a Ni film and a gold (Au) film are sequentially laminated on the surface of the drain electrode 51 by, for example, sputtering to form a drain pad (not shown).

Next, the front surface of the semiconductor substrate 10 is protected with a polyimide film by chemical vapor deposition (CVD), for example. Next, the polyimide film is selectively removed by photolithography and etching to form first protective films 49a covering the electrode pads, and openings are formed in these first protective films 49a.

Next, after a general plating pretreatment, a plating film 47a is formed on the portion of the source pad 21a exposed to the opening of the first protective film 49a by a general plating treatment. At this time, the first protective film 49a functions as a mask for suppressing wetting and spreading of the plating film 47a. The thickness of the plated film 47a may be, for example, about 5 μm.

Next, a polyimide film serving as a second protective film 50a covering each boundary between the plated film 47a and the first protective film 49a is formed by, eg, CVD. Next, terminal pins 48a are joined onto the plated film 47a by solder layers (not shown). At this time, the second protective film 50a functions as a mask that suppresses wetting and spreading of the solder layer.

Thereafter, the semiconductor substrate 10 is diced (cut) into individual chips, thereby completing the semiconductor device 20 shown in FIG.

As described above, according to the silicon carbide semiconductor device sorting method according to the embodiment, a current of a predetermined frequency is applied to the silicon carbide semiconductor device, and for a short time, when the current increases, the time and voltage Silicon carbide semiconductor devices are selected based on whether or not a hump (maximum value) occurs in the curve of . Thereby, silicon carbide semiconductor devices that can be driven at a specific switching frequency can be selected, and silicon carbide semiconductor devices that can be driven at a high frequency can be selected.

In the embodiment, the quality of the n-type epitaxial layer is inspected by inspecting the built-in diode of the MOSFET. In other words, it is judged that there are few crystal defects in the n-type epitaxial layer if no bump occurs in the relationship between voltage and time when the current increases at a high frequency. This is applicable to silicon carbide semiconductor devices having built-in diodes other than MOSFETs. It is also applicable to diodes.

As described above, the present invention can be modified in various ways without departing from the gist of the present invention. Further, in each of the above-described embodiments, the case where silicon carbide is used as a wide bandgap semiconductor is described as an example, but it is also applicable to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). is. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. It holds.

INDUSTRIAL APPLICABILITY As described above, the method for sorting silicon carbide semiconductor devices according to the present invention is useful for high withstand voltage semiconductor devices used in power converters, power supply devices for various industrial machines, and the like.

10 semiconductor substrate 16a built-in diode of main semiconductor element 20 semiconductor device 21a source pad 31 n ⁺ type starting substrate 32 n ⁻ type drift region 33a n type current diffusion region 34a p type base region 35a n ⁺ type source region 36a p ⁺⁺ type Contact region 37a Trench 38a Gate insulating film 39a Gate electrode 40 Interlayer insulating film 40a Contact hole 41a NiSi film 42a First TiN film 43a First Ti film 44a Second TiN film 45a Second Ti film 46a Barrier metal 47a Plating film 48a Terminal pin 49a First protection Film 50a Second protective film 51 Drain electrode 61a, 62a P ⁺ -type region 71 n ^- -type silicon carbide layer 72 p-type silicon carbide layer X Direction parallel to front surface of semiconductor chip (first direction)
Y direction parallel to the front surface of the semiconductor chip and orthogonal to the first direction (second direction)
Z depth direction 101 n ⁺ type silicon carbide substrate 102 n type silicon carbide epitaxial layer 103 p ⁺ type base region 104 p type base layer 105 n ⁺ type source region 106 p ⁺ type contact region 107 n type well region 108 gate insulating film 109 gate electrode 110 source electrode 111 drain electrode

Claims (5)

A method for selecting a silicon carbide semiconductor device having a built-in diode,
a first step of applying a forward current of a predetermined frequency to the built-in diode of the silicon carbide semiconductor device;
The silicon carbide semiconductor device in which a maximum value occurs in a time-voltage curve when the forward current increases for a time shorter than the ON state time of the forward current in one cycle of the predetermined frequency. A second step of selecting
A method for selecting a silicon carbide semiconductor device, comprising: a third step of increasing the predetermined frequency;
The forward current of the increased frequency is passed through the silicon carbide semiconductor device, and the silicon carbide semiconductor device in which a maximum value occurs in a time-voltage curve during the short period of time when the forward current increases. A fourth step of sorting;
2. The method for sorting silicon carbide semiconductor devices according to claim 1, further comprising: The silicon carbide semiconductor device is
a first conductivity type first semiconductor layer provided on a front surface of a silicon carbide semiconductor substrate;
a second conductivity type second semiconductor layer provided on the side opposite to the silicon carbide semiconductor substrate side of the first semiconductor layer;
a first conductivity type first semiconductor region selectively provided in a surface layer of the second semiconductor layer and having an impurity concentration higher than that of the silicon carbide semiconductor substrate;
a gate insulating film in contact with the second semiconductor layer;
a gate electrode provided on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer;
a first electrode provided on the surface of the first semiconductor region and the second semiconductor layer;
a second electrode provided on the back surface of the silicon carbide semiconductor substrate;
3. The method for sorting silicon carbide semiconductor devices according to claim 1, further comprising: The silicon carbide semiconductor device is
further comprising a trench penetrating the second semiconductor layer and reaching the first semiconductor layer;
4. The method of selecting a silicon carbide semiconductor device according to claim 3, wherein said gate electrode is provided inside said trench via said gate insulating film. 5. The method for sorting silicon carbide semiconductor devices according to claim 1, wherein the silicon carbide semiconductor device has a withstand voltage of 3300 V or higher.

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