JP2021012061A - Method for selecting silicon carbide semiconductor devices - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for selecting a silicon carbide semiconductor device capable of selecting a silicon carbide semiconductor device which can be driven at a specific frequency. A method for selecting a silicon carbide semiconductor device having a built-in diode 16a. A forward current of a predetermined frequency is passed through the built-in diode 16a of the silicon carbide semiconductor device. Next, the silicon carbide semiconductor device in which the maximum value is generated in the curve of time and voltage when the forward current increases for a time shorter than the time when the forward current is on in one cycle is selected. Further, the predetermined frequency is increased, and the forward current of the increased frequency is passed through the silicon carbide semiconductor device, and the maximum value is generated in the time and voltage curves when the forward current is increased for a short time. Select silicon semiconductor devices. [Selection diagram] Fig. 1

Description

The present invention relates to a method for selecting a silicon carbide semiconductor device.

Conventionally, silicon (Si) has been used as a constituent material of a power semiconductor device that controls a high voltage or a large current. There are multiple types of power semiconductor devices, such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors: Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: Insulated Gate Field Effect Transistors), which can be used according to the application. Has been done.

For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can increase the current, but they cannot be switched at high speed. Specifically, the bipolar transistor is limited to use at a switching frequency of about several kHz, and the IGBT is limited to use at a switching frequency of about several tens of kHz. On the other hand, the power MOSFET has a lower current density than the bipolar transistor and the IGBT, and it is difficult to increase the current, but high-speed switching operation up to about several MHz is possible.

However, there is a strong demand in the market for power semiconductor devices that have both large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs, and development is now progressing to near the material limit. .. Silicon carbide (SiC) is being studied as a semiconductor material that can replace silicon from the viewpoint of power semiconductor devices, and can manufacture (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. Is attracting attention.

The background to this is as follows. SiC is a chemically stable material, has a wide bandgap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Also, the maximum electric field strength is more than an order of magnitude higher than that of silicon. Since SiC has a high possibility of exceeding the material limit of silicon, future growth is expected in power semiconductor applications, especially MOSFETs. In particular, it is expected that the on-resistance is small, and a vertical SiC-MOSFET having a lower on-resistance while maintaining high withstand voltage characteristics can be expected.

The structure of a conventional silicon carbide semiconductor device will be described by taking a vertical MOSFET as an example. FIG. 14 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 14, the n-type silicon carbide epitaxial layer 102 is deposited on the front surface of the n ⁺ type silicon carbide substrate 101, and the p ⁺ type base region 103 is formed on the surface of the n-type silicon carbide epitaxial layer 102. It is selectively provided, and the p-type base layer 104 is selectively provided in the surface of the n-type silicon carbide epitaxial layer 102. Further, an n ⁺ type source region 105, a p ⁺ type contact region 106, and an n type well region 107 are selectively provided on the surface of the p-type base layer 104.

A gate electrode 109 is provided on the surface of the p-type base layer 104 and the n ⁺ -type source region 105 via a gate insulating film 108. Further, a source electrode 110 is provided on the surfaces of the p ⁺ type contact region 106 and the n ⁺ type source region 105. Further, a drain electrode 111 is provided on the back surface of the n ⁺ type silicon carbide substrate 101.

A vertical MOSFET having such a structure incorporates a parasitic pn diode formed by a p ⁺ type base region 103 and an n-type silicon carbide epitaxial layer 102 as a body diode between a source and a drain. This parasitic pn diode can be operated by applying a high potential to the source electrode 110, and a current flows in the direction indicated by the arrow A in FIG. As described above, unlike the IGBT, the MOSFET has a built-in parasitic pn diode, so that the freewheeling diode (FWD: Free Wheeling Diode) used for the inverter can be omitted, which contributes to cost reduction and miniaturization. Hereinafter, the parasitic pn diode of the MOSFET is referred to as a built-in diode.

A method of selecting a silicon carbide MOSFET using this built-in diode is known. For example, a silicon carbide semiconductor device in which the temperature of the silicon carbide semiconductor device is set to 235 ° C. or higher and 300 ° C. or lower, a forward current having a frequency of 10 kHz or higher and 100 kHz or lower is passed, and the rate of change of the forward voltage is lower than 3% is selected. (See, for example, Patent Document 1). This makes it possible to screen a silicon carbide semiconductor device whose reliability does not deteriorate even when used in an inverter circuit at a high temperature for a long time.

Japanese Unexamined Patent Publication No. 2018-20251

However, the conventional method for selecting silicon carbide MOSFETs has not selected silicon carbide semiconductor devices that can be driven at a specific frequency. Since the silicon carbide semiconductor device is selected by passing a forward current of a predetermined frequency, the silicon carbide semiconductor device that normally operates at a frequency higher than the predetermined frequency is not selected. Further, even a silicon carbide semiconductor device selected as an unqualified product at a predetermined frequency may operate normally at a frequency lower than the predetermined frequency, and a silicon carbide semiconductor device that normally operates at a frequency lower than the predetermined frequency is used. Not sorted.

An object of the present invention is to provide a method for selecting a silicon carbide semiconductor device capable of selecting a silicon carbide semiconductor device that can be driven at a specific frequency in order to solve the above-mentioned problems caused by the prior art.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for selecting a silicon carbide semiconductor device according to the present invention has the following features. This is a method for selecting a silicon carbide semiconductor device having a built-in diode. First, the first step of passing a forward current of a predetermined frequency through the built-in diode of the silicon carbide semiconductor device is performed. Next, the carbide in which a maximum value is generated in the time and voltage curves when the forward current increases for a time shorter than the time during which the forward current is in the ON state during one cycle of the predetermined frequency. The second step of selecting the silicon semiconductor device is performed.

Further, in the method for selecting a silicon carbide semiconductor device according to the present invention, in the above-described invention, the third step of increasing the predetermined frequency and the forward current of the increased frequency are passed through the silicon carbide semiconductor device. It further comprises a fourth step of selecting the silicon carbide semiconductor device in which a maximum value is generated in the time and voltage curves when the forward current increases for the short time.

Further, according to the method for selecting a silicon carbide semiconductor device according to the present invention, in the above-described invention, the silicon carbide semiconductor device is the first conductive type first semiconductor layer provided on the front surface of the silicon carbide semiconductor substrate. , A second conductive type second semiconductor layer provided on the opposite side of the first semiconductor layer with respect to the silicon carbide semiconductor substrate side, and selectively provided on the surface layer of the second semiconductor layer. A first conductive type first semiconductor region having a higher impurity concentration than the silicon carbide semiconductor substrate, a gate insulating film in contact with the second semiconductor layer, and a surface of the gate insulating film in contact with the second semiconductor layer. A gate electrode provided on the opposite surface, a first electrode provided on the surface of the first semiconductor region and the second semiconductor layer, and a second electrode provided on the back surface of the silicon carbide semiconductor substrate. It is characterized by having.

Further, in the method for selecting a silicon carbide semiconductor device according to the present invention, in the above-described invention, the silicon carbide semiconductor device further includes a trench that penetrates the second semiconductor layer and reaches the first semiconductor layer. The gate electrode is characterized in that it is provided inside the trench via the gate insulating film.

Further, the method for selecting a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the withstand voltage of the silicon carbide semiconductor device is 3300 V or more.

According to the above-described invention, a current of a predetermined frequency is applied to a silicon carbide semiconductor device, and the silicon carbide semiconductor is determined by whether or not a maximum value is generated in the time and voltage curves when the current increases for a short time. The equipment is being sorted. Thereby, the silicon carbide semiconductor device that can be driven at a specific switching frequency can be selected, and the silicon carbide semiconductor device that can be driven at a high frequency can be selected.

According to the method for selecting a silicon carbide semiconductor device according to the present invention, it is possible to select a silicon carbide semiconductor device that can be driven at a specific frequency.

It is a flowchart which shows the selection method of the silicon carbide semiconductor device which concerns on embodiment. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on embodiment. It is a graph which shows the frequency dependence of the forward voltage of the built-in diode of the silicon carbide semiconductor device which concerns on embodiment. It is a graph which shows the relationship between the time when the current of the frequency 1kHz was applied to the built-in diode of the silicon carbide semiconductor device which concerns on embodiment, and the current and voltage. It is a graph which shows the relationship between the time when the current of the frequency 100kHz was applied to the built-in diode of the silicon carbide semiconductor device which concerns on embodiment, and the current and voltage. It is a graph which shows the relationship between the time and the electric current when the electric current of a plurality of frequencies is applied to the built-in diode of the silicon carbide semiconductor device which concerns on embodiment. It is a graph which shows the relationship between the voltage and the time when the current of a plurality of frequencies is applied to the built-in diode of the silicon carbide semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 3). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 4). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 5). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 6). It is sectional drawing which shows the structure of the conventional silicon carbide semiconductor device.

Hereinafter, preferred embodiments of the method for selecting a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment)
FIG. 1 is a flowchart showing a method of selecting a silicon carbide semiconductor device according to an embodiment. Hereinafter, MOSFETs will be described as an example of the silicon carbide semiconductor device, but the same applies to other silicon carbide semiconductor devices having a MOS gate structure. First, the silicon carbide semiconductor device according to the embodiment will be described. FIG. 2 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment.

The semiconductor device 20 is a vertical MOSFET having a MOS gate (insulated gate having a three-layer structure of metal-oxide film-semiconductor) on the front surface side of the semiconductor substrate 10. Here, a case where the semiconductor device 20 has a wiring structure having the same configuration using a pin-shaped wiring member (terminal pin 48a described later) will be described as an example, but a wire is used instead of the pin-shaped wiring member. It may have a wiring structure.

The semiconductor substrate 10 has an n ^- type drift region (first conductive type first semiconductor layer) 32 and a p-type base region (second conductive type) on an n ⁺ type starting substrate (silicon carbide semiconductor substrate) 31 made of silicon carbide. This is an epitaxial substrate in which the silicon carbide layers 71 and 72 to be the second semiconductor layer) 34a are epitaxially grown in this order. The semiconductor device 20 includes a p-type base region 34a, an n ⁺ type source region (first conductive type first semiconductor region) 35a, and a p ⁺⁺ type contact region 36a provided on the front surface side of the semiconductor substrate 10. It has a general MOS gate composed of a trench 37a, a gate insulating film 38a, and a gate electrode 39a.

The trench 37a penetrates the p-type silicon carbide layer 72 in the depth direction Z from the front surface (the surface of the p-type silicon carbide layer 72) of the semiconductor substrate 10 and reaches the n ^- type silicon carbide layer 71. The trench 37a is arranged in a stripe shape extending in a direction parallel to the front surface of the semiconductor substrate 10, for example.

A gate electrode 39a is provided inside the trench 37a via a gate insulating film 38a. A p-type base region 34a, an n ⁺ -type source region 35a, and a p ^++- type contact region 36a are selected as the surface region of the front surface of the semiconductor substrate 10 between two trenches 37a adjacent to each other (mesa region). It is provided as a target. The n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a are provided between the front surface of the semiconductor substrate 10 and the p-type base region 34a.

The n ⁺ type source region 35a is provided on the trench 37a side of the p ⁺⁺ type contact region 36a. The p ⁺⁺ type contact region 36a may not be provided. When the p ⁺⁺ type contact region 36a is not provided, the p-type base region 34a reaches the front surface of the semiconductor substrate 10 at a position farther from the trench 37a than the n ⁺ type source region 35a, and the semiconductor substrate 10 It is exposed on the front surface.

Inside the semiconductor substrate 10, an n ^- type drift region 32 is provided in contact with the p-type base region 34a at a position closer to the n ⁺ type drain region (n ⁺ type starting substrate 31) than the p-type base region 34a. ing. An n-type current diffusion region 33a may be provided between the p-type base region 34a and the n ^- type drift region 32 in contact with these regions. The n-type current diffusion region 33a is a so-called current diffusion layer (Curent Spreading Layer: CSL) that reduces the spread resistance of carriers.

Further, inside the semiconductor substrate 10, a second p ⁺ type region 61a and a first p ⁺ type region 62a are provided at positions closer to the n ⁺ type drain region than the p type base region 34a. The second p ⁺ type region 61a is provided apart from the p type base region 34a and faces the bottom surface of the trench 37a in the depth direction Z. A part of the second p ⁺ type region 61a is connected to the first p ⁺ type region 62a.

The first p ⁺ type region 62a is provided in the mesa region apart from the second p ⁺ type region 61a and the trench 37a, and is in contact with the p type base region 34a. The 1,2P ⁺ -type regions 62a, 61a is fixed to the source potential of the semiconductor device 20 via the p-type base region 34a. The first and second p ⁺ type regions 62a and 61a have a function of relaxing the electric field applied to the bottom surface of the trench 37a.

The interlayer insulating film 40 is provided on the entire front surface of the semiconductor substrate 10 and covers the gate electrode 39a. All the gate electrodes 39a of the semiconductor device 20 are electrically connected to the gate pad (not shown) via a gate runner (not shown) at a portion (not shown). The gate runner is provided on the front surface of the semiconductor substrate 10 via a field insulating film (not shown) in the edge termination region that surrounds the active region through which the current flows when turned on and maintains the withstand voltage. It is a gate polysilicon layer that surrounds the periphery in a substantially rectangular shape. The withstand voltage is the limit voltage at which the element does not malfunction or break.

The n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a of the semiconductor device 20 are exposed in the first contact hole 40a that penetrates the interlayer insulating film 40 in the depth direction Z and reaches the semiconductor substrate 10. Inside the first contact hole 40a, on the front surface of the semiconductor substrate 10, a nickel silicide (NiSi, Ni ₂ Si or thermally stable NiSi _2: hereinafter, collectively and NiSi with) the membrane 41a provided ing.

The NiSi film 41a is in ohmic contact with the semiconductor substrate 10 inside the first contact hole 40a and is electrically connected to the n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a. When the p ⁺⁺ type contact region 36a is not provided, the p type base region 34a is exposed to the first contact hole 40a instead of the p ⁺⁺ type contact region 36a and is electrically connected to the NiSi film 41a. Will be done.

A barrier metal 46a is provided on the entire surface of the interlayer insulating film 40 and the NiSi film 41a. The barrier metal 46a has a function of preventing mutual reaction between each metal film of the barrier metal 46a or between regions facing each other across the barrier metal 46a. The barrier metal 46a may have, for example, a laminated structure in which a first titanium nitride (TiN) film 42a, a first titanium (Ti) film 43a, a second TiN film 44a, and a second Ti film 45a are laminated in this order.

The first TiN film 42a is provided only on the surface of the interlayer insulating film 40 and covers the entire surface of the interlayer insulating film 40. The first Ti film 43a is provided on the surfaces of the first TiN film 42a and the NiSi film 41a. The second TiN film 44a is provided on the surface of the first Ti film 43a. The second Ti film 45a is provided on the surface of the second TiN film 44a.

The source pad 21a is embedded in the first contact hole 40a and is provided on the entire surface of the second Ti film 45a. The source pad 21a is electrically connected to the n ⁺ type source region 35a and the p-type base region 34a via the barrier metal 46a and the NiSi film 41a, and functions as a source electrode of the semiconductor device 20. The source pad 21a is, for example, an aluminum (Al) film or an Al alloy film having a thickness of about 5 μm.

Specifically, when the source pad 21a is an Al alloy film, the source pad 21a may be, for example, an aluminum-silicon (Al-Si) film containing about 5% or less of silicon, or may be made of silicon. It may be an aluminum-silicon-copper (Al-Si-Cu) film containing about 5% or less of the whole and about 5% or less of copper (Cu), or an aluminum-containing about 5% or less of copper. It may be a copper (Al—Cu) film.

One end of the terminal pin 48a is joined onto the source pad 21a via a plating film 47a and a solder layer (not shown). The other end of the terminal pin 48a is joined to a metal bar (not shown) arranged so as to face the front surface of the semiconductor substrate 10. The other end of the terminal pin 48a is exposed to the outside of a case (not shown) on which the semiconductor substrate 10 is mounted, and is electrically connected to an external device (not shown). The terminal pin 48a is a round bar-shaped (cylindrical) wiring member having a predetermined diameter.

The terminal pin 48a is solder-bonded to the plating film 47a in a state of standing substantially perpendicular to the front surface of the semiconductor substrate 10. The terminal pin 48a is an external connection terminal that takes out the potential of the source pad 21a to the outside, and is connected to an external ground potential (lowest potential). The portion of the surface of the source pad 21a other than the plating film 47a is covered with the first protective film 49a, and the boundary between the plating film 47a and the first protective film 49a is covered with the second protective film 50a. The first and second protective films 49a and 50a are, for example, polyimide films.

The drain electrode 51 is in ohmic contact with the entire back surface of the semiconductor substrate 10 (the back surface of the n ⁺ type starting substrate 31). On the drain electrode 51, for example, a drain pad (electrode pad: not shown) is provided in a laminated structure in which a Ti film, a nickel (Ni) film, and a gold (Au) film are laminated in this order. The drain pad is solder-bonded to a metal base plate (not shown), and at least a part of the drain pad is in contact with the base portion of the cooling fins (not shown) via the metal base plate.

Returning to FIG. 1, in the method of selecting the silicon carbide semiconductor device, first, the frequency of the current applied to the silicon carbide semiconductor device is set (step S1). For example, the lowest switching frequency used by a silicon carbide semiconductor device is set as the frequency of the applied current. Further, the current applied to the silicon carbide semiconductor device may be a triangular wave in which the current gradually increases or a rectangular wave in which the current rapidly increases.

Next, a forward current is applied to the built-in diode of the MOSFET (step S2). Specifically, the gate electrode 39a of the MOSFET and the source electrode (source pad 21a) are short-circuited, a positive voltage is applied to the source electrode, and the potential of the drain electrode 51 is set to 0, whereby the built-in diode 16a (FIG. 2). (See) is energized.

Here, FIG. 3 is a graph showing the frequency dependence of the forward voltage of the built-in diode of the silicon carbide semiconductor device according to the embodiment. In FIG. 3, the horizontal axis represents the thickness of the n ^- type silicon carbide layer 71, which is n-type epitaxial, and the unit is μm. The vertical axis represents the forward voltage Vf of the built-in diode 16a, and the unit is V.

The forward voltage Vf of the built-in diode 16a of the silicon carbide semiconductor device is about 3V, but as shown in FIG. 3, the thicker the n ^- type silicon carbide layer 71, that is, the higher the withstand voltage, the higher the forward voltage Vf. Become. Further, the higher the frequency of the forward current energized in the built-in diode, the higher the forward voltage Vf.

When the frequency of the forward current becomes high, a time delay occurs in the conductivity modulation inside the n ^- type silicon carbide layer 71, and the conductivity modulation tends to be non-uniform. Therefore, the higher the frequency of the forward current, the higher the forward voltage Vf. Further, the thicker the n ^- type silicon carbide layer 71 is, the more likely it is that crystal defects are potentially generated inside, the lifetime is lowered in the region of the crystal defects, the conductivity modulation is likely to be non-uniform, and the n ^- type silicon carbide is easily generated. The thicker the silicon layer 71, the higher the forward voltage Vf.

FIG. 3 shows the measurement result of the forward voltage Vf after the forward current is applied for a long time. After the forward current is applied for a long time, the forward voltage Vf becomes high, but the built-in diode 16a operates normally. It seems that the silicon carbide semiconductor device cannot be selected. Here, the long time is a time longer than one cycle of the frequency of the forward current. For example, in the case of a frequency of 1 kHz, one cycle is 1 ms, and a long time is longer than 1 ms.

Therefore, in the embodiment, the silicon carbide semiconductor device is selected based on the relationship between the current and the voltage of the built-in diode 16a in a short time. Here, the short time is a time shorter than the time during which the forward current is on in one cycle of the frequency of the forward current. The on state is a state in which the current value of the forward current is larger than 0, and the off state is a state in which the current value of the forward current is 0. For example, when the duty ratio (the ratio of the time in the on state to the total time, which is the sum of the time in the on state and the time in the off state) is 50% at a frequency of 1 kHz, the forward current is in the on state in one cycle. A certain time is 500 μs. Therefore, in the embodiment, it is determined whether or not a hump (maximum value) is generated in the curve of time and voltage when the current increases for a short time (step S3).

FIG. 4 is a graph showing the relationship between the time, current, and voltage when a current having a frequency of 1 kHz is applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment. In FIG. 4, the horizontal axis represents time and the unit is μs. The vertical axis shows the voltage and current of the built-in diode 16a. FIG. 4 shows the current and voltage from 0 μs to 500 μs when a current having a duty ratio of 50% is applied at a frequency of 1 kHz. The current is a straight line of I and the voltage is a straight line of multiple Vs. The voltage when the n ^- type silicon carbide layer 71 is 5 μm to 60 μm, the lowest voltage is 5 μm, the next lowest voltage is 10 μm, and the highest voltage is 60 μm, which is 15 μm and 30 μm, respectively. This is the case. As shown in FIG. 4, at a low frequency of about 1 kHz, the voltage also increases in proportion to the increase in current.

FIG. 5 is a graph showing the relationship between the time, current, and voltage when a current having a frequency of 100 kHz is applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment. In FIG. 5, the horizontal axis represents time and the unit is μs. The vertical axis shows the voltage and current of the built-in diode 16a. FIG. 5 shows the current and voltage from 0 μs to 5 μs when a current having a duty ratio of 50% is passed at a frequency of 100 kHz. The current is a straight line of I and the voltage is a curve of multiple Vs. The voltage when the n ^- type silicon carbide layer 71 is 5 μm to 60 μm, the lowest voltage is 5 μm as in FIG. 4, the next lowest voltage is 10 μm, and the voltage is 15 μm and 30 μm, respectively. The highest voltage is at 60 μm.

As shown in FIG. 5, at a high frequency of about 100 kHz, the voltage may not increase at the same time as the current increases, but may decrease. That is, a hump (maximum value) P is generated on the curve of time and voltage. In FIG. 5, when the thickness of the n ^- type silicon carbide layer 71 is 30 μm or more, humps are generated, and when the thickness is thinner than 30 μm, humps are not generated.

When a negative voltage is applied to the drain electrode and a positive voltage is applied to the source electrode, conductivity modulation occurs in the n ^- type silicon carbide layer 71 and energization starts. When the n ^- type silicon carbide layer 71 becomes thicker and the frequency becomes higher, that is, when the on-state time becomes shorter, the conductivity modulation corresponding to the change in current from the outside cannot be made in time, and the conductivity modulation tends to be non-uniform. Become. In particular, it tends to be non-uniform in the depth direction.

Therefore, when the current is forcibly energized from the outside and the di / dt increases as the frequency increases, the n ^- type drift region 32 and the first p ⁺ type region 62a inside the element are used to maintain this current. It is necessary for the element itself to raise the electric field in the vicinity of the pn junction layer such as the interface with and to allow the current to flow by the drift current. Therefore, the voltage suddenly rises at a low current value. In particular, if the thickness of the n ^- type silicon carbide layer 71 is 20 μm or more and there are many crystal defects in the n ^- type silicon carbide layer 71, the conductivity modulation becomes non-uniform and the voltage corresponds to a sudden rise in current. It becomes an element that cannot be used, and a hump is generated on the time and voltage curves. Such a semiconductor element is not suitable for driving at a high frequency because the voltage cannot follow the sudden rise of the current.

On the other hand, even if the thickness of the n ^- type silicon carbide layer 71 is 20 μm or more, if there are not many crystal defects in the n ^- type silicon carbide layer 71, the di / dt becomes high, that is, the current frequency becomes high. However, the voltage can follow the sudden rise of the current, and no hump is generated in the time and voltage curves. Such a semiconductor element can be driven at a high frequency.

Therefore, in the embodiment, when a hump (maximum value) does not occur in the time and voltage curves when the current increases for a short time (step S3: No), the semiconductor device is moved from the recorded frequency. It is selected as driveable or unusable at a low frequency (step S8). If there is a frequency recorded by step S4, it is selected as driveable at a frequency lower than the recorded frequency, and if there is no frequency recorded by step S4, that is, even the lowest frequency is of current for a short time. If the time and voltage curves have maximum values at the time of increase, it is classified as unusable. Here, the selection criterion does not necessarily have to be based on the presence or absence of a hump (maximum value), and may be the size of the hump (maximum value).

Further, if a hump (maximum value) is generated in the curve of time and voltage when the current increases for a short time (step S3: Yes), it is recorded that the drive can be performed at the set frequency (step S4). For example, when the computer executes this flowchart, it is recorded in the recording device of the computer. Next, the set frequency is increased (step S5). For example, the constant frequency may be increased, or the silicon carbide semiconductor device may be increased for each switching frequency used. For example, when switching frequencies of 1 kHz, 10 kHz, 20 kHz, 50 kHz, and 100 kHz are used in a silicon carbide semiconductor device, the frequencies may be increased in the order of 1 kHz, 10 kHz, 20 kHz, 50 kHz, and 100 kHz.

Next, it is determined whether or not the frequency has reached the upper limit frequency (step S6). The upper limit frequency is the maximum switching frequency used by silicon carbide semiconductor devices. Since it is not necessary to perform the test at the upper limit frequency or higher, when the frequency reaches the upper limit frequency (step S6: Yes), the semiconductor device is selected as being driveable at the upper limit frequency (step S7).

On the other hand, when the frequency has not reached the upper limit frequency (step S6: No), the process returns to step S2, and the test is performed again at the increased frequency. Further, the thicker the n ^- type silicon carbide layer 71 is, the more humps are likely to occur in the time and voltage curves. Therefore, the selection method of the embodiment is based on the thicker n ^- type silicon carbide layer 71. Effective for silicon semiconductor devices. The thickness of the n ^- type silicon carbide layer 71 is, for example, about 5 μm, 10 μm, 15 μm, 30 μm, and 60 μm when the withstand voltage is 600 V, 1200 V, 1700 V, 3300 V, and 6500 V class, respectively. It is effective for silicon carbide semiconductor devices having an n ^- type silicon carbide layer 71 having a thickness of 30 μm or more and a withstand voltage of 3300 V class or more.

Here, FIGS. 6 and 7 show the results of a plurality of tests between steps S2 and S5. FIG. 6 is a graph showing the relationship between the time and the current when currents of a plurality of frequencies are applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment. FIG. 7 is a graph showing the relationship between the voltage and the time when currents of a plurality of frequencies are applied to the built-in diode of the silicon carbide semiconductor device according to the embodiment.

In FIG. 6, the horizontal axis represents time and the unit is μs. The vertical axis shows the current of the built-in diode 16a. In FIG. 7, the horizontal axis represents time and the unit is μs. The vertical axis shows the voltage of the built-in diode 16a.

First, a current having a low frequency (1) of FIG. 6, for example, 10 kHz is passed. In this case, as shown in (1) of FIG. 7, no hump is generated. Next, a current of the frequency (2) of FIG. 6, for example, 20 kHz is passed. In this case, as shown in (2) of FIG. 7, no hump is generated. Next, a current of the frequency (3) of FIG. 6, for example, 50 kHz is passed. In this case, as shown in FIG. 7 (3), a hump is generated. Therefore, the silicon carbide semiconductor device here is used at the frequency (2) of FIG. 6, for example, at a frequency of 20 kHz or less. Further, in FIGS. 6 and 7, a current of the frequency (4) of FIG. 6, for example, 100 kHz is passed. In this case, as shown in (4) of FIG. 7, the hump is larger than that of (3) of FIG.

As a result, a series of processes according to this flowchart is completed. By executing this flowchart, a silicon carbide semiconductor device that can be driven at a specific switching frequency can be selected, and a silicon carbide semiconductor device that can be driven at a high frequency can be selected.

Next, a method of manufacturing the semiconductor device according to the embodiment will be described. 8 to 13 are cross-sectional views showing a state in the middle of manufacturing the semiconductor device according to the embodiment.

First, as shown in FIG. 8, an n ⁺ type starting substrate (semiconductor wafer) 31 made of silicon carbide is prepared. The n ⁺ type starting substrate 31 may be, for example, a nitrogen (N) -doped silicon carbide single crystal substrate. Then, the front surface of the n ⁺ -type starting substrate 31, n nitrogen is lightly doped than n ⁺ -type starting substrate 31 ^- -type silicon carbide layer 71 is epitaxially grown. When the semiconductor device 20 has a withstand voltage of 3300 V class, the thickness t11 of the n ^- type silicon carbide layer 71 may be, for example, about 30 μm.

Next, as shown in FIG. 9, the second p ⁺ type region 61a and the p ⁺ type region 81 are formed on the surface region of the n ⁻ type silicon carbide layer 71 by photolithography and ion implantation of a p-type impurity such as Al. Each is selectively formed. The p ⁺ type region 81 is a part of the first p ⁺ type region 62a. The second p ⁺ type region 61a and the p ⁺ type region 81 are alternately and repeatedly arranged, for example, in the first direction X in FIG.

The distance d2 between the second p ⁺ type region 61a and the p ⁺ type region 81 adjacent to each other may be, for example, about 1.5 μm. The depth d1 and the impurity concentration of the second p ⁺ type region 61a and the p ⁺ type region 81 may be, for example, about 0.5 μm and about 5.0 × 10 ¹⁸ / cm ³ , respectively. Then, the ion implantation mask (not shown) used for forming the second p ⁺ type region 61a and the p ⁺ type region 81 is removed.

Next, by ion implantation of n-type impurities such as photolithography and example nitrogen, n ^- to form an n-type region 82 in the surface region of the -type silicon carbide layer 71. The n-type region 82 is formed, for example, between the second p ⁺ type region 61a and the p ⁺ type region 81 in contact with these regions. The depth d3 and the impurity concentration of the n-type region 82 may be, for example, about 0.4 μm and about 1.0 × 10 ¹⁷ / cm ³ , respectively.

The n-type region 82 is a part of the n-type current diffusion region 33a. The portion of the n ^- type silicon carbide layer 71 sandwiched between the n-type region 82, the second p ⁺ type region 61a and the p ⁺ type region 81, and the n ⁺ type starting substrate 31 is the n ^- type drift region 32. .. Then, the ion implantation mask (not shown) used for forming the n-type region 82 is removed. The formation order of the n-type region 82 and the second p ⁺ type region 61a and the p ⁺ type region 81 may be interchanged.

Next, as shown in FIG. 10, n ^- -type n doped with n-type impurities further on the silicon carbide layer 71 such as nitrogen or the like ^- a type thickness t12 of the silicon carbide layer for example 0.5μm by epitaxial growth, The thickness of the n ^- type silicon carbide layer 71 is increased.

Next, the p ⁺ type region 83 is formed in the portion 71a where the thickness of the n ^- type silicon carbide layer 71 is increased by photolithography and ion implantation of a p-type impurity such as Al at a depth reaching the p ⁺ type region 81. Form selectively. The p ⁺ type regions 81 and 83 adjacent to each other in the depth direction Z are connected to each other to form the first p ⁺ type region 62a. The width and impurity concentration of the p ⁺ type region 83 are substantially the same as, for example, the p ⁺ type region 81. Then, the ion implantation mask (not shown) used for forming the p ⁺ type region 83 is removed.

Next, the n-type region 84 is selected at a depth reaching the n-type region 82 in the portion 71a in which the thickness of the n ^- type silicon carbide layer 71 is increased by photolithography and ion implantation of an n-type impurity such as nitrogen. Form. The impurity concentration of the n-type region 84 is substantially the same as that of, for example, the n-type region 82. The n-type regions 82 and 84 adjacent to each other in the depth direction Z are connected to each other to form the n-type current diffusion region 33a. The formation order of the p ⁺ type region 83 and the n type region 84 may be exchanged. Then, the ion implantation mask (not shown) used for forming the n-type region 84 is removed.

Next, as shown in FIG. 11, a p-type silicon carbide layer 72 doped with a p-type impurity such as Al is epitaxially grown on the n ^- type silicon carbide layer 71. The thickness t13 and the impurity concentration of the p-type silicon carbide layer 72 may be, for example, about 1.3 μm and about 4.0 × 10 ¹⁷ / cm ³ , respectively. As a result, the semiconductor substrate (semiconductor wafer) 10 in which the n ^- type silicon carbide layer 71 and the p-type silicon carbide layer 72 are sequentially laminated on the n ⁺ type starting substrate 31 is formed by epitaxial growth.

Next, the steps of photolithography, ion implantation, and removal of the ion implantation mask are repeated under different conditions, and the p-type silicon carbide layer 72 is subjected to the n ⁺ type source region of the semiconductor device 20 in the main effective region 1a. 35a and p ⁺⁺ type contact region 36a are selectively formed.

The formation order of the n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a may be interchanged. The portion sandwiched between the n ⁺ type source region 35a, the p ⁺⁺ type contact region 36a, and the n ⁻ type silicon carbide layer 71 becomes the p type base region 34a. In each of the above-mentioned ion implantations, for example, a resist film or an oxide film may be used as an ion implantation mask.

Next, the diffusion regions formed by ion implantation (first and second p ⁺ type regions 62a and 61a, n-type current diffusion region 33a, n ⁺ type source region 35a and p ⁺⁺ type contact region 36a) are subjected to impurity activation. For example, heat treatment (activation annealing) for about 2 minutes is performed at a temperature of about 1700 ° C. The activation annealing may be performed once after the formation of all the diffusion regions, or may be performed after each diffusion region is formed by ion implantation.

Next, as shown in FIG. 12, a trench 37a penetrating the n ⁺ type source region 35a and the p-type base region 34a is formed by photolithography and, for example, dry etching. The trench 37a has a depth that reaches, for example, a second p ⁺ type region 61a inside the n-type current diffusion region 33a. For the etching mask for forming the trench 37a, for example, a resist film or an oxide film may be used. Then, the etching mask is removed.

Next, as shown in FIG. 13, a gate insulating film 38a is formed along the surface of the semiconductor substrate 10 and the inner wall of the trench 37a. The gate insulating film 38a may be, for example, a thermal oxide film formed at a temperature of about 1000 ° C. in an oxygen (O ₂ ) atmosphere, or a sedimentary film formed by high temperature oxidation (HTO: High Temperature Oxide). Good. Next, inside the trench 37a, for example, a phosphorus-doped polysilicon layer is formed as the gate electrode 39a on the gate insulating film 38a.

Next, the interlayer insulating film 40 is formed on the entire front surface of the semiconductor substrate 10. The interlayer insulating film 40 may be, for example, PSG (Phospho Silicate Glass). The thickness of the interlayer insulating film 40 may be, for example, about 1 μm. Next, the interlayer insulating film 40 and the gate insulating film 38a are selectively removed by photolithography and etching to form the first contact hole 40a.

At this time, a first contact hole 40a that exposes the n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a is formed. Next, the interlayer insulating film 40 is flattened (reflowed) by heat treatment.

Next, for example, the first TiN film 42a is formed on the entire front surface of the semiconductor substrate 10 by sputtering. The first TiN film 42a covers the entire surface of the interlayer insulating film 40, and the portion of the front surface of the semiconductor substrate 10 exposed to the first contact hole 40a (n ⁺ type source region 35a and p ⁺⁺ type contact). Covers region 36a).

Next, by photolithography and etching, the portion covering the semiconductor substrate 10 is removed inside the first contact hole 40a of the first TiN film 42a, and the n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a are exposed again. Let me. As a result, the first TiN film 42a is left as the barrier metal 46a on the entire surface of the interlayer insulating film 40.

Next, a Ni film (not shown) is formed on the semiconductor portion (front surface of the semiconductor substrate 10) exposed to the first contact hole 40a by, for example, sputtering. At this time, a Ni film is also formed on the first TiN film 42a. Next, for example, by heat treatment at about 970 ° C., the contact portion of the Ni film with the semiconductor portion is silicidized to form a NiSi film 41a that makes ohmic contact with the semiconductor portion.

During the heat treatment for silicifying nickel, the first TiN film 42a is arranged between the interlayer insulating film 40 and the Ni film, so that the nickel atoms in the Ni film are diffused into the interlayer insulating film 40. Can be prevented. The portion of the Ni film on the interlayer insulating film 40 is not silicinated because it is not in contact with the semiconductor portion. After that, the portion of the Ni film on the interlayer insulating film 40 is removed to expose the interlayer insulating film 40.

Next, for example, a Ni film is formed on the back surface of the semiconductor substrate 10. Next, for example, by heat treatment at about 970 ° C., the Ni film is silicinated to form a NiSi film that makes ohmic contact with the semiconductor portion (the back surface of the semiconductor substrate 10) as the drain electrode 51. The heat treatment for silicidation when forming the NiSi film to be the drain electrode 51 may be performed at the same time as the heat treatment for forming the NiSi film 41a on the front surface of the semiconductor substrate 10.

Next, by sputtering, the first Ti film 43a, the second TiN film 44a, and the second Ti film 45a to be the barrier metal 46a and the Al film (or Al alloy film) to be the source pad 21a are placed on the front surface of the semiconductor substrate 10. ) And are stacked in order. The thickness of the Al film is, for example, about 5 μm or less.

Next, the metal film deposited on the front surface of the semiconductor substrate 10 is patterned by photolithography and etching to leave a portion to be the barrier metal 46a.

Next, for example, by sputtering, for example, a Ti film, a Ni film, and a gold (Au) film are laminated in this order on the surface of the drain electrode 51 to form a drain pad (not shown).

Next, for example, the front surface of the semiconductor substrate 10 is protected by a polyimide film by a chemical vapor deposition (CVD) method. Next, the polyimide film is selectively removed by photolithography and etching to form a first protective film 49a that covers each of the electrode pads, and the first protective film 49a is opened.

Next, after the general pre-plating treatment, the plating film 47a is formed on the portion of the source pad 21a exposed to the opening of the first protective film 49a by the general plating treatment. At this time, the first protective film 49a functions as a mask that suppresses the wetting and spreading of the plating film 47a. The thickness of the plating film 47a may be, for example, about 5 μm.

Next, for example, a polyimide film to be a second protective film 50a covering each boundary between the plating film 47a and the first protective film 49a is formed by a CVD method. Next, the terminal pins 48a are joined onto the plating film 47a with solder layers (not shown). At this time, the second protective film 50a functions as a mask for suppressing the wetting and spreading of the solder layer.

After that, the semiconductor device 20 shown in FIG. 2 is completed by dicing (cutting) the semiconductor substrate 10 into individual chips.

As described above, according to the method for selecting a silicon carbide semiconductor device according to the embodiment, a current of a predetermined frequency is applied to the silicon carbide semiconductor device, and the time and voltage are increased when the current increases for a short time. Silicon carbide semiconductor devices are selected based on whether or not a hump (maximum value) is generated in the curve of. Thereby, the silicon carbide semiconductor device that can be driven at a specific switching frequency can be selected, and the silicon carbide semiconductor device that can be driven at a high frequency can be selected.

In the embodiment, the quality of the n-type epitaxial layer is inspected by inspecting the built-in diode of the MOSFET. That is, it is judged that there are few crystal defects in the n-type epitaxial layer unless a hump is generated in the relationship between voltage and time when the current increases at a high frequency. This is applicable to silicon carbide semiconductor devices having built-in diodes other than MOSFETs. It can also be applied to diodes.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set in various ways according to the required specifications and the like. Further, in each of the above-described embodiments, the case where silicon carbide is used as the wide bandgap semiconductor is described as an example, but it can also be applied to a widebandgap semiconductor such as gallium nitride (GaN) other than silicon carbide. Is. Further, in each embodiment, the first conductive type is n-type and the second conductive type is p-type, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. It holds.

As described above, the method for selecting silicon carbide semiconductor devices according to the present invention is useful for high withstand voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines.

10 Semiconductor substrate 16a Built-in diode of main semiconductor element 20 Semiconductor device 21a Source pad 31 n ⁺ type Departure board 32 n ^- type drift region 33an type current diffusion region 34a p type base region 35a n ⁺ type source region 36a p ⁺⁺ type Contact area 37a Trench 38a Gate insulating film 39a Gate electrode 40 Interlayer insulating film 40a Contact hole 41a NiSi film 42a First TiN film 43a First Ti film 44a Second TiN film 45a Second Ti film 46a Barrier metal 47a Plating film 48a Terminal pin 49a First protection Film 50a Second protective film 51 Drain electrode 61a, 62a p ⁺ type region 71 n ^- type silicon carbide layer 72p type silicon carbide layer X Direction parallel to the front surface of the semiconductor chip (first direction)
Y Direction parallel to the front surface of the semiconductor chip and orthogonal to the first direction (second direction)
Z Depth direction 101 n ⁺ type silicon carbide substrate 102 n type silicon carbide epitaxial layer 103 p ⁺ type base area 104 p type base layer 105 n ⁺ type source area 106 p ⁺ type contact area 107 n type well area 108 Gate insulating film 109 Gate electrode 110 Source electrode 111 Drain electrode

Claims (5)

A method for selecting silicon carbide semiconductor devices having a built-in diode.
The first step of passing a forward current of a predetermined frequency through the built-in diode of the silicon carbide semiconductor device, and
The silicon carbide semiconductor device in which a maximum value is generated in the time and voltage curves when the forward current increases for a time shorter than the time during which the forward current is in the ON state during one cycle of the predetermined frequency. The second step of sorting and
A method for selecting a silicon carbide semiconductor device, which comprises. The third step of increasing the predetermined frequency and
The silicon carbide semiconductor device in which the forward current of the increased frequency is passed through the silicon carbide semiconductor device, and the maximum value is generated in the time and voltage curve when the forward current is increased for the short time. The fourth step of sorting and
The method for selecting a silicon carbide semiconductor device according to claim 1, further comprising. The silicon carbide semiconductor device is
A first conductive type first semiconductor layer provided on the front surface of a silicon carbide semiconductor substrate, and
A second conductive type second semiconductor layer provided on the opposite side of the first semiconductor layer with respect to the silicon carbide semiconductor substrate side,
A first conductive type first semiconductor region having a higher impurity concentration than the silicon carbide semiconductor substrate, which is selectively provided on the surface layer of the second semiconductor layer,
The gate insulating film in contact with the second semiconductor layer and
A gate electrode provided on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer, and
The first semiconductor region, the first electrode provided on the surface of the second semiconductor layer, and
A second electrode provided on the back surface of the silicon carbide semiconductor substrate and
The method for selecting a silicon carbide semiconductor device according to claim 1 or 2, wherein the silicon carbide semiconductor device is provided. The silicon carbide semiconductor device is
Further provided with a trench that penetrates the second semiconductor layer and reaches the first semiconductor layer.
The method for selecting a silicon carbide semiconductor device according to claim 3, wherein the gate electrode is provided inside the trench via the gate insulating film. The method for selecting a silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the withstand voltage of the silicon carbide semiconductor device is 3300 V or more.

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