JP7008276B2 - Mounting board and its manufacturing method - Google Patents

Description

The embodiments of the present disclosure relate to a mounting board and a method for manufacturing the same.

A substrate including the first surface and the second surface, a plurality of holes provided in the substrate so as to penetrate from the first surface to the second surface, and provided inside the holes so as to extend from the first surface to the second surface. A through electrode substrate including an electrode portion is disclosed in Patent Document 1.

Such a through electrode substrate can be used when manufacturing a mounting substrate with a thin film capacitor. At this time, a thin film capacitor can be configured by laminating the first conductive layer, the insulating layer, and the second conductive layer on the first surface or the second surface of the substrate in this order. Such a capacitor May be connected to the electrode portion.

Japanese Unexamined Patent Publication No. 2011-3925

In the mounting substrate as described above, the first conductive layer and the second conductive layer can be formed by the seed layer and the electrolytic plating layer, respectively. At this time, the material for forming the seed layer of the first conductive layer and the material for forming the seed layer of the second conductive layer may be the same.

However, if the forming material of each seed layer is the same, the seed layer of the first conductive layer may be side-etched when the seed layer of the second conductive layer is etched. Such side etching can cause relatively large defects in the first conductive layer, especially when the capacitor is fine.

It is an object of the present disclosure to provide a mounting substrate in which an undesired loss of a conductive layer is suppressed.

In one embodiment of the present disclosure, a substrate, a first conductive layer, an insulating layer, and a second conductive layer are laminated in this order, and the first conductive layer includes a first seed layer and a first plating layer. The first seed layer and the first plating layer are laminated on the substrate in this order, and the second conductive layer has a second seed layer and a second plating layer, and the first The two seed layers and the second plating layer are laminated on the insulating layer in this order, and the first seed layer contains a material having corrosion resistance to an etching solution for etching the second seed layer. It is a substrate.

In the mounting substrate according to the embodiment of the present disclosure, the first seed layer includes a base metal layer containing a metal oxide, a coated metal layer containing the same material as the metal material contained in the first plating layer, and the like. The base metal layer and the coating metal layer may be laminated on the substrate in this order, and the base metal layer may be in close contact with the substrate.

In the mounting substrate according to the embodiment of the present disclosure, the metal oxide contained in the base metal layer is zinc oxide, and the metal material contained in the coated metal layer and the first plating layer is copper. There may be.

The mounting substrate according to the embodiment of the present disclosure may include palladium between the base metal layer and the coating metal layer.

In the mounting substrate according to the embodiment of the present disclosure, the second seed layer may contain titanium.

In the mounting substrate according to the embodiment of the present disclosure, the substrate may be a glass substrate.

Further, one embodiment of the present disclosure includes a first seed layer and a first plating layer, and a first conductive layer in which the first seed layer and the first plating layer are laminated on a substrate in this order. A step of providing a second seed layer so as to cover the first conductive layer, the insulating layer and the substrate after laminating and patterning the insulating layer on the substrate in this order, and one of the second seed layers. A step of etching the second seed layer with an etching solution so that the portion remains on the surface of the insulating layer on the side opposite to the side of the first conductive layer, and on the second seed layer after etching. The step of forming a second plating layer and forming a second seed layer and a second conductive layer having the second plating layer is provided, and the first seed layer is etched with the second seed layer. This is a method for manufacturing a mounting substrate, which is formed from a material having corrosion resistance to an etching solution.

In the manufacturing method according to the embodiment of the present disclosure, a base metal layer containing a metal oxide and a coated metal layer containing the same material as the metal material contained in the first plating layer are laminated on the substrate in this order. Then, the step of forming the first seed layer may be further provided, the base metal layer may be formed by a solgel method or a dip coat, and the coated metal layer may be formed by an electroless plating treatment.

In the production method according to the embodiment of the present disclosure, the metal oxide contained in the base metal layer is zinc oxide, and the metal material contained in the coating metal layer and the first plating layer is copper. There may be.

In the production method according to the embodiment of the present disclosure, the first seed layer may be formed by providing palladium on the base metal layer and then forming the coating metal layer.

In the production method according to the embodiment of the present disclosure, the second seed layer may contain titanium.

In the manufacturing method according to the embodiment of the present disclosure, a glass substrate may be used as the substrate.

In the manufacturing method according to the embodiment of the present disclosure, the substrate has a main surface on which the first conductive layer, the insulating layer and the second conductive layer are laminated, and a hole formed in the main surface. The base metal layer is formed by the solgel method or dip coating so that the first conductive layer is located so as to straddle the main surface and the holes, and the coated metal layer is electroless plated. It may be formed by treatment.

According to the embodiment of the present disclosure, it is possible to provide a mounting substrate in which an undesired loss of the conductive layer is suppressed.

It is sectional drawing which shows the mounting board which concerns on one Embodiment. It is sectional drawing which shows the mounting board in an enlarged manner. It is a top view which shows the 1st surface 1st conductive layer, etc. of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is a figure which shows the manufacturing process of a mounting board. It is sectional drawing of an example of the element mounting substrate in which an element is mounted on the mounting substrate. It is a figure which shows the example of the product which mounts a mounting board.

Hereinafter, the configuration of the mounting board and the manufacturing method thereof according to the embodiment of the present disclosure will be described in detail with reference to the drawings. It should be noted that the embodiments shown below are examples of the embodiments of the present disclosure, and the present disclosure is not construed as being limited to these embodiments. Further, in the present specification, terms such as "board", "base material", "sheet" and "film" are not distinguished from each other based only on the difference in names. For example, "base material" and "base material" are concepts including members that can be called sheets or films. Furthermore, the terms such as "parallel" and "orthogonal" and the values of length and angle used in the present specification to specify the shape and geometric conditions and their degrees are bound by a strict meaning. Instead, the interpretation shall be made to include the range in which similar functions can be expected. Further, in the drawings referred to in the present embodiment, the same parts or parts having similar functions may be designated by the same reference numerals or similar reference numerals, and the repeated description thereof may be omitted. Further, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

Mounting Board Hereinafter, embodiments of the present disclosure will be described. First, the configuration of the mounting board 10 according to the present embodiment will be described. FIG. 1 is a cross-sectional view showing a mounting board 10.

The mounting board 10 includes a board 12, a through electrode 22, a first wiring structure portion 30, and a second wiring structure portion 40. Hereinafter, each component of the mounting board 10 will be described.

(substrate)
The substrate 12 is a plate-shaped base material having a pair of main surfaces facing each other, and includes a first surface 13 and a second surface 14 located on the opposite side of the first surface 13. The first surface 13 and the second surface 14 are surfaces corresponding to the main surface. Further, the substrate 12 is provided with a plurality of through holes 20 from the first surface 13 to the second surface 14.

The substrate 12 contains an inorganic material having a certain insulating property. For example, the substrate 12 includes a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al ₂ O ₃ ) substrate, an aluminum nitride (AlN) substrate, a diriconia oxide (ZrO ₂ ) substrate, and the like. Alternatively, these substrates are laminated. The substrate 12 may partially include a substrate made of a conductive material such as an aluminum substrate or a stainless steel substrate. In this embodiment, the substrate 12 is a glass substrate.

Examples of the glass used in the substrate 12 include non-alkali glass and the like. Non-alkali glass is glass that does not contain alkaline components such as sodium and potassium. The non-alkali glass contains, for example, boric acid instead of the alkaline component. Further, the non-alkali glass contains, for example, an alkaline earth metal oxide such as calcium oxide and barium oxide. Examples of non-alkali glass include EN-A1 manufactured by Asahi Glass and Eagle XG manufactured by Corning. When the substrate 12 contains glass, the thickness of the substrate 12 is, for example, 0.25 mm or more and 0.45 mm or less. Since the substrate 12 contains glass, the insulating property of the substrate 12 can be improved. As a result, when the capacitor 15 is formed by a part of the first wiring structure portion 30 as described later, the withstand voltage characteristic of the capacitor 15 can be enhanced.

In the example shown in FIG. 1, the through hole 20 formed in the substrate 12 has a shape in which the width decreases from the first surface 13 and the second surface 14 of the substrate 12 toward the central portion in the thickness direction of the substrate 12. ing. More specifically, the through hole 20 in this example has a circular shape in a plan view, and the inner peripheral surface thereof, that is, the portion of the side wall 21 from the end portion on the first surface 13 side to the central portion in the thickness direction of the substrate 12 and the portion. Each of the inner peripheral surface, that is, the portion of the side wall 21 from the end portion on the second surface 14 side to the central portion in the thickness direction of the substrate 12, is tapered toward the central portion side. However, the shape of the through hole 20 is not particularly limited. For example, the side wall 21 of the through hole 20 may extend from the second surface 14 to the first surface 13 along the normal direction of the first surface 13 of the substrate 12. Further, a part of the side wall 21 may be curved.

The length of the through hole 20, that is, the dimension of the through hole 20 in the normal direction of the first surface 13, is equal to the thickness of the substrate 12. The width of the through hole 20, that is, the dimension S of the through hole 20 in the in-plane direction of the first surface 13, is, for example, 40 μm or more and 150 μm or less. Further, the ratio of the length to the width of the through hole 20, that is, the aspect ratio of the through hole 20, is, for example, 4 or more and 10 or less. The width of the through hole 20 described here means the maximum width of the through hole 20 in the in-plane direction.

(Through Silicon Via)
The through electrode 22 is a member located inside the through hole 20 and having conductivity. In the present embodiment, the thickness of the through electrode 22 is smaller than the width of the through hole 20, so that there is a space inside the through hole 20 in which the through electrode 22 does not exist. That is, the through silicon via 22 is a so-called conformal via. The thickness of the through electrode 22 is, for example, 100 nm or more and 20 μm or less.

FIG. 2 is an enlarged cross-sectional view showing a through electrode 22 or the like provided in the through hole 20. As long as the through electrode 22 has conductivity, the configuration of the through electrode 22 is not particularly limited. For example, the through silicon via 22 may be composed of a single layer having conductivity, or may include a plurality of layers having conductivity. In the present embodiment, as shown in FIG. 2, the through electrode 22 has a first seed layer 22S and a first plating layer 22P arranged in order from the side wall 21 side of the through hole 20 to the center side of the through hole 20.

The first seed layer 22S serves as a base for growing the first plating layer 22P by precipitating metal ions in the plating solution during the electrolytic plating step of forming the first plating layer 22P by the electrolytic plating treatment. It is a layer having conductivity. The first seed layer 22S in the present embodiment has a base metal layer 221 containing a metal oxide and a coated metal layer 222 containing the same material as the metal material contained in the first plating layer 22P, and is a base. The metal layer 221 and the coated metal layer 222 are laminated on the side wall 21 of the through hole 20 in this order, and the base metal layer 221 is in close contact with the side wall 21.

The base metal layer 221 is an adhesion layer formed by a sol-gel method or a dip coat, and the coated metal layer 222 is an electroless plating layer formed by an electroless plating treatment. When the base metal layer 221 containing the metal oxide is adhered to the side wall 21 by a sol-gel method or a dip coat, and the coated metal layer 222 is formed on the base metal layer 221 by electroless plating, the adhesion is high. Moreover, the present inventor has found through diligent research that it is possible to form a seed layer that is flat while suppressing the film thickness and that suppresses the generation of pinholes. Based on this finding, in the present embodiment, the first seed layer 22S is formed by using the base metal layer 221 and the coating metal layer 222.

The metal oxide contained in the base metal layer 221 is not particularly limited as long as it has good adhesion in relation to the substrate 12, but in the diligent research of the present inventor, the substrate 12 is made of glass. In the case of a substrate, it has been found that the underlying metal layer 221 is firmly adhered to the substrate 12 by using zinc oxide as the metal oxide.

Further, the coated metal layer 222 is not particularly limited as long as it has good adhesion in relation to the underlying metal layer 221 and flatness can be ensured after electroless plating, but the intent of the present inventor's research. Then, when the substrate 12 is a glass substrate and the metal oxide contained in the base metal layer 221 is zinc oxide, the coated metal layer 222 is formed by using copper as the metal material contained in the coated metal layer 222. It has been found that the metal layer 221 is firmly adhered to the base metal layer 221 and is flattened while suppressing the film thickness, and the generation of pinholes is suppressed. Therefore, in the present embodiment, in order to form a suitable through electrode 22, the substrate 12 is a glass substrate, the metal oxide contained in the base metal layer 221 is zinc oxide, and the coated metal layer. The metal material contained in 222 is copper.

When the substrate 12 is a glass substrate, the metal oxide contained in the base metal layer 221 is zinc oxide, and the metal material contained in the coated metal layer 222 is copper, the thickness of the base metal layer 221 is set to 0. It is preferable to form the coating metal layer 222 in the range of 0.2 μm or more and 1.0 μm or less while forming it on the side wall 21 of the through hole 20 in the range of 05 μm or more and 0.2 μm or less. When the first seed layer 22S is formed in such a range, it is possible to form a useful first seed layer 22S in the through hole 20 which has high adhesion and is flat while suppressing the film thickness. The inventor of the present invention has confirmed by experiment. Further, when the first seed layer 22S is formed under such conditions, the first plating layer 22P on the first seed layer 22S can also be formed flat while suppressing the film thickness.

Further, the first seed layer 22S may include palladium between the base metal layer 221 and the coating metal layer 222. Such palladium functions as a catalyst and can promote the precipitation of the coated metal layer 222.

On the other hand, the first plating layer 22P is a layer having conductivity formed by the electrolytic plating treatment. As the material constituting the first plating layer 22P, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, chromium, an alloy using these, or a laminated material thereof shall be used. Can be done. In the present embodiment, since the material constituting the first plating layer 22P is the same as the material contained in the coated metal layer 222, copper is contained.

(1st wiring structure part)
Next, the first wiring structure portion 30 will be described. The first wiring structure portion 30 has a layer such as a conductive layer or an insulating layer provided on the first surface 13 side so as to form an electric circuit on the first surface 13 side of the substrate 12. In the present embodiment, the capacitor 15 is configured by a part of the first wiring structure portion 30. Further, a part of the inductor 16 is formed by a part of the first wiring structure portion 30. In the present embodiment, the first wiring structure portion 30 includes a first surface first conductive layer 31, a first surface first inorganic layer 32, a first surface second conductive layer 33, and a first surface first coated organic layer 34. It has a first surface third conductive layer 35 and a first surface second coated organic layer 36.

[First surface, first conductive layer]
The first surface first conductive layer 31 is a layer having conductivity located on the first surface 13 of the substrate 12. The first surface first conductive layer 31 may be electrically connected to the through electrode 22. In the present embodiment, the through electrode 22 is electrically connected to the first surface first conductive layer 31. There is. The first surface first conductive layer 31 of this example is formed in the same process as the through electrode 22, and has a first seed layer 22S and a first plating layer 22P as shown in FIG. Further, the first seed layer 22S on the first surface 13 includes a base metal layer 221 containing a metal oxide and a coated metal layer 222 containing the same material as the metal material contained in the first plating layer 22P. The underlying metal layer 221 and the coated metal layer 222 are laminated on the first surface 13 of the substrate 12 in this order, and the underlying metal layer 221 is in close contact with the first surface 13.

As described above, the base metal layer 221 is an adhesion layer formed by a sol-gel method or a dip coat, and the coating metal layer 222 is an electroless plating layer formed by an electroless plating treatment. In the present embodiment, the metal contained in the base metal layer 221 also in the first seed layer 22S on the first surface 13 in order to ensure high adhesion as in the case of the first seed layer 22S in the through hole 20. The oxide is zinc oxide, and the metal material contained in the coated metal layer 222 is copper.

When the substrate 12 is a glass substrate, the metal oxide contained in the base metal layer 221 is zinc oxide, and the metal material contained in the coated metal layer 222 is copper, the base metal is on the first surface 13. The thickness of the coated metal layer 222 is formed in the range of 0.2 μm or more and 1.0 μm or less while the thickness of the layer 221 is formed on the first surface 13 of the substrate 12 in the range of 0.05 μm or more and 0.2 μm or less. Is preferable. In such a case, a useful first seed layer 22S having high adhesion and being flat while suppressing the film thickness can be formed on the first surface 13. Further, the first plating layer 22P on the first seed layer 22S can also be formed flat while suppressing the film thickness.

Further, the first seed layer 22S constituting the first surface first conductive layer 31 may also be provided with palladium between the base metal layer 221 and the coating metal layer 222. On the other hand, the first plating layer 22P constituting the first surface first conductive layer 31 is a layer having conductivity formed by the electrolytic plating treatment. As the material constituting the first plating layer 22P, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, chromium, an alloy using these, or a laminated material thereof shall be used. Can be done. In the present embodiment, since the material constituting the first plating layer 22P is the same as the material contained in the coated metal layer 222, copper is contained.

[First surface, first inorganic layer]
The first surface first inorganic layer 32 is a layer that is at least partially located on the first surface first conductive layer 31 and contains an inorganic material and has an insulating property. As the inorganic material of the first surface first inorganic layer 32, a silicon nitride such as SiN can be used. In addition, as an example of the inorganic material of the first surface first inorganic layer 32, silicon oxide, aluminum oxide, tantalum pentoxide and the like can be mentioned. The relative permittivity of the inorganic material of the first surface first inorganic layer 32 is, for example, 3 or more and 50 or less. The thickness of the first surface first inorganic layer 32 is, for example, 50 nm or more and 400 nm or less. The first surface first inorganic layer 32 may be composed of a single layer or may include a plurality of layers.

[First surface, second conductive layer]
The first surface second conductive layer 33 is a layer having conductivity located on the first surface first inorganic layer 32. The above-mentioned first surface first conductive layer 31, the above-mentioned first surface first inorganic layer 32 located on the first surface first conductive layer 31, and the first surface located on the first surface first inorganic layer 32. The surface second conductive layer 33 constitutes the capacitor 15. As shown in FIG. 2, the first surface second conductive layer 33 has a second seed layer 33S and a second plating layer 33P, and the second seed layer 33S and the second plating layer 33P are first in this order. It is laminated on the surface first inorganic layer 32.

The second seed layer 33S serves as a base for growing the second plating layer 33P by precipitating metal ions in the plating solution during the electrolytic plating step of forming the second plating layer 33P by the electrolytic plating treatment. It is a layer having conductivity. The second seed layer 33S in the present embodiment has a base metal layer 331 and a coating metal layer 332 containing the same material as the metal material contained in the second plating layer 33P, and includes the base metal layer 331 and the coating. The metal layer 332 is laminated on the first surface first inorganic layer 32 in this order. Both the base metal layer 331 and the coated metal layer 332 are sputter layers formed by sputtering. In the present embodiment, the metal material contained in the base metal layer 331 is titanium, and the metal material contained in the coated metal layer 332 is copper.

On the other hand, the second plating layer 33P is a layer having conductivity formed by the electrolytic plating treatment. As the material constituting the second plating layer 33P, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, chromium, an alloy using these, or a laminated material thereof shall be used. Can be done. In the present embodiment, since the material constituting the second plating layer 33P is the same as the material contained in the coated metal layer 332, copper is contained.

In the second plating layer 33P, the base metal layer 331 containing titanium is formed by etching, and the coated metal layer 332 containing copper is formed on the base metal layer 331 by etching to form the second seed layer 33S. Next, the second seed layer 33S can be formed by etching with an etching solution, patterning, and then performing an electrolytic plating treatment. In such a step, when the second seed layer 33S is etched, a situation may occur in which the first seed layer 22S is side-etched. Therefore, in the present embodiment, the above-mentioned first seed layer 22S contains a material having corrosion resistance to the etching solution for etching the second seed layer 33S.

Specifically, the base metal layer 331 of the second seed layer 33S contains titanium, whereas the base metal layer 221 of the first seed layer 22S contains zinc oxide. When etching the base metal layer 331, for example, TI-391 manufactured by Meltex Inc. can be used as the etching solution, and zinc oxide has corrosion resistance to such an etching solution. As a result, in the present embodiment, when the base metal layer 331 of the second seed layer 33S is etched, it is suppressed that the base metal layer 221 of the first seed layer 22S is missing, and the base metal layer 221 does not. It is in a state where the desired omission has not occurred.

[First surface, first coated organic layer]
Next, the first surface first-coated organic layer 34 is located on the first surface first inorganic layer 32 and on the first surface second conductive layer 33, and is a layer containing an organic material and having insulating properties. As the organic material of the first coated organic layer 34 on the first surface, polyimide, epoxy or the like can be used. The organic material of the first surface first coated organic layer 34 has a dielectric loss tangent of preferably 0.003 or less, more preferably 0.002 or less, still more preferably 0.001 or less. By constructing the first surface first-coated organic layer 34 using an organic material having a small dielectric loss tangent, it is possible that an electric signal to pass through the capacitor 15 and the inductor 16 passes through the first surface first-coated organic layer 34. It can be suppressed. As a result, the band of the mounting board 10 including the capacitor 15 and the inductor 16 can be expanded to the high frequency side.

[First surface, third conductive layer]
The first surface third conductive layer 35 is a layer having conductivity located on the first surface first conductive layer 31 or the first surface second conductive layer 33. In the example shown in FIG. 1, the first surface third conductive layer 35 is a portion connected to the first surface first conductive layer 31 which is one electrode of the capacitor 15, and the other electrode of the capacitor 15. The portion connected to the second conductive layer 33 on the first surface is included.

The first surface third conductive layer 35 may include a seed layer and a plating layer laminated in order, similarly to the through electrode 22 and the first surface first conductive layer 31. The material constituting the first surface third conductive layer 35 may be the same as the material constituting the through electrode 22 and the first surface first conductive layer 31.

[First surface, second coated organic layer]
The first surface second coated organic layer 36 is a layer located on the first surface first coated organic layer 34 and on the first surface third conductive layer 35, containing an organic material, and having an insulating property. Similar to the first surface first-coated organic layer 34, the first surface second-coated organic layer 36 preferably has a dielectric loss tangent of 0.003 or less, more preferably 0.002 or less, still more preferably 0.001 or less. Includes organic materials that have. As the organic material of the first surface second coated organic layer 36, polyimide, epoxy or the like can be used as in the case of the first surface first coated organic layer 34.

(2nd wiring structure part)
Next, the second wiring structure unit 40 will be described. The second wiring structure portion 40 has a layer such as a conductive layer or an insulating layer provided on the second surface 14 side so as to form an electric circuit on the second surface 14 side of the substrate 12. The inductor 16 is composed of a part of the second wiring structure part 40, a part of the first wiring structure part 30 described above, and the through silicon via 22. In the present embodiment, the second wiring structure portion 40 has a second surface first conductive layer 41 and a second surface first coated organic layer 43.

[Second surface, first conductive layer]
The second surface first conductive layer 41 is a layer having conductivity located on the second surface 14 of the substrate 12. The second surface first conductive layer 41 may be connected to the through electrode 22, and in the present embodiment, the through electrode 22 is connected to the second surface first conductive layer 41. Since the second surface first conductive layer 41 is formed in the same process as the through electrode 22 and the first surface first conductive layer 31, it has a first seed layer 22S and a first plating layer 22P. The first seed layer 22S on the second surface 14 also has a base metal layer 221 containing a metal oxide and a coated metal layer 222 containing the same material as the metal material contained in the first plating layer 22P. The underlying metal layer 221 and the coated metal layer 222 are laminated on the second surface 14 in this order, and the underlying metal layer 221 is in close contact with the second surface 14.

Also in the first seed layer 22S on the second surface 14, the base metal layer 221 is an adhesion layer formed by a sol-gel method or a dip coat, and the coating metal layer 222 is an electroless plating process. It is a plating layer. The metal oxide contained in the base metal layer 221 is zinc oxide, and the metal material contained in the coated metal layer 222 is copper.

On the other hand, the first plating layer 22P constituting the second surface first conductive layer 41 is a layer having conductivity formed by the electrolytic plating treatment. As the material constituting the first plating layer 22P, a metal such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, chromium, an alloy using these, or a laminated material thereof shall be used. Can be done. In the present embodiment, since the material constituting the first plating layer 22P is the same as the material contained in the coated metal layer 222, copper is contained.

FIG. 3 is a plan view of the first surface first conductive layer 31 and the second surface first conductive layer 41 of the mounting substrate 10 when viewed from the first surface 13 side. In FIG. 3, layers such as the first surface first inorganic layer 32 laminated on the first surface first conductive layer 31 are omitted. Further, in FIG. 3, the second surface first conductive layer 41 located on the second surface 14 side is represented by a dotted line. As shown in FIGS. 1 and 3, the first surface first conductive layer 41, the through electrode 22 connected to the second surface first conductive layer 41, and the first surface first conductive layer connected to the through electrode 22. The layer 31 constitutes the inductor 16. Incidentally, FIG. 1 is a cross-sectional view taken along the line AA of FIG.

[Second surface, first coated organic layer]
The second surface first coated organic layer 43 is a layer located on the second surface first conductive layer 41, containing an organic material, and having an insulating property. The second surface first-coated organic layer 43 is preferably 0.003 or less, more preferably 0.002 or less, and further, similarly to the first surface first-coated organic layer 34 and the first surface second-coated organic layer 36. It preferably contains an organic material having a dielectric loss tangent of 0.001 or less. As the organic material of the second surface first-coated organic layer 43, polyimide, epoxy or the like can be used as in the case of the first surface first-coated organic layer 34 and the first surface second-coated organic layer 36.

Manufacturing Method of Mounting Board Hereinafter, an example of the manufacturing method of the mounting board 10 will be described with reference to FIGS. 4 to 17.

(Step of forming through holes)
First, a through hole 20 is formed in the substrate 12. At this time, first, a resist layer is provided on at least one of the first surface 13 and the second surface 14 of the substrate 12 before the through hole 20 is formed. After that, an opening is provided in the resist layer at a position corresponding to the through hole 20. Next, by processing the substrate 12 at the opening of the resist layer, a through hole 20 can be formed in the substrate 12 as shown in FIG. As a method for processing the substrate 12, a dry etching method such as a reactive ion etching method or a deep digging reactive ion etching method, a wet etching method, or the like can be used.

(Step of forming through silicon via and first conductive layer)
Next, the through electrode 22 is formed on the side wall 21 of the through hole 20. In the present embodiment, at the same time as the through silicon via 22, the first surface first conductive layer 31 is formed on the first surface 13 of the substrate 12, and the second surface first conductive layer is formed on the second surface 14 of the substrate 12. Form 41.

At this time, first, as shown in FIG. 5, a base metal layer 221 containing zinc oxide is formed on the first surface 13, the second surface 14, and the side wall 21 of the through hole 20. In this embodiment, the base metal layer 221 is formed by the sol-gel method. Next, as shown in FIG. 6, a resist layer 37 is partially formed on the base metal layer 221. Subsequently, as shown in FIG. 7, a coated metal layer 222 containing copper is formed on the base metal layer 221. In this embodiment, the coated metal layer 222 is formed by electroless plating. As a result, the first seed layer 22S is formed on the first surface 13, the second surface 14, and the side wall 21 of the through hole 20.

When the base metal layer 221 containing zinc oxide is formed by the sol-gel method, for example, the base metal layer 221 can be formed by the sol-gel method using an ethanol solution containing zinc acetate dihydrate, placeodium acetate, and diethanolamine. can.

Subsequently, as shown in FIG. 8, a first plating layer 22P containing copper is formed on the first seed layer 22S. The first plating layer 22P is formed by electrolytic plating. Then, as shown in FIG. 9, the resist layer 37 is removed. Further, the portion of the base metal layer 221 that was covered by the resist layer 37 is removed by, for example, wet etching. In this way, the first surface first conductive layer 31, the second surface first conductive layer 41, and the through silicon via 22 having a desired pattern are formed on the substrate 12. As a result, the inductor 16 including the second surface first conductive layer 41, the through electrode 22 connected to the second surface first conductive layer 41, and the first surface first conductive layer 31 connected to the through electrode 22. Can be configured.

When palladium is provided between the base metal layer 221 and the coating metal layer 222, a step of adhering palladium to the surface of the base metal layer 221 is performed. In this case, the substrate 12 provided with the base metal layer 221 is immersed in the catalyst solution containing palladium. If the precipitation of the coated metal layer 222 is promoted when the coated metal layer 222 is formed on the base metal layer 221 by electroless plating, it adheres between the base metal layer 221 and the coated metal layer 222. The substance that causes it is not limited to palladium.

(Step of forming the first inorganic layer on the first surface)
Next, as shown in FIG. 10, the first surface first inorganic layer 32 is formed in a patterned state on the first surface first conductive layer 31. At this time, first, the first surface first inorganic layer 32 is first applied to the entire area of the substrate 12 provided with the first surface first conductive layer 31, the second surface first conductive layer 41, etc., for example, plasma CVD, sputtering, etc. Then, the first surface first inorganic layer 32 may be patterned by etching.

(Step of forming the first surface and the second conductive layer)
Next, the first surface second conductive layer 33 is formed on a part of the first surface first inorganic layer 32. At this time, first, as shown in FIG. 11, a base metal layer 331 containing titanium is formed in the entire area of the substrate 12 provided with the first surface first inorganic layer 32 and the like. In this embodiment, the base metal layer 331 is formed by sputtering. Next, as shown in FIG. 12, a coated metal layer 332 containing copper is formed over the entire area of the substrate 12 covered with the base metal layer 331. In this embodiment, the coated metal layer 332 is also formed by sputtering. As a result, the second seed layer 33S having the base metal layer 331 and the coating metal layer 332 before being patterned is formed.

Subsequently, as shown in FIG. 13, the resist layer 38 is formed in the second seed layer 33S at a position where the second plating layer 33P is expected to be formed. Then, as shown in FIG. 14, the portion of the second seed layer 33S that is not covered by the resist layer 38 is removed. At this time, first, the portion of the coated metal layer 332 that is not covered by the resist layer 38 is etched by the etching solution. After that, the portion of the base metal layer 331 that is not covered by the resist layer 38 is etched by the etching solution. As the etching solution for etching the coated metal layer 332 containing copper, for example, CU-3930 manufactured by Meltex Inc. can be used. Further, as the etching solution for etching the base metal layer 331 containing titanium, for example, TI-391 manufactured by Meltex Inc. can be used.

In the substrate 12 after etching the coated metal layer 332 as described above, the base metal layer 331 of the second seed layer 33S is directly bonded to the end portion of the base metal layer 221 of the first seed layer 22S. It becomes. Therefore, when the base metal layer 221 of the first seed layer 22S does not have corrosion resistance to the etching solution used when etching the base metal layer 331 of the second seed layer 33S, the base metal layer 221 is used. Situations where side etching can occur. However, in the present embodiment, as described above, the base metal layer 221 is formed of a material having corrosion resistance to the etching solution for etching the base metal layer 331 of the second seed layer 33S. As a result, it is possible to prevent the base metal layer 221 of the first seed layer 22S from being missing when the base metal layer 331 of the second seed layer 33S is etched.

Then, as shown in FIG. 15, the resist layer 38 is removed. After that, as shown in FIG. 16, the second plating layer 33P is formed on the second seed layer 33S by the electrolytic plating treatment. In this way, the first surface second conductive layer 33 is formed. As a result, the first surface first conductive layer 31, the first surface first inorganic layer 32 on the first surface first conductive layer 31, and the first surface second conductive layer on the first surface first inorganic layer 32. A capacitor 15 including 33 can be configured.

After that, as shown in FIG. 17, the first surface first coated organic layer 34 is formed in a desired pattern on a part of the first surface second conductive layer 33 and on a part of the first surface first inorganic layer 32. .. Next, the second surface first coated organic layer 43 is formed in a desired pattern on a part of the second surface first conductive layer 41 and on a part of the second surface 14 of the substrate 12. After that, the first surface third conductive layer 35 and the first surface second coated organic layer 36 are sequentially formed, and the mounting substrate 10 is formed.

In the present embodiment described above, the substrate 12, the first surface first conductive layer 31, the first surface first inorganic layer 32 as an insulating layer, and the first surface second conductive layer 33 are the same. Stacked in order. The first surface first conductive layer 31 has a first seed layer 22S and a first plating layer 22P, and the first seed layer 22S and the first plating layer 22P are laminated on the substrate 12 in this order. The first surface second conductive layer 33 has a second seed layer 33S and a second plating layer 33P, and the second seed layer 33S and the second plating layer 33P are laminated on the first surface first inorganic layer 32 in this order. Has been done. The first seed layer 22S contains a material having corrosion resistance to the etching solution for etching the second seed layer 33S.

As a result, a part of the second seed layer 33S remains on the surface of the first surface first inorganic layer 32 opposite to the side of the first surface first conductive layer 31. When the base metal layer 331 is etched with the etching solution, it is possible to prevent the base metal layer 221 of the first seed layer 22S from being chipped. Therefore, according to the present embodiment, it is possible to provide a mounting substrate 10 in which an undesired loss of the conductive layer is suppressed. In the present embodiment, the first seed layer 22S and the second seed layer 33S have two layers, and each of these seed layers may be a single layer. Further, in the present embodiment, the through electrode 22 is provided in the through hole 20, but even if a concave hole is formed in the substrate 12 and an electrode portion is provided in the hole and this is connected to the conductive layer. good.

(Confirmation test on the usefulness of the underlying metal layer containing zinc oxide)
By the way, in the present embodiment, as described above, the base metal layer 221 of the first seed layer 22S contains zinc oxide and is formed by the sol-gel method. The usefulness in this case will be described below by taking Experimental Examples 1 to 3 as an example.

In Experimental Example 1, the base metal layer 221 of the first seed layer 22S containing zinc oxide was formed by the sol-gel method, and the coated metal layer 222 containing copper was formed by electroless plating. The first plating layer 22P was formed on the first seed layer 22S thus formed by an electrolytic plating treatment to form a through electrode 22 and a first surface first conductive layer 31. In this state, confirmation tests were conducted on the adhesion strength, fine wiring reproducibility, pinhole generation status, and continuity status.

In Experimental Example 2, the base metal layer 221 of the first seed layer 22S containing titanium was formed by sputtering. Then, the through electrode and the conductive layer connected to the through electrode were formed by the same treatment as in Example 1. Then, in this state, a confirmation test was conducted on the adhesion strength, the reproducibility of fine wiring, the state of occurrence of pinholes, and the state of continuity, as in Experimental Example 1.

In Experimental Example 3, a seed layer containing copper was formed by electroless plating without providing a layer corresponding to the base metal layer 221 of the first seed layer 22S, and then a plating layer containing copper was formed by electrolytic plating. , A through electrode and a conductive layer connected to it were formed. Then, in this state, a confirmation test was conducted on the adhesion strength, the reproducibility of fine wiring, the state of occurrence of pinholes, and the state of continuity, as in Experimental Example 1.

In each experimental example, the substrate 12 is a glass substrate. Further, the first surface first conductive layer 31 is formed with a line width of 8 μm.

In the adhesion strength confirmation test, the first surface first conductive layer 31 was subjected to a tensile test with an Instron type tensile tester, and the force when each conductive layer was peeled off was measured.

In the confirmation test of the fine wiring reproducibility, it was observed with a microscope whether or not the first surface first conductive layer 31 thus finely formed was peeled off and whether or not there was an appearance defect.

In the confirmation test of the state of occurrence of pinholes, it was observed with a microscope whether or not pinholes were generated in the first conductive layer 31 on the first surface.

In the continuity state confirmation test, in each experimental example, the continuity state was confirmed by an open short test via 100 through electrodes.

The results of each confirmation test are shown in Table 1 below.

In the above confirmation test, it was confirmed that the base metal layer 221 is particularly useful when it contains zinc oxide and is formed by the sol-gel method. In particular, Experimental Example 1 has a good conduction state with respect to Experimental Examples 2 and 3 because the base metal layer 221 is formed by the sol-gel method, so that the first seed layer 22S in the through hole 20 is disconnected. It is presumed that the reason is that it is effectively suppressed. Therefore, when forming the through silicon via 22, it can be said that it is particularly useful to form the base metal layer 221 containing zinc oxide by the sol-gel method. Further, in Experimental Examples 1 and 2, the peel strength is 6 N / m, but this value is a sufficiently high value as the peel strength.

Element mounting board FIG. 18 is an element mounting board including the mounting board 10 shown in FIG. 1 and an element 61 mounted on the mounting board 10 and electrically connected to a through electrode 22 provided in the through hole 20. It is sectional drawing which shows an example of 60. The element 61 is an LSI chip such as a logic IC or a memory IC. Further, the element 61 may be a MEMS (Micro Electro Mechanical Systems) chip. A MEMS chip is an electronic device in which machine element parts, sensors, actuators, electronic circuits, etc. are integrated on one substrate. As shown in FIG. 18, the element 61 has a terminal 62 electrically connected to a conductive layer such as the first surface third conductive layer 35 of the mounting substrate 10.

Example of a Product on which a Mounting Board is Mounted FIG. 19 is a diagram showing an example of a product on which the mounting board 10 according to the embodiment of the present disclosure can be mounted. The mounting board 10 according to the embodiment of the present disclosure can be used in various products. For example, it is mounted on a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

10 ... Mounting substrate 12 ... Substrate 13 ... First surface 14 ... Second surface 20 ... Through hole 22 ... Through electrode 22S ... First seed layer 22P ... First plating layer 221 ... Underlayer metal layer 222 ... Coating metal layer 31 ... First 1st surface 1st conductive layer 32 ... 1st surface 1st inorganic layer 33 ... 1st surface 2nd conductive layer 33S ... 2nd seed layer 33P ... 2nd plating layer 331 ... Underlayer metal layer 332 ... Coating metal layer

Claims (10)

The substrate, the first conductive layer, the insulating layer, and the second conductive layer are laminated in this order.
The first conductive layer has a first seed layer and a first plating layer, and the first seed layer and the first plating layer are laminated on the substrate in this order.
The second conductive layer has a second seed layer and a second plating layer, and the second seed layer and the second plating layer are laminated on the insulating layer in this order.
The first seed layer contains a material having corrosion resistance to an etching solution for etching the second seed layer.
The first seed layer has a base metal layer containing a metal oxide and a coated metal layer containing the same material as the metal material contained in the first plating layer, and the base metal layer and the coated metal. The layers are laminated on the substrate in this order, and the base metal layer is in close contact with the substrate.
The metal oxide contained in the base metal layer is zinc oxide.
The metal material contained in the coating metal layer and the first plating layer is copper.
A mounting substrate comprising palladium between the underlying metal layer and the coated metal layer . The mounting substrate according to claim 1 , wherein the second seed layer contains titanium. The mounting substrate according to claim 1 or 2 , wherein the substrate is a glass substrate. The substrate, the first conductive layer, the insulating layer, and the second conductive layer are laminated in this order.
The first conductive layer has a first seed layer and a first plating layer, and the first seed layer and the first plating layer are laminated on the substrate in this order.
The second conductive layer has a second seed layer and a second plating layer, and the second seed layer and the second plating layer are laminated on the insulating layer in this order.
The first seed layer contains a material having corrosion resistance to an etching solution for etching the second seed layer.
The first seed layer has a base metal layer containing a metal oxide and a coated metal layer containing the same material as the metal material contained in the first plating layer, and the base metal layer and the coated metal. The layers are laminated on the substrate in this order, and the base metal layer is in close contact with the substrate.
A mounting substrate comprising palladium between the underlying metal layer and the coated metal layer . It is a step of forming the first seed layer in the first conductive layer having the first seed layer and the first plating layer, and the first seed layer and the first plating layer are laminated on the substrate in this order. The base metal layer containing the metal oxide and the coated metal layer containing the same material as the metal material contained in the first plating layer are laminated on the substrate in this order to form the first seed layer. And the process to do
A step of laminating and patterning the first conductive layer and the insulating layer on the substrate in this order, and then providing a second seed layer so as to cover the first conductive layer, the insulating layer, and the substrate.
A step of etching the second seed layer with an etching solution so that a part of the second seed layer remains on the surface of the insulating layer on the side opposite to the side of the first conductive layer.
A step of forming a second plating layer on the second seed layer after etching, and forming a second conductive layer having the second seed layer and the second plating layer.
Equipped with
The first seed layer is formed of a material having corrosion resistance to the etching solution for etching the second seed layer.
The base metal layer is formed by a sol-gel method or a dip coat, and is formed.
A method for manufacturing a mounting substrate, wherein the coated metal layer is formed by electroless plating . The metal oxide contained in the base metal layer is zinc oxide.
The method for manufacturing a mounting substrate according to claim 5 , wherein the metal material contained in the coated metal layer and the first plating layer is copper. The method for manufacturing a mounting substrate according to claim 6 , wherein the first seed layer is formed by forming the coated metal layer after providing palladium on the base metal layer. The method for manufacturing a mounting substrate according to claim 6 or 7 , wherein the second seed layer contains titanium. The method for manufacturing a mounting substrate according to any one of claims 6 to 8 , wherein a glass substrate is used as the substrate. The substrate has a main surface on which the first conductive layer, the insulating layer, and the second conductive layer are laminated, and a hole formed in the main surface.
The base metal layer is formed by a sol-gel method or a dip coat so that the first conductive layer is located so as to straddle the main surface and the holes, and the coated metal layer is formed by electroless plating. The method for manufacturing a mounting board according to claim 5 .

Images