JP7059776B2 - Parallelization method, parallelization tool, and multi-core microcontroller - Google Patents

Description

The present invention relates to a parallelization method and a parallelization tool for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer, and a multi-core microcomputer for executing a parallel program generated from the single program.

Conventionally, the parallel compilation method disclosed in Patent Document 1 is known as an example of a parallelization method for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer.

In this parallel compilation method, the source code of a single program is lexically analyzed and parsed and expanded into an intermediate language, and this intermediate language is used to analyze and optimize the dependencies of multiple macro tasks (processing units). And so on. Further, in the conventional parallel compilation method, a parallel program is generated by allocating and scheduling to the core based on the dependency of each macro task and the execution time of each macro task.

Japanese Unexamined Patent Publication No. 2015-1807

A multi-core microcomputer that executes a parallel program has multiple memories such as multiple RAMs and multiple ROMs that can be accessed by multiple cores, and the time required to access multiple memories by multiple cores (access latency). ) Is different, it is possible that the execution time of the parallel program will differ depending on which memory the data is stored in. For example, when the first core and the second core execute the assigned processing units, the data that is accessed from the first core more frequently than the frequency accessed from the second core is accessed from the first core. If the required time is stored in a memory longer than the required access time from the second core, the execution time of the parallel program becomes longer due to the longer access time from the first core, which is frequently accessed. ..

The present invention has been made in view of the above points, and is parallel to a parallelization method for generating a parallel program capable of shortening the access time to the memory by a plurality of cores at the time of executing the parallel program as a whole. The purpose is to provide a computerization tool and a multi-core microcomputer that executes its parallel program.

In order to achieve the above objectives, one of the present disclosures is
From a single program for a single-core microcomputer with one core, there are multiple cores (C0, C1, C2) and multiple memories (L0, L1, L2, G0, G1) that can be accessed by multiple cores. However, the plurality of memories are a parallelization method for generating a parallel program (18a) for a multi-core microcomputer (20) including memories having different access times required for access by a plurality of cores.
For each task consisting of a plurality of processing units included in a single program, the allocation and execution order of the plurality of processing units to the plurality of cores are determined based on the dependency of the plurality of processing units, and the determined plurality of processing units are determined. Parallel program generation procedure (10a to 10e) to generate a parallel program so that a plurality of processing units are executed according to the allocation to the core and the execution order.
Allocation information of multiple processing units to multiple cores, data access information regarding data accessed by multiple processing units, execution frequency information indicating the execution frequency of tasks, and access to each of multiple memories by multiple cores is required. Storage memory determination procedure (10h) that determines the memory for storing data from a plurality of memories so that the access time to data by a plurality of cores is shortened as a whole based on the access required time information indicating the time. When,
A memory map generation procedure (10i) for generating a memory map (18b) showing the relationship between the data determined by the storage memory determination procedure and the storage destination memory thereof is provided.

According to the parallelization method of the present disclosure, in the storage memory determination procedure, information on allocation of a plurality of processing units to a plurality of cores, data access information on data accessed by a plurality of processing units, and execution frequency indicating the execution frequency of a task are shown. By using information and access time information indicating the time required to access each of multiple memories by multiple cores, the access time to data by multiple cores can be shortened as a whole. From the inside, it becomes possible to determine the memory to store the data.

Then, according to the parallelization method of the present disclosure, a memory map showing the relationship between the determined data and the memory of the storage destination is generated in the memory map generation procedure. By using this memory map, it is possible to determine the memory for storing each data so as to satisfy the relationship between the data included in the memory map and the storage destination memory in the multi-core microcomputer. As a result, the data access time by the plurality of cores of the multi-core microcomputer can be shortened as a whole, and the execution time of the parallel program can be shortened.

The other one of this disclosure is
From a single program for a single-core microcomputer with one core, there are multiple cores (C0, C1, C2) and multiple memories (L0, L1, L2, G0, G1) that can be accessed by multiple cores. However, the plurality of memories are parallelization tools for generating a parallel program (18a) for a multi-core microcomputer (20) including memories having different access times required for access by a plurality of cores.
For each task consisting of multiple processing units included in a single program, the allocation and execution order of multiple processing units to multiple cores are determined based on the dependencies of multiple processing units, and the determined plurality of processes are determined. A parallel program generator (10a to 10e) that generates a parallel program so that a plurality of processing units are executed according to the allocation to the core and the execution order.
Allocation information of multiple processing units to multiple cores, data access information regarding data accessed by multiple processing units, execution frequency information indicating the execution frequency of tasks, and access to each of multiple memories by multiple cores is required. A storage memory determination unit (10h) that determines a memory for storing data from a plurality of memories so that the access time to data by a plurality of cores is shortened as a whole based on the access required time information indicating the time. When,
According to the parallelization tool of the present disclosure, which comprises a memory map generation unit (10i) that generates a memory map (18b) showing the relationship between the data determined by the storage memory determination unit and the storage destination memory thereof. The memory determination unit determines the allocation information of multiple processing units to multiple cores, data access information regarding data accessed by multiple processing units, execution frequency information indicating the execution frequency of tasks, and multiple memories by multiple cores. By using the access required time information indicating the access required time for each, the memory for storing the data is determined from the multiple memories so that the access time to the data by the multiple cores is shortened as a whole. Will be possible.

Then, the memory map generation unit generates a memory map showing the relationship between the determined data and the memory of the storage destination. By using this memory map, in a multi-core microcomputer, a memory for storing each data can be determined so as to satisfy the relationship between the data included in the memory map and the storage destination memory. As a result, the data access time by the plurality of cores of the multi-core microcomputer can be shortened as a whole, and the execution time of the parallel program can be shortened.

The other one of this disclosure is
A multi-core microcomputer that executes a parallel program (18a) for a multi-core microcomputer (20) having a plurality of cores (C0, C1, C2) generated from a single program for a single-core microcomputer having one core. ,
It has a plurality of memories (L0, L1, L2, G0, G1) that can be accessed by a plurality of cores, and the plurality of memories include memories that require different access times for access by the plurality of cores.
In a parallel program, for each task consisting of multiple processing units included in a single program, the allocation and execution order of multiple processing units to multiple cores are determined based on the dependencies of multiple processing units. It was generated so that multiple processing units would be executed according to the determined allocation to multiple cores and the execution order.
When multiple cores access data stored in multiple memories for the execution of each allocated processing unit, the access target memory is the allocation information to the multiple cores of the multiple processing units. Multiple cores based on data access information about data accessed by multiple processing units, execution frequency information indicating task execution frequency, and access required time information indicating the time required to access each of multiple memories by multiple cores. The memory to store the data is determined from multiple memories so that the access time to the data by the data is shortened as a whole, and it is generated to show the relationship between the determined data and the storage destination memory. It is a memory defined according to the memory map (18b).

The memory map defines the optimum memory for storing the data when a plurality of cores access the data for the execution of the assigned processing unit. Therefore, by using this memory map, it is possible to determine the memory for storing each data so as to satisfy the relationship between the data included in the memory map and the storage destination memory in the multi-core microcomputer. As a result, the data access time by the plurality of cores of the multi-core microcomputer can be shortened as a whole, and the execution time of the parallel program can be shortened.

The reference numbers in parentheses are merely examples of the correspondence with the specific configurations in the embodiments described below, and are intended to limit the scope of the invention in order to facilitate the understanding of the present disclosure. Not what I did.

Further, the technical features described in each claim of the claims other than the above-mentioned features will be clarified from the description of the embodiment described later and the attached drawings.

It is a block diagram which shows the schematic structure of the computer as an automatic parallelization tool in embodiment. It is a block diagram which shows the function of a computer as an automatic parallelization tool in an embodiment. It is a figure which shows an example of the core allocation information which allocated the processing unit of each task to a plurality of cores. It is a figure which shows an example of the data access information about the data which is generated by the data access analysis part, and is accessed by the processing unit of each task. It is a figure which shows an example of the memory arrangement for each core in a multi-core microcomputer. It is a figure which shows an example of the access latency information which shows the access required time from each core to each memory. It is a flowchart which shows the process for deciding the memory which becomes the storage destination for the data stored in a RAM, and creating a memory map. It is a flowchart which shows the process for deciding the memory which becomes the storage destination for the data stored in a data ROM, and creating a memory map. It is a flowchart which shows the process for deciding the memory which becomes the storage destination for the data stored in a code ROM, and creating a memory map. It is a figure which shows an example of the result of having calculated the access frequency to each data by each processing unit per unit time. It is a figure which shows an example of the result of having calculated the access frequency to each data by each core per unit time. It is a figure which shows an example of the result of calculating the total access required time per unit time when it is assumed that each data is stored in each memory in consideration of access latency information.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the present embodiment, the computer 10 as a parallelization tool is a parallel program in which a single program for a single-core microcomputer having one core is parallelized for a multi-core microcomputer 20 having three cores C0, C1 and C2. An example of generating 18a will be described. The number of cores included in the multi-core microcomputer 20 is not limited to three, and may be two or four or more.

As described above, as a background for generating the parallel program 18a from the single program, the program amount tends to increase year by year due to the sophistication of control, but there is a limit to the performance improvement of the single core microcomputer. That is, for example, even if an attempt is made to increase the operating frequency of a single-core microcomputer to improve the processing capacity, there is a limit to increasing the operating frequency, and increasing the operating frequency causes an increase in heat generation and an increase in power consumption. .. Therefore, it is considered effective to apply the multi-core microcomputer 20 for improving the processing capacity by increasing the number of cores.

At this time, if the program developer must appropriately allocate processing to each core and schedule it so that the multi-core capability can be maximized, the program development load increases. Resulting in. In order to reduce the development load of such a program, it is technically significant to automatically generate a parallel program 18a from a single program. Furthermore, by automatically generating the parallel program 18a from the single program, it is possible to effectively utilize the existing software assets developed for the single processor.

First, the configuration of the computer 10 will be described with reference to FIG. The computer 10 corresponds to a parallelization tool that executes a parallelization method, and generates a parallel program 18a from a single program. In this embodiment, the computer 10 is configured to generate a parallel program 18a written in C language based on a single program written in C language. Therefore, as shown in FIG. 2, the parallel program 18a'stored in the ROM of the multi-core microcomputer 20 described later and executed by the multi-core microcomputer 20 is further compiled by the compiler 19 and translated into binary code. Become.

However, the present invention is not limited to this. The single program may be written in a programming language different from C language. Further, the parallel program 18a may be written in, for example, an intermediate language used when analyzing a single program. Alternatively, the computer 10 may generate both a parallel program written in C language and a parallel program written in an intermediate language. Further, the computer 10 may also incorporate the function as the compiler 19 and directly generate the binary code parallel program 18a'.

As shown in FIG. 1, the computer 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, a reading unit 17, and the like. The computer 10 can read the stored contents stored in the storage medium 1 by the reading unit 17. As shown in FIG. 1, for example, the automatic parallelizing compiler 1a is stored in the storage medium 1. Since the computer 10 and the storage medium 1 are the same as the personal computer 100 and the storage medium 180 described in JP-A-2015-1807, refer to JP-A-2015-1807 for details.

The automatic parallelization compiler 1a is software that causes the computer 10 to execute a procedure for generating a parallel program 18a. Therefore, the automatic parallelization compiler 1a enables the computer 10 to execute the parallelization method. In other words, the automatic parallelization compiler 1a is a program including a parallelization method. The computer 10 generates a parallel program 18a as a parallelization tool by executing the automatic parallelization compiler 1a.

Next, with reference to FIG. 2, each function and processing procedure for generating the parallel program 18a from the single program, which the computer 10 as the parallelization tool has, will be described. FIG. 2 is a diagram showing each function and processing procedure of the computer 10 as a functional block. As shown in FIG. 2, the computer 10 includes a lexical analysis unit 10a, a syntax / semantic analysis unit 10b, a dependency analysis unit 10c, a core allocation and scheduling unit 10d, a code generation unit 10e, a task execution frequency analysis unit 10f, and data access. It has functions as an analysis unit 10g, a storage memory determination unit 10h, and a memory map generation unit 10i.

In the present embodiment, as shown in FIG. 2, the computer 10 does not generate a parallel program by analyzing the entire single program for controlling the controlled device at once, but has an independent processing function (task). A parallel program is generated for a single program divided for each. Since the parallel program 18a generated by the present embodiment can increase the execution speed when executed by the multi-core microcomputer 20, it is mounted on a vehicle as a controlled target device, for example, where a quick processing speed is required. It is preferable to use an engine or an electric motor. In this case, the multi-core microcomputer 20 is embodied as an in-vehicle device such as an engine control device, a motor control device, and a hybrid control device mounted on a vehicle.

A single program divided for each task includes a plurality of processing units, and by executing the plurality of processing units, the target processing function for each task can be realized. In this way, the plurality of processing units cooperate to realize the target processing function, for example, a processing unit after referring to the variable data processed in the previous processing unit, or a previous processing unit. Includes the processing unit after being executed by the conditional branch of.

Here, the processing unit refers to a core placement unit or a function, which is the minimum unit when allocating to each core. The core placement unit can be rephrased as a processing block, a macro task, or a simple processing unit. The relationship between the core placement unit and the function is that the core placement unit ≧ function. That is, the function may be the core placement unit itself, or it may be a parent function or a subfunction included in the core placement unit.

The lexical analysis unit 10a and the syntax / semantic analysis unit 10b perform lexical analysis and syntax and meaning analysis on the source code of a single program written in C language, and develop it into an intermediate language. The intermediate language developed by the lexical analysis unit 10a and the syntax / semantic analysis unit 10b includes general-purpose instructions. Since the lexical analysis unit 10a and the syntax / semantic analysis unit 10b correspond to FE3 of JP-A-2015-1807, refer to JP-A-2015-1807 for details.

The dependency analysis unit 10c analyzes the dependency of the processing units included in the single program developed in the intermediate language, and extracts the processing units that can be executed in parallel. Dependencies include data dependencies such that the processing unit executed later refers to variable data updated in the processing unit executed first, and the processing unit executed later is the processing unit executed first. It includes control dependencies such as conditional branch destinations. A plurality of processing units having such a dependency must be executed in a processing order according to the dependency. In the present embodiment, as described above, the single program divided for each task is the target of parallelization. A plurality of processing units included in a single program divided for each task have a data dependency and a control dependency.

The core allocation and scheduling unit 10d allocates (allocates) a plurality of processing units to the three cores C0 to C2 based on the analysis result analyzed by the dependency analysis unit 10c. At this time, the core allocation and scheduling unit 10d allocates a plurality of processing units so that, for example, the processing units that can be executed in parallel are executed in parallel by two or more cores C0 to C2. The core allocation and scheduling unit 10d assigns which processing unit to which core C0 at any timing, such as every time the allocation of the processing unit of each task is completed or when the allocation of the processing unit of all tasks is completed. The core allocation information regarding whether or not it has been allocated to C2 is output to the storage memory determination unit 10h.

FIG. 3 shows an example of core allocation information. In the core allocation information shown in FIG. 3, the tasks included in the single program are two tasks, the first task and the second task, and the first task includes six processing units, and the processing units are included. It shows that the processing unit whose number is "1" and the processing unit whose number is "4" are assigned to the core C0. Further, it is shown that the processing unit whose processing unit number is "2" and the processing unit whose processing unit number is "5" are assigned to the core C1. Further, it is shown that the processing unit whose processing unit number is "3" and the processing unit whose processing unit number is "6" are assigned to the core C2. Regarding the second task, of the four processing units, the processing unit whose processing unit number is "1" and the processing unit whose processing unit number is "4" are assigned to the core C0, and the processing unit number is "2". It shows that the unit is assigned to the core C1 and the processing unit having the processing unit number "3" is assigned to the core C2. The processing unit number is given for convenience in order to distinguish a plurality of processing units included in each task of the first task and the second task.

Further, the core allocation and scheduling unit 10d schedules a plurality of processing units allocated to the three cores C0 to C2. Specifically, the core allocation and scheduling unit 10d determines the execution schedule of each processing unit assigned to the three cores C0 to C2 based on the execution time and the dependency of each processing unit. Since the dependency analysis unit 10c and the core allocation and scheduling unit 10d correspond to MP5 of JP-A-2015-1807, refer to JP-A-2015-1807 for details.

The code generation unit 10e is a program code corresponding to a parallel program so that a plurality of processing units of the corresponding task are executed according to the allocation and execution order to each core C0 to C2 determined by the core allocation and scheduling unit 10d. To generate. The computer 10 outputs the program code generated by the code generation unit 10e as the parallel program 21a1.

The task execution frequency analysis unit 10f analyzes the execution frequency of each task by extracting information on the execution frequency of the corresponding task from the program of the task to be parallelized. Specifically, the task execution frequency analysis unit 10f extracts information indicating the task execution cycle as the task execution frequency information. Then, the task execution frequency analysis unit 10f outputs the extracted execution frequency information to the storage memory determination unit 10h.

In the data access analysis unit 10g, each processing unit included in the single program developed in the intermediate language by the syntax / semantic analysis unit 10b is stored in the memory (RAM, data ROM, code ROM) of the multi-core microcomputer 20. Whether or not it is to be accessed, and if so, the data to be accessed is analyzed. Then, the data access analysis unit 10g collects the analysis result as data access information at an arbitrary timing such as when the analysis of all tasks is completed, and outputs the analysis result to the storage memory determination unit 10h. The data stored in the memory of the multi-core microcomputer 20 accessed by a plurality of processing units included in each task is stored in the variable or constant data stored in the RAM, the constant data stored in the data ROM, and the code ROM. At least one of the function data to be shared as a processing unit is included. The data access analysis unit 10g generates data access information separately for each of the data stored in the RAM, the data stored in the data ROM, and the data stored in the code ROM.

Here, as an example, FIG. 4 shows data access information generated by the data access analysis unit 10g for the data stored in the RAM of the multi-core microcomputer 20. In the example shown in FIG. 4, the data numbers 1 to 10 are stored in the RAM of the multi-core microcomputer 20 and cover all the data accessed by any processing unit of all the tasks included in the parallel program 18a. As, it is a number given for convenience to distinguish those data. However, the data included in the data access information may be limited to the data accessed by a plurality of processing units by excluding the data accessed by a single processing unit. This is because the data accessed by a single processing unit only needs to be stored in the RAM accessible by the core to which the single processing unit is allocated with the shortest access time.

Further, the data access information includes information on which data of each task, which is distinguished by the processing unit number, accesses which data is distinguished by the data number. For example, in the data access information exemplified in FIG. 4, the processing unit whose processing unit number is "1" in the first task is the data whose data number is "1", the data "3", and the data "7". Contains information that each will be accessed once. Further, when the processing unit whose processing unit number of the first task is "2" accesses the data whose data number is "2", the data "3", the data "7", and the data "8", respectively, once. Information is included. The data access information also includes information on which data is to be accessed for each of the other processing units of the first task and each processing unit of the second task.

In the storage memory determination unit 10h, in addition to the above-mentioned task execution frequency information, data access information by each processing unit, and core allocation information of each processing unit, as shown in FIG. 2, each core C0 in the multi-core microcomputer 20 Access latency information (access required time information) 2 indicating the required access time to each memory is input from C2. This access latency information 2 requires access to each memory from each core C0 to C2 by calculation or actual measurement based on the arrangement of each memory for each core C0 to C2 in the multi-core microcomputer 20 that implements the parallel program 18a'in advance. It was converted into data in search of time.

For example, it is assumed that the multi-core microcomputer 20 has a RAM arrangement as shown in FIG. 5 as a memory arrangement for each core C0 to C2. Specifically, in the example shown in FIG. 5, the local RAML0 is arranged in the vicinity of the core C0, the local RAML1 is arranged in the vicinity of the core C1, the local RAML2 is arranged in the vicinity of the core C2, and the core C0 and the core C1 are arranged. The global RAMG0 is arranged so as to be connected to the bus connecting the core C0, and the global RAMG1 is arranged so as to be connected to the bus connecting the core C0 and the core C1 and the core C2. Although omitted in FIG. 5, the multi-core microcomputer 20 has a plurality of data ROMs for storing constant data and the like used for control as memories, and a plurality of code ROMs for storing parallel programs 18a and function data. Also has. The plurality of data ROMs and the plurality of code ROMs also have different access required times from the cores C0 to C2.

In the arrangement of the memories L0 to L2 and G0 to G1 for each core C0 to C2 as shown in FIG. 5, the required access time from the cores C0 to C2 to the memories L0 to L2 and G0 to G1 is obtained and accessed. FIG. 6 shows an example of the results summarized as the latency information 2. Note that FIG. 6 shows the required access time for each instruction execution cycle of the multi-core microcomputer 20 as a time unit.

As shown in FIG. 6, for example, when the core C0 accesses the local RAML0, the time corresponding to one cycle is sufficient. However, when the core C0 accesses the local RAML1, it has 3 cycles, when it accesses the local RAML2, it has 5 cycles, when it accesses the global RAMG0, it has 2 cycles, and when it accesses the global RAMG1, it has 4 cycles. It will take a considerable amount of time. As described above, in general, the memory L0 to L2 arranged in the vicinity of each core C0 to C2 requires a shorter access time by the corresponding cores C0 to C2. On the contrary, the memory arranged apart from each core C0 to C2 (for example, the memory L2 with respect to the core C0) has a longer access time. Therefore, for example, if the data frequently accessed by the processing unit assigned to the core C0 is stored in the local RAML2, the access time from the core C0 to the local RAML2 becomes long, which in turn takes a long time. , There arises a problem that the execution time of the parallel program 18a becomes long.

Therefore, the storage memory determination unit 10h transfers data by a plurality of cores C0 to C2 based on task execution frequency information, data access information by each processing unit, core allocation information by each processing unit, and access latency information 2. A memory for storing data is determined from a plurality of memories (for example, memories L0 to L2 and G0 to G1) so that the access time is shortened as a whole. Then, the memory map generation unit 10i shows the relationship between the data determined by the storage memory determination unit 10h and the storage destination memory, and the memory map 18b showing the address information indicating the storage location of each data in the storage destination memory. To generate.

As described above, the parallel program 18a generated by the computer 10 as a parallelization tool is compiled by the compiler 19 and converted into the parallel program 18a'translated into binary code. As shown in FIG. 2, the compiler 19 refers to the memory map 18b provided by the computer 10 and performs a parallel program 18a'after compilation so as to satisfy the relationship between the data contained in the memory map 18b and the storage destination memory. Defines the memory for storing each data and the address indicating the storage location in the memory. That is, the compiler 19 determines the storage location of each data according to the storage destination memory and the address information of the memory. In this way, by using the memory map 18b, when the parallel program 18a'is executed by the multi-core microcomputer 20, each data is stored so as to satisfy the relationship between the data included in the memory map 18b and the storage destination memory. The memory to be stored can be determined. As a result, the data access time by the plurality of cores C0 to C2 of the multi-core microcomputer 20 can be shortened as a whole, and the execution time of the parallel program 181'can be shortened.

When a memory map related to the data ROM and / or the code ROM is generated, when the parallel program 18a'is mounted on the ROM of the multi-core microcomputer 20, the corresponding data ROM and / or according to the memory map 18b are also generated. Alternatively, the constant data and / or the function data may be stored in the specified address of the code ROM.

Hereinafter, with reference to the flowcharts of FIGS. 7 to 9 and the explanatory diagrams of FIGS. 10 to 12, the storage memory determination unit 10h determines the memory for storing data from the plurality of memories, and the memory map generation unit. Describes in detail the process for generating a memory map. The flowchart of FIG. 7 shows a process for determining a memory to be stored and creating a memory map for the data stored in the RAM. The flowchart of FIG. 8 shows a process for determining a memory to be stored and creating a memory map for the data stored in the data ROM. The flowchart of FIG. 9 shows a process for determining a memory to be stored and creating a memory map for the data stored in the code ROM.

First, the process shown in the flowchart of FIG. 7 will be described. In the first step S100, the execution frequency information of each task is acquired from the task execution frequency analysis unit 10f. Further, the core allocation information to each core C0 to C2 of the processing unit included in each task is acquired from the core allocation and scheduling unit 10d as shown in FIG. Further, the data access information of the data stored in the RAM as shown in FIG. 4 is acquired from the data access analysis unit 10g. It should be noted that the acquisition of each information in step S100 does not have to be performed all at once. For example, it is possible to acquire each information by acquiring a part of each information in a plurality of times and collecting the information acquired so far when all the information can be collected.

In the following step S110, the access frequency from each core C0 to C2 per unit time is calculated for each data based on the execution frequency information, core allocation information, and data access information of each task acquired in step S100. A specific example of calculating the access frequency from each core C0 to C2 will be described in detail with reference to the explanatory diagrams of FIGS. 10 and 11.

First, based on the execution frequency information of each task and the data access information, the access frequency (access count) to each data by each processing unit per unit time as shown in FIG. 10 is calculated. The access frequency to each data by each processing unit per unit time in FIG. 10 is calculated based on the access information to each data in each processing unit shown in FIG. As shown in FIG. 4, the first task has an execution cycle of every 1 ms, and the second task has an execution cycle of every 4 ms. In this way, the execution cycle is different between the first task and the second task, and the first task is executed four times as frequently as the second task. Therefore, the number of data accesses by the processing unit of the first task and the number of data accesses by the processing unit of the second task, which are shown in FIG. 4, cannot be treated as they are.

Therefore, the number of times each data is accessed by the processing unit of each task is calculated per unit time by using the execution cycle of each task. As a result, the meaning of the number of accesses to each data by the processing unit of each task becomes the same. In the example shown in FIG. 10, the unit time is 8 ms. During the unit time of 8 ms, the number of executions of the processing unit included in the first task is eight, and the number of executions of the processing unit included in the second task is two. Therefore, the number of times of access of the data access information shown in FIG. 4 is multiplied by 8 for the processing unit included in the first task and doubled for the processing unit included in the second task. As a result, the access frequency to each data by each processing unit per unit time shown in FIG. 10 can be obtained.

Further, based on the access frequency to each data by each processing unit per unit time as shown in FIG. 10 and the allocation information to each core C0 to C2 of each processing unit as shown in FIG. By summarizing the access frequency (access count) to each data for each core, the access frequency to each data by each core C0 to C2 per unit time as shown in FIG. 11 is calculated. For example, when the core allocation information shown in FIG. 3 is obtained, the processing unit numbers of the first task are "1" and "4", and the processing unit numbers of the second task are "1" and "4". The processing unit is assigned to the core C0. All processing units assigned to core C0 in order to obtain the number of accesses to each data from core C0 per unit time (processing units whose first task processing unit numbers are "1" and "4", and the first The total number of accesses to each data by the processing unit numbers of 2 tasks (processing units of "1" and "4") is calculated for each data. Similarly, in order to obtain the number of accesses to each data from the cores C1 and C2 per unit time, the total number of accesses to each data by all the processing units assigned to the cores C1 and C2 is obtained for each data. By summarizing the total number of accesses to each data from each core C0 to C2 in this way, the access frequency to each data by each core C0 to C2 per unit time shown in FIG. 11 can be obtained.

Next, in step S120 of the flowchart of FIG. 7, access latency information regarding the time required to access each RAM L0, L1, L2, G0, and G1 is acquired from each core C0 to C2 as shown in FIG. In the following step S130, the total access required time per unit time is calculated assuming that each data is stored in each RAM L0, L1, L2, G0, G1. The total required access time can be calculated from the access frequency from each core per unit time in FIG. 11 and the access latency information in FIG.

For example, when the data with the data number "1" is stored in the RAM L0, the access frequency from the core C0 to the data with the data number "1" is 18 times, and the time required to access the RAM L0 is one cycle. , The total required access time from the core C0 to the RAML0 is 18 × 1 = 18 (cycle). Further, the total time required to access the data whose data number is "1" stored in RAML0 from the core C1 and the core C2 is 2 × 3 = 6 (cycle) and 16 × 5 = 80 (cycle), respectively. Become. Therefore, when the data whose data number is "1" is stored in RAML0, the total required access time from each core C0 to C2 is 18 + 6 + 80 = 104 (cycle). Similarly, when the data having the data number "1" is stored in the other RAM L1, L2, G0, G1, the total access required time from each core C0 to C2 can be obtained. Furthermore, for other data, the total access time required from each core C0 to C2 per unit time is calculated and summarized assuming that the data is stored in each RAM L0, L1, L2, G0, G1. Is the total data of the required access time shown in FIG.

In step S140, based on the total data of the required access time, the memory having the minimum total of the required access time is determined as the memory for storing the corresponding data for each data. For example, when the total access required time data shown in FIG. 12 is obtained, the total access required time between RAML0 and RAMG0 is the smallest for the data whose data number is "1". Therefore, the memory for storing the data whose data number is "1" is determined to be RAML1 (or RAMG0). For the data of other data numbers, the memory for storing the corresponding data can be determined in the same manner.

Then, in step S150, in addition to the relationship between each data determined in step S140 and the storage destination RAM, the address of the storage location in the storage destination RAM is determined, and the determined address information is generated as the memory map 18b. ..

The above is the process for determining the memory to be stored in the data stored in the RAM and creating the memory map 18b. As for the data stored in the data ROM and the code ROM, as shown in the flowcharts of FIGS. 8 and 9, basically the same processing as that of the flowchart of FIG. 7 described above is performed to determine the storage destination memory and the memory. Map 18b can be created. Therefore, detailed description of the flowcharts of FIGS. 8 and 9 will be omitted.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

(Modification 1)
For example, in the above-described embodiment, the example in which the multi-core microcomputer 20 includes a plurality of RAMs, data ROMs, and code RAMs, and stores the data stored in the RAMs, data ROMs, and code RAMs in the optimum memory will be described. bottom. However, the multi-core microcomputer 20 includes a plurality of memories for at least one type of memory of RAM, data ROM, and code ROM, and determines the optimum memory for storing data from the plurality of memories. There may be.

(Modification 2)
Further, in the above-described embodiment, in order to determine the memory for storing the data, the total access required time from each core C0 to C2 per unit time is calculated assuming that each data is stored in each memory. An example of selecting the memory that minimizes the total access time required was explained. However, the method for determining the memory for storing data is not limited to this. For example, the core having the highest access frequency per unit time may be selected for each data, and the memory having the shortest access time required from the core may be determined as the memory for storing the corresponding data. In this case, when there are a plurality of cores having the highest access frequency per unit time, it is preferable to determine the global memory between the plurality of cores as the memory for storing the corresponding data.

(Modification 3)
Further, in the above-described embodiment, one type of access required time from each core C0 to C2 to each memory is used as the access latency information. However, if there is a significant difference in the required access time between when each core C0 to C2 makes an access for reading data from each memory and when making an access for writing data to each memory, As the access latency information, the read required time and the write required time may be separately determined.

(Modification example 4)
Further, in the above-described embodiment, an example in which the multi-core microcomputer 20 is applied as an in-vehicle device has been described, but the application target of the multi-core microcomputer 20 is not limited to this.

1 ... Storage medium, 1a ... Automatic parallelizing compiler, 2 ... Access latency information, 10 ... Computer, 10a ... Lexical analysis unit, 10b ... Syntax / semantic analysis unit, 10c ... Dependency analysis unit, 10d ... Core allocation and scheduling unit 10e ... Code generation unit, 10f ... Task execution frequency analysis unit, 10g ... Data access analysis unit, 10h ... Storage memory determination unit, 10i ... Memory map generation unit, 11 ... Display, 12 ... HDD, 13 ... CPU, 14 ... ROM, 15 ... RAM, 16 ... input device, 17 ... reader, 19 ... compiler, 20 ... multi-core computer

Claims (18)

From a single program for a single-core microcomputer having one core, a plurality of cores (C0, C1, C2) and a plurality of memories (L0, L1, L2, G0, G1) accessible by the plurality of cores can be obtained. The plurality of memories are a parallelization method for generating a parallel program (18a) for a multi-core microcomputer (20) including memories having different access required times required for access by the plurality of cores.
For each task composed of a plurality of processing units included in the single program, the allocation and execution order of the plurality of processing units to the plurality of cores are determined based on the dependency of the plurality of processing units. A parallel program generation procedure (10a to 10e) for generating the parallel program so that the plurality of processing units are executed according to the determined allocation to the plurality of cores and the execution order.
Allocation information of the plurality of processing units to the plurality of cores, data access information regarding data accessed by the plurality of processing units, execution frequency information indicating the execution frequency of the task, and the plurality of memories by the plurality of cores. A memory for storing the data from the plurality of memories so that the access time to the data by the plurality of cores is shortened as a whole based on the access required time information indicating the access required time for each of the above. Storage memory determination procedure (10h) to determine
A parallelization method comprising a memory map generation procedure (10i) for generating a memory map (18b) showing a relationship between the data determined by the storage memory determination procedure and the storage destination memory thereof. The storage memory determination procedure is as follows.
The data by the plurality of cores per unit time based on the allocation information of the plurality of processing units to the plurality of cores, the data access information regarding the data accessed by the plurality of processing units, and the execution frequency information of the task. Including the access frequency calculation procedure (S110, S210, S310) for calculating the access frequency to
The parallel according to claim 1, wherein the memory for storing the data is determined based on the access frequency of the data by the plurality of cores and the access required time information for each of the plurality of memories by the plurality of cores. How to make it. The storage memory determination procedure is as follows.
Based on the access frequency of the data by the plurality of cores and the access required time information for each of the plurality of memories by the plurality of cores, the plurality of memories per unit time as the memory for storing the data. It includes a memory selection procedure (S140, S240, S340) that selects the memory that minimizes the total access time required by the core.
The parallelization method according to claim 2, wherein the memory selected by the memory selection procedure is determined as the memory for storing the data. The data accessed by the plurality of cores includes any of variable or constant data stored in the RAM, constant data stored in the data ROM, and function data stored in the code ROM and shared as the processing unit. The parallelization method according to any one of claims 1 to 3, which includes. The parallelization method according to claim 4, wherein the multi-core microcomputer is provided with a plurality of memories for at least one type of memory of the RAM, the data ROM, and the code ROM. A multi-core microcomputer (20) that executes the parallel program generated by the parallelization method according to any one of claims 1 to 5.
When the plurality of cores of the multi-core microcomputer access the data for execution of the processing unit assigned to each, the memory to be accessed is the memory defined according to the memory map. From a single program for a single-core microcomputer having one core, a plurality of cores (C0, C1, C2) and a plurality of memories (L0, L1, L2, G0, G1) accessible by the plurality of cores can be obtained. The plurality of memories are parallelization tools for generating a parallel program (18a) for a multi-core microcomputer (20) including memories having different access required times for access by the plurality of cores.
For each task composed of a plurality of processing units included in the single program, the allocation and execution order of the plurality of processing units to the plurality of cores are determined based on the dependency of the plurality of processing units. A parallel program generation unit (10a to 10e) that generates the parallel program so that the plurality of processing units are executed according to the determined allocation to the plurality of cores and the execution order.
Allocation information of the plurality of processing units to the plurality of cores, data access information regarding data accessed by the plurality of processing units, execution frequency information indicating the execution frequency of the task, and the plurality of memories by the plurality of cores. A memory for storing the data from the plurality of memories so that the access time to the data by the plurality of cores is shortened as a whole based on the access required time information indicating the access required time for each of the above. Storage memory determination unit (10h) that determines
A parallelization tool including a memory map generation unit (10i) that generates a memory map (18b) showing the relationship between the data determined by the storage memory determination unit and the storage destination memory thereof. The storage memory determination unit is
The data by the plurality of cores per unit time based on the allocation information of the plurality of processing units to the plurality of cores, the data access information regarding the data accessed by the plurality of processing units, and the execution frequency information of the task. Includes an access frequency calculation unit (S110, S210, S310) that calculates the access frequency to
The parallel according to claim 7, wherein the memory for storing the data is determined based on the access frequency of the data by the plurality of cores and the access required time information for each of the plurality of memories by the plurality of cores. Tool. The storage memory determination unit is
Based on the access frequency of the data by the plurality of cores and the access required time information for each of the plurality of memories by the plurality of cores, the plurality of memories per unit time as the memory for storing the data. Includes memory selection units (S140, S240, S340) that select the memory that minimizes the total access time required by the core.
The parallelization tool according to claim 8, wherein the memory selected by the memory selection unit is determined as the memory for storing the data. The data accessed by the plurality of cores includes any of variable or constant data stored in the RAM, constant data stored in the data ROM, and function data stored in the code ROM and shared as the processing unit. The parallelization tool according to any one of claims 7 to 9, which includes. The parallelization tool according to claim 10, wherein the multi-core microcomputer is provided with a plurality of memories for at least one type of memory of the RAM, the data ROM, and the code ROM. A multi-core microcomputer (20) that executes the parallel program generated by the parallelization tool according to any one of claims 7 to 11.
When the plurality of cores of the multi-core microcomputer access the data for execution of the processing unit assigned to each, the memory to be accessed is the memory defined according to the memory map. A multi-core microcomputer that executes a parallel program (18a) for a multi-core microcomputer (20) having a plurality of cores (C0, C1, C2) generated from a single program for a single-core microcomputer having one core. ,
The plurality of cores have a plurality of memories (L0, L1, L2, G0, G1) that can be accessed, and the plurality of memories include memories that require different access times for access by the plurality of cores.
In the parallel program, for each task including a plurality of processing units included in the single program, the allocation and execution order of the plurality of processing units to the plurality of cores based on the dependency relationship of the plurality of processing units. Is determined, and the plurality of processing units are generated to be executed according to the determined allocation to the plurality of cores and the execution order.
When the plurality of cores access the data stored in the plurality of memories for the execution of the allocated processing unit, the memory to be accessed is the plurality of cores of the plurality of processing units. Allocation information to, data access information regarding data accessed by the plurality of processing units, execution frequency information indicating the execution frequency of the task, and access indicating the time required to access each of the plurality of memories by the plurality of cores. Based on the required time information, a memory for storing the data is determined from the plurality of memories so that the access time to the data by the plurality of cores is shortened as a whole, and the determined data is determined. A multi-core microcomputer that is a memory defined according to a memory map (18b) generated to show the relationship between the data and the storage destination memory. The multi-core microcomputer is applied to an in-vehicle device for controlling an in-vehicle device mounted on a vehicle, and any one of claims 6, 12, and 13 for controlling the in-vehicle device by executing the parallel program. The multi-core microcomputer described in. The memory map is based on the allocation information of the plurality of processing units to the plurality of cores, the data access information regarding the data accessed by the plurality of processing units, and the execution frequency information of the task. The access frequency of the data by the plurality of cores is calculated, and based on the calculated access frequency of the data by the plurality of cores and the access required time information for each of the plurality of memories by the plurality of cores. The multi-core microcomputer according to claim 13 or 14, wherein a memory for storing data is determined and is generated according to the determined content. Based on the access frequency of the data by the plurality of cores and the access required time information for each of the plurality of memories by the plurality of cores, the plurality of cores per unit time are used as the memory for storing the data. The multi-core microcomputer according to claim 15, wherein a memory having the minimum total access required time is selected, and the selected memory is determined as a memory for storing the data. The data accessed by the plurality of cores includes any of variable or constant data stored in the RAM, constant data stored in the data ROM, and function data stored in the code ROM and shared as the processing unit. The multi-core microcomputer according to any one of claims 13 to 16, including. The multi-core microcomputer according to claim 17, wherein the multi-core microcomputer is provided with a plurality of memories for at least one type of memory of the RAM, the data ROM, and the code ROM.

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