JP6933001B2 - Parallelization method, parallelization tool - Google Patents

Description

The present invention relates to a parallelization method for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer, a parallelization tool, and an in-vehicle device equipped with a parallel program generated by the parallelization method.

Conventionally, there is a parallel compilation method disclosed in Patent Document 1 as an example of a parallelization method for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer.

In this parallel compilation method, the source code of a single program is lexically analyzed and parsed to generate an intermediate language, and the intermediate language is used to analyze the dependencies of multiple macro tasks (hereinafter referred to as processing MT). Perform optimization, etc. Further, in the parallel compilation method, a parallel program is generated by scheduling based on the dependency of each processing MT and the execution time of each processing MT.

Japanese Unexamined Patent Publication No. 2015-1807

However, the processing MT of a single program and the processing unit that is a function also include impossible processing that is a processing unit that cannot analyze the dependency. A multi-core microcomputer may not operate properly if this impossible process is executed in parallel. Therefore, the parallel compilation method cannot parallelize impossible processing.

The present invention has been made in view of the above problems, and is a parallelization method capable of creating a parallel program in which more processing units are parallelized, a parallelization tool, and parallelism in which more processing units are parallelized. An object of the present invention is to provide an in-vehicle device capable of executing a program.

To achieve the above objectives, one of the present disclosures is
A parallel program (21a1) for a multi-core microcomputer (21) having a plurality of cores (21c, 21d) from a single program is analyzed by analyzing the dependency of a plurality of processing units in a single program for a single-core microcomputer having one core. ) Is a parallelization method that generates
The acquisition procedure (10a) for acquiring the dependency information for determining the dependency for the impossible process for which the dependency cannot be analyzed in a plurality of processing units, and the acquisition procedure (10a).
It is possible to analyze dependencies in multiple processing units. Analysis procedure (10b) for analyzing dependencies and analysis procedure (10b) for processing that can be analyzed.
Based on the dependency information acquired in the acquisition procedure and the analysis result analyzed in the analysis procedure, an allocation procedure (10d) for allocating impossible processing and possible processing to each core while satisfying the dependency is provided .
The processing unit is a function
The allocation procedure is to allocate to each core while satisfying the dependency for each core placement unit including at least one function.
The dependency information of the core placement unit including the upper function which is the upper function and the lower function which is the lower function called by the upper function is merged as the information of the uppermost upper function included in the core arrangement unit. Has been done.

In this way, in the parallelization method, even if the dependency cannot be analyzed, the dependency information for determining the dependency of the impossible process can be acquired. Then, in the parallelization method, impossible processing and possible processing are assigned to each core based on the dependency information and the analysis result in the possible processing. Therefore, in the parallelization method, not only possible processing but also impossible processing can be parallelized. Therefore, in the parallelization method, it is possible to create a parallel program in which more processing units are parallelized.

The other one of this disclosure is
A parallel program (21a1) for a multi-core microcomputer (21) having a plurality of cores (21c, 21d) from a single program is analyzed by analyzing the dependency of a plurality of processing units in a single program for a single-core microcomputer having one core. ), A parallelization tool that includes a computer,
An acquisition unit (10a) for acquiring dependency information for determining a dependency for an impossible process for which it is impossible to analyze the dependency in a plurality of processing units.
It is possible to analyze the dependency relationship in multiple processing units. Regarding the processing, the analysis unit (10b) that analyzes the dependency relationship and
It is provided with an allocation unit (10d) that allocates impossible processing and possible processing to each core while satisfying the dependency relationship based on the dependency information acquired by the acquisition unit and the analysis result analyzed by the analysis unit.
The processing unit is a function
The allocation unit is assigned to each core while satisfying the dependency for each core placement unit including at least one function.
The dependency information of the core placement unit including the upper function which is the upper function and the lower function which is the lower function called by the upper function is merged as the information of the uppermost upper function included in the core arrangement unit. Has been done.

In this way, the parallelization tool can create a parallel program in which more processing units are parallelized, similar to the above parallelization method.

The scope of claims and the reference numerals in parentheses described in this section indicate, as one embodiment, the correspondence with the specific means described in the embodiments described later, and define the technical scope of the invention. It is not limited.

It is a block diagram which shows the schematic structure of the computer in embodiment. It is a block diagram which shows the schematic structure of the vehicle-mounted device in an embodiment. It is a block diagram which shows the function of the computer in embodiment. It is a flowchart which shows the processing of the computer in embodiment. It is an image diagram which shows the dependency information which specifies the dependency by the processing unit in embodiment. It is an image diagram which shows the dependency information which specifies the dependency by the resource in the modification 1. It is an image diagram which shows an example of the processing unit in the modification 2. It is an image diagram which shows an example of the dependency relation information in the modification 2. It is a flowchart which shows the processing of the computer in the modification 5. It is an image diagram which shows the processing unit after parallelization in the modification 2. It is an image diagram which shows the relationship between the processing unit and a resource in the modification 3. It is an image diagram which shows the dependency information which specifies the dependency by the processing unit in the modification 3. It is an image diagram which shows the dependency information which specifies the dependency by the resource in the modification 3. It is an image diagram which shows the relationship between the processing unit and a resource in the modification 4. It is an image diagram which shows the dependency information which specifies the dependency by the resource in the modification 4. It is an image diagram which shows the dependency information which the resource and the module are associated with in the modification 4. It is an image which shows the processing unit in the modification 5.

Hereinafter, a plurality of modes for carrying out the invention will be described with reference to the drawings. In each form, the same reference numerals may be given to the parts corresponding to the matters described in the preceding forms, and duplicate explanations may be omitted. In each form, when only a part of the configuration is described, the other parts of the configuration can be applied with reference to the other forms described above.

In the present embodiment, an example of generating a parallel program 21a1 parallelized for a multi-core processor 21 having a first core 21c and a second core 21d from a plurality of processing units in a single program for a single-core microcomputer having one core. Is adopted. The processor can be rephrased as a microcomputer. Therefore, the multi-core processor can be rephrased as a multi-core microcomputer.

The processing unit is a core placement unit or a function, which is the minimum unit when allocating to each core. The core placement unit can be rephrased as a processing block, a macro task, a processing MT, or the like. The relationship between these processing units is core placement unit ≥ function. That is, the function may be the core placement unit itself, or may be a parent function or a subfunction included in the core placement unit. In this embodiment, the processing MT is adopted as the processing unit.

As described above, the background for generating the parallel program 21a1 is that the multi-core processor 21 becomes mainstream due to an increase in the amount of heat generated by the processor, an increase in power consumption, and a problem of a clock frequency limit. The multi-core processor 21 also needs to be applied in the field of in-vehicle devices. Further, the parallel program 21a1 is required to be highly reliable and capable of executing processing at high speed while suppressing the development period and development cost of software.

Here, the configuration of the computer 10 will be described with reference to FIG. The computer 10 corresponds to a parallelization tool that executes the parallelization method, and generates a parallel program 21a1. The computer 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, a reading unit 17, and the like. Further, the computer 10 is configured to be able to read the stored contents stored in the storage medium 18. The automatic parallelizing compiler 1 is stored in the storage medium 18.

For the configurations of the computer 10 and the storage medium 18, refer to the personal computer 100 and the storage medium 180 described in Japanese Patent Application Laid-Open No. 2015-1807. The automatic parallelizing compiler 1 includes a reading unit 10a and the like as shown in FIG. 3 in addition to those described in Japanese Patent Application Laid-Open No. 2015-1807. The reading unit 10a will be described later.

The automatic parallelizing compiler 1 includes a procedure for generating the parallel program 21a1. Therefore, the automatic parallelization compiler 1 corresponds to the parallelization method. That is, the automatic parallelization compiler 1 is a program including a parallelization method. The computer 10 generates the parallel program 21a1 by executing the automatic parallelization compiler 1.

For example, the computer 10 generates a parallel program 21a1 which is a source code written in C language from a single program which is a source code written in C language. However, the present invention is not limited to this. The single program may be written in a programming language different from C language. Similarly, the parallel program 21a1 may be written in a programming language different from the C language.

When the parallel program 21a1 is generated, the dependencies of the plurality of processing MTs in the single program are analyzed, and the plurality of processing MTs are allocated to the different cores 21c and 21d of the multi-core processor 21. In other words, it analyzes the program written for the single-core microcomputer and generates software that parallelizes the processing MT that can be parallelized for the multi-core microcomputer. Allocating can be rephrased as arranging, allocating, or allocating.

When allocating, each of the plurality of processing MTs is assigned to the first core 21c and the second core 21d while maintaining the dependency of the plurality of processing MTs. Regarding this point, refer to Japanese Patent Application Laid-Open No. 2015-1807.

The dependency relationship is, for example, a relationship in which a certain processing MT refers to data updated by a processing MT executed before itself. That is, the plurality of processing MTs include a predecessor process in which the execution order in the single program is first, and a subsequent process to be executed after the execution of the predecessor process is completed. The subsequent processing is a processing MT that is affected by the preceding processing, and is, for example, a processing MT that uses data whose contents may be updated in the preceding processing. More specifically, when both the preceding processing and the succeeding processing only refer to the data, the processing result does not change even if the two processing orders are exchanged, and it can be said that there is no dependency in such a case.

However, the single program also includes impossible processing, which is a processing MT in which dependency analysis is impossible or difficult. Further, the fact that the dependency analysis is impossible or difficult means that the dependency analysis by the dependency analysis unit 10b in the computer 10 described later is impossible or difficult. This impossible processing includes, for example, a pointer-related processing MT. The reason is that it cannot be completely analyzed without the value estimation (behavior estimation) of the variable. However, the impossible processing is not limited to the pointer-related processing MT. Among the processing MTs of the single program, the processing MT capable of analyzing the dependency relationship by the dependency analysis unit 10b is referred to as a possible processing.

As described above, the impossible processing cannot be parallelized because the dependency analysis unit 10b cannot analyze the dependency. When the impossible processing cannot be parallelized, the parallel program 21a1 has only the possible processing in the single program parallelized. In the parallel program 21a1 in which only the possible processing is parallelized, the number of processing MTs that can be executed in parallel by the first core 21c and the second core 21d is smaller than in the case where the possible processing and the impossible processing are parallelized. Therefore, the parallel program 21a1 in which only the possible processing is parallelized cannot operate the first core 21c and the second core 21d more efficiently than in the case where the possible processing and the impossible processing are parallelized. Therefore, the computer 10 also determines the dependency relationship with respect to the impossible processing by using the dependency information 30 indicating the dependency relationship in the impossible processing. The dependency information 30 will be described later.

As shown in FIG. 3, the computer 10 includes a processing time analysis unit 10c, a core allocation unit 10d, and a scheduling unit 1e in addition to the reading unit 10a and the dependency analysis unit 10b as functional blocks. Although illustration and description are omitted, the computer 10 is configured to include a well-known lexical analysis unit and the like.

The reading unit 10a reads the dependency information 30 in order to determine the dependency in the impossible processing. That is, the computer 10 is input with the dependency information 30. The reading unit 10a corresponds to an acquisition unit within the scope of claims. The computer 10 reads the dependency information 30 by executing the automatic parallelizing compiler 1. Therefore, the reading unit 10a can be regarded as corresponding to the procedure for acquiring the claims.

The dependency information 30 is information for determining the dependency in the impossible processing as described above, and is a part of the information used when designing a single program, for example. Therefore, the dependency information 30 can be rephrased as design information.

In particular, the dependency information 30 of the present embodiment is information indicating a processing MT having a dependency relationship with the impossible processing. In other words, the dependency information 30 is information indicating that there is a dependency relationship with respect to a plurality of processing MTs having the dependency relationship, although the dependency relationship analysis unit 10b cannot analyze the dependency relationship. That is, in the dependency information 30 of the present embodiment, the impossible processing and the processing MT having a dependency relationship with the impossible processing are directly linked. Therefore, the dependency information 30 can be rephrased as the direct type information 30.

The direct type information 30 includes, for example, the name of the processing MT that has a dependency relationship with the impossible processing. That is, the direct type information 30 includes the name of the impossible process and the name of the processing MT having a dependency relationship with the impossible process, and the names of the processing MTs having a dependency relationship are associated with each other.

Each information in which the name of the impossible process and the name of the process MT having a dependency relationship with the impossible process are associated with each other can be referred to as a list. Therefore, it can be said that the dependency information 30 includes a list for each impossible process. Then, when the dependency information 30 is read, the dependency information 30 reads the list corresponding to the impossible processing. That is, the dependency information 30 reads a list of target impossible processes from the dependency information 30 including a plurality of lists.

Here, it will be described with reference to the example shown in FIG. The first processing MT writes to the variable V1. The second processing MT reads to 0x000000AA. And the variable V1 and 0x000000AA are the same data. In this case, the first processing MT and the second processing MT have a dependency relationship. However, the dependency analysis unit 10b cannot determine whether or not the variables V1 and 0x000000AA have the same data. In the direct type information 30 in this case, the name of the first processing MT and the name of the second processing MT are associated with each other. Therefore, the computer 10 can determine that there is a dependency relationship between the first processing MT and the second processing MT by using the direct type information 30.

The dependency analysis unit 10b analyzes the dependency with respect to the possible processing. In other words, the dependency analysis unit 10b extracts information for determining the dependency in the possible processing by analyzing the dependency in the possible processing. The dependency analysis unit 10b is a well-known technique. Therefore, a detailed description of the dependency analysis unit 10b will be omitted. The dependency analysis unit 10b corresponds to an analysis unit within the scope of claims. The computer 10 analyzes the dependency by executing the automatic parallelizing compiler 1. Therefore, the dependency analysis unit 10b can be regarded as corresponding to the analysis procedure of the claims.

The core allocation unit 10d performs impossible processing and possible processing based on the dependency information 30 acquired by the reading unit 10a and the analysis result analyzed by the dependency analysis unit 10b, while satisfying the dependency relationships, respectively, for the cores 21c and 21d. Assign to. As described above, since the computer 10 acquires the dependency information 30, the dependency can be determined even for the impossible processing. Therefore, the core allocation unit 10d can be assigned to the cores 21c and 21d not only for possible processing but also for impossible processing.

The core allocation portion 10d corresponds to the allocation portion in the claims. The computer 10 allocates each processing MT to each core by executing the automatic parallelizing compiler 1. Therefore, the core allocation unit 10d can be regarded as corresponding to the procedure for allocating the claims.

The processing time analysis unit 10c and the scheduling unit 10e are well-known techniques. Therefore, detailed description of the processing time analysis unit 10c and the scheduling unit 10e will be omitted.

Next, with reference to FIG. 4, the processing operation when the computer 10 executes the automatic parallelizing compiler 1 will be described. The computer 10 generates the parallel program 21a1 by executing the automatic parallelization compiler 1. It should be noted that each step in FIG. 4 can be regarded as corresponding to the procedure in the automatic parallelizing compiler 1.

In step S10, the unanalyzed processed MT is searched. The computer 10 individually executes the processing of FIG. 4 for each of the plurality of processing MTs in the single program. That is, in step S10, the computer 10 searches for the processing MT that has not been processed after step S12 among the plurality of processing MTs in the single program. In other words, the computer 10 extracts the processed MTs that have not been processed after step S12 from the plurality of processed MTs in the single program.

The impossible process extracted in step S10 this time is also referred to as a target MT. For example, in a single program including the first processed MT, the second processed MT, and the nth processed MT, when the second processed MT is extracted in step S10 this time, the target MT is the second processed MT. n is a natural number of 3 or more.

In step S12, it is determined whether or not there is a target MT in the dependency information (direct type information 30). The computer 10 determines whether or not the processing MT associated with the target MT extracted in step S10 is included in the direct type information 30. If the computer 10 determines that the direct type information 30 includes the target MT, the computer 10 proceeds to step S16, and if it determines that the direct type information 30 includes the target MT, the computer 10 proceeds to step S14.

In step S14, the code in the target MT is analyzed to extract the dependency. That is, the dependency analysis unit 10b of the computer 10 extracts the dependency of each target MT as is well known. In other words, in step S14, the dependency analysis unit 10b of the computer 10 extracts information for determining the dependency in each target MT, that is, the access destination resource and the processing content for the resource. Then, the dependency analysis unit 10b of the computer 10 extracts the processing MT having a dependency relationship with the target MT.

The access destination resource is a resource accessed by the core when the processing MT is executed. The processing content for the resource is writing or reading for the resource. In addition, resources include data, registers, and order constraints. Then, the information in which the access destination resource in the processing unit and the processing content for the resource in the processing unit are associated with each other can be said to be resource access information.

On the other hand, in step S16, the dependency relationship of the target MT is set based on the direct type information 30. That is, the computer 10 makes the processing MT associated with the target MT in the direct type information 30 a dependency relationship of the target MT. In other words, the computer 10 sets the processing MT associated with the target MT in the direct type information 30 as the processing MT having a dependency relationship with the target MT.

By repeatedly executing steps S10 to S16, the computer 10 executes the flowchart of FIG. 4 for all the processing MTs in the single program. Then, the computer 10 allocates impossible processing and possible processing to each core while satisfying the dependency relationship, based on the dependency information and the analysis result analyzed by the dependency analysis unit 10b.

In the parallel program 21a1, two processing MTs having a dependency relationship may be arranged in separate cores 21c and 21d. Therefore, in the parallel program 21a1, when two processing MTs having a dependency relationship are arranged in different cores 21c and 21d, the parallel program 21a1 waits for the processing order assigned to the other cores to complete the execution of the previous processing MT. , Includes synchronous processing to execute later processing MT in the processing order. That is, when the execution of the processing MT assigned to the own core is completed, the parallel program 21a1 waits for the execution of the processing MT assigned to the other core to be completed, and then waits for the execution of the processing MT assigned to the own core to be completed, and then the next processing assigned to the own core. It includes a synchronization process to execute MT. The processing MT allocated to the other core here has a dependency relationship with the next processing MT allocated to the own core, and the execution order is earlier than the next processing MT allocated to the own core.

Therefore, when the execution of the processing MT assigned to the first core 21c and the second core 21d is completed in order to perform the synchronization processing, the first core 21c and the second core 21d access the RAM 21b and indicate that they are waiting for synchronization (information indicating that they are waiting for synchronization ( Hereinafter, completion information) is stored in the RAM 21b. Then, the own core waiting for the completion of execution of the processing MT having a dependency in the other core periodically accesses the RAM 21b without executing the processing MT, and whether or not the completion information is stored in the RAM 21b. To confirm. That is, the own core waiting for the completion of execution of the processing MT having a dependency in the other core operates periodically during non-operation, accesses the RAM 21b, and confirms whether or not the completion information is stored. .. In this way, the first core 21c and the second core 21d execute the processing MT while waiting for each other, in other words, synchronizing with each other. Therefore, the synchronization process can also be called a wait process. The parallel program 21a1 includes a program executed by the first core 21c and a program executed by the second core 21d.

Next, the configuration of the in-vehicle device 20 will be described. As shown in FIG. 2, the in-vehicle device 20 includes a multi-core processor 21, a communication unit 22, a sensor unit 23, and an input / output port 24. Further, the multi-core processor 21 includes a ROM 21a, a RAM 21b, a first core 21c, and a second core 21d. The in-vehicle device 20 can be applied to, for example, an engine control device or a hybrid control device mounted on an automobile. Here, as an example, an example in which the in-vehicle device 20 is applied to the engine control device is adopted. In this case, the parallel program 21a1 can be said to be an automobile control program such as engine control. However, the parallel program 21a1 is not limited to this. The core can also be referred to as a processor element.

The first core 21c and the second core 21d control the engine by executing the parallel program 21a1. More specifically, the first core 21c and the second core 21d perform engine control by executing the processing MT assigned to themselves in the parallel program 21a1 and executing the waiting process and the like. For the RAM 21b, the communication unit 22, the sensor unit 23, and the input / output port 24, refer to the RAM 420, the communication unit 430, the sensor unit 450, and the input / output port 460 described in Japanese Patent Application Laid-Open No. 2015-1807.

As described above, the computer 10 can acquire the direct type information 30 indicating the dependency of the impossible process even if the dependency cannot be analyzed. Then, the computer 10 allocates the impossible process and the possible process to the cores 21c and 21d based on the direct type information 30 and the analysis result in the possible process. Therefore, in the computer 10, in addition to the possible processing, the impossible processing can be parallelized. Therefore, the computer 10 can create a parallel program 21a1 in which more processing MTs are parallelized. That is, the computer 10 can create a parallel program 21a1 in which more processing MTs are parallelized than a parallel program in which only possible processes are parallelized.

The computer 10 analyzes the dependency by executing the automatic parallelizing compiler 1. Therefore, the automatic parallelizing compiler 1 can have the same effect as the computer 10.

Further, the in-vehicle device 20 includes a parallel program 21a1 in which more processing MTs are parallelized. Therefore, the in-vehicle device 20 can optimally execute each processing MT. That is, since the in-vehicle device 20 includes the parallel program 21a1, it can be said that the first core 21c and the second core 21d can be effectively utilized. In other words, the in-vehicle device 20 is more likely to exhibit the performance of the multi-core processor 21 including the first core 21c and the second core 21d than when the in-vehicle device 20 includes a parallel program in which only possible processing is parallelized.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. Hereinafter, modifications 1 to 5 will be described as other embodiments of the present invention. The above-described embodiments and modifications 1 to 5 can be carried out individually, but can also be carried out in combination as appropriate. The present invention is not limited to the combinations shown in the embodiments, but can be implemented by various combinations.

(Modification example 1)
As shown in FIG. 6, the dependency information 31 of the first modification includes the name of the resource to be accessed when the impossible process is executed. That is, although the name of the dependency information 31 is unknown, resources indicating the same data are associated with each other. In other words, in the dependency information 31, the impossible processing and the processing MT having a dependency relationship with the impossible processing are indirectly associated with each other via a resource. Therefore, the dependency information 31 can be said to be indirect information 31.

Here, it will be described with reference to the example shown in FIG. The first processing MT writes to the variable V1. The second processing MT reads to 0x000000AA. And the variable V1 and 0x000000AA are the same data. In this case, the first processing MT and the second processing MT have a dependency relationship. However, the dependency analysis unit 10b cannot determine whether or not the variables V1 and 0x000000AA have the same data. In the indirect type information 31 in this case, the name of the variable V1 and the name of 0x000000AA are associated with each other. That is, the indirect type information 31 includes information (list) indicating that the variable V1 and 0x000000AA are the same data. Further, the indirect type information 31 is information indicating that the variable V1 and 0x000000AA are the same resource.

Therefore, the computer 10 can determine that there is a dependency relationship between the first processing MT and the second processing MT by using the indirect type information 31. Note that each information indicating that the resource and other resources are the same resource can be referred to as a list. Therefore, it can be said that the dependency information 31 includes a list for each resource.

The computer 10 of the first modification can exert the same effect as that of the above embodiment. Similarly, the automatic parallelizing compiler 1 and the in-vehicle device 20 of the modification 1 can achieve the same effect as that of the above embodiment.

(Modification 2)
In the second modification, as shown in FIGS. 7, 8 and 9, a function is adopted as the processing unit. The function is included in the processing MT. In addition, some processing MTs include a plurality of functions.

As shown in FIG. 7, the funcA () function is the writing of the variable X. The funcC () function writes the variable Y. The funcD () function reads the variable X, reads the variable Y, and writes the variable Z. Therefore, the dependency analysis unit 10b can analyze the dependency of the funcA () function, the funcC () function, and the funcD () function. Therefore, the funcA () function, funcC () function, and funcD () function can be regarded as possible processing.

However, the funcB () function includes p = 0x ..., In which the dependency analysis unit 10b cannot grasp the resource. Therefore, the dependency analysis unit 10b cannot analyze the dependency of the funcB () function. Therefore, the funcB () function can be regarded as an impossible process. Note that p = 0x ... Is the address of the variable W. That is, the funcB () function is the writing of the variable W and has nothing to do with the variables X, Y, and Z.

In this case, as shown in FIG. 8, the dependency information 32 includes information indicating that the variable W is written (W) as the resource information of the funcB () function. In this way, in the dependency information 32, the resource of the access destination in the impossible process and the processing content for the resource of the impossible process are associated with the impossible process. It should be noted that each information in which the impossible processing, the resource of the access destination in the impossible processing, and the processing content for the resource of the impossible processing are associated with each other can be referred to as a list. Therefore, it can be said that the dependency information 32 includes a list for each impossible process.

In other words, the dependency information 32 is information that can indirectly associate the impossible process with the function having the dependency relationship with the impossible process via the resource. Therefore, the dependency information 32 can be said to be indirect information.

By referring to the dependency information 32, the computer 10 can grasp the resource to be accessed when each impossible process is executed. Therefore, the computer 10 can grasp the function having the dependency with the impossible processing by referring to the dependency information 32.

As shown in FIG. 8, the dependency information 32 may include a resource list indicating the definition of the resource in addition to the information for determining the dependency of each processing unit. Further, the resource list may be a set with the resource access information for each function. In this case, the association information indicating which function's resource is the same as the resource is added to the resource list.

In addition, the information of the function of another module called from the own function is analyzed at the time of automatic parallelization. Information required at the time of core placement can be obtained by merging and analyzing the call source processing (core placement unit) based on the call relationship.

Next, with reference to FIG. 9, the processing operation when the computer 10 in the modification 2 executes the automatic parallelizing compiler 1 will be described. The computer 10 generates the parallel program 21a1 by executing the automatic parallelization compiler 1. It should be noted that each step in FIG. 9 can be regarded as corresponding to the procedure in the automatic parallelizing compiler 1.

In step S20, an unanalyzed function is searched. The computer 10 individually executes the process of FIG. 9 for each of the plurality of functions in the single program. That is, in step S20, the computer 10 searches for a function that has not been processed after step S22 among the plurality of functions in the single program. In other words, the computer 10 extracts the functions that have not been processed after step S12 from the plurality of functions in the single program.

The impossible processing extracted in step S20 this time is also referred to as a target function. For example, in a single program including the funcA () function to the funcD () function, when the funcB () function is extracted in step S20 this time, the target function is the funcB () function.

In step S22, it is determined whether or not the dependency information 32 has the target function. That is, the computer 10 determines whether or not the resource information of the target function extracted in step S20 is included in the dependency information 32. When the dependency information 32 includes the resource information of the target function, the computer 10 considers that the dependency information 32 has the target function and proceeds to step S26. On the contrary, when the dependency information 32 does not include the resource information of the target function, the computer 10 considers that the dependency information 32 does not have the target function and proceeds to step S24.

In step S24, the code in the target function is analyzed to extract the dependency. That is, the dependency analysis unit 10b of the computer 10 extracts the dependency of the target function as is well known. In other words, in step S24, the dependency analysis unit 10b of the computer 10 extracts information for determining the dependency in each target function, that is, the access destination resource and the processing content for the resource. Then, the dependency analysis unit 10b of the computer 10 extracts the processing MT having a dependency relationship with the target function.

On the other hand, in step S26, the dependency of the target function is set based on the dependency information 32. That is, the computer 10 uses the information related to the target process included in the dependency information 32 as the information for analyzing the dependency. In other words, the computer 10 extracts from the dependency information 32 information for determining the dependency in the target function, that is, the resource to be accessed and the processing content for the resource. For example, when the target function is the funcB () function, the computer 10 adopts the writing of the variable W as the information for analyzing the dependency in the funcB () function. That is, the computer 10 extracts from the dependency information 32 the information about the funcB () function, that is, the writing of the variable W.

In step S28, the dependency of the target function is added to the dependency of the MT to which the target function belongs. The computer 10 adds the information for analyzing the dependency extracted in step S24 and the information for analyzing the dependency extracted in step S26 to the processing MT to which each target function belongs.

By repeatedly executing steps S20 to S28, the computer 10 executes the flowchart of FIG. 9 for all the processing MTs in the single program. Then, the computer 10 allocates impossible processing and possible processing to each core while satisfying the dependency relationship, based on the dependency information and the analysis result analyzed by the dependency analysis unit 10b. As a result, the funcA () and funcD () functions are parallelized as shown in FIG. In FIG. 10, an example is adopted in which each processing MT includes only one function as a function.

The computer 10 of the second modification can exert the same effect as that of the above embodiment. Similarly, the automatic parallelizing compiler 1 and the in-vehicle device 20 of the second modification can achieve the same effects as those of the above embodiment. Further, even when the software is developed in units smaller than the processing MT, the computer 10 and the automatic parallelizing compiler 1 of the modification 2 can achieve the same effect as that of the above embodiment.

(Modification example 3)
A modification 3 will be described with reference to FIGS. 11, 12, and 13. In the third modification, as shown in FIG. 11, the eleventh processing MT, the twelfth processing MT, and the thirteenth processing MT, which are the processing MTs, are adopted as the processing units. Further, the eleventh processing MT writes to the variable V1 and writes to the variable V2. The twelfth processing MT reads the variable V1. The thirteenth processing MT reads the variable V2.

In the third modification, the dependency information 33, which is the direct type information shown in FIG. 12, and the dependency information 34, which is the indirect type information shown in FIG. 13, can be adopted. In the dependency information 33, the twelfth processing MT and the thirteenth processing MT are associated with the eleventh processing MT as the processing MT names having a dependency relationship. Further, in the dependency information 33, the 11th processing MT is associated with the 12th processing MT and the 13th processing MT as the processing MT names having a dependency relationship. The dependency information 33 includes a case where each item is managed as a separate list.

On the other hand, in the dependency information 34, the variable V1 which is the access destination resource in the 11th processing MT and the Write which is the processing content for the variable V1 of the 11th processing MT are associated with the 11th processing MT. There is. Further, the 11th processing MT is associated with the variable V2 which is the access destination resource in the 11th processing MT and the Write which is the processing content for the variable V2 of the 11th processing MT.

Further, in the dependency information 34, the variable V1 which is the access destination resource in the 12th processing MT and the Read which is the processing content for the variable V1 of the 12th processing MT are associated with the 12th processing MT. There is. Further, in the dependency information 34, the variable V2, which is the access destination resource in the 13th processing MT, and the Read, which is the processing content for the variable V2 of the 13th processing MT, are associated with the 13th processing MT. There is. The dependency information 34 includes a case where the dependency information 34 is managed as a separate list for each processing MT.

The computer 10 of the third modification can exert the same effect as that of the above embodiment. Similarly, the automatic parallelizing compiler 1 and the in-vehicle device 20 of the modification 3 can exert the same effect as that of the above embodiment.

(Modification example 4)
A modified example 4 will be described with reference to FIGS. 14, 15, and 16. In the modified example 4, as shown in FIG. 14, the func1a function, the func2a function, and the func3a function, which are functions, are adopted as the processing unit. The func1a function writes to 0xFFFF0000 and writes to pointer access * P. Pointer access * P cannot analyze fingertips. The func2a function reads the variable V1. The func3a function reads 0xFFFF0004.

Here, the case where different names are defined for the resources is adopted in each of the plurality of functions indicating access to the same resource. For example, 0xFFFF0000 and the variable V1 indicate the same resource. However, in the func1a function, 0xFFFF0000 is defined as Unknown2. Also, pointer access * P and 0xFFFF0004 indicate the same resource. However, in the func1a function, pointer access * P is defined as Unknown3. On the other hand, in the func3a function, 0xFFFF0004 is defined as Unknown4.

Further, 0xFFFF0000 and the variable V1 are the data defined in the first Module. The pointer access * P and 0xFFFF0004 are the data defined in the second module. In the following, Module is also referred to as a module.

A module is a unit of function and a unit of software development. A module can also be referred to as a translation unit, and is realized by associating one source file with one translation unit. However, since there is a header file include process, strictly speaking, the program text after preprocessing one source file becomes the translation unit. And the module corresponds to this translation unit. In addition, resources are defined for each module without duplication with other modules.

In the third modification, the dependency information 35 which is the indirect type information shown in FIG. 15 and the dependency information 36 which is the indirect type information shown in FIG. 16 can be adopted.

In the dependency information 35, as in FIG. 13, for each processing unit, the resource of the access destination in each processing unit and the processing content for the resource that is the access destination of each processing unit are associated with each other. Further, the dependency information 35 is associated with a plurality of names indicating the same resource. For example, as shown in FIG. 15, in the dependency information 35, 0xFFFF0000 and Unknown2 are associated with each other, and Unknown3 and Unknown4 are associated with each other. By doing so, the computer 10 can analyze the dependency even if different names are defined for each processing unit even though the resources are the same. Further, the computer 10 does not have to make the resource names defined in each processing unit consistent.

In the dependency information 36, a plurality of names indicating the same resource are associated with each other, and the name and the module in which the resource of the name is defined are associated with each other. For example, as shown in FIG. 16, the variable V1 is associated with the first module. In addition, Unknown2 is associated with the second module.

The computer 10 of the modified example 4 can exert the same effect as that of the above embodiment. Similarly, the automatic parallelizing compiler 1 and the in-vehicle device 20 of the modified example 4 can achieve the same effect as that of the above embodiment.

(Modification 5)
A modified example 5 will be described with reference to FIG. Here, a computer 10 that is assigned to each core while satisfying the dependency is adopted for each processing MT including at least one function. Therefore, the automatic parallelizing compiler 1 includes a procedure of allocating to each core while satisfying the dependency for each processing MT including at least one function. Further, in the modification 5, as shown in FIG. 17, a single program including the 21st processing MT, the 22nd processing MT, and the like is adopted.

The computer 10 extracts the function call relationship of the entire process that is the target of the parallel analysis. The computer 10 searches for a function according to the function call relationship. The computer 10 determines whether or not there is a target process for list input in the target function. The computer 10 analyzes the resource access in the target function. The computer 10 specifies the target range of the list input. The target range of this list input refers to the function written in the resource access list. In other words, it is a processing unit (MT or function) to which resource access is associated with a list.

Computer 10 reads the list from the dependency information. In the processing in the target function, the computer 10 stores the acquired list as the source access information for the target range, and stores the resource access analysis result as the resource access information of the target function for the non-target function. The computer 10 merges the storage result of each target function as the information of the parent function until the processing MT is reached according to the function call relationship. Therefore, the dependency information of the processing MT including the upper function which is the upper function and the lower function which is the lower function called by the upper function is merged as the information of the uppermost upper function included in the processing MT. Has been done.

That is, the computer 10 determines the impossible processing and the possible processing in the processing MT. The impossible process here refers to a process in which a human determines that the process is impossible and inputs a resource access list. On the other hand, the possible processing here refers to processing other than the impossible processing. Then, the computer 10 acquires and stores the resource access information corresponding to the impossible processing from the dependency information, and also stores the resource access information of the possible processing. Further, the computer 10 merges the stored resource access information as the resource access information of the highest-level function (parent function) in the processing MT. Therefore, the dependency information of the processing MT, that is, the resource access information is the information obtained by merging the resource access information of the impossible processing in the processing MT and the resource access information of the possible processing.

The target range is the whole or a part of the processing MT. The list contains the symbol names of the RAMs that the processing in the scope accesses. The list contains the names of the resources that the scoped operations access. The resource name is associated with a processing unit name that is unique throughout the program.

Here, as an example, the single program shown in FIG. 17 will be used for description. The contents of each function in FIG. 17 are indicated by dotted line balloons. In this single program, as a result of searching the 21st processing MT, the function F1 becomes the target function. This function F1 includes a function F2 which is an impossible process, a function F3 which is a possible process, and an indicator which indicates a logic which is an impossible process.

The computer 10 does not analyze (extract) the resource access information in the function F2, but acquires and stores the resource access information from the dependency information. For example, the resource access information of the function F2 is a write to the variable y. Further, the computer 10 moves on to the analysis of the subfunction F4 of the function F2.

Further, since the computer 10 is a possible process in which the function F3 writes to the variable x, the computer 10 does not acquire the resource access information from the dependency information. Then, the computer 10 stores that the variable x is being written as the resource access information of the function F3.

Further, the computer 10 does not analyze (extract) the resource access information in the specified range of the indicator, but acquires and stores the resource access information from the dependency information. For example, the resource access information in the specified range of the specifier is a write to the resource called Unknown4 defined in the third module.

Then, the computer 10 merges the plurality of resource access information stored as described above as the resource access information of the function F1. That is, as a result of merging the resource access information of the functions under the 21st processing MT, the 21st processing MT has a variable x, a variable y, a variable v, a variable w, and a resource called Unknown5 defined in the third module. It is a process of writing. The computer 10 uses the merged resource access information when analyzing the dependency. The 21st processing MT has a dependency relationship with other processing MTs that similarly access the above resources (data, etc.).

The computer 10 of the modified example 5 can exert the same effect as that of the above embodiment. Similarly, the automatic parallelizing compiler 1 and the in-vehicle device 20 of the modified example 5 can achieve the same effect as that of the above embodiment.

Further, the computer 10 of the modified example 5 can determine whether or not analysis is possible (clarification of the part that cannot be analyzed) and information on the part that cannot be analyzed for each function (for each person in charge of software development). Therefore, the computer 10 of the modified example 5 can analyze and parallelize the dependency relationship including the conventional unanalyzable part.

1 ... Automatic parallelizing compiler, 10 ... Computer, 10a ... Reading unit, 10b ... Dependency analysis unit, 10c ... Processing time analysis unit, 10d ... Core allocation unit, 10e ... Scheduling unit, 11 ... Display, 12 ... HDD, 13 ... CPU, 14 ... ROM, 15 ... RAM, 16 ... input device, 17 ... reader, 18 ... storage medium, 20 ... in-vehicle device, 21 ... multi-core processor, 21a ... ROM, 21a1 ... parallel program, 21b ... RAM, 21c ... 1st core, 21d ... 2nd core, 22 ... Communication unit, 23 ... Sensor unit, 24 ... Input / output port, 30-36 ... Dependency information

Claims (10)

A parallel program for a multi-core microcomputer (21) having a plurality of the cores (21c, 21d) from the single program by analyzing the dependency of a plurality of processing units in a single program for a single-core microcomputer having one core. This is a parallelization method for generating (21a1).
The acquisition procedure (10a) for acquiring the dependency information for determining the dependency for the impossible process in which the dependency cannot be analyzed in the plurality of processing units, and the acquisition procedure (10a).
An analysis procedure (10b) for analyzing the dependency relationship and an analysis procedure (10b) for analyzing the dependency relationship in a plurality of processing units capable of analyzing the dependency relationship.
Based on the dependency information acquired in the acquisition procedure and the analysis result analyzed in the analysis procedure, the allocation procedure (10d) in which the impossible process and the possible process are assigned to each core while satisfying the dependency relationship. , With
The processing unit is a function and
In the allocation procedure, each core placement unit including at least one of the functions is assigned to each core while satisfying the dependency.
The dependency information of the core arrangement unit including the upper function which is the upper function and the lower function which is the lower function called by the upper function is the highest-level information included in the core arrangement unit. The parallelization method that is merged as the information of the superordinate function. The parallelization method according to claim 1, wherein the dependency information includes the name of the processing unit having the dependency relationship with the impossible processing. The parallelization method according to claim 1, wherein the dependency information includes a name of a resource to be accessed when the impossible processing is executed. When different names are defined for the resource in each of the plurality of processing units indicating access to the same resource, the dependency information includes the plurality of the names indicating the same resource. The parallelization method according to claim 3, which is linked. The single program is composed of a plurality of translation units, and each translation unit defines the resource without overlapping with other translation units.
The dependency information is a claim in which a plurality of the names indicating the same resource are associated with each other, and the name is associated with the translation unit in which the resource of the name is defined. Item 4. The parallelization method according to Item 4. A parallel program for a multi-core microcomputer (21) having a plurality of the cores (21c, 21d) from the single program by analyzing the dependency of a plurality of processing units in a single program for a single-core microcomputer having one core. A parallelization tool that includes a computer to generate (21a1).
An acquisition unit (10a) for acquiring dependency information for determining the dependency for an impossible process in which the dependency cannot be analyzed in a plurality of processing units.
With respect to possible processing capable of analyzing the dependency relationship in a plurality of the processing units, an analysis unit (10b) for analyzing the dependency relationship and
Based on the dependency information acquired by the acquisition unit and the analysis result analyzed by the analysis unit, the allocation unit (10d) that allocates the impossible process and the possible process to each core while satisfying the dependency relationship. , With
The processing unit is a function and
The allocation unit allocates to each core while satisfying the dependency for each core arrangement unit including at least one of the functions.
The dependency information of the core arrangement unit including the upper function which is the upper function and the lower function which is the lower function called by the upper function is the highest-level information included in the core arrangement unit. A parallelization tool that has been merged as information on the superordinate function. The parallelization tool according to claim 6 , wherein the dependency information includes a name of the processing unit that has a dependency relationship with the impossible processing. The parallelization tool according to claim 6 , wherein the dependency information includes a name of a resource to be accessed when the impossible processing is executed. When different names are defined for the resource in each of the plurality of processing units indicating access to the same resource, the dependency information includes the plurality of the names indicating the same resource. The parallelization tool according to claim 8 , which is linked. The single program is composed of a plurality of translation units, and each translation unit defines the resource without overlapping with other translation units.
The dependency information is a claim in which a plurality of the names indicating the same resource are associated with each other, and the name is associated with the translation unit in which the resource of the name is defined. Item 9. The parallelization tool according to Item 9.

Images