JP6934324B2 - Elastic wave device - Google Patents

Description

The present invention relates to an elastic wave device, for example, an elastic wave device provided with wiring connected to an IDT.

Elastic wave devices are used in filters and the like for mobile communication. It is known that an IDT (Interdigital Transducer) is provided on a piezoelectric substrate bonded onto a support substrate. It is known that the wiring connected to the IDT is provided on the upper surface of the support substrate from which the piezoelectric substrate has been removed (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2016-40882

However, in Patent Document 1, the wiring and the IDT are connected on the piezoelectric substrate. With such a structure, the heat generated in the IDT is not sufficiently released.

The present invention has been made in view of the above problems, and an object of the present invention is to improve heat dissipation.

The present invention includes an IDT having a support substrate, a piezoelectric substrate bonded onto the support substrate, a bus bar provided on the piezoelectric substrate and to which a plurality of electrode fingers and the plurality of electrode fingers are connected, and the above. The opening is filled in the opening provided in the piezoelectric substrate, and includes a first wiring layer in which at least a part of the upper surface is in contact with at least a part of the bus bar of the IDT, and the opening penetrates the piezoelectric substrate. The surface of the first wiring board on the support substrate side does not penetrate the support substrate and comes into contact with the support substrate, and the thermal conductivity of the support substrate and the first wiring layer is higher than the thermal conductivity of the piezoelectric substrate. It is an elastic wave device.

In the above configuration, at least a part of the upper surface of the first wiring layer and the upper surface of the piezoelectric substrate can be flat.

In the above configuration, a second wiring layer provided on the first wiring layer may be provided so as to face the first wiring layer with an insulating film or gap provided in the opening sandwiched therein. can.

In the above configuration, a third wiring layer provided adjacent to the first wiring layer may be provided on the piezoelectric substrate.

In the above configuration, the first wiring layer is provided between the two IDTs and contacts the bus bar of one of the two IDTs, and the third wiring layer is provided between the two IDTs. , The bus bar of the other of the two IDTs can be contacted and adjacent to the first wiring layer.

In the above configuration, an annular metal layer that surrounds the IDT and is embedded in the peripheral edge of the piezoelectric substrate, a substrate mounted on the piezoelectric substrate, and a gap between the IDT and the lower surface of the substrate that surrounds the substrate in a plan view. It can be configured to include a sealing portion for sealing the IDT so as to sandwich and face the IDT.

In the above configuration, the first wiring layer may be provided so as to surround the IDT in a plan view.

In the above configuration, the upper surface of the support substrate may have a recess, and the first wiring layer may be configured to come into contact with the support substrate at least in the recess.

In the above configuration, the configuration may include a filter including the IDT.

In the above configuration, the input terminal and the output terminal are connected in series, each of which is connected in parallel between a plurality of series resonators including the IDT and the input terminal and the output terminal, and each of the above is described. A filter including one or a plurality of parallel resonators including an IDT may be provided, and the first wiring layer may be configured to be connected between at least two of the plurality of series resonators.

In the above configuration, the configuration may include a multiplexer including the filter.

According to the present invention, heat dissipation can be improved.

1 (a) is a plan view of the elastic wave resonator according to the first embodiment, and FIG. 1 (b) is a cross-sectional view taken along the line AA of FIG. 1 (a). 2 (a) to 2 (d) are cross-sectional views (No. 1) showing a method of manufacturing an elastic wave resonator according to the first embodiment. 3 (a) to 3 (c) are cross-sectional views (No. 2) showing a method of manufacturing an elastic wave resonator according to the first embodiment. 4 (a) to 4 (d) are cross-sectional views (No. 1) showing a method of manufacturing an elastic wave resonator according to a modification 1 of the first embodiment. 5 (a) and 5 (b) are cross-sectional views (No. 2) showing a method of manufacturing an elastic wave resonator according to a modification 1 of the first embodiment. 6 (a) to 6 (j) are cross-sectional views showing the wiring layers in the modified examples 2 and 3 of the first embodiment. 7 (a) is a plan view of the filter according to the second embodiment, and FIG. 7 (b) is a cross-sectional view taken along the line AA of FIG. 7 (a). FIG. 8 is a cross-sectional view of the elastic wave device according to the third embodiment. FIG. 9 is a plan view of the piezoelectric substrate according to the third embodiment. FIG. 10 is a circuit diagram of the duplexer according to the fourth embodiment. 11 (a) is a plan view of the duplexer according to the fourth embodiment, and FIG. 11 (b) is a cross-sectional view taken along the line AA of FIG. 11 (a). 12 (a) is a plan view of the filter according to the fifth embodiment, and FIG. 12 (b) is a cross-sectional view taken along the line AA of FIG. 12 (a).

Hereinafter, examples of the present invention will be described with reference to the drawings.

The first embodiment is an example of an elastic wave resonator as an elastic wave device. 1 (a) is a plan view of the elastic wave resonator according to the first embodiment, and FIG. 1 (b) is a cross-sectional view taken along the line AA of FIG. 1 (a). As shown in FIGS. 1A and 1B, the piezoelectric substrate 10 is bonded to the support substrate 11. The support substrate 11 is, for example, a sapphire substrate, an alumina substrate, a spinel substrate, or a silicon substrate. The piezoelectric substrate 10 is, for example, a lithium tantalate substrate or a lithium niobate substrate. The support substrate 11 and the piezoelectric substrate 10 are joined, for example, at room temperature.

An opening is provided in the piezoelectric substrate 10, and the wiring layer 14 is filled in the opening. The wiring layer 14 is, for example, a metal layer such as a copper layer, a gold layer, a silver layer, a tungsten layer, or a molybdenum layer. A metal film 12 is formed on the piezoelectric substrate 10 and the wiring layer 14. The metal film 12 includes, for example, a barrier film 12a and a low resistance film 12b. The barrier film 12a is, for example, a titanium film, which suppresses mutual diffusion between the low resistance film 12b and the piezoelectric substrate 10. The low resistance film 12b has a lower resistance than the barrier film 12a, for example, an aluminum film or a copper film.

The 1-port elastic wave resonator 25 has an IDT 20 and a reflector 22 formed of a metal film 12. Reflectors 22 are provided on both sides of the IDT 20. The IDT 20 has a pair of comb-shaped electrodes 27. The comb-shaped electrode 27 has a plurality of electrode fingers 24 and a bus bar 26 to which the plurality of electrode fingers 24 are connected. One electrode finger 24 and the other electrode finger 24 of the pair of comb-shaped electrodes 27 are provided substantially alternately. A part of the lower surface of the bus bar 26 comes into contact with the upper surface of the wiring layer 14. As a result, the bus bar 26 and the wiring layer 14 are electrically connected. A protective film 16 is provided so as to cover the metal film 12 and the wiring layer 14. The protective film 16 is, for example, a silicon nitride film or a silicon oxide film. The protective film 16 protects the metal film 12 and the wiring layer 14, and also suppresses the diffusion of metal atoms in the metal film 12 and the wiring layer 14 to the upper layer.

The electrode finger 24 of the IDT 20 excites a surface acoustic wave on the piezoelectric substrate 10. The excited elastic wave is reflected by the reflector 22. The wavelength λ of the elastic wave substantially corresponds to the pitch of the electrode finger 24. The propagation direction of the elastic wave is the X direction, and the extension direction of the electrode finger 24 is the Y direction. The X and Y directions do not have to be the X-axis orientation and the Y-axis orientation of the piezoelectric substrate 10. When the piezoelectric substrate 10 is a Y-cut X-propagated lithium tantalate substrate or a Y-cut X-propagated lithium niobate substrate, the X direction is the X-axis direction. The coefficient of linear thermal expansion of the support substrate 11 is smaller than the coefficient of linear thermal expansion of the piezoelectric substrate 10. As a result, the temperature coefficient of frequency can be brought close to zero. A temperature compensation film may be provided on the piezoelectric substrate 10 so as to cover the IDT 20. The temperature compensation film is, for example, a silicon oxide film or a silicon oxide film containing fluorine.

2 (a) to 3 (c) are cross-sectional views showing a method of manufacturing an elastic wave resonator according to the first embodiment. As shown in FIG. 2A, the lower surface of the piezoelectric substrate 10 is joined to the upper surface of the support substrate 11. For example, the upper surface of the support substrate 11 and the lower surface of the piezoelectric substrate 10 are irradiated with an ion beam, a neutral beam, or plasma of an inert gas. As a result, an amorphous layer of several nm or less is formed on the upper surface of the support substrate 11 and the lower surface of the piezoelectric substrate 10. Unbonded bonds are generated on the surface of the amorphous layer. Due to the presence of unbonded bonds, the upper surface of the support substrate 11 and the lower surface of the piezoelectric substrate 10 are in an activated state. The unbonded hands of the upper surface of the support substrate 11 and the lower surface of the piezoelectric substrate 10 are bonded to each other. As a result, the support substrate 11 and the piezoelectric substrate 10 are joined at room temperature. The piezoelectric substrate 10 and the support substrate 11 may be joined by an adhesive or the like. The film thickness of the piezoelectric substrate 10 is, for example, 1 μm to 30 μm.

As shown in FIG. 2B, an opening 30 is formed in the piezoelectric substrate 10. The opening 30 is formed by using a dry etching method or a wet etching method. The width of the opening 30 is, for example, 5 μm or more.

As shown in FIG. 2C, the seed layer 32 is formed on the inner surface of the opening 30 and the upper surface of the piezoelectric substrate 10. The seed layer 32 is, for example, a titanium film and a copper film from the support substrate 11 side. The titanium film functions as an adhesion layer for improving the adhesion between the wiring layer and the support substrate 11 and the piezoelectric substrate 10. The copper film functions as a layer that supplies the current for electroplating.

As shown in FIG. 2D, a copper layer is formed as a wiring layer 14 on the seed layer 32 by an electrolytic plating method by supplying an electric current through the seed layer 32. The seed layer 32 and the wiring layer 14 on the piezoelectric substrate 10 are removed by using, for example, a CMP (Chemical Mechanical Polishing) method. As a result, the seed layer 32 and the wiring layer 14 on the piezoelectric substrate 10 are removed, and the upper surface of the piezoelectric substrate 10 and the upper surface of the wiring layer 14 are flattened. The wiring layer 14 may be formed by using an electroless plating method, a sputtering method, a vapor deposition method, or a CVD (Chemical Vapor Deposition) method. In FIG. 1B, the illustration of the seed layer 32 is omitted.

As shown in FIG. 3A, a metal film 12 having a predetermined pattern is formed on the piezoelectric substrate 10. The metal film 12 forms the electrode finger 24 and the bus bar 26. The width of contact between the bus bar 26 and the wiring layer 14 is, for example, 1 μm or more. The metal film 12 is formed by, for example, a vapor deposition method and a lift-off method, or a sputtering method and an etching method.

As shown in FIG. 3B, the protective film 16 is formed on the piezoelectric substrate 10 so as to cover the metal film 12. The protective film 16 is formed by using, for example, a CVD method or a sputtering method. The protective film 16 is patterned.

As shown in FIG. 3C, a pad 28 for bumps is formed on the wiring layer 14. The pad 28 is a metal layer such as a gold layer. The pad 28 is formed by using, for example, a plating method, a sputtering method or a vapor deposition method.

According to the first embodiment, the wiring layer 14 and the seed layer 32 (first wiring layer) are filled in the openings provided in the piezoelectric substrate 10. At least a portion of the wiring layer 14 contacts at least a portion of the IDT 20 bus bar 26. As a result, as shown by the arrow 80 in FIG. 1B, the heat generated in the IDT 20 is directly conducted from the metal film 12 to the wiring layer 14 and released from the support substrate 11. Therefore, it is possible to promote the release of heat generated in the IDT 20.

Further, the wiring layer 14 and the seed layer 32 do not have to be in contact with the upper surface of the support substrate 11, but the opening penetrates the piezoelectric substrate 10 and the wiring layer 14 and the seed layer 32 are in contact with the support substrate 11. Is preferable. As a result, heat is directly conducted from the wiring layer 14 and the seed layer 32 to the support substrate 11. Therefore, the release of heat generated in the IDT 20 can be further promoted.

Further, at least a part of the upper surface of the wiring layer 14 and the upper surface of the piezoelectric substrate 10 are flat. As a result, disconnection of the metal film 12 at the boundary between the piezoelectric substrate 10 and the wiring layer 14 can be suppressed.

The thermal conductivity of the support substrate 11 (for example, sapphire) and the wiring layer 14 (for example, copper) is higher than the thermal conductivity of the piezoelectric substrate 10 (for example, lithium tantalate). As a result, the heat generated in the IDT 20 can be released to the support substrate 11 via the wiring layer 14 and the seed layer 32. Therefore, the release of heat generated in the IDT 20 can be further promoted.

[Modification 1 of Example 1]
4 (a) to 5 (b) are cross-sectional views showing a method of manufacturing an elastic wave resonator according to a modification 1 of the first embodiment. As shown in FIG. 4A, the piezoelectric substrate 10 is prepared. As shown in FIG. 4B, an opening 30 is formed in the piezoelectric substrate 10 by, for example, an etching method. As shown in FIG. 4 (c), the seed layer 32 and the wiring layer 14 embedded in the opening 30 are formed in the same manner as in FIGS. 2 (c) and 2 (d). As shown in FIG. 4 (d), the lower surface of the piezoelectric substrate 10 (upper surface in FIG. 4 (d)) is joined to the upper surface of the support substrate 11 (lower surface in FIG. 4 (d)) as in FIG. 2 (a). do.

As shown in FIG. 5A, for example, the CMP method is used to flatten the upper surface (lower surface in FIG. 5A) of the piezoelectric substrate 10 and the wiring layer 14. As shown in FIG. 5 (b), the metal film 12 is formed on the upper surface (lower surface in FIG. 5 (b)) of the piezoelectric substrate 10 and the wiring layer 14. After that, a protective film or the like is formed.

In the first modification of the first embodiment, the side surface of the wiring layer 14 is inclined so that the upper surface of the wiring layer 14 is smaller than the lower surface. As a result, the upper surface of the piezoelectric substrate 10 can be effectively used. Therefore, the chip size can be reduced.

[Modification 2 of Example 1]
6 (a) to 6 (h) are cross-sectional views showing the wiring layer in the second modification of the first embodiment. As shown in FIG. 6A, the side surface of the wiring layer 14 may be inclined so that the upper surface of the wiring layer 14 is larger than the lower surface. As shown in FIG. 6B, a recess may be provided on the upper surface of the wiring layer 14, and a gap 34 may be provided in the recess. As shown in FIG. 6C, the insulating film 33 may be embedded in the recess on the upper surface of the wiring layer 14. The insulating film 33 is, for example, a silicon oxide film or a silicon nitride film. As shown in FIG. 6D, when the upper surfaces of the piezoelectric substrate 10 and the wiring layer 14 are flattened by the CMP method, the upper surface of the wiring layer 14 may be a concave surface 34a by dishing.

As shown in FIG. 6E, another wiring layer 36 may be provided on the wiring layer 14, and the wiring layers 14 and 36 may be in electrical contact with each other. The wiring layer 36 is a metal layer such as a copper layer or a gold layer. As shown in FIG. 6 (f), a gap 35 may be provided between the wiring layer 14 and the piezoelectric substrate 10.

As shown in FIG. 6 (g), even if the wiring layer 36 (second wiring layer) is provided on the wiring layer 14 so as to sandwich the insulating film 33 provided in the opening and face the wiring layer 14. good. As shown in FIG. 6H, the wiring layer 36 may be provided on the wiring layer 14 so as to face the wiring layer 14 with the gap 34 provided in the opening sandwiched therein. The wiring layers 14 and 36 are electrically separated by an insulating film 33 or a gap 34 to form an intersecting wiring. The thickness of the insulating film 33 and the void 34 is, for example, 1 μm.

[Modification 3 of Example 1]
6 (i) and 6 (j) are cross-sectional views showing the wiring layer in the third modification of the first embodiment. As shown in FIG. 6 (i), the upper surface of the support substrate 11 has a recess 31 defined by an opening of the piezoelectric substrate 10. The seed layer 32 is in contact with the upper surface of the support substrate 11 in the recess 31. In FIG. 6 (i), the first wiring layer including the wiring layer 14 and the seed layer 32 comes into contact with the recess 31. As a result, the area where the seed layer 32 contacts the support substrate 11 becomes large. Therefore, the adhesion strength between the seed layer 32 and the support substrate 11 is improved. Further, the heat dissipation from the wiring layer 14 to the support substrate 11 is improved. In FIG. 2B, after forming an opening in the piezoelectric substrate 10, a dry process such as ion milling or dry etching, or mechanical processing such as blasting or processing using a dicing blade is performed. As a result, the recess 31 can be formed. Other configurations are the same as those in FIG. 6A, and the description thereof will be omitted.

As shown in FIG. 6J, the upper surface of the recess 31 is a curved surface protruding upward. As a result, the contact area between the seed layer 32 and the support substrate 11 becomes larger than that in FIG. 6 (i). Therefore, the adhesion strength and heat dissipation can be further improved. By performing a dry process such as ion milling or dry etching on the formation of the concave portion 31, the concave portion 31 tends to have a curved surface. Other configurations are the same as those in FIG. 6 (i), and the description thereof will be omitted.

As shown in FIGS. 6 (i) and 6 (j), the upper surface of the support substrate 11 has a recess 31, and the wiring layer 14 and the seed layer 32 (first wiring layer) are in contact with the support substrate 11 at least in the recess 31. do. As a result, the adhesion strength between the first wiring layer and the seed layer 32 and the heat dissipation from the wiring layer to the support substrate 31 can be improved.

The second embodiment is an example of a filter as an elastic wave device. 7 (a) is a plan view of the filter according to the second embodiment, and FIG. 7 (b) is a cross-sectional view taken along the line AA of FIG. 7 (a). As shown in FIG. 7A, elastic wave resonators 25, wiring layers 14, 18 and pads 28 are provided on the piezoelectric substrate 10 and the support substrate 11. The elastic wave resonator 25 has an IDT 20 and a reflector 22. As shown in FIG. 7B, the wiring layer 14 is embedded in the opening formed in the piezoelectric substrate 10. The wiring layer 18 is provided on the piezoelectric substrate 10. At least a part of the lower surface of one bus bar 26 contacts the upper surface of the wiring layer 14, and at least a part of the upper surface of the other bus bar 26 contacts the lower surface of the wiring layer 18. The wiring layer 18 is a metal layer such as a copper layer or a gold layer.

As shown in FIG. 7A, the plurality of elastic wave resonators 25 correspond to the series resonators S1 to S4 and the parallel resonators P1 to P3. The pad 28 corresponds to the input terminal Tin, the output terminal Tout, and the ground terminal Tgnd. A bump (not shown) is formed on the pad 28. The series resonators S1 to S4 are connected in series between the input terminal Tin and the output terminal Tout via the wiring layers 14 and / or 18. The parallel resonators P1 to P3 are connected in parallel between the input terminal Tin and the output terminal Tout via the wiring layers 14 and / or 18.

The wiring layers 14 and 18 are provided along the bus bar 26 in order to reduce the resistance between the wiring layers 14 and 18 and the electrode fingers 24. Therefore, wiring layers having different potentials are extended to face each other between adjacent parallel resonators. This causes a short circuit between the wiring layers and / or increases the parasitic capacitance between the wiring layers. In addition, it becomes difficult to miniaturize the wiring layer.

Therefore, among the parallel resonators P1 and P2, the wiring layer connected to the parallel resonator P1 is referred to as a wiring layer 14, and the wiring layer connected to the parallel resonator P2 is referred to as a wiring layer 18. Of the parallel resonators P2 and P3, the wiring layer connected to the parallel resonator P2 is referred to as a wiring layer 14, and the wiring layer connected to the parallel resonator P3 is referred to as a wiring layer 18. As a result, as shown in FIG. 7B, one wiring layer 14 is embedded in the piezoelectric substrate 10, and the other wiring layer 1 is provided on the piezoelectric substrate 10. Therefore, a short circuit between the wiring layers 14 and 18 can be suppressed. In addition, the parasitic capacitance between the wiring layers 14 and 18 can be suppressed. Further, the wiring layer can be miniaturized.

According to the second embodiment, the wiring layer 18 (third wiring layer) is provided on the piezoelectric substrate 10 adjacent to the wiring layer 14 (first wiring layer). As a result, a short circuit between the wiring layers 14 and 18 can be suppressed, and a parasitic capacitance between the wiring layers 14 and 18 can be suppressed. Further, the wiring layers 14 and 18 can be miniaturized.

Further, as shown in FIG. 7B, the wiring layer 14 is provided between the two IDT 20s and contacts one of the IDT 20s, the bus bar 26, and the wiring layer 18 contacts the other bus bar 26. This makes it possible to suppress short circuits and parasitic capacitances between the wiring layers 14 and 18, which are connected between two adjacent IDTs 20, respectively.

In the ladder type filter, high frequency power is mainly applied to the series resonator, so that the series resonator becomes hot. Therefore, as shown in FIG. 7A, the wiring layer connected between at least two of the plurality of series resonators S1 to S4 is referred to as the wiring layer 14. As a result, the heat generated in the series resonator can be efficiently released.

The series resonators (eg, S2 and S3) sandwiched between the series resonators have a limited heat release path. Therefore, the wiring layer connected to the series resonators S2 and S3 is preferably the wiring layer 14.

FIG. 8 is a cross-sectional view of the elastic wave device according to the third embodiment. As shown in FIG. 8, the terminal 40 is provided on the lower surface of the support substrate 11. The terminal 40 is a foot pad for connecting the elastic wave resonator 25 to the outside. An elastic wave resonator 25 is provided on the upper surface of the piezoelectric substrate 10. A wiring layer 14 and an annular metal layer 68 that penetrate the piezoelectric substrate 10 are provided. An elastic wave resonator 25 is electrically connected to the wiring layer 14. A pad 28 is provided on the wiring layer 14.

The annular metal layer 68 is provided on the peripheral edge of the piezoelectric substrate 10 so as to surround the elastic wave resonator 25. The wiring layer 14 and the annular metal layer 68 are metal layers of the same material. A through electrode 42 that penetrates the support substrate 11 is provided. The through silicon via 42 electrically connects the wiring layer 14 and the terminal 40. The through electrode 42 is a metal layer such as a copper layer or a gold layer. An annular electrode 62 is provided on the annular metal layer 68. The annular electrode 62 is a metal layer such as a nickel layer, a tungsten layer, a copper layer, an aluminum layer, or a gold layer. If the upper surface of the annular metal layer 68 has good solder wettability, the annular electrode 62 may not be provided.

An elastic wave resonator 52 and a wiring layer 54 are provided on the lower surface of the substrate 50. The elastic wave resonator 52 is, for example, a piezoelectric thin film resonator. The substrate 50 is, for example, a silicon substrate, a sapphire substrate, a spinel substrate, or an alumina substrate. The wiring layer 54 is a metal layer such as a copper layer, an aluminum layer, or a gold layer. The substrate 50 is flip-chip mounted (face-down mounted) on the piezoelectric substrate 10 via bumps 44. The bump 44 is, for example, a gold bump, a solder bump or a copper bump. The bump 44 joins the pad 28 and the wiring layer 54.

A sealing portion 60 is provided on the piezoelectric substrate 10 so as to surround the substrate 50. The sealing portion 60 is a metal material such as solder. The sealing portion 60 is joined to the annular electrode 62. A flat lid 64 is provided on the upper surface of the substrate 50 and the upper surface of the sealing portion 60. The lid 64 is, for example, a metal plate or an insulating plate. A protective film 66 is provided so as to cover the lid 64 and the sealing portion 60. The protective film 66 is a metal film or an insulating film.

The elastic wave resonators 25 and 52 face each other through the gap 65. The gap 65 is sealed by the sealing portion 60, the piezoelectric substrate 10, the substrate 50, and the lid 64. The elastic wave resonators 25 and 52 are surrounded by the gap 65, so that vibration is not regulated.

FIG. 9 is a plan view of the piezoelectric substrate according to the third embodiment. As shown in FIG. 9, an elastic wave resonator 25 is provided on the piezoelectric substrate 10. A wiring layer 14 is provided in the piezoelectric substrate 10. An annular metal layer 68 is provided in the piezoelectric substrate 10 on the periphery of the support substrate 11. A bump 44 is provided on the pad 28. The plurality of elastic wave resonators 25 correspond to the series resonators S1 to S3 and the parallel resonators P1 and P2. The plurality of bumps 44 correspond to the input terminal Tin, the output terminal Tout, and the ground terminal Tgnd. The series resonators S1 to S3 are connected in series, and the parallel resonators P1 and P2 are connected in parallel between the input terminal Tin and the output terminal Tout.

According to the third embodiment, the annular metal layer 68 surrounds the IDT 20 and is embedded in the peripheral edge of the piezoelectric substrate 10. The substrate 50 is mounted on the piezoelectric substrate 10. The sealing portion 60 seals the IDT 20 so as to surround the substrate 50 in a plan view and the IDT 20 and the lower surface of the substrate 50 face each other with the gap 65 interposed therebetween. As a result, as shown by the arrow 82 in FIG. 8, the heat generated in the elastic wave resonator 25 is dissipated from the terminal 40 via the wiring layer 14 and the support substrate 11. Further, as shown by the arrow 84, the heat generated in the elastic wave resonator 25 is released through the wiring layer 14, the support substrate 11, the annular metal layer 68, the annular electrode 62, and the sealing portion 60. Therefore, the heat generated in the elastic wave resonator 25 can be efficiently released.

It is preferable that the thermal conductivity of the annular metal layer 68, the annular electrode 62 and the sealing portion 60 is larger than the thermal conductivity of the piezoelectric substrate 10. As a result, heat can be released more efficiently. Although the example in which the ladder type filter is formed on the piezoelectric substrate 10 has been described, the piezoelectric substrate 10 may be provided with the multiple mode type filter. Although an example in which a piezoelectric thin film resonator is provided as an elastic wave resonator 52 on the lower surface of the substrate 50 has been described, an elastic surface wave resonator, a passive element, or an active element may be provided on the lower surface of the substrate 50. .. An electronic element may not be provided on the lower surface of the substrate 50.

Example 4 is an example of a duplexer as an elastic wave device. FIG. 10 is a circuit diagram of the duplexer according to the fourth embodiment. As shown in FIG. 10, a transmission filter 90 is connected between the common terminal Ant and the transmission terminal Tx. A reception filter 92 is connected between the common terminal Ant and the reception terminal Rx. The transmission filter 90 passes a signal in the transmission band among the high-frequency signals input from the transmission terminal Tx to the common terminal Ant as a transmission signal, and suppresses signals of other frequencies. The reception filter 92 passes a signal in the reception band among the high frequency signals input from the common terminal Ant to the reception terminal Rx as a reception signal, and suppresses signals of other frequencies.

11 (a) is a plan view of the duplexer according to the fourth embodiment, and FIG. 11 (b) is a cross-sectional view taken along the line AA of FIG. 11 (a). As shown in FIGS. 11A and 11B, a transmission filter 90 and a reception filter 92 are provided on the piezoelectric substrate 10. The transmitting filter 90 and the receiving filter 92 each have an elastic wave resonator 25, a wiring layer 14, and a pad 28. The transmit filter 90 and the receive filter 92 are ladder type filters having series resonators S1 to S3 and parallel resonators P1 and P2, respectively. A wiring layer 14a embedded in the piezoelectric substrate 10 is provided between the transmission filter 90 and the reception filter 92. For example, a ground potential is supplied to the wiring layer 14a.

According to the fourth embodiment, the wiring layer 14a can improve the isolation between the transmission filter 90 and the reception filter 92. Although the duplexer transmission filter and reception filter have been described as examples of filters for improving isolation, other filters may be used. It is preferable that the pass bands of the filter for improving isolation do not overlap. Although the ladder type filter has been described as an example of the transmission filter 90 and the reception filter 92, a multiple mode type filter may also be used. Although the Dureplexer has been described as an example, a multiplexer such as a triplexer or a quadplexer may be used.

12 (a) is a plan view of the filter according to the fifth embodiment, and FIG. 12 (b) is a cross-sectional view taken along the line AA of FIG. 12 (a). As shown in FIGS. 12 (a) and 12 (b), an elastic wave resonator 25, a wiring layer 14, and a pad 28 are provided on the piezoelectric substrate 10. A wiring layer 14b is embedded in the piezoelectric substrate 10 so as to surround the elastic wave resonator 25. For example, a ground potential is supplied to the wiring layer 14b.

According to the fifth embodiment, the wiring layer 14b is provided so as to surround the IDT 20 in a plan view. Thereby, the isolation between the IDT 20 can be improved.

As in Examples 2 to 5, the heat dissipation of the filter can be improved by including the IDT and the wiring layer 14 in the first embodiment and its modifications. The number of series resonators and parallel resonators in the ladder type filter can be set arbitrarily. In the second embodiment, a ladder type filter has been described as an example of the filter using the wiring layer 14, but a multiple mode filter may also be used.

By including the filters of Examples 2, 4 and 5 in the multiplexer as in the fourth embodiment, the heat dissipation property of the multiplexer can be improved.

Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

10 Piezoelectric substrate 11 Support substrate 12 Metal film 14, 14a, 14b, 18, 36 Wiring layer 16 Protective film 20 IDT
22 Reflector 24 Electrode finger 25 Elastic wave resonator 26 Bus bar 27 Comb-shaped electrode 30 Opening 34, 35 Void 33 Insulation film 44 Bump 50 Substrate 52 Elastic wave resonator 60 Sealing part 65 Void 68 Cyclic metal layer

Claims (11)

Support board and
With the piezoelectric substrate bonded on the support substrate,
An IDT provided on the piezoelectric substrate and having a plurality of electrode fingers and a bus bar to which the plurality of electrode fingers are connected.
A first wiring layer that is filled in the opening provided in the piezoelectric substrate and in which at least a part of the upper surface is in contact with at least a part of the IDT bus bar.
Equipped with
The opening penetrates the piezoelectric substrate and does not penetrate the support substrate.
The surface of the first wiring layer on the support substrate side comes into contact with the support substrate.
An elastic wave device in which the thermal conductivity of the support substrate and the first wiring layer is higher than the thermal conductivity of the piezoelectric substrate. The elastic wave device according to claim 1 or 2, wherein at least a part of the upper surface of the first wiring layer and the upper surface of the piezoelectric substrate are flat. The elastic wave according to claim 1 or 2 , further comprising a second wiring layer provided on the first wiring layer so as to face the first wiring layer with an insulating film or gap provided in the opening interposed therebetween. device. The elastic wave device according to any one of claims 1 to 3 , further comprising a third wiring layer provided adjacent to the first wiring layer on the piezoelectric substrate. The first wiring layer is provided between the two IDTs and comes into contact with the bus bar of one of the two IDTs.
The elastic wave device according to claim 4, wherein the third wiring layer is provided between the two IDTs, contacts the bus bar of the other of the two IDTs, and is adjacent to the first wiring layer. An annular metal layer that surrounds the IDT and is embedded in the periphery of the piezoelectric substrate.
The substrate mounted on the piezoelectric substrate and
A sealing portion that encloses the IDT and seals the IDT so that the IDT and the lower surface of the substrate face each other with a gap in between in a plan view.
The elastic wave device according to any one of claims 1 to 5. The elastic wave device according to any one of claims 1 to 6 , wherein the first wiring layer is provided so as to surround the IDT in a plan view. The elastic wave device according to any one of claims 1 to 7, wherein the upper surface of the support substrate has a recess, and the first wiring layer contacts the support substrate at least in the recess. The elastic wave device according to any one of claims 1 to 8 , further comprising a filter including the IDT. A plurality of series resonators connected in series between an input terminal and an output terminal, each containing the IDT, and connected in parallel between the input terminal and the output terminal, each containing the IDT. Or equipped with multiple parallel resonators and a filter including
The elastic wave device according to claim 4, wherein the first wiring layer is connected between at least two of the plurality of series resonators. The elastic wave device according to claim 9 or 10 , further comprising a multiplexer including the filter.

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