JP6929804B2 - Semiconductor device - Google Patents

Description

Embodiments of the present invention relate to semiconductor devices.

An IGBT (Insulated Gate Bipolar Transistor) is an example of a semiconductor device for electric power. In the IGBT, for example, a p-type collector region, an n-base region, and a p-base region are provided on the collector electrode. Then, a trench gate electrode is provided in the trench that penetrates the p-base region and reaches the n-base region via the trench gate insulating film. Further, an emitter region connected to the emitter electrode is provided in a region adjacent to the trench on the surface of the p-base region.

In the IGBT, a channel is formed in the p-base region by applying a positive voltage to the gate electrode. Then, at the same time that electrons are injected from the emitter region into the n-base region, holes are injected from the collector region into the n-base region. As a result, a current flows between the collector electrode and the emitter electrode.

In order to reduce the on-resistance between the collector electrode and the emitter electrode of the IGBT, there is a method of suppressing the discharge of holes from the n-based region. In this method, the emission of holes from the n-based region to the emitter electrode is suppressed, so that the amount of electrons injected is relatively increased and the on-resistance of the IGBT is reduced.

For example, in order to realize the above method, a thinning type IGBT in which a dummy trench gate electrode that does not contribute to the formation of a channel is provided between the trench gate electrodes has been proposed. It is desired to realize a thinned-out IGBT with improved characteristics such as improvement of switching speed and reduction of on-resistance.

Japanese Unexamined Patent Publication No. 2013-251296

An object to be solved by the present invention is to provide a semiconductor device capable of improving the characteristics of a thinned IGBT.

The semiconductor device of the embodiment includes a first surface, a semiconductor layer having a second surface facing the first surface, an emitter electrode in which at least a part is in contact with the first surface, and at least a part thereof. A collector electrode in contact with the second surface, an upper trench gate electrode provided in the semiconductor layer and extending in a first direction substantially parallel to the first surface, and an upper trench gate electrode provided in the semiconductor layer. The lower trench gate electrode, which is provided between the upper trench gate electrode and the second surface, extends in the first direction, and is electrically separated from the upper trench gate electrode, and the semiconductor layer. An upper dummy trench gate electrode provided inside and extending in the first direction, and an upper dummy trench gate electrode provided in the semiconductor layer and provided between the upper dummy trench gate electrode and the second surface, the first. In the lower dummy trench gate electrode extending in the direction 1 and electrically separated from the upper dummy trench gate electrode, the p-type p-base region provided in the semiconductor layer, and the semiconductor layer. An n-type emitter region provided between the p-base region and the first surface and electrically connected to the emitter electrode, and an n-type emitter region provided in the semiconductor layer and provided in the p-base region. And an n-type n-base region provided between the second surface and the collector, which is provided in the semiconductor layer and is provided between the n-base region and the second surface. A p-type collector region electrically connected to an electrode, between the upper trench gate electrode and the p-base region, between the upper trench gate electrode and the emitter region, and the lower trench gate electrode. A trench gate insulating film provided between the n-base region and in contact with the p-base region, the emitter region, and the n-base region, and between the upper dummy trench gate electrode and the p-base region, and A dummy trench gate insulating film provided between the lower dummy trench gate electrode and the n-base region and in contact with the p-base region and the n-base region, the upper trench gate electrode, and the lower trench gate electrode. The first gate pad electrode electrically connected to the lower dummy trench gate electrode, and the first gate pad electrode electrically connected between the first gate pad electrode and the upper trench gate electrode. The electrical resistance, between the first gate pad electrode and the lower trench gate electrode, and between the first gate pad electrode and the lower dummy trench A second electrical resistance electrically connected to the electrode is provided, and the CR time constant based on the product of the capacitance and the resistance value of the upper trench gate electrode is the capacitance of the lower dummy trench gate electrode. It is smaller than the CR time constant based on the product of and the resistance value .

The schematic plan view of the semiconductor device of 1st Embodiment. The schematic cross-sectional view of the semiconductor device of 1st Embodiment. The schematic plan view of the semiconductor device of the 1st comparative form. FIG. 3 is a schematic cross-sectional view of the semiconductor device of the first comparative embodiment. The schematic plan view of the semiconductor device of the 2nd comparative form. FIG. 3 is a schematic cross-sectional view of the semiconductor device of the second comparative embodiment. The explanatory view of the operation and effect of the semiconductor device of 1st Embodiment. The explanatory view of the operation and effect of the semiconductor device of 1st Embodiment. The schematic plan view of the semiconductor device of 2nd Embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device of the second embodiment. The equivalent circuit diagram of the semiconductor device of the 2nd Embodiment. The schematic plan view of the semiconductor device of 3rd Embodiment. The schematic plan view of the semiconductor device of 4th Embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment. The explanatory view of the operation and effect of the semiconductor device of 4th Embodiment. The schematic plan view of the semiconductor device of 5th Embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device of the fifth embodiment. The explanatory view of the operation and effect of the semiconductor device of 5th Embodiment. The schematic plan view of the semiconductor device of 5th Embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device of the fifth embodiment. The explanatory view of the operation and effect of the semiconductor device of 5th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same members and the like are designated by the same reference numerals, and the description of the members and the like once described will be omitted as appropriate.

Herein, n ⁺ -type, n-type, n ^- if there is a representation of the type, n ⁺ -type, n-type, n ^- n-type impurity concentration in the order of type means that are lower. Further, p ⁺ -type, p-type, p ^- if there is a type of notation, p ⁺ -type, p-type, p ^- in the order of type impurity concentration of the p-type means that are lower.

(First Embodiment)
In the semiconductor device of the present embodiment, a semiconductor layer having a first surface, a second surface facing the first surface, an emitter electrode having at least a part in contact with the first surface, and at least a part having a first surface are present. A collector electrode in contact with the second surface, a trench gate electrode provided in the semiconductor layer and extending in the first direction substantially parallel to the first surface, and a trench gate electrode provided in the semiconductor layer and in the first direction. An elongated dummy trench gate electrode, a p-type p-base region provided in the semiconductor layer, and a p-base region provided in the semiconductor layer and provided between the p-base region and the first surface are provided on the emitter electrode. An electrically connected n-type emitter region, an n-type n-base region provided in the semiconductor layer and provided between the p-base region and the second surface, and an n-type n-base region provided in the semiconductor layer. A trench gate electrode and an emitter are provided between a p-type collector region provided between the n-base region and the second surface and electrically connected to the collector electrode, and between the trench gate electrode and the p-base region. A trench gate insulating film provided between the region and between the trench gate electrode and the n-base region and in contact with the p-base region, the emitter region, and the n-base region, and a dummy trench gate electrode and the p-base region. The dummy trench gate insulating film, which is provided between the dummy trench gate electrode and the n-base region and is in contact with the p-base region and the n-base region, and the trench gate electrode and the dummy trench gate electrode are electrically charged. First gate pad electrode connected to the surface, first electrical resistance electrically connected between the first gate pad electrode and the trench gate electrode, and the first gate pad electrode and the dummy trench gate. It comprises a second electrical resistance electrically connected to and from the electrode, and the CR time constant of the trench gate electrode is smaller than the CR time constant of the dummy trench gate electrode.

FIG. 1 is a schematic plan view of the semiconductor device of the present embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor device of the present embodiment. FIG. 2A is a cross-sectional view taken along the line AA'of FIG. FIG. 2B is an explanatory diagram in which an equivalent circuit is overlaid on FIG. 2A.

The semiconductor device of this embodiment is a trench IGBT 100 having a gate electrode in a trench formed in a semiconductor layer. The trench IGBT 100 is a thinned IGBT having a dummy trench gate electrode.

The trench IGBT 100 of the present embodiment includes a semiconductor layer 10, an emitter electrode 12, a collector electrode 14, a trench gate electrode 16, a dummy trench gate electrode 18, a p-base region 20, an emitter region 22, an n-base region 24, and a barrier region 26 (n). Type semiconductor region), collector region 28, trench gate insulating film 30, dummy trench gate insulating film 32, gate pad electrode 34 (first gate pad electrode), internal gate resistance 36 (first electrical resistance), dummy gate resistance 38 (second electric resistance), emitter pad electrode 40, gate electrode connection wiring 42 (first connection wiring), dummy gate electrode connection wiring 44 (second connection wiring), trench 50, dummy trench 52 are provided.

The semiconductor layer 10 has a first surface P1 and a second surface P2 facing the first surface P1. The semiconductor layer 10 is, for example, single crystal silicon. The film thickness of the semiconductor layer 10 is, for example, 50 μm or more and 700 μm or less.

At least a part of the emitter electrode 12 is in contact with the first surface P1 of the semiconductor layer 10. The emitter electrode 12 is, for example, a metal. An emitter voltage (Ve) is applied to the emitter electrode 12. The emitter voltage is, for example, 0V.

At least a part of the collector electrode 14 is in contact with the second surface P2 of the semiconductor layer 10. The collector electrode 14 is, for example, a metal. A collector voltage (Vc) is applied to the collector electrode 14. The collector voltage is, for example, 200 V or more and 6500 V or less.

A plurality of trench gate electrodes 16 are provided in the semiconductor layer 10. The trench gate electrode 16 is provided in the trench 50 formed in the semiconductor layer 10. The trench gate electrode 16 extends in a first direction substantially parallel to the first surface P1. The trench gate electrode 16 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

A plurality of dummy trench gate electrodes 18 are provided in the semiconductor layer 10. The dummy trench gate electrode 18 is provided in the dummy trench 52 formed in the semiconductor layer 10. The dummy trench gate electrode 18 extends in a first direction substantially parallel to the first surface P1. The dummy trench gate electrode 18 is provided between the trench gate electrodes 16 in parallel with the trench gate electrode 16. The dummy trench gate electrode 18 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

The p-base region 20 is provided in the semiconductor layer 10. The p-base region 20 is a p-type semiconductor region. The region of the p-base region 20 in contact with the trench gate insulating film 30 functions as a channel region of the IGBT 100.

The emitter region 22 is provided in the semiconductor layer 10. The emitter region 22 is provided between the p-base region 20 and the first surface P1 and is in contact with the trench gate insulating film 30. The emitter region 22 is an n-type semiconductor region. The emitter region 22 is not provided between the two dummy trench gate electrodes 18. The emitter region 22 is electrically connected to the emitter electrode 12.

The n-base region 24 is provided in the semiconductor layer 10. The n-base region 24 is provided between the p-base region 20 and the second surface. The n-base region 24 is an n-type semiconductor region.

The barrier region 26 is provided in the semiconductor layer 10. The barrier region 26 is provided between the p-base region 20 and the n-base region 24. The barrier region 26 is an n-type semiconductor region. The concentration of n-type impurities in the barrier region 26 is higher than the concentration of n-type impurities in the n-base region 24. The concentration of n-type impurities in the barrier region 26 is lower than the concentration of n-type impurities in the emitter region 22. The barrier region 26 has a function of reducing the on-resistance of the trench IGBT 100.

The collector region 28 is provided in the semiconductor layer 10. The collector region 28 is provided between the n-base region 24 and the second surface P2. The collector region 28 is a p-type semiconductor region. The p-type impurity concentration in the collector region 28 is higher than the p-type impurity concentration in the p-base region 20. The collector region 28 is electrically connected to the collector electrode 14.

It is also possible to provide a buffer region having a higher n-type impurity concentration than the n-base region 24 between the n-base region 24 and the collector region 28. By providing the buffer region, it is possible to suppress the elongation of the depletion layer when the trench IGBT 100 is in the off state.

The trench gate insulating film 30 is provided between the trench gate electrode 16, the p-base region 20, the emitter region 22, and the n-base region 24. The trench gate insulating film 30 is provided in the trench 50. The trench gate insulating film 30 is in contact with the p-base region 20, the emitter region 22, and the n-base region 24. The trench gate insulating film 30 is, for example, silicon oxide.

The dummy trench gate insulating film 32 is provided between the dummy trench gate electrode 18, the p-base region 20, and the n-base region 24. The dummy trench gate insulating film 32 is provided in the dummy trench 52. The dummy trench gate insulating film 32 is in contact with the p-base region 20 and the n-base region 24. The dummy trench gate insulating film 32 does not come into contact with the emitter region 22. The dummy trench gate insulating film 32 is, for example, silicon oxide.

The gate pad electrode 34 is provided on the semiconductor layer 10. The gate pad electrode 34 is provided on the side of the first surface P1 of the semiconductor layer 10. The gate pad electrode 34 is electrically connected to the trench gate electrode 16 and the dummy trench gate electrode 18. The gate pad electrode 34 is, for example, metal.

The internal gate resistor 36 is provided on the semiconductor layer 10. The internal gate resistor 36 is provided on the side of the first surface P1 of the semiconductor layer 10. The internal gate resistor 36 is electrically connected between the gate pad electrode 34 and the trench gate electrode 16.

The internal gate resistor 36 is, for example, a semiconductor. The internal gate resistor 36 is, for example, polycrystalline silicon containing conductive impurities. The internal gate resistor 36 is formed of, for example, a material having a higher specific resistance than the gate electrode connection wiring 42.

The dummy gate resistor 38 is provided on the semiconductor layer 10. The dummy gate resistor 38 is provided on the side of the first surface P1 of the semiconductor layer 10. The dummy gate resistor 38 is electrically connected between the gate pad electrode 34 and the dummy trench gate electrode 18.

The dummy gate resistor 38 is, for example, a semiconductor. The dummy gate resistor 38 is, for example, polycrystalline silicon containing conductive impurities. The dummy gate resistor 38 is formed of, for example, a material having a higher specific resistance than the gate electrode connection wiring 42.

The gate electrode connection wiring 42 is electrically connected between the trench gate electrode 16 and the internal gate resistor 36. The gate electrode connection wiring 42 is connected to the end portion of the trench gate electrode 16. The gate electrode connection wiring 42 is connected to the trench gate electrode 16 at a contact portion (not shown), for example. The gate electrode connection wiring 42 is, for example, metal.

The dummy gate electrode connection wiring 44 is electrically connected between the dummy trench gate electrode 18 and the dummy gate resistor 38. The dummy gate electrode connection wiring 44 is connected to the end portion of the dummy trench gate electrode 18. The dummy gate electrode connection wiring 44 is connected to the dummy trench gate electrode 18 at a contact portion (not shown), for example. The dummy trench gate electrode 18 is, for example, metal.

The trench gate electrode 16 and the dummy trench gate electrode 18 are located between the gate electrode connection wiring 42 and the dummy gate electrode connection wiring 44. In other words, the gate electrode connection wiring 42 is located at one end of the trench gate electrode 16 and the dummy trench gate electrode 18, and the dummy gate electrode connection wiring 44 is the trench gate electrode 16 and the dummy trench gate electrode. It is located at the other end of 18.

The CR time constant of the trench gate electrode 16 is smaller than the CR time constant of the dummy trench gate electrode 18. The CR time constant of the trench gate electrode 16 is mainly defined by the capacitance between the trench gate electrode 16 and the semiconductor layer 10, the resistance value of the trench gate electrode 16, and the resistance value of the internal gate resistance 36. The CR time constant of the dummy trench gate electrode 18 is mainly defined by the capacitance between the dummy trench gate electrode 18 and the semiconductor layer 10, the resistance value of the dummy trench gate electrode 18, and the resistance value of the dummy gate resistor 38. NS.

The emitter pad electrode 40 is provided on the semiconductor layer 10. The emitter pad electrode 40 is provided on the side of the first surface P1 of the semiconductor layer 10. The emitter pad electrode 40 is electrically connected to the emitter electrode 12.

The IGBT 100 is a three-terminal device having three electrodes of an emitter pad electrode 40, a collector electrode 14, and a gate pad electrode 34 as terminals.

As shown in FIG. 2B, in the trench IGBT 100 of the present embodiment, an internal gate resistor (Rg-in) and a dummy gate resistor (Rg-dummy) are connected in parallel. The internal gate resistor (Rg-in) and the dummy gate resistor (Rg-dummy) are connected to the gate driver outside the IGBT 100, for example, via an external gate resistor. A gate voltage (Vg) is applied to the trench gate electrode 16 and the dummy trench gate electrode 18 by the gate driver.

The internal gate resistance (Rg-in) corresponds to the internal gate resistance 36 in FIG. The dummy gate resistor (Rg-dummy) corresponds to the dummy gate resistor 38 in FIG.

The p-base region 20 is electrically connected to, for example, the emitter electrode 12. The p-base region 20 is fixed to, for example, the ground potential. The p-base region 20 sandwiched between the dummy trench gate electrodes 18 may be, for example, floating.

Hereinafter, the action and effect of the trench IGBT 100 of the present embodiment will be described.

FIG. 3 is a schematic plan view of the semiconductor device of the first comparative embodiment. FIG. 4 is a schematic cross-sectional view of the semiconductor device of the first comparative embodiment. FIG. 4A is a cross-sectional view taken along the line BB'of FIG. FIG. 4B is an explanatory diagram in which an equivalent circuit is overlaid on FIG. 4A.

The semiconductor device of the first comparative embodiment is a trench IGBT 800 having a gate electrode in a trench formed in a semiconductor layer. The trench IGBT 800 is a thinned IGBT having a dummy trench gate electrode.

The trench IGBT 800 is different from the trench IGBT 100 of the embodiment in that the dummy trench gate electrode 18 is electrically connected to the emitter electrode 12 and that the dummy gate resistor 38 is not provided.

The dummy trench gate electrode 18 of the trench IGBT 800 is electrically connected to the emitter electrode 12. An emitter voltage (Ve) is applied to the dummy trench gate electrode 18. The emitter voltage is, for example, 0V. Therefore, an electron storage layer is not formed in the n-base region 24 near the bottom of the dummy trench 52.

As can be seen from FIG. 4B, since the electron storage layer is not formed in the n-base region 24 near the bottom of the dummy trench 52, it exists between the dummy trench gate electrodes 18, and the collector region 28, the n-base region 24, Further, the parasitic pn diode composed of the barrier region 26 is circuit-divided from the transistor having the trench gate electrode 16 as a gate. Therefore, the carrier concentration in the n-base region 24 does not increase, and the parasitic pn diode does not effectively contribute as an on-current path. Therefore, it is difficult to reduce the on-resistance of the trench IGBT 800. In other words, the saturation voltage (Vce (sat)) of the collector-emitter voltage (Vce) becomes high.

FIG. 5 is a schematic plan view of the semiconductor device of the second comparative embodiment. FIG. 6 is a schematic cross-sectional view of the semiconductor device of the second comparative embodiment. FIG. 6A is a cross-sectional view taken along the line CC'of FIG. FIG. 6B is an explanatory diagram in which an equivalent circuit is overlaid on FIG. 6A.

The semiconductor device of the second comparative embodiment is a trench IGBT 900 having a gate electrode in a trench formed in the semiconductor layer. The trench IGBT 900 is a thinned IGBT having a dummy trench gate electrode.

The trench IGBT 900 differs from the trench IGBT 800 of the first comparative form in that the dummy trench gate electrode 18 is electrically connected to the trench gate electrode 16.

When the trench IGBT 900 is in the ON state, a gate voltage (Vg) is applied to the dummy trench gate electrode 18 of the trench IGBT 900, similarly to the trench gate electrode 16. Therefore, an electron storage layer is formed in the n-base region 24 near the bottom of the dummy trench 52.

As can be seen from FIG. 6B, since the electron storage layer is formed, the parasite exists between the dummy trench gate electrodes 18 and is composed of the collector region 28, the n-base region 24, and the barrier region 26. The pn diode is circuit-connected to a transistor whose gate is the trench gate electrode 16. Therefore, the carrier concentration in the n-base region 24 becomes high, and the parasitic pn diode effectively contributes as an on-current path. Therefore, the on-resistance of the trench IGBT 900 is reduced. In other words, the saturation voltage (Vce (sat)) of the collector-emitter voltage (Vce) becomes low. When the n-type impurity concentration is higher than the n-base region 24 and the barrier region 26 having a low resistance is provided, the on-resistance is reduced.

On the other hand, in the trench IGBT 900, the dummy trench gate electrode 18 is electrically connected to the trench gate electrode 16, so that the gate capacitance becomes large. Therefore, the CR time constant of the gate electrode becomes large. Therefore, there arises a problem that the switching speed is lowered.

Further, since the gate capacitance becomes large, the non-linearity of the switching speed with respect to the external gate resistor provided outside the trench IGBT 900 increases. Therefore, there arises a problem that it is difficult to adjust the switching speed by the external gate resistance.

In the trench IGBT 100 of the present embodiment, the gate resistor provided in the semiconductor chip is separated into two, an internal gate resistor 36 and a dummy gate resistor 38. Then, only the internal gate resistor 36 is electrically connected between the gate pad electrode 34 and the trench gate electrode 16, and only the dummy gate resistor 38 is electrically connected between the gate pad electrode 34 and the dummy trench gate electrode 18. Connect to.

By separating the gate resistor into two, an internal gate resistor 36 and a dummy gate resistor 38, the current flowing through the trench gate electrode 16 and the current flowing through the dummy trench gate electrode 18 are separated into the internal gate resistor 36 and the dummy gate resistor 38. It is possible to control by the resistance value of. The ratio of the current flowing through the trench gate electrode 16 to the current flowing through the dummy trench gate electrode 18 can be controlled by changing the ratio of the resistance values of the internal gate resistor 36 and the dummy gate resistor 38. For example, by reducing the resistance value of the internal gate resistor 36, the current flowing through the trench gate electrode 16 can be increased.

For example, the resistance values of the internal gate resistor 36 and the dummy gate resistor 38 are adjusted so that the CR time constant of the trench gate electrode 16 is made smaller than the CR time constant of the dummy trench gate electrode 18. As a result, the charging / discharging of the trench gate electrode 16 can be made faster than the charging / discharging of the dummy trench gate electrode 18. Therefore, it is possible to improve the switching speed of the trench IGBT 100.

Further, when the trench IGBT 100 is in the ON state, the dummy trench gate electrode 18 is also charged to the gate voltage (Vg) behind the trench gate electrode 16. Therefore, as in the second comparative embodiment, an electron storage layer is formed in the n-base region 24 near the bottom of the dummy trench 52, and the on-resistance is reduced.

FIG. 7 is an explanatory diagram of the operation and effect of the semiconductor device of the present embodiment. FIG. 7 is a diagram showing a time change of the collector-emitter voltage (Vce) at the time of turning on the IGBT.

In the case of the trench IGBT 900 of the second comparative form, the turn-on speed is slower than that of the trench IGBT 800 of the first comparative form, so that the rate of decrease of the collector-emitter voltage is slow. This is because the dummy trench gate electrode 18 is connected to the trench gate electrode 16, and it takes time to charge the dummy trench gate electrode 18 and the trench gate electrode 16.

In the trench IGBT 800 of the first comparative form, a step is seen in the waveform. This is because the parasitic pn diode composed of the collector region 28, the n-base region 24, and the barrier region 26 is circuit-separated from the transistor having the trench gate electrode 16 as a gate, so that the holes are emitter electrodes. It is thought that this is because it is easy to drop to 12 and the accumulation of carriers is delayed.

In the trench IGBT 100 of the present embodiment, the charging of the trench gate electrode 16 can be made faster than the charging of the dummy trench gate electrode 18 by separating the internal gate resistor 36 and the dummy gate resistor 38. Further, since the parasitic pn diode composed of the collector region 28, the n-base region 24, and the barrier region 26 is connected to the transistor having the trench gate electrode 16 as a gate in a circuit, there is a delay in carrier accumulation. It is unlikely to occur. Therefore, the turn-on speed is higher than that of the first comparative form and the second comparative form.

At the time of turn-off of the trench IGBT 100 of the present embodiment, the discharge of the trench gate electrode 16 can be made faster than the discharge of the dummy trench gate electrode 18. Therefore, the turn-off speed is also faster than that of the first comparative form and the second comparative form.

FIG. 8 is an explanatory diagram of the operation and effect of the semiconductor device of the present embodiment. FIG. 8A is a diagram showing the relationship between the gate resistance at the time of turn-off of the IGBT and the time change rate (dV / dt) of the collector-emitter voltage (Vce). FIG. 8B is a diagram showing the relationship between the gate resistance at the time of turning on the IGBT and the time change rate (di / dt) of the collector-emitter current. The resistance value of the gate resistance is the resistance value of the external gate resistance provided outside the IGBT. The time change rate (dV / dt) of the collector-emitter voltage (Vce) and the time change rate (di / dt) of the collector current are indicators of the switching speed at the time of turn-off and at the time of turn-on, respectively.

As can be seen from FIGS. 8A and 8B, in the case of the second comparative mode, the time change rate (dV / dt) of the collector-emitter voltage (Vce) and the time change rate (di) of the collector current. The non-linearity of / dt) increases. It is considered that this is because the dummy trench gate electrode 18 is connected to the trench gate electrode 16 and therefore the gate mirror capacitance becomes large. Since the non-linearity is large, the controllability of the switching speed due to the external gate resistance deteriorates.

In the case of the present embodiment, the same degree of linearity as that of the first comparative embodiment can be obtained. It is considered that this is because the charging / discharging of the trench gate electrode 16 is performed faster than the charging / discharging of the dummy trench gate electrode 18, so that the influence of connecting the dummy trench gate electrode 18 to the trench gate electrode 16 does not become apparent. Therefore, the controllability of the switching speed by the external gate resistance is improved.

Further, in the trench IGBT 900 of the second comparative form, problems such as gate vibration due to the negative gate capacitance and overshoot / undershoot of the gate voltage are likely to occur. It is considered that this is because the dummy trench gate electrode 18 is directly connected to the trench gate electrode 16, so that the parasitic capacitance composed of the dummy trench gate electrode and the collector electrode is directly transmitted to the trench gate electrode 16.

According to the trench IGBT 100 of the present embodiment, the CR time constant of the trench gate electrode 16 can be independently reduced. Therefore, problems such as gate vibration due to the negative gate capacitance and overshoot / undershoot of the gate voltage are suppressed.

As shown in FIG. 1, the gate electrode connection wiring 42 and the dummy gate are located so that the trench gate electrode 16 and the dummy trench gate electrode 18 are located between the gate electrode connection wiring 42 and the dummy gate electrode connection wiring 44. It is preferable that the electrode connection wiring 44 is arranged. In other words, it is preferable that the trench gate electrode 16 and the dummy trench gate electrode 18 are arranged so as to be sandwiched between the gate electrode connection wiring 42 and the dummy gate electrode connection wiring 44.

With the above arrangement, for example, crossing of wirings can be avoided, and the gate electrode connection wiring 42 and the dummy gate electrode connection wiring 44 can be easily routed. Therefore, for example, the chip area can be reduced and the manufacturing process can be simplified.

As described above, the trench IGBT 100 of the present embodiment can realize an IGBT having a low on-resistance and a high switching speed. Further, it is possible to realize an IGBT capable of suppressing vibration of the gate voltage and overshoot / undershoot. In addition, the chip area can be reduced and the manufacturing process can be simplified.

(Second Embodiment)
The semiconductor device of the present embodiment includes at least one semiconductor layer having a first surface, a second surface facing the first surface, and a first emitter electrode having at least a part in contact with the first surface. A first collector electrode whose portion is in contact with the second surface, a first trench gate electrode provided in the semiconductor layer and extending in a first direction substantially parallel to the first surface, and a semiconductor layer. A first dummy trench gate electrode provided in the semiconductor layer and extending in the first direction, a p-type first p-base region provided in the semiconductor layer, and a first dummy trench gate region provided in the semiconductor layer. An n-type first emitter region provided between the p-base region and the first surface and electrically connected to the first emitter electrode, and a first p-base provided in the semiconductor layer. An n-type first n-base region provided between the region and the second surface, and an n-type first n-base region provided in the semiconductor layer and provided between the first n-base region and the second surface. , The first trench gate electrode and the first between the p-type first collector region electrically connected to the first collector electrode and the first trench gate electrode and the first p base region. Provided between the emitter region and between the first trench gate electrode and the first n-base region, in the first p-base region, the first emitter region, and the first n-base region. It is provided between the first trench gate insulating film in contact with the first dummy trench gate electrode and the first p-base region, and between the first dummy trench gate electrode and the first n-base region. , A first dummy trench gate insulating film in contact with the first p-base region and the first n-base region, a second emitter electrode in at least a part in contact with the first surface, and at least a part in the first A second collector electrode in contact with the second surface, a second trench gate electrode provided in the semiconductor layer and extending in the first direction substantially parallel to the first surface, and a second trench gate electrode provided in the semiconductor layer. , A second dummy trench gate electrode extending in the first direction, a p-type second p-base region provided in the semiconductor layer, and a second p-base region provided in the semiconductor layer. An n-type second emitter region provided between the surface and the first surface and electrically connected to the second emitter electrode, a second p-base region provided in the semiconductor layer, and a second p-base region. An n-type second n-base region provided between the second surface and a second n-base region provided in the semiconductor layer and provided between the second n-base region and the second surface. A p-type second collector region electrically connected to the collector electrode and a second trench gate electrode And a second p-base region, between a second trench gate electrode and a second emitter region, and between a second trench gate electrode and a second n-base region. Between the second trench gate insulating film in contact with the second p-base region, the second emitter region, and the second n-base region, and between the second dummy trench gate electrode and the second p-base region, and , A second dummy trench gate insulating film provided between the second dummy trench gate electrode and the second n-base region and in contact with the second p-base region and the second n-base region, and a second A trench gate electrode, a first dummy trench gate electrode, a second trench gate electrode, a gate pad electrode electrically connected to a second dummy trench gate electrode, a gate pad electrode, and a first trench. A first electrical resistance electrically connected to the gate electrode, a second electrical resistance electrically connected to the gate pad electrode and the first dummy trench gate electrode, and a gate pad electrode. A third electrical resistance electrically connected between the and the second trench gate electrode and a fourth electrical resistance electrically connected between the gate pad electrode and the second dummy trench gate electrode. The CR time constant of the first trench gate electrode is smaller than the CR time constant of the first dummy trench gate electrode, and the CR time constant of the second trench gate electrode is the second dummy. It is smaller than the CR time constant of the trench gate electrode.

The semiconductor device of the present embodiment has a first segment having the same configuration as the semiconductor device of the first embodiment and a second segment having the same configuration as the semiconductor device of the first embodiment. It is different from the semiconductor device of the first embodiment in that it is provided with. Hereinafter, some descriptions of the contents overlapping with the first embodiment will be omitted.

FIG. 9 is a schematic plan view of the semiconductor device of the present embodiment. FIG. 10 is a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 10A is a cross-sectional view taken along the line DD'of FIG. FIG. 10B is a cross-sectional view taken along the line EE'of FIG. FIG. 11 is an equivalent circuit diagram of the semiconductor device of this embodiment. FIG. 11 is an explanatory diagram in which an equivalent circuit is overlaid on FIG.

The semiconductor device of this embodiment is a trench IGBT 200 having a gate electrode in a trench formed in a semiconductor layer. The trench IGBT 200 is a thinned IGBT having a dummy trench gate electrode.

The trench IGBT 200 includes a first segment 201 and a second segment 202. The first segment 201 and the second segment 202 each have the same configuration as the IGBT 100 of the first embodiment. However, the emitter pad electrode, collector electrode, and gate pad electrode are shared between the first segment 201 and the second segment 202.

The trench IGBT 200 of the present embodiment includes a semiconductor layer 110, a gate pad electrode 134, and an emitter pad electrode 140.

The first segment 201 includes a first emitter electrode 112, a first collector electrode 114, a first trench gate electrode 116, a first dummy trench gate electrode 118, a first p-base region 120, and a first emitter. Region 122, first n-base region 124, first barrier region 126, first collector region 128, first trench gate insulating film 130, first dummy trench gate insulating film 132, first internal gate resistance 136 (first resistance), first dummy gate resistance 138 (second resistance), first gate electrode connection wiring 142 (first connection wiring), first dummy gate electrode connection wiring 144 (second resistance) The connection wiring), the first trench 150, and the first dummy trench 152 are provided.

The second segment 202 includes a second emitter electrode 212, a second collector electrode 214, a second trench gate electrode 216, a second dummy trench gate electrode 218, a second p-base region 220, and a second emitter. Region 222, second n-base region 224, second barrier region 226, second collector region 228, second trench gate insulating film 230, second dummy trench gate insulating film 232, second internal gate resistance 236 (third resistance), second dummy gate resistance 238 (fourth resistance), second gate electrode connection wiring 242 (third connection wiring), second dummy gate electrode connection wiring 244 (fourth) The connection wiring), the second trench 250, and the second dummy trench 252 are provided.

The first internal gate resistor 136 is provided on the semiconductor layer 110. The first internal gate resistor 136 is provided on the side of the first surface P1 of the semiconductor layer 110. The first internal gate resistor 136 is electrically connected between the gate pad electrode 134 and the first trench gate electrode 116. The first internal gate resistor 136 is, for example, polycrystalline silicon.

The first dummy gate resistor 138 is provided on the semiconductor layer 110. The first dummy gate resistor 138 is provided on the side of the first surface P1 of the semiconductor layer 110. The first dummy gate resistor 138 is electrically connected between the gate pad electrode 134 and the first dummy trench gate electrode 118. The first dummy gate resistor 138 is, for example, polycrystalline silicon.

The first gate electrode connection wiring 142 is electrically connected between the first trench gate electrode 116 and the first internal gate resistor 136. The first gate electrode connection wiring 142 is connected to the end of the first trench gate electrode 116. The first gate electrode connection wiring 142 is connected to the first trench gate electrode 116 by, for example, a control portion (not shown).

The first dummy gate electrode connection wiring 144 is electrically connected between the first dummy trench gate electrode 118 and the first dummy gate resistor 138. The first dummy gate electrode connection wiring 144 is connected to the end of the first dummy trench gate electrode 118. The first dummy gate electrode connection wiring 144 is connected to the first dummy trench gate electrode 118 by, for example, a control portion (not shown).

The first trench gate electrode 116 and the first dummy trench gate electrode 118 are located between the first gate electrode connection wiring 142 and the first dummy gate electrode connection wiring 144. In other words, the first gate electrode connection wiring 142 is located at one end of the first trench gate electrode 116 and the first dummy trench gate electrode 118, and the first dummy gate electrode connection wiring 144 is located. , The first trench gate electrode 116, and the other end of the first dummy trench gate electrode 118.

The CR time constant of the first trench gate electrode 116 is smaller than the CR time constant of the first dummy trench gate electrode 118. The CR time constant of the first trench gate electrode 116 mainly includes the capacitance between the first trench gate electrode 116 and the semiconductor layer 110, the resistance value of the first trench gate electrode 116, and the first interior. It is defined by the resistance value of the gate resistance 136. The CR time constant of the first dummy trench gate electrode 118 is mainly the capacitance between the first dummy trench gate electrode 118 and the semiconductor layer 110, the resistance value of the first dummy trench gate electrode 118, and the first dummy trench gate electrode 118. It is defined by the resistance value of the dummy gate resistor 138 of 1.

The second internal gate resistor 236 is provided on the semiconductor layer 110. The second internal gate resistor 236 is provided on the side of the first surface P1 of the semiconductor layer 110. The second internal gate resistor 236 is electrically connected between the gate pad electrode 134 and the second trench gate electrode 216. The second internal gate resistor 236 is, for example, polycrystalline silicon.

The second dummy gate resistor 238 is provided on the semiconductor layer 110. The second dummy gate resistor 238 is provided on the side of the first surface P1 of the semiconductor layer 110. The second dummy gate resistor 238 is electrically connected between the gate pad electrode 234 and the second dummy trench gate electrode 218. The second dummy gate resistor 238 is, for example, polycrystalline silicon.

The second gate electrode connection wiring 242 is electrically connected between the second trench gate electrode 216 and the second internal gate resistor 236. The second gate electrode connection wiring 242 is connected to the end of the second trench gate electrode 216. The second gate electrode connection wiring 242 is connected to the second trench gate electrode 216, for example, at a control portion (not shown).

The second dummy gate electrode connection wiring 244 is electrically connected between the second dummy trench gate electrode 218 and the second dummy gate resistor 238. The second dummy gate electrode connection wiring 244 is connected to the end of the second dummy trench gate electrode 218. The second dummy gate electrode connection wiring 244 is connected to the second dummy trench gate electrode 218 by, for example, a control portion (not shown).

The second trench gate electrode 216 and the second dummy trench gate electrode 218 are located between the second gate electrode connection wiring 242 and the second dummy gate electrode connection wiring 244. In other words, the second gate electrode connection wiring 242 is located at one end of the second trench gate electrode 216 and the second dummy trench gate electrode 218, and the second dummy gate electrode connection wiring 244 is located. , The second trench gate electrode 216, and the second dummy trench gate electrode 218 are located at the other end.

The CR time constant of the second trench gate electrode 216 is smaller than the CR time constant of the second dummy trench gate electrode 218. The CR time constant of the second trench gate electrode 216 is mainly the capacitance between the second trench gate electrode 216 and the semiconductor layer 110, the resistance value of the second trench gate electrode 216, and the second interior. It is defined by the resistance value of the gate resistance 236. The CR time constant of the second dummy trench gate electrode 218 is mainly the capacitance between the second dummy trench gate electrode 218 and the semiconductor layer 110, the resistance value of the second dummy trench gate electrode 218, and the second dummy trench gate electrode 218. It is defined by the resistance value of the dummy gate resistor 238 of 2.

As shown in FIG. 11, in the trench IGBT 200 of the present embodiment, the first internal gate resistor (Rg-in (1)) and the first dummy gate resistor (Rg-dummy (1)) are connected in parallel. .. The first internal gate resistor (Rg-in (1)) and the first dummy gate resistor (Rg-dummy (1)) are connected to the gate driver outside the IGBT 200, for example via an external gate resistor. .. A gate voltage (Vg) is applied to the first trench gate electrode 116 and the first dummy trench gate electrode 118 by the gate driver.

The first internal gate resistor (Rg-in (1)) corresponds to the first internal gate resistor 136 in FIG. The first dummy gate resistor (Rg-dummy (1)) corresponds to the first dummy gate resistor 138 in FIG.

Further, in the trench IGBT 200 of the embodiment, a second internal gate resistor (Rg-in (2)) and a second dummy gate resistor (Rg-dummy (2)) are connected in parallel. The second internal gate resistor (Rg-in (2)) and the second dummy gate resistor (Rg-dummy (2)) are connected to the gate driver outside the IGBT 200, for example via an external gate resistor. .. A gate voltage (Vg) is applied to the second trench gate electrode 216 and the second dummy trench gate electrode 218 by the gate driver.

The second internal gate resistor (Rg-in (2)) corresponds to the second internal gate resistor 236 of FIG. The second dummy gate resistor (Rg-dummy (2)) corresponds to the second dummy gate resistor 238 in FIG.

In the trench IGBT 200 of the present embodiment, each of the first segment 201 and the second segment 202 includes an internal gate resistor and a dummy gate resistor. A first internal gate resistor 136 and a second internal gate resistor 236 are formed between the first trench gate electrode 116 of the first segment 201 and the second trench gate electrode 216 of the second segment 202. exist. Further, between the first dummy trench gate electrode 118 of the first segment 201 and the second dummy trench gate electrode 218 of the second segment 202, a first dummy gate resistor 138 and a second dummy are inserted. There is a gate resistor 238.

Therefore, for example, even if a vibration of the gate voltage occurs in one segment, the vibration is suppressed from propagating to the other segment. Therefore, the malfunction of the IGBT caused by the vibration of the gate voltage can be reduced.

As described above, according to the trench IGBT 200 of the present embodiment, as with the trench IGBT 100 of the first embodiment, an IGBT having a low on-resistance and a high switching speed can be realized. Further, it is possible to realize an IGBT capable of suppressing vibration of the gate voltage and overshoot / undershoot. In addition, the chip area can be reduced and the manufacturing process can be simplified. Further, the defect of the IGBT caused by the vibration of the gate voltage can be reduced.

(Third Embodiment)
The semiconductor device of the present embodiment has a third electric resistance electrically connected between the second electric resistance and the dummy trench gate electrode, and electricity between the third electric resistance and the dummy trench gate electrode. A fourth electrical resistance connected to the surface, a second gate electrode pad electrically connected between the second electrical resistance and the third electrical resistance, and a third electrical resistance and a dummy trench gate. It differs from the first embodiment in that it further includes a third gate electrode pad electrically connected to the electrode. Hereinafter, some descriptions of the contents overlapping with the first embodiment will be omitted.

FIG. 12 is a schematic plan view of the semiconductor device of this embodiment.

The semiconductor device of this embodiment is a trench IGBT 300 having a gate electrode in a trench formed in a semiconductor layer. The trench IGBT 300 is a thinned IGBT having a dummy trench gate electrode.

The trench IGBT 300 of the present embodiment includes an emitter electrode 12, a trench gate electrode 16, a dummy trench gate electrode 18, a gate pad electrode 34 (first gate pad electrode), a gate pad electrode 134 (second gate pad electrode), and a gate. Pad electrode 234 (third gate pad electrode), first internal gate resistance 336 (first electric resistance), second internal gate resistance 436 (second electric resistance), third internal gate resistance 536 (third internal gate resistance) 3rd electric resistance), 4th internal gate resistance 636 (4th electric resistance), emitter pad electrode 40, gate electrode connection wiring 42 (1st connection wiring), dummy gate electrode connection wiring 44 (2nd electric resistance) (Connection wiring) is provided.

The first internal gate resistor 336 is electrically connected between the gate pad electrode 34 and the trench gate electrode 16. The second internal gate resistor 436 (second electrical resistance) is electrically connected between the gate pad electrode 34 and the dummy trench gate electrode 18. The third internal gate resistor 536 (third electrical resistance) is electrically connected between the second internal gate resistor 436 (second electrical resistance) and the dummy trench gate electrode 18. The fourth internal gate resistor 636 (fourth electrical resistance) is electrically connected between the third internal gate resistor 536 (third electrical resistance) and the dummy trench gate electrode 18.

The gate pad electrode 134 is electrically connected between the second internal gate resistor 436 (second electrical resistance) and the third internal gate resistor 536. The gate pad electrode 234 is electrically connected between the third internal gate resistor 536 and the fourth internal gate resistor 636.

According to the IGBT 300 of the present embodiment, an internal gate connected to the trench gate electrode 16 by selecting a desired gate pad electrode from the three gate pad electrodes 34, 134, 234 and applying a gate voltage. It is possible to change the ratio of the resistance (Rg-in) to the dummy gate resistance (Rg-dummy) connected to the dummy trench gate electrode 18. In other words, it is possible to change the ratio of the CR time constant of the trench gate electrode 16 to the CR time constant of the dummy trench gate electrode 18. Therefore, for example, after the device is manufactured, the switching speed can be adjusted according to the application of the IGBT.

As described above, according to the trench IGBT 300 of the present embodiment, as with the IGBT 100 of the first embodiment, an IGBT having a low on-resistance and a high switching speed can be realized. Further, it is possible to realize an IGBT capable of suppressing vibration of the gate voltage and overshoot / undershoot. In addition, the chip area can be reduced and the manufacturing process can be simplified. Furthermore, the switching speed can be adjusted after the device is manufactured.

(Fourth Embodiment)
In the semiconductor device of the present embodiment, a semiconductor layer having a first surface, a second surface facing the first surface, an emitter electrode having at least a part in contact with the first surface, and at least a part having a first surface are present. A collector electrode in contact with the second surface, an upper trench gate electrode provided in the semiconductor layer and extending in the first direction substantially parallel to the first surface, and an upper trench gate electrode provided in the semiconductor layer. A lower trench gate electrode, which is provided between the surface and the second surface and extends in the first direction and is electrically separated from the upper trench gate electrode, and a lower trench gate electrode which is provided in the semiconductor layer and is provided in the semiconductor layer in the first direction. An extending upper dummy trench gate electrode, provided in the semiconductor layer, provided between the upper dummy trench gate electrode and the second surface, extending in the first direction, and electrically with the upper dummy trench gate electrode. The lower dummy trench gate electrode separated into the semiconductor layer, the p-type p-base region provided in the semiconductor layer, and the p-base region provided in the semiconductor layer and provided between the p-base region and the first surface. An n-type emitter region electrically connected to an emitter electrode, an n-type n-base region provided in a semiconductor layer and provided between a p-base region and a second surface, and a semiconductor layer. Between the p-type collector region, which is provided inside and between the n-base region and the second surface, and is electrically connected to the collector electrode, and between the upper trench gate electrode and the p-base region, the upper part. A trench gate insulating film provided between the trench gate electrode and the emitter region and between the lower trench gate electrode and the n-base region and in contact with the p-base region, the emitter region, and the n-base region, and an upper dummy trench. A dummy trench gate insulating film provided between the gate electrode and the p-base region and between the lower dummy trench gate electrode and the n-base region and in contact with the p-base region and the n-base region, and an upper trench gate electrode. , The lower trench gate electrode, and the first gate pad electrode electrically connected to the lower dummy trench gate electrode, and the first gate pad electrode electrically connected between the first gate pad electrode and the upper trench gate electrode. The electrical resistance of 1 and the second electrical resistance electrically connected between the first gate pad electrode and the lower trench gate electrode and between the first gate pad electrode and the lower dummy trench gate electrode. The CR time constant of the upper trench gate electrode is smaller than the CR time constant of the lower dummy trench gate electrode.

FIG. 13 is a schematic plan view of the semiconductor device of this embodiment. FIG. 14 is a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 14A is a cross-sectional view taken along the line FF'of FIG. FIG. 14B is an explanatory diagram in which an equivalent circuit is overlaid on FIG. 14A.

The semiconductor device of this embodiment is a trench IGBT 400 having a gate electrode in a trench formed in a semiconductor layer. The trench IGBT 400 is a thinned IGBT having a dummy trench gate electrode. The trench IGBT 400 is an IGBT having a double gate electrode structure having vertically separated gate electrodes in one trench.

The trench IGBT 400 of the present embodiment includes a semiconductor layer 10, an emitter electrode 12, a collector electrode 14, an upper trench gate electrode 16a, a lower trench gate electrode 16b, an upper dummy trench gate electrode 18a, a lower dummy trench gate electrode 18c, and a p-base region 20. , Emitter region 22, n-base region 24, barrier region 26 (n-type semiconductor region), collector region 28, trench gate insulating film 30, dummy trench gate insulating film 32, gate pad electrode 34 (first gate pad electrode), Internal gate resistance 36 (first electric resistance), dummy gate resistance 38 (second electric resistance), emitter pad electrode 40, gate electrode connection wiring 42 (first connection wiring), dummy gate electrode connection wiring 44 (first) 2 connection wiring), a trench 50, and a dummy trench 52 are provided.

The semiconductor layer 10 has a first surface P1 and a second surface P2 facing the first surface P1. The semiconductor layer 10 is, for example, single crystal silicon. The film thickness of the semiconductor layer 10 is, for example, 50 μm or more and 700 μm or less.

At least a part of the emitter electrode 12 is in contact with the first surface P1 of the semiconductor layer 10. For example, at least a part of the emitter electrode 12 is in contact with the upper dummy trench gate electrode 18a. The emitter electrode 12 is, for example, a metal. An emitter voltage (Ve) is applied to the emitter electrode 12. The emitter voltage is, for example, 0V.

At least a part of the collector electrode 14 is in contact with the second surface P2 of the semiconductor layer 10. The collector electrode 14 is, for example, a metal. A collector voltage (Vc) is applied to the collector electrode 14. The collector voltage is, for example, 200 V or more and 6500 V or less.

A plurality of upper trench gate electrodes 16a and lower trench gate electrodes 16b are provided in the semiconductor layer 10. The upper trench gate electrode 16a and the lower trench gate electrode 16b are provided in the trench 50 formed in the semiconductor layer 10. The upper trench gate electrode 16a and the lower trench gate electrode 16b extend in a first direction substantially parallel to the first surface P1. The lower trench gate electrode 16b is provided between the upper trench gate electrode 16a and the second surface P2. The upper trench gate electrode 16a and the lower trench gate electrode 16b are electrically separated. An insulating film is provided between the upper trench gate electrode 16a and the lower trench gate electrode 16b. The upper trench gate electrode 16a and the lower trench gate electrode 16b are, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

A plurality of upper dummy trench gate electrodes 18a and lower dummy trench gate electrodes 18b are provided in the semiconductor layer 10. The upper dummy trench gate electrode 18a and the lower dummy trench gate electrode 18b are provided in the dummy trench 52 formed in the semiconductor layer 10. The upper dummy trench gate electrode 18a and the lower dummy trench gate electrode 18b extend in the first direction substantially parallel to the first surface P1. The lower dummy trench gate electrode 18b is provided between the upper dummy trench gate electrode 18a and the second surface P2. The upper dummy trench gate electrode 18a and the lower dummy trench gate electrode 18b are electrically separated. An insulating film is provided between the upper dummy trench gate electrode 18a and the lower dummy trench gate electrode 18b. The upper dummy trench gate electrode 18a is provided between the two upper trench gate electrodes 16a in parallel with the upper trench gate electrode 16a. The lower dummy trench gate electrode 18b is provided between the two lower trench gate electrodes 16b in parallel with the lower trench gate electrode 16b. The upper dummy trench gate electrode 18a and the lower dummy trench gate electrode 18b are, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

The upper dummy trench gate electrode 18a is electrically connected to, for example, the emitter electrode 12. The upper dummy trench gate electrode 18a is in contact with, for example, the emitter electrode 12. The upper dummy trench gate electrode 18a can be made floating, for example.

The p-base region 20 is provided in the semiconductor layer 10. The p-base region 20 is a p-type semiconductor region. The region of the p-base region 20 in contact with the trench gate insulating film 30 functions as a channel region of the IGBT 400.

The emitter region 22 is provided in the semiconductor layer 10. The emitter region 22 is provided between the p-base region 20 and the first surface P1 and is in contact with the trench gate insulating film 30. The emitter region 22 is an n-type semiconductor region. The emitter region 22 is not provided between the two dummy trenches 52. The emitter region 22 is electrically connected to the emitter electrode 12.

The n-base region 24 is provided in the semiconductor layer 10. The n-base region 24 is provided between the p-base region 20 and the second surface. The n-base region 24 is an n-type semiconductor region.

The barrier region 26 is provided in the semiconductor layer 10. The barrier region 26 is provided between the p-base region 20 and the n-base region 24. The barrier region 26 is an n-type semiconductor region. The concentration of n-type impurities in the barrier region 26 is higher than the concentration of n-type impurities in the n-base region 24. The concentration of n-type impurities in the barrier region 26 is lower than the concentration of n-type impurities in the emitter region 22. The barrier region 26 has a function of reducing the on-resistance of the trench IGBT 400.

The distance from the first surface P1 to the interface between the n-base region 24 and the barrier region 26 is larger than the distance from the first surface P1 to the lower trench gate electrode 16b. Further, the distance from the first surface P1 to the interface between the n-base region 24 and the barrier region 26 is larger than the distance from the first surface P1 to the lower dummy trench gate electrode 18b.

The collector region 28 is provided in the semiconductor layer 10. The collector region 28 is provided between the n-base region 24 and the second surface P2. The collector region 28 is a p-type semiconductor region. The p-type impurity concentration in the collector region 28 is higher than the p-type impurity concentration in the p-base region 20. The collector region 28 is electrically connected to the collector electrode 14.

It is also possible to provide a buffer region having a higher n-type impurity concentration than the n-base region 24 between the n-base region 24 and the collector region 28. By providing the buffer region, it is possible to suppress the elongation of the depletion layer when the trench IGBT 400 is in the off state.

The trench gate insulating film 30 is formed between the upper trench gate electrode 16a and the p-base region 20, between the upper trench gate electrode 16a and the emitter region 22, between the upper trench gate electrode 16a and the barrier region 26, and the lower portion. It is provided between the trench gate electrode 16b and the n-base region 24. The trench gate insulating film 30 is provided in the trench 50. The trench gate insulating film 30 is in contact with the p-base region 20, the emitter region 22, the barrier region 26, and the n-base region 24. The trench gate insulating film 30 is, for example, silicon oxide.

The dummy trench gate insulating film 32 is formed between the upper dummy trench gate electrode 18a and the p-base region 20, between the upper dummy trench gate electrode 18a and the barrier region 26, and between the lower dummy trench gate electrode 18b and the n-base region 24. It is provided between and. The dummy trench gate insulating film 32 is provided in the dummy trench 52. The dummy trench gate insulating film 32 is in contact with the p-base region 20, the barrier region 26, and the n-base region 24. The dummy trench gate insulating film 32 does not come into contact with the emitter region 22. The dummy trench gate insulating film 32 is, for example, silicon oxide.

The gate pad electrode 34 is provided on the semiconductor layer 10. The gate pad electrode 34 is provided on the side of the first surface P1 of the semiconductor layer 10. The gate pad electrode 34 is electrically connected to the upper trench gate electrode 16a, the lower trench gate electrode 16b, and the lower dummy trench gate electrode 18b. The gate pad electrode 34 is, for example, metal.

The internal gate resistor 36 is provided on the semiconductor layer 10. The internal gate resistor 36 is provided on the side of the first surface P1 of the semiconductor layer 10. The internal gate resistor 36 is electrically connected between the gate pad electrode 34 and the upper trench gate electrode 16a.

The internal gate resistor 36 is, for example, a semiconductor. The internal gate resistor 36 is, for example, polycrystalline silicon containing conductive impurities. The internal gate resistor 36 is formed of, for example, a material having a higher specific resistance than the gate electrode connection wiring 42.

The dummy gate resistor 38 is provided on the semiconductor layer 10. The dummy gate resistor 38 is provided on the side of the first surface P1 of the semiconductor layer 10. The dummy gate resistor 38 is electrically connected between the gate pad electrode 34 and the lower trench gate electrode 16b and between the lower dummy trench gate electrode 18b.

The dummy gate resistor 38 is, for example, a semiconductor. The dummy gate resistor 38 is, for example, polycrystalline silicon containing conductive impurities. The dummy gate resistor 38 is formed of, for example, a material having a higher specific resistance than the dummy gate electrode connection wiring 44.

The gate electrode connection wiring 42 is electrically connected between the upper trench gate electrode 16a and the internal gate resistor 36. The gate electrode connection wiring 42 is connected to the end of the upper trench gate electrode 16a. The gate electrode connection wiring 42 is connected to the upper trench gate electrode 16a by, for example, a contact portion (not shown). The gate electrode connection wiring 42 is, for example, metal.

The dummy gate electrode connection wiring 44 is electrically connected between the lower trench gate electrode 16b and the lower dummy trench gate electrode 18b and the dummy gate resistor 38. The dummy gate electrode connection wiring 44 is connected to the ends of the lower trench gate electrode 16b and the lower dummy trench gate electrode 18b. The dummy gate electrode connection wiring 44 is connected to the lower trench gate electrode 16b and the lower dummy trench gate electrode 18b at a contact portion (not shown), for example. The dummy gate electrode connection wiring 44 is made of metal, for example.

The upper trench gate electrode 16a and the lower dummy trench gate electrode 18b are located between the gate electrode connection wiring 42 and the dummy gate electrode connection wiring 44. In other words, the gate electrode connection wiring 42 is located at one end of the upper trench gate electrode 16a and the lower dummy trench gate electrode 18b, and the dummy gate electrode connection wiring 44 is the upper trench gate electrode 16a and the lower part. It is located at the other end of the dummy trench gate electrode 18b.

The CR time constant of the upper trench gate electrode 16a is smaller than the CR time constant of the lower dummy trench gate electrode 18b. The CR time constant of the upper trench gate electrode 16a is mainly defined by the capacitance between the upper trench gate electrode 16a and the semiconductor layer 10, the resistance value of the upper trench gate electrode 16a, and the resistance value of the internal gate resistance 36. NS. The CR time constant of the lower dummy trench gate electrode 18b is mainly the capacitance between the lower dummy trench gate electrode 18b and the semiconductor layer 10, the resistance value of the lower dummy trench gate electrode 18b, and the resistance value of the dummy gate resistor 38. Is specified in.

Further, the CR time constant of the upper trench gate electrode 16a is smaller than the CR time constant of the lower trench gate electrode 16b.

The emitter pad electrode 40 is provided on the semiconductor layer 10. The emitter pad electrode 40 is provided on the side of the first surface P1 of the semiconductor layer 10. The emitter pad electrode 40 is electrically connected to the emitter electrode 12.

The IGBT 400 is a three-terminal device having three electrodes of an emitter pad electrode 40, a collector electrode 14, and a gate pad electrode 34 as terminals.

As shown in FIG. 14B, in the trench IGBT 400 of the present embodiment, an internal gate resistor (Rg-in) and a dummy gate resistor (Rg-dummy) are connected in parallel. The internal gate resistor (Rg-in) and dummy gate resistor (Rg-dummy) are connected to the gate driver outside the IGBT 400, for example, via an external gate resistor. A gate voltage (Vg) is applied to the upper trench gate electrode 16a, the lower trench gate electrode 16b, and the lower dummy trench gate electrode 18b by the gate driver.

The internal gate resistance (Rg-in) corresponds to the internal gate resistance 36 in FIG. The dummy gate resistor (Rg-dummy) corresponds to the dummy gate resistor 38 in FIG.

The p-base region 20 is electrically connected to, for example, the emitter electrode 12. The p-base region 20 is fixed to, for example, the ground potential. The p-base region 20 sandwiched between the dummy trench 52 may be, for example, floating.

Hereinafter, the action and effect of the trench IGBT 400 of the present embodiment will be described.

The trench IGBT 400 of the present embodiment has a double gate electrode structure having an upper trench gate electrode 16a and a lower trench gate electrode 16b in one trench 50.

For example, the resistance values of the internal gate resistor 36 and the dummy gate resistor 38 are adjusted so that the CR time constant of the upper trench gate electrode 16a is made smaller than the CR time constant of the lower trench gate electrode 16b. As a result, the charging / discharging of the upper trench gate electrode 16a can be made faster than the charging / discharging of the lower trench gate electrode 16b. Therefore, it is possible to improve the switching speed of the trench IGBT 400.

When the trench IGBT 400 is in the ON state, the lower trench gate electrode 16b is also charged to the gate voltage (Vg) behind the upper trench gate electrode 16a. Therefore, an electron storage layer is formed in the n-base region 24 near the bottom of the trench 50, and the on-resistance is reduced.

Further, as in the trench IGBT 100 of the first embodiment, for example, the resistance values of the internal gate resistance 36 and the dummy gate resistance 38 are adjusted, and the CR time constant of the upper trench gate electrode 16a is set to the CR of the lower dummy trench gate electrode 18b. Make it smaller than the time constant. As a result, the charging / discharging of the upper trench gate electrode 16a can be made faster than the charging / discharging of the lower dummy trench gate electrode 18b. Therefore, it is possible to improve the switching speed of the trench IGBT 400.

Further, similarly to the trench IGBT 100 of the first embodiment, when the trench IGBT 400 is in the ON state, the lower dummy trench gate electrode 18b is also charged to the gate voltage (Vg) behind the upper trench gate electrode 16a. Therefore, an electron storage layer is formed in the n-base region 24 near the bottom of the dummy trench 52, and the on-resistance is reduced.

Further, the upper dummy trench gate electrode 18a is electrically separated from the lower dummy trench gate electrode 18b. Therefore, as compared with the case of the trench IGBT 100 of the first embodiment, the gate capacitance is reduced by the amount of the upper dummy trench gate electrode 18a. Therefore, for example, the drive capacity of the gate driver can be reduced, and the size of the gate driver can be reduced.

FIG. 15 is an explanatory diagram of the operation and effect of the semiconductor device of the present embodiment. FIG. 15 is a diagram showing the relationship between the gate resistance and the time change rate (dV / dt) of the collector-emitter voltage (Vce) at the time of turn-off of the IGBT. The resistance value of the gate resistance is the resistance value of the external gate resistance provided outside the IGBT. The time change rate (dV / dt) of the collector-emitter voltage (Vce) is an index of the switching speed at the time of turn-off.

FIG. 15 also shows the case of the structure of the second comparative embodiment described in the first embodiment for comparison. Further, regarding the present embodiment (fourth embodiment), the cases where the values of the dummy gate resistance (Rg-dummy) are 6.4 Ω, 12.8 Ω, and 25.6 Ω are shown.

In the present embodiment, the feedback capacitance between the collector and the gate is entirely charged and discharged by the current (Ig-dummy) flowing through the dummy gate resistor (Rg-dummy). Therefore, the time change rate (dV / dt) can be adjusted by the value of the dummy gate resistance (Rg-dummy).

As can be seen from FIG. 15, high linearity can be obtained by increasing the value of the dummy gate resistance (Rg-dummy). Therefore, by increasing the value of the dummy gate resistance (Rg-dummy), the controllability of the switching speed by the external gate resistance becomes good.

(Fifth Embodiment)
The semiconductor device of this embodiment has a Zener diode having an anode and a cathode, the anode being electrically connected to the emitter electrode, and the cathode being connected between the second electrical resistance and the dummy trench gate electrode. It differs from the first embodiment in that it is provided. Hereinafter, some descriptions of the contents overlapping with the first embodiment will be omitted.

FIG. 16 is a schematic plan view of the semiconductor device of this embodiment. FIG. 17 is a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 17A is a cross-sectional view taken along the line GG'of FIG. FIG. 17B is an explanatory diagram in which an equivalent circuit is overlaid on FIG. 17A.

The semiconductor device of this embodiment is a trench IGBT 500 having a gate electrode in a trench formed in a semiconductor layer. The trench IGBT 500 is a thinned IGBT having a dummy trench gate electrode.

The trench IGBT 500 includes a Zener diode 60 (ZD in FIG. 17B) having an anode and a cathode. The anode is electrically connected to the emitter electrode 12. The cathode is connected between the dummy gate resistor 38 (second electrical resistance) and the dummy trench gate electrode 18. The Zener diode 60 is formed using, for example, polycrystalline silicon.

In the present embodiment, the feedback capacitance between the collector and the gate is bypassed to the emitter electrode 12 by providing the Zener diode 60. Therefore, the feedback capacitance can be charged and discharged with a smaller gate current as compared with the case without the Zener diode 60. Therefore, the switching speed at the time of turn-off is improved.

From the viewpoint of turning on the Zener diode 60 at the time of turning off the trench IGBT 500, it is preferable to increase the value of the dummy gate resistance (Rg-dummy). By increasing the value of the dummy gate resistance (Rg-dummy), the voltage of the dummy trench gate electrode 18 is pulled by the collector voltage, so that it becomes higher than the Zener voltage of the Zener diode 60, and the Zener diode 60 is turned on. do.

The Zener voltage of the Zener diode 60 is higher than the gate-on voltage applied to the gate pad electrode 34 (first gate pad electrode) when the trench IGBT 500 is turned on. By making the Zener voltage of the Zener diode 60 higher than the gate-on voltage during the ON operation of the trench IGBT 500, it is possible to prevent the Zener diode 60 from operating the Zener diode 60 during the ON operation of the trench IGBT 500 and causing a malfunction of the trench IGBT 500.

FIG. 18 is an explanatory diagram of the operation and effect of the semiconductor device of the present embodiment. FIG. 18 is a diagram showing the relationship between the gate resistance and the time change rate (dV / dt) of the collector-emitter voltage (Vce) at the time of turn-off of the IGBT. The resistance value of the gate resistance is the resistance value of the external gate resistance provided outside the IGBT. The time change rate (dV / dt) of the collector-emitter voltage (Vce) is an index of the switching speed at the time of turn-off.

FIG. 18 also shows the IGBT 100 structure of the first embodiment, the IGBT 800 of the first comparative embodiment and the IGBT 900 of the second comparative embodiment described in the first embodiment for comparison. In the present embodiment, the time change rate (dV / dt) is larger than that in the first embodiment, and the switching speed at the time of turn-off is improved. Further, a switching speed equivalent to that of the first comparative mode can be obtained.

As described above, the trench IGBT 500 of the present embodiment can realize an IGBT having a low on-resistance and a high switching speed.

(Sixth Embodiment)
The semiconductor device of the present embodiment has an anode and a cathode, the anode is electrically connected to the emitter electrode, and the cathode is between the second electric resistance and the lower dummy trench gate electrode, and the second electricity. It differs from the fourth embodiment in that it further includes a Zener diode connected between the resistor and the lower trench gate electrode. Hereinafter, some descriptions of the contents overlapping with the fourth embodiment will be omitted.

FIG. 19 is a schematic plan view of the semiconductor device of this embodiment. FIG. 20 is a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 20A is a cross-sectional view taken along the line HH'of FIG. FIG. 20B is an explanatory diagram in which an equivalent circuit is overlaid on FIG. 20A.

The semiconductor device of this embodiment is a trench IGBT 600 having a gate electrode in a trench formed in a semiconductor layer. The trench IGBT 600 is a thinned IGBT having a dummy trench gate electrode. The trench IGBT 600 is an IGBT having a double gate electrode structure having vertically separated gate electrodes in one trench.

The trench IGBT 600 includes a Zener diode 60 (ZD in FIG. 20B) having an anode and a cathode. The anode is electrically connected to the emitter electrode 12. The cathode is connected between the dummy gate resistor 38 (second electrical resistance) and the lower dummy trench gate electrode 18b. The cathode is connected between the dummy gate resistor 38 (second electrical resistance) and the lower trench gate electrode 16b. The Zener diode 60 is formed using, for example, polycrystalline silicon.

In the present embodiment, the feedback capacitance between the collector and the gate is bypassed to the emitter electrode 12 by providing the Zener diode 60. Therefore, the feedback capacitance can be charged and discharged with a smaller gate current as compared with the case without the Zener diode 60. Therefore, the switching speed at the time of turn-off is improved.

From the viewpoint of turning on the Zener diode 60 at the time of turning off the trench IGBT 600, it is preferable to increase the value of the dummy gate resistance (Rg-dummy).

The Zener voltage of the Zener diode 60 is higher than the gate-on voltage applied to the gate pad electrode 34 (first gate pad electrode) when the trench IGBT 600 is turned on. By making the Zener voltage of the Zener diode 60 higher than the gate-on voltage during the ON operation of the trench IGBT 600, it is possible to prevent the Zener diode 60 from operating the Zener diode 60 during the ON operation of the trench IGBT 600 and causing a malfunction of the trench IGBT 600.

FIG. 21 is an explanatory diagram of the operation and effect of the semiconductor device of the present embodiment. FIG. 21A is a diagram showing the relationship between the gate resistance and the time change rate (dV / dt) of the collector-emitter voltage (Vce) at the time of turn-off of the IGBT. The resistance value of the gate resistance is the resistance value of the external gate resistance provided outside the IGBT. The time change rate (dV / dt) of the collector-emitter voltage (Vce) is an index of the switching speed at the time of turn-off. FIG. 21B is a diagram showing the relationship between the time change rate (dV / dt) of the collector-emitter voltage (Vce) and the maximum value of the gate current (Ig) at the time of turn-off of the IGBT.

FIG. 21 also shows the case of the IGBT 500 of the fifth embodiment, the IGBT 800 of the first comparative embodiment described in the first embodiment, and the IGBT 900 of the second comparative embodiment for comparison.

As is clear from FIG. 21 (a), in the present embodiment, the time change rate (dV / dt) is larger than that in the first comparative embodiment, and the switching speed at the time of turn-off is improved. Further, since higher linearity can be obtained than in the first comparative embodiment, the controllability of the switching speed by the external gate resistance is improved.

Further, as is clear from FIG. 21A, in the present embodiment, the time change rate (dV / dt) is larger than that in the fifth embodiment, and the switching speed at the time of turn-off is improved. Further, since higher linearity than that of the fifth embodiment can be obtained, the controllability of the switching speed by the external gate resistance is improved. This is because, in the case of the present embodiment, unlike the fifth embodiment, by providing the lower trench gate electrode 16b, almost all the feedback capacitance is bypassed to the emitter electrode.

Further, as is clear from FIG. 21B, in the present embodiment, a fast switching speed can be realized with a small gate current.

As described above, the trench IGBT 600 of the present embodiment can realize an IGBT having a low on-resistance and a high switching speed.

In the first to sixth embodiments, the case where the semiconductor layer is single crystal silicon has been described as an example, but the semiconductor layer is not limited to single crystal silicon. For example, other single crystal semiconductors such as single crystal silicon carbide may be used.

In the first to sixth embodiments, the case where the number of dummy trench gate electrodes sandwiched between the two trench gate electrodes is three has been described as an example, but the number of dummy trench gate electrodes is three. The number is not limited to the above, and the number may be one, two, or four or more.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or modified with the components of another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

10 Semiconductor layer 12 Emitter electrode 14 Collector electrode 16 Trench gate electrode 16a Upper trench gate electrode 16b Lower trench gate electrode 18 Dummy trench gate electrode 18a Upper dummy trench gate electrode 18b Lower dummy trench gate electrode 20 p Base region 22 Emitter region 24 n Base Region 26 Barrier region (n-type semiconductor region)
28 Collector area 30 Trench gate insulating film 32 Dummy trench gate insulating film 34 Gate pad electrode (first gate pad electrode)
36 Internal gate resistance (first electrical resistance)
38 Dummy gate resistance (second electrical resistance)
42 Gate electrode connection wiring (first connection wiring)
44 Dummy gate electrode connection wiring (second connection wiring)
60 Zener diode 100 Trench IGBT (semiconductor device)
110 Semiconductor layer 112 First emitter electrode 114 First collector electrode 116 First trench gate electrode 118 First dummy trench gate electrode 120 First p base region 122 First emitter region 124 First n base region 128 First collector region 130 First trench gate insulating film 132 First dummy trench gate insulating film 134 Gate pad electrode (second gate pad electrode)
136 First internal gate resistance (first electrical resistance)
138 First dummy gate resistance (second electrical resistance)
142 First gate electrode connection wiring (first connection wiring)
144 First dummy gate electrode connection wiring (second connection wiring)
200 Trench IGBT (Semiconductor Device)
212 Second emitter electrode 214 Second collector electrode 216 Second trench gate electrode 218 Second dummy trench gate electrode 220 Second p base region 222 Second emitter region 224 Second n base region 228 Second Collector area 230 Second trench gate insulating film 232 Second dummy trench gate insulating film 234 Gate pad electrode (third gate pad electrode)
236 Second internal gate resistance (third electrical resistance)
238 Second dummy gate resistance (fourth electrical resistance)
242 Second gate electrode connection wiring (third connection wiring)
244 Second dummy gate electrode connection wiring (fourth connection wiring)
300 Trench IGBT (Semiconductor Device)
336 First internal gate resistance (first electrical resistance)
400 Trench IGBT (Semiconductor Device)
436 Second internal gate resistance 436 (second electrical resistance)
536 Third internal gate resistance (third electrical resistance)
636 Fourth internal gate resistance (fourth electrical resistance)
P1 first surface P2 second surface

Claims (3)

A semiconductor layer having a first surface and a second surface facing the first surface,
An emitter electrode, which is at least partially in contact with the first surface,
With a collector electrode, at least part of which is in contact with the second surface,
An upper trench gate electrode provided in the semiconductor layer and extending in a first direction substantially parallel to the first surface,
A lower trench provided in the semiconductor layer, provided between the upper trench gate electrode and the second surface, extending in the first direction and electrically separated from the upper trench gate electrode. With the gate electrode
An upper dummy trench gate electrode provided in the semiconductor layer and extending in the first direction, and
It is provided in the semiconductor layer, is provided between the upper dummy trench gate electrode and the second surface, extends in the first direction, and is electrically separated from the upper dummy trench gate electrode. Lower dummy trench gate electrode and
A p-type p-base region provided in the semiconductor layer and
An n-type emitter region provided in the semiconductor layer, provided between the p-base region and the first surface, and electrically connected to the emitter electrode.
An n-type n-base region provided in the semiconductor layer and provided between the p-base region and the second surface.
A p-type collector region provided in the semiconductor layer, provided between the n-base region and the second surface, and electrically connected to the collector electrode.
The p-base region is provided between the upper trench gate electrode and the p-base region, between the upper trench gate electrode and the emitter region, and between the lower trench gate electrode and the n-base region. , The emitter region and the trench gate insulating film in contact with the n-base region.
A dummy trench provided between the upper dummy trench gate electrode and the p-base region and between the lower dummy trench gate electrode and the n-base region and in contact with the p-base region and the n-base region. With the gate insulating film
The upper trench gate electrode, the lower trench gate electrode, and the first gate pad electrode electrically connected to the lower dummy trench gate electrode.
A first electrical resistance electrically connected between the first gate pad electrode and the upper trench gate electrode,
A second electrical resistance electrically connected between the first gate pad electrode and the lower trench gate electrode and between the first gate pad electrode and the lower dummy trench gate electrode.
With
A semiconductor device in which the CR time constant based on the product of the capacitance and the resistance value of the upper trench gate electrode is smaller than the CR time constant based on the product of the capacitance and the resistance value of the lower dummy trench gate electrode. A first connection wiring electrically connected between the upper trench gate electrode and the first electrical resistance,
Further comprising a second connection wiring electrically connected between the lower dummy trench gate electrode and the second electrical resistance.
The upper trench gate electrode and the lower dummy trench gate electrode, the semiconductor device according to claim 1 wherein located between the first connecting line and the second connection wiring. The semiconductor device according to claim 2 , wherein the specific resistance of the first electric resistance and the material of the second electric resistance is higher than the specific resistance of the material of the first connection wiring and the second connection wiring. ..

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