JP2012164851A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suitably adjust the parasitic capacitance component of a semiconductor device.SOLUTION: A semiconductor device 10 comprises: a plurality number of emitter regions 20; a body region 12 formed in a region from a surface of a semiconductor layer to a predetermined depth; a drift region 4 formed under the body region 12; a collector region 3 formed under the drift region 4; first trenches 31 extending through the body region 12 from a surface of each emitter region 20; gate insulating films 18 covering the inner surfaces of the first trenches 31; gate electrodes 8 housed in the first trenches 31; second trenches 32 that are each formed between the adjacent first trenches 31 and extend through the body region 12; trench insulating films 33 covering the inner surfaces of the second trenches 32; and conductive layers 35 housed in the second trenches 32. The conductive layers 35 are electrically connected to the gate electrodes 8.

Description

  The present application relates to a technique capable of suitably adjusting a parasitic capacitance component of a semiconductor device.

  A semiconductor structure (MOS, IGBT, etc.) that functions as a semiconductor device on a semiconductor substrate in which a body region of the second conductivity type (eg, p-type) is stacked on the surface of the drift region of the first conductivity type (eg, n-type) The technology to make is developed. In such a semiconductor device, a capacitance formed as a parasitic component around the gate is an important parameter for determining switching characteristics. The parasitic capacitance component is formed by a configuration such as a gate electrode, an insulating film, and a drift region around the gate. For example, in order to realize a high-speed switching operation with low loss, it is necessary to reduce the feedback capacitance between the gate and the collector (drain).

  Patent Document 1 discloses a semiconductor device having a thick oxide film at the bottom of a trench gate. A thick insulating layer separates the trench gate and drain regions at the bottom of the trench. Thereby, the feedback capacity can be reduced.

JP-T-2004-538648

  In the technique of Patent Document 1, the parasitic capacitance component is adjusted by increasing the thickness of the oxide film at the bottom of the trench gate. Therefore, in order to reduce the parasitic capacitance component, the oxide film at the bottom of the trench gate must be thickened. However, if the oxide film at the bottom of the trench gate is too thick, a channel cannot be formed, and the main characteristics of the semiconductor device (Switch characteristics, conduction performance, etc.) cannot be obtained. Therefore, there is a problem that the parasitic capacitance component can be adjusted only within a range in which the main characteristics of the semiconductor device can be ensured, and the function of adjusting the parasitic capacitance cannot be sufficiently obtained.

  The technology of the present application has been developed to solve the above problems. That is, the present application provides a technique capable of suitably adjusting the parasitic capacitance component of a semiconductor device without affecting the main characteristics of the semiconductor device.

  A semiconductor device disclosed in the present application surrounds a plurality of first semiconductor regions of a first conductivity type formed facing a part of the surface of a semiconductor layer, and the first semiconductor region. A second conductivity type body region formed in a region from the surface to a predetermined depth and a first conductivity type drift formed in the lower portion of the body region and separated from the first semiconductor region by the body region A plurality of first trenches extending through the body region from the surface of each region, a second semiconductor region formed below the drift region, and the surface of each first semiconductor region, and the bottom surface of which protrudes into the drift region A gate insulating layer covering the inner surface of each first trench, a first trench gate electrode housed in each first trench surrounded by the gate insulating layer, and an adjacent first trench A plurality of second trenches extending between the body regions and extending through the body region, the bottom surface of which protrudes into the drift region, and a trench insulating layer covering the inner surface of each second trench; And a plurality of conductive layers accommodated in each second trench in a state surrounded by the trench insulating layer. In addition, at least one of the plurality of conductive layers can be electrically connected to the first trench gate electrode, or can be selectively electrically connected to the first semiconductor region.

  The first trench operates as a trench gate. The second trench functions as a capacitor for increasing the input capacitance (capacitance component between the gate and the first semiconductor region) when the conductive layer is electrically connected to the first trench gate electrode. The second trench functions as a capacitor for increasing output capacitance (capacitance component of the first semiconductor region-second semiconductor region) when the conductive layer is electrically connected to the first semiconductor region. To do. Examples of the first semiconductor region include an emitter region or a source region. Examples of the second semiconductor region include a collector region or a drain region.

  Further, since it is not necessary to change the structure of the first trench in order to increase the input capacitance and the output capacitance, it is possible to prevent the main characteristics (switch characteristics, conduction performance, etc.) of the semiconductor device from being affected. As described above, a sufficient capacity adjustment function can be obtained without affecting the main characteristics of the semiconductor device.

  In the semiconductor device disclosed in the present application, a bottom insulating layer is formed at the bottom of the second trench in a state surrounded by the trench insulating layer, and the top surface of the bottom insulating layer includes a body region and a drift region. The conductive layer may be formed on the bottom insulating layer, and the conductive layer may be electrically connected to the first trench gate electrode.

  Since the upper surface of the bottom insulating layer formed at the bottom in the second trench is located on the body region side with respect to the interface between the body region and the drift region, the channel does not conduct when the semiconductor device is turned on. Therefore, no electrical operation is performed in the second trench. Thereby, the second trench can be suitably functioned as a capacitor for increasing the input capacitance (capacitance component between the gate and the first semiconductor region).

  When a capacitor element is connected externally to the trench gate, the wiring length becomes long. Then, since the parasitic inductance of the wiring increases, LC resonance due to the capacitor element and the parasitic inductance may not be ignored. On the other hand, in this application, since the 2nd trench which is a capacitor is located in the immediate vicinity of the 1st trench which is a trench gate, the wiring length at the time of connecting a capacitor to a trench gate can be shortened. Accordingly, since the parasitic inductance of the wiring can be reduced, the influence of resonance can be reduced.

  In addition, the semiconductor device may become high temperature. When a capacitor element is connected externally to the trench gate, it is necessary to consider the high temperature reliability of the capacitor element. On the other hand, in the present application, the second trench functions as a capacitor for increasing the input capacitance (capacitance component between the gate and the first semiconductor region). Therefore, the high temperature reliability of the capacitor can be made equivalent to that of the semiconductor device.

  In the semiconductor device disclosed in the present application, when the conductive layer is connected to the first trench gate electrode, the first gate which is the resistance component of the path from the gate voltage supply source to the first trench gate electrode The resistance component is made smaller than the second gate resistance component that is the resistance component of the path from the gate voltage supply source to the first trench gate electrode when the conductive layer is not connected to the first trench gate electrode. May be. Further, the integrated value of the sum of the capacitance component of the first trench and the capacitance component of the second trench and the first gate resistance component is equal to or less than the integration value of the capacitance component of the first trench and the second gate resistance component. As described above, the first gate resistance component may be set.

  The capacitance component of the first trench is a capacitance formed by the configuration of the first trench gate electrode, the gate insulating layer, and the region between the bottom surface of the first trench and the second semiconductor region. The capacitance component of the second trench is a capacitance formed by the configuration of the conductive layer, the trench insulating layer, and the region between the bottom surface of the second trench and the second semiconductor region. An operation when the semiconductor device is turned off will be described. When the gate resistance component is reduced, the rise time of the element voltage at the turn-off time is shortened, so that the switching loss can be reduced. At the same time, however, there is a trade-off relationship in which the surge voltage increases because the reduction rate of the device current increases. In the present application, the total value of the capacitance components can be increased by adding the capacitance component of the second trench to the capacitance component of the first trench. As a result, only the decrease rate of the device current can be reduced while maintaining the rise time of the device voltage in a short state. Therefore, turn-off loss can be reduced while suppressing an increase in surge voltage. From the above, it is possible to achieve both a reduction in switching loss and suppression of surge voltage.

  In the semiconductor device disclosed in the present application, a plurality of second trenches are formed in a region where the body region is exposed on the surface of the semiconductor layer, and the conductive material accommodated in each of the plurality of second trenches. At least one of the layers may be selectively electrically connected to the first semiconductor region.

  Since the second trench is formed in a region where the body region is exposed on the surface of the semiconductor layer, the first semiconductor region does not exist around the second trench. Therefore, no electrical operation is performed in the second trench. Accordingly, the second trench can be suitably functioned as a capacitor for increasing the output capacitance (capacitance component between the first semiconductor region and the second semiconductor region).

  When a semiconductor device is mounted on various devices using wiring, the resonance frequency is determined by the output capacity and wiring inductance of the semiconductor device. If the resonance frequency is inappropriate for the mounted device, resonance may occur. In the present application, at least one of the conductive layers in the second trench gate can be selectively electrically connected to the first semiconductor region. The output capacitance can be changed by changing the number of conductive layers in the second trench gate connected to the first semiconductor region. This makes it possible to intentionally shift the resonance frequency. Therefore, it is possible to set the resonance frequency to a value at which resonance does not occur, thereby preventing the occurrence of resonance. Thereby, the situation where the lifetime of a semiconductor device becomes short by resonance etc. can be prevented.

  Moreover, in this application, since the 2nd trench which is a capacitor is located in the immediate vicinity of the 1st trench which is a trench gate, the wiring length at the time of connecting a capacitor to a trench gate can be shortened. Accordingly, since the parasitic inductance of the wiring can be reduced, the influence of resonance can be reduced. In the present application, the second trench functions as a capacitor for increasing the output capacitance (capacitance component between the second semiconductor region and the first semiconductor region). Therefore, the high temperature reliability of the capacitor can be made equivalent to that of the semiconductor device.

  In the semiconductor device disclosed in the present application, an upper insulating layer is formed above the first trench and the second trench, and an upper electrode is formed above the upper insulating layer and the first semiconductor region. And a pad portion connected to the conductive layer accommodated in each of the plurality of second trenches, and the pad portion and the upper electrode may be electrically connected.

  As an example of a method for electrically connecting the pad portion and the upper electrode, there is a method for connecting both with a wire. Thereby, the second trench functioning as a capacitor can be selectively connected to the first semiconductor region. Therefore, it is possible to appropriately change the output capacity and shift the resonance frequency.

1 is a cross-sectional view of a semiconductor device of Example 1. FIG. 6 is a graph showing the operation of the semiconductor device of Example 1. It is sectional drawing of the semiconductor device of a conventional structure. 6 is a plan view of a semiconductor device according to Example 2. FIG. 6 is a cross-sectional view of a semiconductor device of Example 2. FIG. 6 is an equivalent circuit of the semiconductor device of Example 2. It is a figure which shows a full bridge circuit. It is a figure which shows the equivalent circuit of a resonance part. It is a figure which shows the equivalent circuit of a resonance part. It is a graph which shows the oscillation operation | movement of a resonance part.

The main features of the embodiments described below are listed.
(Feature 1) The semiconductor substrate is Si.
(Feature 2) The semiconductor structure formed in the cell area is an IGBT structure.
(Feature 3) The semiconductor structure formed in the cell area is a MOS structure.

Example 1
The basic principle of the semiconductor element driving circuit according to the present invention will be described by taking an IGBT (insulated gate bipolar transistor) element as an example of the semiconductor element. Of course, it is not limited to the IGBT, and may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  As shown in FIG. 1, a collector electrode 2 is formed on the back surface of the semiconductor device 10 of the first embodiment. A p + -type (second conductivity type) second semiconductor region (collector region) 3 is formed on the surface of the collector electrode 2. An n − type drift region 4 is formed on the surface of the collector region 3. A p-type (second conductivity type) body region 12 is formed on the surface of the drift region 4. A plurality of n + type (first conductivity type) first semiconductor regions (emitter regions) 20 are formed on the surface of the body region 12. The body region 12 surrounds the emitter region 20. Each emitter region 20 is separated from the drift region 4 by the body region 12.

  A first trench 31 extending from the surface of each emitter region 20 through the body region 12 is formed. The bottom surface of the first trench 31 protrudes into the drift region 4. The inner wall of the first trench 31 is covered with the gate insulating film 18. The gate electrode 8 is accommodated in the first trench 31 in a state surrounded by the gate insulating film 18. The gate electrode 8 is opposed to the body region 12 in a range separating the drift region 4 and the emitter region 20 via the gate insulating film 18.

  A second trench 32 is formed between the adjacent first trenches 31. The second trench 32 extends through the body region 12 from the surface of the emitter region 20, and its bottom surface projects into the drift region 4. The inner wall of the second trench is covered with a trench insulating film 33. In the state surrounded by the trench insulating film 33, an insulating layer 34 is disposed at the bottom in the second trench 32. An example of the insulating layer 34 is n-type polycrystalline silicon (n-polySi). The upper surface of the insulating layer 34 is located closer to the body region 12 than the interface between the body region 12 and the drift region 4. A conductive layer 35 is accommodated in an upper layer of the insulating layer 34 in a state surrounded by the trench insulating film 33.

  Emitter electrodes 14 are formed on the surfaces of the body region 12 and the emitter region 20. The gate electrode 8 and the conductive layer 35 are insulated from the emitter electrode 14 by the insulating film 16. In the insulating film 16, a contact hole (not shown) that exposes the surface of the gate electrode 8 and the conductive layer 35 is formed in any cross section in the depth direction of FIG. 1. The conductive layer 35 and the gate electrode 8 are electrically connected through these contact holes. The conductive layer 35 and the gate electrode 8 are connected to a drive circuit (not shown) for supplying a gate voltage via a contact hole.

  The function of the first trench 31 will be described. In the semiconductor device 10, a gate voltage (for example, 15 V and 0 V) output from the drive circuit is supplied to the gate electrode 8 through a path from the drive circuit to the gate electrode 8. Thereby, each of the first trenches 31 operates as a trench gate, and the turn-on / turn-off of the semiconductor device 10 is controlled. The first trench 31 has a first trench capacitance component. The first trench capacitance component is a capacitance component formed by the configuration of the gate electrode 8, the gate insulating film 18, and the region between the bottom surface of the first trench 31 and the collector region 3.

  The function of the second trench 32 will be described. Since the upper surface of the insulating layer 34 formed at the bottom in the second trench 32 is located on the body region 12 side with respect to the interface between the body region 12 and the drift region 4, at the time of turning on the semiconductor device 10, The channel does not conduct. Therefore, no electrical operation is performed in the second trench 32. Thus, by making it the structure which does not operate a trench bottom part electrically, the 2nd trench 32 can be functioned suitably as a capacitor. The capacitance component when the second trench 32 functions as a capacitor is formed by the configuration of the conductive layer 35, the insulating layer 34, the trench insulating film 33, and the region between the bottom surface of the second trench 32 and the collector region 3. .

  The conductive layer 35 of the second trench 32 is electrically connected to the gate electrode 8. As a result, the second trench 32 can function as a capacitor for increasing the input capacitance (capacitance component between the gate electrode 8 and the emitter region 20).

  A semiconductor device 100 having a conventional structure will be described with reference to FIG. 3 as an object to be compared with the semiconductor device 10 of the present application. The semiconductor device 100 is a dummy trench type IGBT including a second trench 132 that functions as a dummy trench. The second trench 132 extends from the surface of the body region 12 through the body region 12, and its bottom surface protrudes into the drift region 4. The conductive layer 135 is accommodated in the entire region inside the second trench 132. In addition, since the insulating film 16 that insulates the conductive layer 135 is not formed on the second trench 132, the conductive layer 135 is electrically connected to the emitter electrode 14. Since other structures are the same as those of the semiconductor device 10 of FIG. 1, detailed description thereof is omitted here.

  The function of the dummy trench will be described. In order to reduce the on-resistance, it may be desirable to increase the distance between the trench gates (first trenches 31) to some extent. However, when the inter-trench distance of the first trench 31 is increased, a large electric field may be applied to the pn junction between the body region 12 and the drift region 4 in the region between the first trenches 31. Therefore, by forming a dummy trench (second trench 132) in the region, the pn depletion layer can be expanded evenly and the electric field concentration can be reduced.

  The gate resistance component will be described. The gate resistance component is a resistance component of a path from a drive circuit (not shown) that supplies a gate voltage to the gate electrode 8. The gate resistance component can be adjusted to an arbitrary value by inserting a resistor on the path. Here, the gate resistance component in the conventional semiconductor device 100 (FIG. 3) is defined as a gate resistance component Rg1. The gate resistance component in the semiconductor device 10 (FIG. 1) of the present application is a gate resistance component Rg2. The gate resistance component Rg2 of the semiconductor device 10 is smaller than the gate resistance component Rg1 of the semiconductor device 100.

  In the conventional semiconductor device 100, the integrated value of the combined capacitance component of all the first trenches 31 and the gate resistance component Rg1 is defined as the first integrated value. On the other hand, in the semiconductor device 10 of the present application, the integrated value of the sum of the combined capacitance component of all the first trenches 31 and the combined capacitance component of all the second trenches 32 and the gate resistance component Rg2 is expressed as the second integrated value. To do. The value of the gate resistance component Rg2 is set so that the second integrated value is equal to or less than the first integrated value.

  An operation of the semiconductor device 10 will be described. As an example, the operation of the conventional semiconductor device 100 (FIG. 3) and the operation of the semiconductor device 10 (FIG. 1) of the present application will be compared and described. The turn-off operation will be described with reference to FIG. FIG. 2 is a diagram illustrating an operation when the turn-off operation is started at time t1. 2A is a graph showing the time change of the gate voltage Vg, FIG. 2B is a graph showing the time change of the collector current Ic, FIG. 2C is a graph showing the time change of the collector voltage Vc, FIG. (D) is a graph which shows the time change of switching loss. In FIG. 2, the solid line is the characteristic in the case of the semiconductor device 10 of the present application, and the broken line is the characteristic in the case of the semiconductor device 100 having the conventional structure.

  The switching loss of the conventional semiconductor device 100 (FIG. 2, dotted line) will be described. The switching loss is determined by the collector current Ic and the collector voltage Vc, and is represented by the area of the hatched portion of the region R1 shown in FIG. In order to reduce the switching loss, it is necessary to shorten the rise time P1 (FIG. 2C) of the collector voltage Vc or reduce the maximum value of the collector voltage Vc.

  Here, when the gate resistance component is reduced, the rise time of the collector voltage Vc at the turn-off time is shortened. However, at the same time, the decreasing rate (di / dt) of the collector current Ic (FIG. 2B, region R3) increases. Further, a surge voltage (FIG. 2C, region R4) is generated at the time of turn-off, and the surge voltage is given by di / dt × Lp (Lp: parasitic component inductance). Therefore, there is a trade-off relationship that if the rise time of the collector voltage Vc is shortened, the surge voltage increases. Then, simply reducing the gate resistance component increases the maximum value of the collector voltage Vc due to the increase of the surge voltage, so that the switching loss cannot be reduced.

  The switching loss of the semiconductor device 10 (FIG. 2, solid line) of the present application will be described. As described above, when the gate resistance component is reduced, the rise time of the collector voltage Vc at the turn-off time is shortened. Further, when the input capacitance of the semiconductor device 10 (the total value of the capacitance components between the gate electrode 8 and the emitter region 20) is increased, only the decrease rate of the collector current Ic is maintained while maintaining the rise time of the collector voltage Vc at a constant value. As a result, the surge voltage can be reduced. Therefore, in the semiconductor device 10 of the present application, the gate resistance component is reduced from Rg1 to Rg2. Further, the second trench 32 is set such that the current decrease rate (region R3) when driven by the gate resistance component Rg1 is the same as the current decrease rate (region R5) when driven by the gate resistance component Rg2. Are set (the total value of the capacitance components of the plurality of second trenches 32). The input capacitance is increased by adding the capacitance component of the second trench 32 to the input capacitance. As a result, the rise time of the collector voltage Vc can be shortened from time P1 to P2, while the surge voltage (region R6) is the same as the surge voltage (region R4) of the gate resistance component Rg1. The switching loss in the semiconductor device 10 of the present application is represented by the area of the hatched portion of the region R2 shown in FIG. Since the area of the region R2 is smaller than that of the region R1, it can be seen that the turn-off loss is lower in the semiconductor device 10 of the present application than in the conventional semiconductor device 100. From the above, it is possible to achieve both a reduction in switching loss and suppression of surge voltage.

  A method for manufacturing the semiconductor device 10 will be described. The semiconductor device 10 (FIG. 1) of the present application is obtained by partially changing the structure of the conventional dummy trench type semiconductor device 100 (FIG. 3). First, a semiconductor substrate containing n-type impurities is prepared. A body region 12 is formed by ion implantation of p-type impurities into the surface of the semiconductor substrate. A collector region 3 is formed by ion-implanting p-type impurities into the back surface of the semiconductor substrate. Next, after forming a mask layer on a predetermined portion of the surface of the body region 12, the emitter region 20 shown in FIG. 1 is formed.

  A mask layer having an opening on the surface is formed, and the emitter region 20 and the body region 12 are etched from the surface to form a first trench 31 and a second trench 32 that reach the drift region 4. For etching, dry etching such as RIE (Reactive Ion Etching) can be used. Next, the gate insulating film 18 is formed on the inner wall of the first trench 31, and the trench insulating film 33 is formed on the inner wall of the second trench 32. The gate insulating film 18 and the trench insulating film 33 can be formed simultaneously by thermal oxidation. Then, an insulating layer 34 (n-polySi) is selectively embedded only in the bottom of the second trench 32. Thereafter, the first trench 31 and the second trench 32 are simultaneously filled with a conductive layer such as polysilicon. Thereby, the gate electrode 8 and the conductive layer 35 can be formed simultaneously. Next, after forming the insulating film 16, the gate electrode 8 and the conductive layer 35 are electrically connected to the gate wiring, and the emitter electrode 14 is formed on the surface of the body region 12, the emitter region 20, and the insulating film 16. . The step of connecting the conductive layer 35 to the gate wiring can be performed simultaneously with the step of connecting the gate electrode 8 to the gate wiring. Next, the collector electrode 2 is formed on the back surface of the collector region 3. Through the above steps, the semiconductor device 10 shown in FIG. 1 can be obtained.

  In the manufacturing flow of the semiconductor device 10 of the present application described above, it is only necessary to add a step of embedding the insulating layer 34 to the manufacturing flow of the conventional semiconductor device 100. Therefore, since the manufacturing flow of the conventional semiconductor device 100 can be used, the semiconductor device 10 can be easily manufactured.

  The effect of the semiconductor device 10 will be described. In order to increase the input capacitance of the semiconductor device 10, it is not necessary to change the structure of the first trench 31 by using the second trench 32. Therefore, the input capacitance adjustment function can be sufficiently obtained without affecting the main characteristics (switch characteristics, conduction performance, etc.) of the semiconductor device 10.

  In addition, when the input capacitance is increased, if a capacitor element is separately connected to the first trench 31, the wiring length becomes long. Then, since the parasitic inductance of the wiring increases, LC resonance due to the capacitor element and the parasitic inductance may not be ignored. On the other hand, in the semiconductor device 10 of the present application, since the second trench 32 functioning as a capacitor is positioned in the immediate vicinity of the first trench 31, the wiring length when connecting the capacitor to the first trench 31 can be shortened. it can. Accordingly, since the parasitic inductance of the wiring can be reduced, the influence of resonance can be reduced.

  In addition, since the semiconductor device may become high temperature, when a capacitor element is connected to the first trench 31 separately from the outside, it is necessary to consider the high temperature reliability of the capacitor element. In the semiconductor device 10 of the present application, the second trench 32 formed inside the semiconductor device 10 functions as a capacitor. Therefore, the high temperature reliability of the capacitor can be made equivalent to that of the semiconductor device 10, and the high temperature reliability of the capacitor can be ensured.

(Example 2)
FIG. 6 shows an equivalent circuit of the semiconductor device 210 according to the second embodiment. The semiconductor device 210 includes an output capacitance component C0, capacitance components C1 to C3, pads 251 to 253, and an emitter electrode 14. One end of the output capacitance component C0 and one end of the capacitance components C1 to C3 are commonly connected to the collector. The other end of the output capacitance component C0 is connected to the emitter. The other ends of the capacitive components C1 to C3 are connected to the pads 251 to 253, respectively. An emitter electrode 14 is connected to the emitter. The emitter electrode 14 and the pads 251 to 253 can be connected to each other by using a wire 290 or the like.

An application mode of the semiconductor device 210 will be described. As an example, a case where the semiconductor device 210 of the present application is used in the full bridge circuit 300 shown in FIG. 7 will be described. Further, the case where the resonance unit 301 assumes a resonance loop between parallel arms will be described. In this case, when none of the pads 251 to 253 of the semiconductor device 210 (FIG. 6) is connected to the emitter electrode 14, the equivalent circuit of the resonance unit 301 is an equivalent circuit 310 shown in FIG. 8. The resonance frequency f1 (Hz) of the equivalent circuit 310 is determined by the output capacity and wiring inductance of the semiconductor device 210, and is expressed by the following equation.
f1 = 1 / 2π × (C0 × L1) ^1/2 ... Formula (1)
Here, L1 is a wiring inductance. C0 is an output capacitance component of the semiconductor device 210.

  When the resonance frequency f1 is inappropriate for the full bridge circuit 300, the resonance unit 301 may oscillate when the full bridge circuit 300 is actually driven. An example of oscillation of the resonating unit 301 is shown in FIG. FIG. 10 is an image diagram of the oscillation operation when the turn-on operation is started at time t11. FIG. 10A is a graph showing the time change of the gate voltage Vg in the switching arm, and FIG. 10B is a graph showing the time change of the collector voltage Vc in the switching arm. FIG. 10C is a graph showing the time change of the diode voltage Vd in the return arm, and FIG. 10D is a graph showing the time change of the diode current Id in the return arm. As shown in FIG. 10, when oscillation occurs, the time change of the gate voltage Vg and the collector voltage Vc increases, which causes problems such as failure of the semiconductor device 210 and shortening of the element life.

  Therefore, in order to prevent oscillation, it may be necessary to shift the resonance frequency of the equivalent circuit 310 from the frequency at which oscillation occurs when the full bridge circuit 300 is actually driven. In this case, in FIG. 6, at least one of the pads 251 to 253 may be connected to the emitter electrode 14 with a wire or the like. As an example, a case where the pad 251 is connected to the emitter electrode 14 using a wire 290 as shown in FIGS. 4 and 6 will be described.

An equivalent circuit of the resonance unit 301 in this case is an equivalent circuit 320 shown in FIG. Since the capacitance component C1 is connected in parallel to the output capacitance component C0, the value of the output capacitance component can be increased. The resonance frequency f2 (Hz) of the equivalent circuit 320 is expressed by the following equation.
f2 = 1 / 2π × ((C0 + C1) × L1) ^1/2 (2)
From the equations (1) and (2), it can be seen that the resonance frequency can be increased by adding the capacitance component C1.

  The capacity output capacity can be increased as the number of pads connected to the emitter electrode 14 among the pads 251 to 253 is increased. Therefore, it can be seen that the resonance frequency can be shifted to a larger side. The number of pads connected to the emitter electrode 14 may be determined by tuning the full bridge circuit 300 while actually operating.

  Next, a specific configuration for realizing the equivalent circuit of the semiconductor device 210 described in FIG. 6 will be described. FIG. 4 schematically shows a plan view of the semiconductor device 210. FIG. 5 schematically shows a cross-sectional view taken along line VV in FIG. As shown in FIG. 4, the semiconductor device 210 is manufactured using a semiconductor substrate 202 having an outer periphery 204. The semiconductor substrate 202 is divided into cell areas 271 to 273 in which a semiconductor structure that operates as a transistor is formed, and a terminal area 207 that surrounds the cell areas 271 to 273. A large number of first trenches 231 and second trenches 232 are formed in the cell areas 271 to 273 so as to extend in the left-right direction in FIG. An aluminum metal layer (not shown) that functions as the emitter electrode 14 is formed on the entire surface in the cell areas 271 to 273. The number of cell areas is not limited to three and can be set to an arbitrary number.

  The semiconductor device 210 is provided with pads 250 to 253. The gate wiring 280 drawn out from the pad 250 is disposed on the right side surface of the cell areas 271 to 273. The gate wiring 280 is connected to each of the first trenches 231. The pad 250 is connected to a drive circuit (not shown) that supplies a gate voltage.

  The wiring 281 drawn out from the pad 251 is arranged on the left side surface of the cell area 271. The wiring 281 is connected to the conductive layer 235 of the second trench 232 located in the cell area 271. The structure of the wirings 282 and 283 is similar to that of the wiring 281, and thus description thereof is omitted here. The gate wiring 280 and the wirings 281 to 283 are routed separately from each other.

  In the termination area 207, four termination trenches 261 and 262 extending along the outer periphery 204 are formed inside the outer periphery 204. The termination trenches 261 and 262 have a closed loop shape that goes around the cell area 205 along the outer periphery 204.

  The internal structure of the semiconductor device 210 will be described with reference to FIG. The second trench 232 in FIG. 5 extends from the surface of the body region 12 through the body region 12, and its bottom surface projects into the drift region 4. Further, the conductive layer 235 is accommodated in the entire region inside the second trench 232. In the insulating film 16 formed above the second trench 232, a contact hole (not shown) for connecting to the wiring 281 is formed in any cross section in the depth direction of FIG. In addition, a contact hole (not shown) for connecting to the gate wiring 280 is formed in the insulating film 16 formed above the first trench 231 in any cross section in the front direction of FIG. . Since other structures are the same as those of the semiconductor device 10 of FIG. 1, detailed description thereof is omitted here.

  The second trench 232 does not have the emitter region 20 as compared to the first trench 231. Therefore, in the second trench 232, the channel is not conducted when the semiconductor device 210 is turned on. That is, since no electrical operation is performed in the second trench 232, the second trench 32 can function suitably as a capacitor. 6 corresponds to the combined capacitance of the plurality of second trenches 232 included in the cell area 271. The capacitance component C1 illustrated in FIG. 6 corresponds to the combined capacitance of the plurality of second trenches 232 included in the cell area 272. The capacitance component C2 in FIG. The capacitance component C3 in FIG. 6 corresponds to the combined capacitance of the plurality of second trenches 232 included in the cell area 273. 6 corresponds to a composite value of the output capacitance components (capacitance components between the emitter region 20 and the collector region 3) of all the first trenches 231 included in the cell areas 271 to 273. . Thus, it can be seen that the equivalent circuit shown in FIG. 6 can be realized by the specific structure of the semiconductor device 210 shown in FIGS.

  The effect of the semiconductor device 210 will be described. In the semiconductor device 210, it is possible to intentionally shift the resonance frequency of the actual circuit in which the semiconductor device 210 is incorporated. Therefore, it is possible to set the resonance frequency while avoiding the frequency at which oscillation occurs in the actual circuit, thereby preventing the occurrence of resonance. Thereby, the situation where the life of the semiconductor device 210 is shortened can be prevented.

  In the semiconductor device 210, since the second trench 232 that functions as a capacitor is positioned in the immediate vicinity of the first trench 231 that is a trench gate, the wiring length when the capacitor is connected to the first trench 231 is shortened. be able to. Accordingly, since the parasitic inductance of the wiring can be reduced, the influence of resonance can be reduced. In the semiconductor device 210, since the second trench 232 formed inside the semiconductor device 210 functions as a capacitor, the high temperature reliability of the capacitor can be ensured.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  The insulating material disposed at the bottom of the second trench may be a silicon oxide film. A manufacturing method in this case will be described. A thick oxide film is deposited on the bottoms of both the first trench 31 and the second trench 32 by a CVD method. Next, a mask layer having an opening only in the first trench is formed, and the oxide film in the first trench 31 is removed by etching the oxide film. Thereafter, the gate insulating film 18 and the trench insulating film 33 are formed in each of the first trench 31 and the second trench 32. As a result, a structure in which only the first trench 31 can form a channel can be formed.

  The form in which the second trench 32 is formed between the adjacent first trenches 31 may be various. In the first embodiment, an example in which one second trench 32 is formed between adjacent first trenches 31 is shown, but a plurality of second trenches 32 may be formed. Further, a region where the second trench 32 is formed between the adjacent first trenches 31 and a region where the second trench 32 is not formed between the adjacent first trenches 31 are mixed. It may be.

  In Example 1, although the case where the insulating layer 34 was arrange | positioned at the bottom part in the 2nd trench 32 was demonstrated, it is not restricted to this form. The form in which the insulating layer 34 is disposed at any position in the depth direction of the second trench 32 may be employed.

  In the second embodiment, there are various methods for connecting at least one of the pads 251 to 253 and the emitter electrode 14. For example, in FIG. 4, the mask pattern for forming the metal layer on the entire surface in the cell areas 271 to 273 may be a pattern having a connection portion to the pads 250 to 253. Good. As a result, the step of connecting the wires can be omitted.

  Further, the technique disclosed in the first embodiment and the technique disclosed in the second embodiment can be performed simultaneously. Specifically, the structure of the second trench 32 shown in FIG. 1 and the structure of the second trench 232 shown in FIG. 5 may be formed in one semiconductor device. Thereby, it becomes possible to adjust the input capacitance and the output capacitance of the semiconductor device at the same time.

  Further, the semiconductor used is not limited to Si. Other types of semiconductors such as SiC, GaN, and GaAs may be used. Moreover, although this embodiment demonstrated IGBT structure, it is not restricted to this form. Even if the technique of the present application is applied to the power MOS structure, the same effect can be obtained.

The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

3: collector region, 4: drift region, 8: gate electrode, 10 and 100 and 210: semiconductor device, 12: body region, 14: emitter electrode, 16: insulating film, 18: gate insulating layer, 20: emitter region, 31: first trench, 32 and 232: second trench, 33: trench insulating film, 35 and 235: conductive layer, 251 to 253: pad

Claims (5)

A plurality of first semiconductor regions of a first conductivity type formed facing part of the surface of the semiconductor layer;
A second conductivity type body region surrounding the first semiconductor region and formed in a region from the surface of the semiconductor layer to a predetermined depth;
A drift region of a first conductivity type formed under the body region and separated from the first semiconductor region by the body region;
A second semiconductor region formed below the drift region;
A plurality of first trenches extending from the surface of each first semiconductor region through the body region, the bottom surface of which protrudes into the drift region;
A gate insulating layer covering the inner surface of each first trench;
A first trench gate electrode housed in each first trench in a state surrounded by a gate insulating layer;
A plurality of second trenches formed between adjacent first trenches and extending through the body region, the bottom surface of which protrudes into the drift region;
A trench insulating layer covering the inner surface of each second trench;
A plurality of conductive layers housed in each second trench in a state surrounded by a trench insulating layer;
With
At least one of the plurality of conductive layers can be electrically connected to the first trench gate electrode, or can be selectively electrically connected to the first semiconductor region. . A bottom insulating layer is formed at the bottom of the second trench in a state surrounded by the trench insulating layer,
The upper surface of the bottom insulating layer is located closer to the body region than the interface between the body region and the drift region,
A conductive layer is formed on the bottom insulating layer,
The semiconductor device according to claim 1, wherein the conductive layer is electrically connected to the first trench gate electrode. When the conductive layer is connected to the first trench gate electrode, the first gate resistance component that is the resistance component of the path from the gate voltage supply source to the first trench gate electrode is:
When the conductive layer is not connected to the first trench gate electrode, the conductive layer is made smaller than the second gate resistance component that is the resistance component of the path from the gate voltage supply source to the first trench gate electrode,
The integrated value of the sum of the capacitance component of the first trench and the capacitance component of the second trench and the first gate resistance component is less than or equal to the integrated value of the capacitance component of the first trench and the second gate resistance component. The semiconductor device according to claim 1, wherein a first gate resistance component is set. A plurality of second trenches are formed in a region where the body region is exposed on the surface of the semiconductor layer,
2. The semiconductor device according to claim 1, wherein at least one of the conductive layers accommodated in each of the plurality of second trenches is selectively electrically connected to the first semiconductor region. An upper insulating layer is formed above the first trench and the second trench,
An upper electrode is formed on the upper insulating layer and the first semiconductor region,
A pad portion connected to the conductive layer housed in each of the plurality of second trenches;
The semiconductor device according to claim 4, wherein the pad portion and the upper electrode are electrically connectable.

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