JP6916062B2 - Semiconductor light emitting device and manufacturing method of semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

The light emitting diode of Patent Document 1 has an ohmic contact layer, a second metal layer, a first metal layer, an insulating layer, a p-type contact layer, a p-type clad layer, and MQW (Multiple Quantum Well) on one surface of a support substrate. It has a semiconductor layer in which a light emitting layer, an n-type clad layer, and an n-type contact layer are laminated in this order, and has an ODR (Omni-Directional-Reflector) structure. That is, a contact portion is embedded in a part of the insulating layer between the p-type contact layer and the first metal layer, whereby the first metal layer and the p-type contact layer are electrically connected. There is. A p-side electrode is provided on the back surface of the support substrate, and a ring-shaped n-side electrode is provided on the n-type contact layer.

Japanese Unexamined Patent Publication No. 2007-2221029

An object of the present invention is a contact on the semiconductor layer side in a semiconductor light emitting device having an ODR structure including a semiconductor layer and a metal layer electrically connected to the semiconductor layer via a contact portion in a through hole of the insulating layer. It is an object of the present invention to provide a semiconductor light emitting device capable of improving the adhesion of an insulating layer to a semiconductor layer while reducing the resistance of the region, and a method for manufacturing the same.

_{The semiconductor light emitting device according to the embodiment of the present invention has an Al x} Ga _1-x As (0 ≦ x) that includes a light emitting region and has a front surface as a light extraction surface and a back surface on the opposite side thereof, and forms the back surface. <1) A semiconductor layer including a contact region made of a system semiconductor, an insulating layer arranged on the back surface side of the semiconductor layer and having a through hole, and arranged between the semiconductor layer and the insulating layer (Al). _y Ga _1-y ) _z In _1-z P (0 ≦ y ≦ 1, 0 ≦ z ≦ 1) system The intermediate adhesive layer made of semiconductor and the insulating layer are arranged on the opposite side of the semiconductor layer and penetrate. It includes a metal layer electrically connected to the contact area via a contact portion in the hole.

According to this configuration, the contact region forming the back surface of the semiconductor layer is composed of an Al _x Ga _1-x As (0 ≦ x <1) -based semiconductor. The _{carrier concentration of the Al x} Ga _1-x As (0 ≦ x <1) -based semiconductor can be increased relatively easily. Therefore, impurities can be doped at a sufficiently high carrier concentration without forming a thick contact region. That is, since impurities are contained in a relatively thin contact region at a high concentration, the resistance of the contact region can be reduced.

On the other hand, since _{the adhesion between the Al x} Ga _1-x As (0 ≦ x <1) -based semiconductor and the insulating layer is not high, it is said that the insulating layer is easily peeled off from the semiconductor layer in order to achieve the above-mentioned low resistance. A contradictory event occurs. However, in this configuration, between the semiconductor layer and the insulating _layer, the intermediate bonding layer consisting of _{(Al y Ga 1-y)} z In 1-z P (0 ≦ y ≦ 1,0 ≦ z ≦ 1) based semiconductor Therefore, high adhesion can be ensured between the semiconductor layer and the insulating layer.

The semiconductor light emitting device according to an embodiment of the present invention may be arranged between the insulating layer and the metal layer, and may further include a translucent conductive layer including the contact portion.
In the semiconductor light emitting device according to the embodiment of the present invention, the through hole is formed in the intermediate adhesive layer in addition to the insulating layer, and the translucent conductive layer makes the contact through the through hole. It may be directly connected to the area.

According to this configuration, ohmic contact can be formed between the contact region and the translucent conductive layer, so that the forward voltage (VF) of the semiconductor light emitting device can be reduced.
In the semiconductor light emitting device according to the embodiment of the present invention, the contact region may contain carbon (C) as an impurity at a concentration of ^{1.0 × 10 19} cm ^{-3 or more.}
When the contact region ^{contains carbon (C) at a concentration of 1.0 × 10 19} cm ^-3 or more, low resistance of the contact region can be satisfactorily achieved.

In the semiconductor light emitting device according to the embodiment of the present invention, the contact region may be composed of a layer having a thickness of 500 Å to 5000 Å.
In the semiconductor light emitting device according to the embodiment of the present invention, the through hole has a side etching portion in the portion of the intermediate adhesive layer covered with the edge portion of the through hole in the portion of the insulating layer. The translucent conductive layer may include a convex portion formed by spreading laterally so as to enter the side etching portion.

According to this configuration, the convex portion of the translucent conductive layer is caught by the edge of the through hole in the portion of the insulating layer, so that the translucent conductive layer can be prevented from peeling off.
In the semiconductor light emitting device according to the embodiment of the present invention, a gap may be formed between the side portion of the side etching portion and the convex portion.
According to this configuration, voids (air) having a refractive index (n2 = 1) smaller than the refractive index (n1> 1) of the intermediate adhesive layer are formed in a part of the intermediate adhesive layer, and thus are intermediate with the insulating layer. The refractive index of light at the interface with the adhesive layer can be improved. Therefore, it is possible to reduce the loss of light generated in the path from the interface through the intermediate adhesive layer and the translucent conductive layer to the metal layer.

In the semiconductor light emitting device according to the embodiment of the present invention, the intermediate adhesive layer may be composed of an InGaP layer.
In the semiconductor light emitting device according to the embodiment of the present invention, the insulating layer may be made of SiO ₂ , SiN or SiON.
In the semiconductor light emitting device according to the embodiment of the present invention, the light emitting wavelength in the light emitting region may be 800 nm or more.

With this configuration, it is possible to provide an infrared light emitting semiconductor light emitting device capable of improving the adhesion of the insulating layer to the semiconductor layer while reducing the resistance of the contact region on the semiconductor layer side.
The method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention includes a light emitting region on a first substrate and a contact made of an Al _x Ga _1-x As (0 ≦ x <1) -based semiconductor on the uppermost surface. forming a semiconductor layer including a region on the semiconductor _layer, the intermediate bonding consisting of _{(Al y Ga 1-y)} z in 1-z P (0 ≦ y ≦ 1,0 ≦ z ≦ 1) based semiconductor A step of forming a layer, a step of forming an insulating layer on the intermediate adhesive layer, a step of forming a through hole in the insulating layer, and a step of forming a through hole on the insulating layer via a contact portion in the through hole. A step of forming a first metal layer electrically connected to the contact region, a step of forming a second metal layer on a second substrate, and joining the first metal layer and the second metal layer to each other. This includes a step of bonding the first substrate and the second substrate, and a step of removing the first substrate after the bonding.

By this method, the semiconductor light emitting device according to the embodiment of the present invention can be manufactured.
The method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention includes a step of ashing the intermediate adhesive layer before forming the insulating layer, and the insulating layer is an ashed intermediate adhesive layer. It may be formed on the surface.

By ashing the surface of the intermediate adhesive layer, the frictional force of the insulating layer with respect to the intermediate adhesive layer can be increased, so that the adhesion of the insulating layer can be improved.
In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, the ashing treatment may include a step of treating the surface of the intermediate adhesive layer using oxygen plasma.
In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, before forming the first metal layer, light is transmitted onto the insulating layer so that a part of the contact portion is embedded in the through hole. It may further include a step of forming a conductive layer.

In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, the step of forming the through hole includes the step of forming the through hole in the intermediate adhesive layer in addition to the insulating layer, and the light transmissive. The conductive layer may be formed so as to be directly connected to the contact region through the through hole.
In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, the intermediate adhesive layer is formed so that the step of forming the through hole extends laterally from the edge of the through hole in the portion of the insulating layer. A step of forming a side etching portion may be included in the portion of the above, and the translucent conductive layer may be formed so as to include a convex portion formed so as to enter the side etching portion.

FIG. 1 is a schematic plan view of a semiconductor light emitting device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment of the present invention. FIG. 3 is a diagram showing an example of the layer structure of the group III-V semiconductor structure of FIG. FIG. 4 is a diagram showing an example of the layer structure of the light emitting layer of FIG. FIG. 5 is a diagram showing the relationship between the Al composition of the AlGaAs layer and the absorption edge wavelength of the AlGaAs layer. FIG. 6A is an enlarged view specifically showing the structure in the vicinity of the interface between the insulating layer and the intermediate adhesive layer of FIG. FIG. 6B is an enlarged plan view of the through hole of FIG. 6A. FIG. 7A is a diagram showing a part of the manufacturing process of the semiconductor light emitting device of FIG. FIG. 7B is a diagram showing the next step of FIG. 7A. FIG. 7C is a diagram showing the next step of FIG. 7B. FIG. 7D is a diagram showing the next step of FIG. 7C. FIG. 7E is a diagram showing the next step of FIG. 7D. FIG. 7F is a diagram showing the next step of FIG. 7E. FIG. 7G is a diagram showing the next step of FIG. 7F. FIG. 7H is a diagram showing the next step of FIG. 7G. FIG. 7I is a diagram showing the next step of FIG. 7H. FIG. 7J is a diagram showing the next step of FIG. 7I. FIG. 8A is a diagram showing steps related to the formation of the intermediate adhesive layer, the insulating layer and the translucent conductive layer. FIG. 8B is a diagram showing the next step of FIG. 8A. FIG. 8C is a diagram showing the next step of FIG. 8B. FIG. 8D is a diagram showing the next step of FIG. 8C. FIG. 8E is a diagram showing the next step of FIG. 8D. FIG. 9 is a diagram showing a first modification of the semiconductor light emitting device. FIG. 10 is a diagram showing a second modification of the semiconductor light emitting device. FIG. 11 is a diagram showing a TLM pattern. FIG. 12 is a diagram showing the IV characteristics of the AlGaAs layer and the GaP layer. FIG. 13 is a diagram showing the contact resistance of ITO to the AlGaAs layer and the GaP layer. FIG. 14 is a diagram showing the IV characteristics of the semiconductor light emitting devices of Examples and Reference Examples.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a semiconductor light emitting device 1 according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the semiconductor light emitting device 1 according to the embodiment of the present invention. Note that FIG. 2 does not show the cross section of the semiconductor light emitting device 1 of FIG. 1 at a specific position, but shows the cross-sectional structure of the semiconductor light emitting device 1 for convenience. Therefore, in FIG. 2, even if the components are the same as those shown in FIG. 1, the size ratio may be different.

The semiconductor light emitting device 1 includes the substrate 2, the metal layer 3 on the substrate 2, the translucent conductive layer 4 on the metal layer 3, the insulating layer 5 on the translucent conductive layer 4, and the present invention on the insulating layer 5. III-V semiconductor structure 6 as an example of the semiconductor layer, the intermediate adhesive layer 7 between the insulating layer 5 and the III-V semiconductor structure 6, and the back surface of the substrate 2 (III-V semiconductor structure 6). The p-side electrode 8 as an example of the back surface electrode formed so as to be in contact with the surface on the opposite side) and the n-side as an example of the front surface electrode formed so as to be in contact with the surface of the group III-V semiconductor structure 6. Includes electrode 9.

The substrate 2 is made of a silicon substrate in this embodiment. Of course, the substrate 2 may be composed of a semiconductor substrate such as GaAs (gallium arsenide) or GaP (gallium phosphide). In this embodiment, the substrate 2 is formed in a substantially square shape in a plan view as shown in FIG. 1, but the plan shape of the substrate 2 is not particularly limited, and may be, for example, a rectangular shape in a plan view. Further, the thickness of the substrate 2 may be, for example, 50 μm to 250 μm. Further, the refractive index of the substrate 2 (silicon substrate) may be about 3.705.

In this embodiment, the metal layer 3 is composed of Au or an alloy containing Au. The metal layer 3 may be a single layer of each of the Au layer and the Au alloy layer, or may be a layer in which a plurality of these layers and other metal layers are laminated. When the metal layer 3 has a plurality of laminated structures, at least the contact surface of the first metal layer 31 in contact with the translucent conductive layer 4 is an Au layer or an Au alloy layer (for example, AuBeNi). It is preferably composed of. On the other hand, it is preferable that at least the contact surface of the second metal layer 32 in contact with the substrate 2 with the substrate 2 is made of a Ti layer. In this embodiment, for example, the metal layer 3 has a laminated structure shown by (translucent conductive layer 4 side) Au layer 33 / Au layer 34 / Ti layer 35 (board 2 side). Further, in the metal layer 3, a clear boundary is not formed between the plurality of metal materials constituting the metal layer 3, and even if the plurality of metal materials are sequentially distributed from the substrate 2 side, for example. good. On the other hand, in this embodiment, as will be described later, the metal layer 3 is formed by joining the first metal layer 31 and the second metal layer 32 by bonding the growth substrate 44 (described later) and the substrate 2. It is a thing. Therefore, in FIG. 2, the boundary (bonded surface) between the first metal layer 31 and the second metal layer 32 is shown for convenience, but this boundary may not be clearly visible.

The metal layer 3 is formed so as to cover the entire surface of the substrate 2. The total thickness of the metal layer 3 is, for example, 4000 Å to 10000 Å, preferably 5000 Å to 7000 Å. The thickness of the individual layers 33 to 35 constituting the metal layer 3 is, for example, Au layer 33 = 5000 Å ± 500 Å, Au layer 34 = 1000 Å ± 100 Å, and Ti layer 35 = 500 Å ± 50 Å. May be good.

In this embodiment, the translucent conductive layer 4 is made of ITO (indium tin oxide). Of course, the translucent conductive layer 4 may be made of a transparent electrode material such as ZnO (zinc oxide) or IZO (indium oxide-zinc oxide). The optical film thickness of the translucent conductive layer 4 is preferably 0.5λ and 1λ (however, the emission wavelength λ = 800 nm or more), and the physical film thickness is 500 Å to 6000 Å (for example, about 2700 Å). May be good. Further, the refractive index of the translucent conductive layer 4 (ITO) may be about 1.60 (emission wavelength λ = 870 nm).

The insulating layer 5 is made of an insulating material that has translucency and does not have conductivity, and in this embodiment, it is made of SiO ₂ (silicon oxide). Of course, the insulating layer 5 may be made of an insulating material such as SiN (silicon nitride) or SiON (silicon oxynitride). The optical film thickness of the insulating layer 5 is preferably 0.25λ and 0.75λ (however, the emission wavelength λ = 800 nm or more), and the physical film thickness is 1000 Å to 2000 Å (for example, about 1500 Å). May be good.

The intermediate adhesive layer 7 is composed of a (Al _y Ga _1-y ) _z In _1-z P (0 ≦ y ≦ 1, 0 ≦ z ≦ 1) -based semiconductor. Examples of the semiconductor represented by the formula include InGaP, AlInGaP, GaP and the like. These are appropriately selected depending on the type of the insulating layer 5. For example, when the insulating layer 5 is made of _{an oxygen-containing insulating material such as SiO 2} or SiON, InGaP is preferable, and the insulating layer 5 is SiN or the like. GaP is preferred when it is composed of a nitrogen-containing insulating material. The thickness of the intermediate adhesive layer 7 is, for example, 50 Å to 700 Å, and may be, for example, about 500 Å.

Then, in this embodiment, a through hole 10 is formed which continuously penetrates the insulating layer 5 and the intermediate adhesive layer 7. As shown in FIG. 1, the through holes 10 are discretely arranged in the plane of the substrate 2. For example, they may be arranged in a matrix in the mesa portion 26 (described later) having a rectangular shape in a plan view. A part of the translucent conductive layer 4 is embedded in the through hole 10 as a contact portion 11 and is connected to the III-V group semiconductor structure 6. As a result, the semiconductor light emitting device 1 is formed with an ODR (Omni-Directional-Reflector) structure.

The group III-V semiconductor structure 6 includes a light emitting layer 12 as an example of a light emitting region, a p-type semiconductor layer 13 as an example of a first conductive type layer, and an n-type semiconductor layer 14 as an example of a second conductive type layer. And include. The p-type semiconductor layer 13 is arranged on the substrate 2 side with respect to the light emitting layer 12, and the n-type semiconductor layer 14 is arranged on the n-side electrode 9 side with respect to the light emitting layer 12. In this way, the light emitting layer 12 is sandwiched between the p-type semiconductor layer 13 and the n-type semiconductor layer 14, and a double heterojunction is formed. Electrons are injected into the light emitting layer 12 from the n-type semiconductor layer 14, and holes are injected from the p-type semiconductor layer 13. Light is generated by recombination of these in the light emitting layer 12. The total thickness of the substrate 2 and the III-V semiconductor structure 6 may be, for example, 60 μm to 260 μm.

The composition of each layer constituting the light emitting layer 12, the p-type semiconductor layer 13 and the n-type semiconductor layer 14 is appropriately selected according to the emission wavelength range of the light emitting layer 12, and for example, when the emission wavelength is in the infrared wavelength region of 800 nm or more. AlGaAs-based semiconductors are mainly selected, and when the emission wavelength is in the visible light wavelength range of about 380 nm to 780 nm, AlInGaP-based semiconductors are mainly selected. Of these, as an example, the layer configurations of the light emitting layer 12, the p-type semiconductor layer 13 and the n-type semiconductor layer 14 when the emission wavelength is in the infrared wavelength region of 800 nm or more will be described with reference to FIGS. 3 and 4. do. FIG. 3 is a diagram showing an example of the layer structure of the III-V semiconductor structure 6 of FIG. FIG. 4 is a diagram showing an example of the layer structure of the light emitting layer 12 of FIG. FIG. 5 is a diagram showing the relationship between the Al composition of the AlGaAs layer and the absorption edge wavelength of the AlGaAs layer.

As shown in FIG. 3, the p-type semiconductor layer 13 is configured by laminating a p-type contact layer 15, a p-type window layer 16 and a p-type clad layer 17 in this order from the substrate 2 side. On the other hand, the n-type semiconductor layer 14 is configured by laminating an n-type clad layer 18, an n-type window layer 19 and an n-type contact layer 20 in this order on the light emitting layer 12.
The p-type contact layer 15, the p-type window layer 16, and the p-type clad layer 17 are composed of an Al _x Ga _1-x As (0 ≦ x <1) -based semiconductor. The Al composition in the formula is appropriately set according to the range of the emission wavelength of the light emitting layer 12. For example, in the case of an infrared wavelength region of 800 nm or more, as shown in FIG. 5, _{the Al composition of the Al x} Ga _1-x As (0 ≦ x <1) -based semiconductor is less than 0.1 (less than 10%). In this case, since the absorption edge wavelength is 800 nm or more, the infrared light from the light emitting layer 12 is easily absorbed by each layer. Therefore, _{the Al composition of the Al x} Ga _1-x As (0 ≦ x <1) -based semiconductor is set to, for example, 10% to 70% (x = 0.1 to 0.7), preferably 15%. It is set to ~ 60% (x = 0.15-0.6). The larger the Al composition, the lower the absorption edge wavelength. Therefore, if only the absorption edge wavelength is considered, the Al composition may exceed 60%. However, when the Al composition is high, the surface of the AlGaAs layer is easily oxidized, and it becomes difficult to make ohmic contact with the AlGaAs layer due _{to the Al 2} O _{3 (aluminum oxide) film formed on the surface by the oxidation of Al.} .. Therefore, with respect to the p-type contact layer 15 in which the contact with the electrode is formed, the absorption edge wavelength is slightly higher, but Al _x Ga having an Al composition of 15% to 30% (x = 0.15 to 0.3). _{It is preferably composed of a 1-x} As (0 ≦ x <1) -based semiconductor. On the other hand, the Al composition of the p-type window layer 16 and the p-type clad layer 17 may be about 30% to 60% (x = 0.3 to 0.6). By setting the Al composition of the p-type window layer 16 and the p-type clad layer 17 to this range, it is possible to reliably prevent infrared light from being absorbed by these layers 16 and 17.

Further, the p-type contact layer 15 is preferably a low resistance layer in order to make ohmic contact with the translucent conductive layer 4, and has a high concentration of carbon (C) and zinc (Zn) as the p-type dopant. It is contained in. In this embodiment, the p-type contact layer 15 contains carbon (C) at a concentration of ^{1.0 × 10 19} cm ^{-3 or more.} The p-type window layer 16 and the p-type clad layer 17 also contain the p-type dopant at an appropriate concentration.

Further, the thickness of each of the p-type contact layer 15, the p-type window layer 16 and the p-type clad layer 17 is as follows, for example, the p-type contact layer 15 has a thickness of 500 Å to 5000 Å, and the p-type window layer 16 has a thickness of 500 Å to 5000 Å. It may have a thickness of 25,000 Å to 40,000 Å, and the p-type clad layer 17 may have a thickness of 7,000 Å to 15,000 Å.
The p-type contact layer 15, the p-type window layer 16, and the p-type clad layer 17 may each be formed of a single layer, or may be formed of a plurality of layers having different Al compositions. good.

The n-type contact layer 20, the n-type window layer 19, and the n-type clad layer 18 are composed of an Al _x Ga _1-x As (0 ≦ x <1) -based semiconductor. The Al composition in the formula is appropriately set according to the range of the emission wavelength of the light emitting layer 12. For example, in the case of an infrared wavelength region of 800 nm or more, _{the Al composition of the Al x} Ga _1-x As (0 ≦ x <1) -based semiconductor is, for example, according to FIG. 5 as in the p-type semiconductor layer 13. It is set to 10% to 70% (x = 0.1 to 0.7), preferably 15% to 60% (x = 0.15 to 0.6).

Regarding the n-type contact layer 20, similarly to the p-type contact layer 15, even if the Al composition is 15% to 30% (x = 0.15 to 0.3) in consideration of ohmic contact with the n-side electrode 9. However, in this embodiment, it is composed of GaAs having an Al composition of 0% (x = 0). When the Al composition is 0%, based on FIG. 5, there is a concern that the absorption edge wavelength becomes high and the infrared light from the light emitting layer 12 is easily absorbed by the n-type contact layer 20. However, as will be described later, the n-type contact layer 20 is formed in the same pattern as the n-side electrode 9 made of metal, and in the region covered by the n-side electrode 9, light is shielded by the n-side electrode 9. Since it is not emitted, there is no problem even if infrared light is absorbed in the region (that is, the n-type contact layer 20).

On the other hand, the Al composition of the n-type window layer 19 and the n-type clad layer 18 may be about 30% to 60% (x = 0.3 to 0.6). By setting the Al composition of the n-type window layer 19 and the n-type clad layer 18 in this range, it is possible to reliably prevent the infrared light from being absorbed in these layers 18 and 19.
Further, the n-type contact layer 20 preferably has a low resistance layer in order to make ohmic contact with the translucent conductive layer 4, and contains silicon (Si) as an n-type dopant at a high concentration. .. In this embodiment, the n-type contact layer 20 contains silicon (Si) at a concentration of ^{1.0 × 10 18} cm ^{-3 or more.} The n-type window layer 19 and the n-type clad layer 18 also contain the n-type dopant at an appropriate concentration.

Further, the thickness of each of the n-type contact layer 20, the n-type window layer 19 and the n-type clad layer 18 is as follows, for example, the n-type contact layer 20 has a thickness of 500 Å to 9000 Å, and the n-type window layer 19 has a thickness of 500 Å to 9000 Å. The n-type clad layer 18 may have a thickness of 10000 Å to 100,000 Å and a thickness of 500 Å to 15000 Å.
The n-type contact layer 20, the n-type window layer 19, and the n-type clad layer 18 may each be formed of a single layer, or may be formed of, for example, a plurality of layers having different Al compositions. good.

The light emitting layer 12 has an MQW (multiple-quantum well) structure (multiple-quantum well structure), and light is generated by recombination of electrons and holes, and the generated light is amplified. It is a layer.
In this embodiment, as shown in FIG. 4, the light emitting layer 12 alternately has a plurality of quantum well layers 21 made of InGaAs layers (for example, about 90 Å thickness) and barrier layers 22 made of AlGaAs layers (for example, about 110 Å thickness). It has a multiple-quantum well (MQW: Multiple-Quantum Well) structure 23 formed by periodically and repeatedly stacking, and a p-type guide layer 24 and an n-type guide layer 25 sandwiching the multiple quantum well structure 23 from both upper and lower sides. ing. The p-type guide layer 24 and the n-type guide layer 25 have, for example, Al _x Ga _1-x As (0 <x <1) having an Al composition of about 15% to 60% (x = 0.15 to 0.6). It is composed of system semiconductors.

For example, the quantum well layer 21 (InGaAs) and the barrier layer 22 (AlGaAs) are alternately and repeatedly laminated for 2 to 50 cycles, thereby forming a light emitting layer 12 having a multiple quantum well structure. Note that FIG. 4 shows only the one-period structure of the quantum well layer 21 and the barrier layer 22. The emission wavelength corresponds to the band gap of the quantum well layer 21, and the band gap can be adjusted by adjusting the composition ratio of In or Ga and adjusting the film thickness of the quantum well layer 21. .. In this embodiment, the emission wavelength of the light emitting layer 12 is set to 800 nm or more (for example, 870 nm) by adjusting the composition of In and Ga in the quantum well layer 21 (InGaAs).

As shown in FIGS. 1 and 2, the semiconductor light emitting device 1 forms the mesa portion 26 by removing a part thereof. More specifically, from the surface of the group III-V semiconductor structure 6, the n-type semiconductor layer 14, the light emitting layer 12, the p-type semiconductor layer 13 and the intermediate adhesive layer 7 extend over the entire circumference of the group III-V semiconductor structure 6. Is removed by etching to form a mesa portion 26 having a substantially trapezoidal shape in cross section. More specifically, the mesa portion 26 has an outer peripheral surface 26B formed in a tapered shape whose diameter increases in the direction toward the substrate 2 side. The shape of the mesa portion 26 is not limited to a substantially trapezoidal shape in cross-sectional view, and may be, for example, a substantially square shape in cross-sectional view. As a result, the insulating layer 5 constitutes a drawer portion 27 that is pulled out from the mesa portion 26 in the lateral direction. As shown in FIG. 1, in a plan view, the mesa portion 26 is surrounded by the drawer portion 27.

The intermediate adhesive layer 7 may not be removed by etching, and the surface 27A of the drawer portion 27 may be formed by the intermediate adhesive layer 7. However, considering the yield at the time of manufacturing the semiconductor light emitting device 1, as shown in FIG. In addition, it is preferable that the insulating layer 5 is exposed as the surface 27A of the lead-out portion 27. After the mesa portion 26 is formed in FIG. 7I and then the fine concavo-convex structure 28 (described later) is formed as shown in FIG. 7J, the substrate 2 in the wafer state is diced to individual chip sizes. In addition, chipping is unlikely to occur. That is, if the contact surface with the dicing blade is an insulating material, the surface 27A of the lead-out portion 27 is less likely to be chipped and scattered due to cutting, as compared with the case where the contact surface is a III-V semiconductor, and the scattered small pieces are used. It is possible to prevent the mesa portion 26, which is a light emitting portion, from being damaged.

A fine uneven structure 28 is formed on the surface 26A of the mesa portion 26. The fine concavo-convex structure 28 can diffuse the light extracted from the III-V semiconductor structure 6. In this embodiment, as will be described later, the n-type window layer 19 is exposed by selectively removing the n-type contact layer 20 in the same pattern as the shape of the n-side electrode 9, and the exposed surface is fine. The uneven structure 28 is formed. In FIG. 1, the fine concavo-convex structure 28 is omitted for clarification.

In this embodiment, the p-side electrode 8 as the back surface electrode is composed of Au or an alloy containing Au. Specifically, the laminated structure shown by the Ti layer 81 / Au layer 82 (on the substrate 2 side) may be used. Further, the p-side electrode 8 is formed so as to cover the entire back surface of the substrate 2. The total thickness of the p-side electrode 8 is, for example, 1300 Å to 1700 Å. Further, the thickness of the individual layers 81 and 82 constituting the p-side electrode 8 may be, for example, about Ti layer 81 = 500 Å ± 50 Å and about Au layer 82 = 1000 Å ± 100 Å.

In this embodiment, the n-side electrode 9 as the surface electrode is composed of Au or an alloy containing Au. Specifically, the laminated structure shown by the AuGeNi layer 91 / Au layer 92 (III-V semiconductor structure 6 side) may be used. The total thickness of the n-side electrode 9 is, for example, 15,000 Å to 20,000 Å. The thickness of the individual layers 91 and 92 constituting the n-side electrode 9 may be, for example, AuGeNi layer 91 = 2000 Å ± 200 Å and Au layer 92 = 17000 Å ± 1700 Å.

Further, the n-side electrode 9 has a substantially circular pad electrode portion 93 and a branch-shaped electrode portion that selectively extends from the pad electrode portion 93 in a branch shape so as to partition a certain region around the pad electrode portion 93. Including 94 integrally.
In this embodiment, the pad electrode portion 93 is arranged substantially in the center of the mesa portion 26 in a plan view, and the surrounding areas 29A and 29B are located between the pad electrode portion 93 and each of the four corners of the mesa portion 26. , 29C, 29D are formed so as to partition the branch-shaped electrode portion 94. Each of the surrounding areas 29A to 29D intersects the intermediate portion 94A of the branch-shaped electrode portion 94 extending in a cross shape from the pad electrode portion 93 toward each peripheral edge (or end face) of the mesa portion 26 and the cross-shaped intermediate portion 94A. The outer peripheral portion 94B of the branch-shaped electrode portion extending along the pair of peripheral edges (or the outer peripheral surface 26B) of the mesa portion 26 facing each other is surrounded by the pad electrode portion 93.

In this embodiment, since the n-type contact layer 20 has the same shape as the n-side electrode 9, FIG. 6A shows FIG. 2A in which the n-type semiconductor layer 14 is exposed in the surrounding regions 29A to 29D. It is an enlarged view concretely showing the structure in the vicinity of the interface between the insulating layer 5 and the intermediate adhesive layer 7. FIG. 6B is an enlarged plan view of the through hole 10 of FIG. 6A.
As described above, in this embodiment, the translucent conductive layer 4, the insulating layer 5, the intermediate adhesive layer 7, and the III-V group semiconductor structure 6 are laminated in this order on the metal layer 3.

The insulating layer 5 and the intermediate adhesive layer 7 are formed with through holes 10 that continuously penetrate the insulating layer 5. The through hole 10 includes a first portion 36 of the portion of the insulating layer 5 and a second portion 37 of the portion of the intermediate adhesive layer 7.
Both the first portion 36 and the second portion 37 are formed in a tapered shape whose diameter decreases in the direction from the translucent conductive layer 4 toward the III-V semiconductor structure 6. In this embodiment, the tapered surface (side surface) of the first portion 36 and the tapered surface (side surface) of the second portion 37 are not formed as continuous surfaces, and as shown in FIG. 6B, the second portion. The start end 37A (end on the translucent conductive layer 4 side) of the tapered surface of 37 is radially outward at regular intervals with respect to the end 37B (end on the side of the group III-V semiconductor structure 6) of the tapered surface of the first portion 36. It is a stepped surface on which. Such a stepped surface is caused by the side etching of the intermediate adhesive layer 7 when forming the second portion 37 of the through hole 10, as will be described later.

As a result, the second portion 37 of the through hole 10 has a side etching portion 39 covered with the edge portion 38 of the through hole 10 in the first portion 36. As shown in FIG. 6B, the side etching portion 39 is formed in an annular shape over the entire circumference of the through hole 10 in the circumferential direction.
The translucent conductive layer 4 is embedded in the through hole 10 and is directly connected to the p-type contact layer 15 exposed in the through hole 10. Further, the translucent conductive layer 4 (contact portion 11) is formed in the second portion 37 of the through hole 10 so as to enter the side etching portion 39 so as to spread laterally to the convex portion 40 (hatched portion in FIG. 6B). )have. As shown in FIG. 6B, the convex portion 40 may be formed in an annular shape over the entire circumference of the through hole 10 in the circumferential direction, or may be formed in a curved shape only in a part in the circumferential direction. Further, in this embodiment, the convex portion 40 is not formed so as to completely fill the side etching portion 39, and a gap 41 is formed between the side portion of the side etching portion 39 and the convex portion 40. Has been done. In this embodiment, the void 41 is formed in an annular shape over the entire circumference of the through hole 10, as shown in FIG. 6B.

Further, in this embodiment, the translucent conductive layer 4 is formed to have a substantially uniform thickness along the surface of the insulating layer 5 and the inner surface of the through hole 10, and the recess 42 is formed in the portion on the through hole 10. Have. The metal layer 3 (first metal layer 31) is formed so as to cover the recess 42, and is composed of a recess 42 in a portion of the through hole 10 between the translucent conductive layer 4 and the metal layer 3. A second void 43 is formed. The second gap 43 is formed so as to be surrounded by the gap 41.

The interface 7A of the intermediate adhesive layer 7 with the insulating layer 5 is subjected to an ashing treatment (see FIG. 8A) described later, and has a fine uneven surface. Since the frictional force of the insulating layer 5 with respect to the intermediate adhesive layer 7 can be increased by this uneven surface, the adhesion of the insulating layer 5 can be improved.
Then, referring to FIG. 2, in this semiconductor light emitting device 1, when a forward voltage is applied between the p-side electrode 8 and the n-side electrode 9, electrons are sent from the n-type semiconductor layer 14 to the light emitting layer 12. Is injected, and holes are injected from the p-type semiconductor layer 13. Light is generated by recombination of these in the light emitting layer 12. This light passes through the n-type semiconductor layer 14 and is extracted from the surface 26A of the mesa portion 26 as a light extraction surface via a fine uneven structure 28. On the other hand, the light directed from the light emitting layer 12 toward the p-type semiconductor layer 13 passes through the p-type semiconductor layer 13 and the translucent conductive layer 4 in this order, and is reflected by the metal layer 3. The reflected light passes through the translucent conductive layer 4, the p-type semiconductor layer 13, the light emitting layer 12, and the n-type semiconductor layer 14 in this order, and is transmitted from the surface 26A of the mesa portion 26 through the fine uneven structure 28. Taken out.

According to the configuration of the semiconductor light emitting device 1, the p-type contact layer 15 forming the back surface of the III-V group semiconductor structure 6 is made of an Al _x Ga _1-x As (0 ≦ x <1) -based semiconductor. The _{carrier concentration of the Al x} Ga _1-x As (0 ≦ x <1) -based semiconductor can be increased relatively easily. Therefore, as described above, even if the thickness of the p-type contact layer 15 is about 500 Å to 5000 Å, carbon (C) can be doped at a high concentration of ^{1.0 × 10 19} cm ^{-3 or more.} That is, since the p-type contact layer 15 having a relatively thin thickness contains impurities at a high concentration, the resistance of the p-type contact layer 15 can be reduced.

Further, according to the above configuration, _{since the translucent conductive layer 4 is directly connected to the p-type contact layer 15 made of an Al x} Ga _1-x As (0 ≦ x <1) -based semiconductor, the translucent conductive layer 4 is directly connected between the two. Ohmic contacts can be formed well. As a result, the forward voltage (VF) of the semiconductor light emitting device 1 can be reduced.
On the other hand, since _{the adhesion between the Al x} Ga _1-x As (0 ≦ x <1) -based semiconductor and the insulating layer 5 is not high, the above-mentioned low resistance is achieved by insulating from the III-V group semiconductor structure 6. A contradictory event occurs in which the layer 5 is easily peeled off. However, in this semiconductor light emitting device 1, between the group III-V semiconductor structure 6 and the insulating layer 5, (Al _y Ga _1-y ) _z In _1-z P (0 ≦ y ≦ 1, 0 ≦ z ≦) 1) Since the intermediate adhesive layer 7 made of a system semiconductor is interposed, high adhesion can be ensured between the III-V semiconductor structure 6 and the insulating layer 5. Further, according to the above configuration, since the convex portion 40 of the translucent conductive layer 4 is caught by the edge portion 38 of the through hole 10, the translucent conductive layer 4 can be made difficult to peel off.

Further, according to the above configuration, a void 41 (air) having a refractive index (n2 = 1) smaller than the refractive index (n1> 1) of the intermediate adhesive layer 7 is formed in a part of the intermediate adhesive layer 7. Therefore, the refractive index of light at the interface between the insulating layer 5 and the intermediate adhesive layer 7 can be improved. Therefore, it is possible to reduce the loss of light generated in the path from the interface through the intermediate adhesive layer 7 and the translucent conductive layer 4 to the metal layer 3.

7A to 7J are diagrams showing the manufacturing process of the semiconductor light emitting device 1 of FIGS. 1 to 3 in order of process. 8A to 8E are diagrams showing steps related to the formation of the intermediate adhesive layer 7, the insulating layer 5, and the translucent conductive layer 4 in the order of steps.
In order to manufacture the semiconductor light emitting device 1, for example, as shown in FIG. 7A, a group III-V semiconductor structure 6 and intermediate bonding are carried out by epitaxial growth on a growth substrate 44 (wafer) as an example of a first substrate made of GaAs or the like. Layer 7 is formed. As the growth method of the III-V group semiconductor structure 6, known growth methods such as a molecular beam epitaxial growth method and a metalorganic vapor phase growth method can be applied. At this time, if necessary, each layer is doped with a dopant (for example, the above-mentioned n-type dopant or p-type dopant). At this stage, the group III-V semiconductor structure 6 includes an n-type semiconductor layer 14, a light emitting layer 12, and a p-type semiconductor layer 13 in this order from the growth substrate 44 side.

Next, as shown in FIG. 8A, the surface 7A of the intermediate adhesive layer 7 is subjected to an ashing treatment. The ashing process is performed using, for example, oxygen plasma.
Next, as shown in FIGS. 7B and 8B, the insulating layer 5 is formed on the surface 7A of the ashed intermediate adhesive layer 7 by, for example, a CVD method. After the insulating layer 5 is formed, the heat treatment is performed at a temperature higher than the film forming temperature of the insulating layer 5 (for example, 240 ° C. to 300 ° C.) (for example, 350 ° C. to 500 ° C.). As a result, even if the stress of the insulating layer 5 is determined and the heat treatment step is performed thereafter, it is possible to suppress the generation of extra stress in the insulating layer 5.

Next, according to FIG. 8C, the insulating layer 5 is selectively patterned by wet etching using, for example, HF (hydrofluoric acid). As a result, the insulating layer 5 is isotropically etched to form a tapered through hole 10 (first portion 36).
Next, as shown in FIG. 8D, the intermediate adhesive layer 7 is continuously patterned from the first portion 36 by changing the etching solution, specifically, by wet etching using a Cl-based etching solution. As a result, the intermediate adhesive layer 7 is isotropically etched to form a tapered through hole (second portion 37). Since the intermediate adhesive layer 7 is isotropically etched, the etching proceeds in the lateral direction along the interface between the insulating layer 5 and the intermediate adhesive layer 7, and the side etching portion 39 is formed. In this way, as shown in FIG. 7C, a through hole 10 that exposes the p-type contact layer 15 is formed.

Next, as shown in FIGS. 7D and 8E, the translucent conductive layer 4 is formed on the insulating layer 5 by, for example, a thin-film deposition method. The translucent conductive layer 4 is embedded in the through hole 10 as a contact portion 11 and is directly connected to the p-type contact layer 15 exposed in the through hole 10. Further, the translucent conductive layer 4 (contact portion 11) spreads laterally so as to enter the side etching portion 39 in the second portion 37 of the through hole 10, and the widened portion is formed as a convex portion 40. ..

Next, as shown in FIG. 7E, the first metal layer 31 is formed on the translucent conductive layer 4 by, for example, a thin-film deposition method. The first metal layer 31 is made of Au or an alloy containing Au, and at least the outermost surface is made of an Au layer.
The next step is a bonding step between the growth substrate 44 and the substrate 2. In the bonding step, the first metal layer 31 on the growth substrate 44 and the second metal layer 32 on the substrate 2 are joined. The second metal layer 32 is made of Au or an alloy containing Au, and at least the outermost surface is made of an Au layer. The second metal layer 32 is formed on the surface of the substrate 2 as an example of the second substrate (the surface opposite to the surface on which the p-side electrode 8 is formed) before bonding, for example, by a vapor deposition method. Is.

More specifically, as shown in FIG. 7F, the growth substrate 44 and the substrate 2 are overlapped with the first and second metal layers 31, 32 facing each other, and the first and second metal layers 31, 32 are joined. The first and second metal layers 31, 32 may be joined by thermocompression bonding, for example. The conditions for thermocompression bonding are, for example, a temperature of 250 ° C. to 700 ° C., preferably about 300 ° C. to 400 ° C., and a pressure of 10 MPa to 20 MPa. By this joining, as shown in FIG. 7F, the first and second metal layers 31 and 32 are combined to form the metal layer 3. The growth substrate 44 is then removed, for example by wet etching.

The next step is a step of forming the n-side electrode 9. In this embodiment, the n-side electrode 9 is formed by the lift-off method. More specifically, first, a resist (not shown) having an opening having the same pattern as the electrode pattern of the n-side electrode 9 is formed on the group III-V semiconductor structure 6 (n-type contact layer 20). Next, for example, an electrode material film (not shown) is laminated on the group III-V semiconductor structure 6 by a vapor deposition method. Next, the electrode material film on the resist is removed together with the resist. As a result, the n-side electrode 9 made of the electrode material film remaining on the n-type contact layer 20 is formed. After that, although not shown, the n-type contact layer 20 exposed from the n-side electrode 9 is removed by etching. As a result, the n-type window layer 19 is exposed to a portion other than the n-side electrode 9.

Next, as shown in FIG. 7H, the p-side electrode 8 is formed on the back surface of the substrate 2 by, for example, a thin-film deposition method.
Next, as shown in FIG. 7I, the mesa portion 26 and the drawer portion 27 are formed by selectively removing the peripheral portion of the III-V semiconductor structure 6. The mesa portion 26 and the drawer portion 27 may be formed by, for example, wet etching. By wet etching, the outer peripheral surface 26B of the mesa portion 26 is formed in a tapered shape whose diameter increases in the direction toward the substrate 2.

Next, as shown in FIG. 7J, a fine uneven structure 28 is formed on the surface 26A of the mesa portion 26 by, for example, frost treatment (wet etching) or the like. The frost treatment may be performed by dry etching.
Next, although not shown, the semiconductor light emitting device 1 shown in FIGS. 1 to 3 can be obtained by dividing the substrate 2 (wafer) into chip sizes.

Although one embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.
For example, in the above-described embodiment, the through hole 10 is formed so as to continuously penetrate the insulating layer 5 and the intermediate adhesive layer 7, but is formed only in the insulating layer 5, for example, as shown in FIG. You may be. In this case, ToruHikarishirube conductive layer 4 _through the _{(Al y Ga 1-y)} z In 1-z P (0 ≦ y ≦ 1,0 ≦ z ≦ 1) based intermediate adhesive layer 7 made of a semiconductor, p It may be connected to the mold contact layer 15.

Further, the first portion 36 and the second portion 37 of the through hole 10 are formed so as to be stepped surfaces, but are formed so as to be substantially continuous surfaces with each other, for example, as shown in FIG. You may. That is, the side etching portion 39 and the void 41 are not formed, and the translucent conductive layer 4 may be in contact with the side portion of the second portion 37 in the through hole 10.
Further, although not shown, the translucent conductive layer 4 is not provided, and the metal layer 3 is connected to the p-type contact layer 15 directly or via a contact portion (metal contact or the like) embedded in the through hole 10. You may be.

In addition, the present invention can be modified in various ways within the scope of the matters described in the claims.

Next, the present invention will be described based on examples, but the present invention is not limited to the following examples.
(1) Evaluation of Adhesion of Insulation Layer The adhesion of the insulation layer to each of the InGaP layer as an example and the AlGaAs layer as a reference example was evaluated.

Specifically, the surfaces of the InGaP layer and the AlGaAs layer were subjected to the ashing treatment shown in FIG. 8A _{to form a SiO 2} film (n = 1.46, thickness = 3000 Å). Then, a tape (“SPV-C-300 (product name)” manufactured by Nitto Denko KK) was _{attached to the SiO 2} film, and a peeling test was performed by pulling the tape. As a result of the peeling test, the SiO ₂ film on the InGaP layer was not peeled off, whereas the SiO ₂ film on the AlGaAs layer was peeled off.

Similarly, a peeling test of the SiON film was also performed instead of the SiO _{2 film.} As a result, the SiON film on the InGaP layer was not peeled off, whereas the SiON film on the AlGaAs layer was peeled off.
From the above, it was found that the InGaP layer has higher adhesion to the insulating layer than the AlGaAs layer.
(2) Resistance evaluation of p-type contact layer The p-AlGaAs layer (carbon-doped, thickness = 2000 Å) as an example of the p-type contact layer and the p-GaP layer (carbon-doped, thickness = 3000 Å) as a reference example. The contact resistance of the translucent conductive layer (ITO) with respect to each of these was measured and compared.

Specifically, an ITO film is formed on the surfaces of the p-AlGaAs layer and the p-Gap layer in the TLM (Transmission Line Model) pattern shown in FIG. 11, and the IV measurement is performed by the TLM method using this pattern. Then, the contact resistance of ITO was graphed based on the result of the IV measurement. The result of IV measurement is shown in FIG. 12, and the result of contact resistance is shown in FIG.

As shown in FIG. 12, in the AlGaAs layer, the voltage (VF) and the current (IF) are in a proportional relationship, and from this, a good ohmic contact is formed between the AlGaAs layer and ITO. Do you get it. On the other hand, based on the graph of the GaP layer of FIG. 12, it is considered that a Schottky contact is formed between the GaP layer and ITO, not an ohmic contact.

Further, as shown in FIG. 13, it was found that the AlGaAs layer can significantly reduce the contact resistance of ITO as compared with the GaP layer.
(3) VF Comparison by Difference in P-type Contact Layer According to the above-described embodiment, a semiconductor light-emitting device having a p-type contact layer made of AlGaAs and a semiconductor light-emitting device having a p-type contact layer made of GaP were produced. The configurations other than the p-type contact layer were the same as each other. Further, in each semiconductor light emitting device, the chip size (size of the substrate 2) = 200 μm × 200 μm, the light emitting area (surface size of the mesa portion 26) = 175 μm × 175 μm, and the electrode diameter (diameter of the pad electrode portion 93) = φ90 μm. ..

Then, the IV characteristics of each semiconductor light emitting device were measured using a semiconductor parameter analyzer. The results are shown in FIG.
From FIG. 14, it was found that the forward voltage (VF) can be reduced by using the AlGaAs layer as compared with the case of using the GaP layer as the p-type contact layer. For example, when the forward current (IF) = 20 mA, the VF of the AlGaAs layer was lower than that of the GaP layer by about 0.1 V.

1 Semiconductor light emitting device 2 Substrate 3 Metal layer 4 Translucent conductive layer 5 Insulation layer 6 III-V semiconductor structure 7 Intermediate adhesive layer 10 Through hole 11 Contact part 12 Light emitting layer 15 p-type contact layer 31 First metal layer 32 Second Metal layer 36 1st part (through hole)
37 Second part (through hole)
38 Edge 39 Side etching 40 Convex 41 Void 44 Growth substrate

Claims (16)

_{A semiconductor layer including a contact region including an Al x} Ga _1-x As (0 ≦ x <1) -based semiconductor that includes a light emitting region and has a front surface as a light extraction surface and a back surface on the opposite side thereof, and forms the back surface. When,
An insulating layer arranged on the back surface side of the semiconductor layer and having a through hole,
An intermediate adhesive layer arranged between the semiconductor layer and the insulating layer and made of a (Al _y Ga _1-y ) _z In _1-z P (0 ≦ y ≦ 1, 0 ≦ z ≦ 1) -based semiconductor.
A semiconductor light emitting device including a metal layer arranged on the opposite side of the semiconductor layer of the insulating layer and electrically connected to the contact region via a contact portion in the through hole. The semiconductor light emitting device according to claim 1, further comprising a translucent conductive layer arranged between the insulating layer and the metal layer and including the contact portion. The second aspect of the present invention, wherein the through hole is formed not only in the insulating layer but also in the intermediate adhesive layer, and the translucent conductive layer is directly connected to the contact region through the through hole. Semiconductor light emitting device. The semiconductor light emitting device according to claim 3, wherein the contact region contains carbon (C) as an impurity at ^{a concentration of 1.0 × 10 19} cm ^{-3 or more.} The semiconductor light emitting device according to claim 4, wherein the contact region is composed of a layer having a thickness of 500 Å to 5000 Å. The through hole has a side-etched portion covered with an edge portion of the through hole in the portion of the insulating layer in the portion of the intermediate adhesive layer.
The semiconductor light emitting device according to any one of claims 3 to 5, wherein the translucent conductive layer includes a convex portion formed so as to spread laterally so as to enter the side etching portion. The semiconductor light emitting device according to claim 6, wherein a gap is formed between the side portion of the side etching portion and the convex portion. The semiconductor light emitting device according to any one of claims 1 to 7, wherein the intermediate adhesive layer is an InGaP layer. The semiconductor light emitting device according to any one of claims 1 to 8, wherein the insulating layer is made of SiO _{2, SiN or SiON.} The semiconductor light emitting device according to any one of claims 1 to 9, wherein the light emitting wavelength in the light emitting region is 800 nm or more. A step of forming a semiconductor layer including a light emitting region on the first substrate and a contact region including an Al _x Ga _1-x As (0 ≦ x <1) -based semiconductor on the uppermost surface.
On the semiconductor _layer, forming an intermediate adhesive layer made of _{(Al y Ga 1-y)} z In 1-z P (0 ≦ y ≦ 1,0 ≦ z ≦ 1) based semiconductor,
A step of forming an insulating layer on the intermediate adhesive layer and
The step of forming a through hole in the insulating layer and
A step of forming a first metal layer electrically connected to the contact region via a contact portion in the through hole on the insulating layer.
The process of forming the second metal layer on the second substrate and
A step of bonding the first substrate and the second substrate by joining the first metal layer and the second metal layer to each other.
A method for manufacturing a semiconductor light emitting device, which comprises a step of removing the first substrate after the bonding. A step of ashing the intermediate adhesive layer before forming the insulating layer is included.
The method for manufacturing a semiconductor light emitting device according to claim 11, wherein the insulating layer is formed on the surface of the intermediate adhesive layer that has been ashed. The method for manufacturing a semiconductor light emitting device according to claim 12, wherein the ashing treatment includes a step of treating the surface of the intermediate adhesive layer using oxygen plasma. Claims 11 to 13 further include a step of forming a translucent conductive layer on the insulating layer so that a part of the contact portion is embedded in the through hole before forming the first metal layer. The method for manufacturing a semiconductor light emitting device according to any one of the above. The step of forming the through hole includes a step of forming the through hole in the intermediate adhesive layer in addition to the insulating layer.
The method for manufacturing a semiconductor light emitting device according to claim 14, wherein the translucent conductive layer is formed so as to be directly connected to the contact region through the through hole. The step of forming the through hole includes a step of forming a side etching portion in the portion of the intermediate adhesive layer so as to spread laterally from the edge portion of the through hole in the portion of the insulating layer.
The method for manufacturing a semiconductor light emitting device according to claim 15, wherein the translucent conductive layer is formed so as to include a convex portion formed so as to enter the side etching portion.

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