JP6968404B2 - Group III nitride semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a group III nitride semiconductor device, particularly an FET using a group III nitride semiconductor and a method for manufacturing the same.

Group III nitride wide-gap semiconductors represented by GaN have the features of high withstand voltage and high electron mobility, and are being applied to power devices that require high output and high voltage operation. A typical example of such a power device is a field effect transistor (FET) using a group III nitride semiconductor.
The problem with insulated gate-type FETs using group III nitride semiconductors is that it is difficult to form a gate insulating film with a small interface state with the surface of group III nitride semiconductors because the vapor pressure of nitrogen is high and nitrogen leakage is likely to occur. Therefore, the instability of the interface state (Vth shift) and the increase of the leakage current between the source and drain are likely to occur, and the common problem of FET is the reduction of the contact resistance with the source and drain regions of the group III nitride semiconductor. It is difficult.

For example, as an FET using a GaN-based semiconductor, Patent Document 1 discloses a method of forming a plasma-free silicon nitride film on GaN by a CAT-CVD method to manufacture a high-performance insulated gate-type FET. There is.
Further, in Patent Document 2, in order to reduce the contact resistance between the source / drain region of the Schottky gate type and the insulated gate type AlGaN / GaN-HEMT using a GaN-based semiconductor and the electrode, MOCVD is performed without performing recess etching. A technique is disclosed in which an n + GaN layer is selectively regrown on an AlGaN layer in a source / drain region by a method, an electrode is formed on the n + GaN layer, and ohmic contact is realized. Since recess etching is not performed, there is no etching damage, a high-quality n + GaN layer can be formed, and the contact resistance is reduced.

As described above, the transistor using the GaN-based semiconductor has the above-mentioned problems, and it is particularly difficult to realize a normally-off type transistor in which the leakage current between the source and drain is suppressed and to increase the on-current at the same time. .. As a solution for achieving both of these problems, for example, Patent Document 3 discloses a technique for forming nickel oxide (NiO) in a gate region. In addition, Non-Patent Documents 2 and 3 also disclose a gate electrode structure using a NiO film.

Japanese Unexamined Patent Publication No. 2008-103408 Japanese Unexamined Patent Publication No. 2008-124262 WO2014 / 020809

M. H. Kim, et al. , "Investigation of the initial stage of GaN epitaxial growth on 6H-SiC6H-SiC (0001) at room temperature", Appl. Phys. Let. 89,031916 (2006) N. Kaneko, et al. , "Normally-off AlGaN / GaN HFETs using NiOx gate with pressure", IEEE ISPSD, pp. 25-28, 2009. A. Suzuki, et al, "NiO gate GaN-based enhance-mode heterojunction field-effect transistor with extension remory low on-resistance handling general electric" 55, Num. 12

As described above, although a technique for preventing damage to the surface of the group III nitride has been developed, further improvement is required in order to realize a high-performance FET.
That is, GaN is prone to nitrogen desorption (nitrogen loss), and there is a problem that defects due to nitrogen vacancies generated in the manufacturing process may exist in the vicinity of the GaN surface. This problem cannot be solved.

In Patent Document 1, it is stated that the occurrence of plasma damage to the underlying GaN layer can be eliminated by forming a plasma-free film, but the defects near the surface generated in the previous step are not considered. Further, CAT-CVD promotes decomposition of the raw material gas by the catalytic action of the metal surface, but it is basically thermal CVD, and the problem of nitrogen desorption due to the heat treatment of GaN cannot be solved.

The above-mentioned Patent Document 2 can eliminate plasma damage due to recess etching of a Group III nitride substrate. However, in the actual manufacturing process, when the silicon oxide film on the AlGaN layer is dry-etched for the purpose of forming a mask for selective regrowth, over-etching is unavoidable in order to cope with the variation in the film thickness of the silicon oxide film. .. Therefore, it is difficult to avoid plasma damage to the outermost surface of the AlGaN layer. Furthermore, since the MOCVD method selectively grows GaN at a high temperature of 1000 ° C or higher, nitrogen desorption from the GaN surface is performed in the process of stopping the supply of raw material gas and cooling the group III nitride semiconductor substrate in a high temperature state to room temperature. , And crystal defects due to nitrogen vacancies cannot be prevented.

By using MOMBE using an organometallic gas source instead of MOCVD, selective growth at a relatively low substrate temperature is possible. However, even if MOMBE is used, the substrate temperature is 800 [° C.] or higher, and the problem of crystal defects due to nitrogen desorption cannot be solved.

Further, the treatment method for recovering the crystal defects on the surface of the group III nitride semiconductor generated in the manufacturing process is not disclosed in any of the patent documents. When heat treatment is performed to recover crystal defects, there is a problem that defects due to nitrogen desorption are newly generated.

As described above, both the problem of the gate insulating film of the group III nitride semiconductor mentioned in Patent Documents 1 and 2 and the problem of the contact resistance with the group III nitride semiconductor are taken into consideration for crystal defects due to nitrogen desorption. No technology has been developed that can solve this problem of crystal defects.

Further, the NiO film described in Patent Document 3 can increase the hole concentration by oxidative heat treatment and obtain good normalization-off characteristics, but the group III nitride caused by substrate oxidation and nitrogen desorption by oxidative heat treatment. There is a risk of increasing crystal defects on the semiconductor surface. Therefore, advanced technology for adjusting temperature, oxygen partial pressure, etc. is required. Further, when the insulation protective film layer in the gate region is opened by the dry etching method, there is a risk of plasma damage occurring on the surface of the group III nitride semiconductor, but when the dry etching method is used, it is applied to the substrate. The above-mentioned Patent Document 3 does not disclose a method for avoiding or repairing damage.

In view of the above problems, it is an object of the present invention to provide a high-performance group III nitride semiconductor device and a method for manufacturing the same while suppressing crystal defects near the surface of the group III nitride semiconductor.

The method for manufacturing a semiconductor device according to the present invention is as follows.
It is characterized by comprising a step of performing a nitrogen radical treatment of heating a substrate having a group III nitride semiconductor on the surface while irradiating the surface of the substrate with nitrogen radicals.

In this way, by heating the Group III nitride semiconductor while irradiating it with nitrogen radicals while it is exposed on the surface, it is possible to prevent the generation of defects due to nitrogen desorption on the surface of the Group III nitride semiconductor, which has been a conventional problem. Further, even when a crystal defect occurs on the surface of the group III nitride semiconductor due to nitrogen desorption in the manufacturing process of the semiconductor device, the defect can be repaired. As a result, a crystal surface of a group III nitride semiconductor for manufacturing a high-performance semiconductor device can be easily obtained.

The method for manufacturing a semiconductor device according to the present invention is as follows.
The semiconductor device is a transistor,
The first step of performing the nitrogen radical treatment and
After the first step, the surface of the substrate is continuously irradiated with nitrogen radicals, and a silicon nitride film is formed on the surface of the substrate by the PLD method targeting silicon to form a gate insulating film. Process and
The third step of forming the gate electrode on the silicon nitride film and
It is characterized by including a fourth step of removing the silicon nitride film on a region to be a source region and a drain region to form a source electrode and a drain electrode.

Further, the method for manufacturing a semiconductor device according to the present invention is as follows.
The gate electrode formed in the third step is made of metal.

By adopting such a method for manufacturing a semiconductor device,
Since silicon nitride, which is a gate insulating film, is formed after preventing crystal defects on the surface of the group III nitride semiconductor due to nitrogen desorption, a gate insulating film with few interface states can be formed, and the transistor is stable. The operation can be realized.
In particular, by irradiating a heated substrate with nitrogen radicals, crystal defects can be effectively repaired.

Further, the method for manufacturing a semiconductor device according to the present invention is as follows.
In the third step, a NiO film containing Ag on the silicon nitride film by a PLD method under an oxygen atmosphere as a target in which an acid nitride of Ag or Ag and an acid nitride of Ni or Ni are mixed. NiO film and Ag oxide film by the PLD method in an oxygen atmosphere targeting Ni or Ni oxynitrides and the PLD method in an oxygen atmosphere targeting Ag or Ag oxynitrides. And the process of forming a laminated film with
A step of heat-treating the Ag-containing NiO film or the laminated film of the NiO film and the Ag oxide film at a temperature of 200 [° C.] or higher in an oxygen atmosphere to form a p-type NiO film.
It is characterized by including a step of patterning the p-type NiO film and forming a gate electrode.

As described above, the hole concentration in the NiO film can be increased by heat-treating the NiO film in an oxygen atmosphere at a temperature of 200 [° C.] or higher. Further, it is possible to obtain the same effect by raising the substrate temperature during PLD film formation in an oxygen atmosphere to 200 [° C.] or higher.
In either case, the underlying silicon nitride film can effectively block the oxidation of the III-nitride semiconductor surface and also cause nitrogen desorption (defects or deep levels) on the III-nitride semiconductor surface. However, it is possible to easily prevent the interface state from increasing.
Further, by introducing Ag as a p-type dopant into the NiO film, the hole concentration can be increased and the hole concentration can be controlled by the Ag content (concentration).
By controlling the work function of the NiO film formed on the gate insulating film by the concentration of Ag, increasing the Ag concentration, and increasing the hole concentration, the work function has an electron affinity of 2.5 [eV] and a band of NiO. It can be brought close to the sum of the gap energy of 4.0 [eV].
As a result, a gate electrode having a high work function can be formed, and an enhancement type FET can be provided.

Further, the method for manufacturing a semiconductor device according to the present invention is as follows.
In the step of patterning the p-type NiO film to form a gate electrode,
It is characterized by comprising a step of etching the p-type NiO film by immersing the substrate in a mixed solution containing concentrated sulfuric acid and hydrogen peroxide solution at a temperature of 60 [° C.] or higher.

By adopting such a method for manufacturing a semiconductor device,
The p-type NiO film, which was difficult to etch, can be etched by the wet etching method, and the gate electrode made of the p-type NiO film can be patterned at low cost.

The method for manufacturing a semiconductor device according to the present invention is as follows.
The semiconductor device is a transistor,
The first step of forming an etching mask having a source region and a drain region on a substrate having a group III nitride semiconductor on the surface thereof.
A second step of etching the source region and the drain region of the substrate using the etching mask as a mask.
The third step of performing the nitrogen radical treatment and
After the third step, the n-type III nitride semiconductor becomes the source region and the drain region by the PLD method targeting the group III element containing the group IV element while continuously irradiating the nitrogen radical. The fourth step of epitaxial growth in the region and
It is characterized by including a fifth step of forming a conductive film on the epitaxially grown n-type III-nitride semiconductor.

Further, the method for manufacturing a semiconductor device according to the present invention is as follows.
The fifth step, the 12CaO · _7Al 2 _{O 3} by PLD on a substrate (hereinafter, referred to as. "C12A7 film") forming a,
The step of forming a film containing Ti on the substrate and
It is characterized by including a step of heat-treating the substrate in a vacuum at a temperature of 200 [° C.] or higher.

By adopting such a method for manufacturing a semiconductor device,
It is possible to regrow a group III nitride semiconductor containing an n-type dopant while suppressing crystal defects on the group III nitride semiconductor of the substrate, and the regrown n-type group III nitride semiconductor and the substrate The contact resistance (contact resistance) and the contact resistance between the n-type III nitride semiconductor and the electrode (contact electrode) are reduced, and a high-performance transistor can be provided.
In particular, the PLD method can effectively prevent nitrogen desorption as compared with the film formation by the MBE method or the MOCVD method. In the MOCVD method used for film formation of group III nitride semiconductors, the substrate temperature is 1000 [° C] or higher, and even in the MBE method, which enables film formation at relatively low temperatures, the substrate temperature is 800 [° C] or higher. be. However, as described in Non-Patent Document 1, the PLD method enables crystal growth of a group III nitride semiconductor even when the substrate temperature is 700 [° C.] and further 500 [° C.] or less. Therefore, the substrate temperature can be lowered as compared with the MBE method and the MOCVD method, and nitrogen desorption can be prevented.
Further, the C12A7 film can be effectively reduced by continuously performing a heat treatment of 200 [° C.] or more after forming Ti. As a result, by using the C12A7 film as a contact electrode that makes ohmic contact with the n-type III nitride semiconductor, the contact resistance can be further reduced.
In this specification, the 12CaO · _7Al 2 _{O 3,} known as electride, may be described as a general notation C12A7.

The method for manufacturing a semiconductor device according to the present invention is as follows.
The semiconductor device is a transistor,
The first step of forming an etching mask having a region to be a source region and a drain region on a substrate having a group III nitride semiconductor on the surface, and using the etching mask as a mask, the source region and the drain of the substrate. The second step of etching the region to be the region and
The third step of performing the nitrogen radical treatment and
After the third step, the p-type III nitride semiconductor is applied to the source region and the drain region by the PLD method targeting the Group III element containing Mg while continuously irradiating the nitrogen radical. 4th step of epitaxial growth and
A fifth step of forming a source electrode and a drain electrode on the p-type III nitride semiconductor that has been epitaxially grown, and
It is characterized by including.

Further, the method for manufacturing a semiconductor device according to the present invention is as follows.
In the fifth step, a NiO film containing Ag is formed on the substrate by a PLD method targeting NiO containing Ag, or a PLD method targeting NiO and a PLD method targeting Ag. The process of forming a laminated film of NiO and Ag by
A step of heat-treating the substrate at a temperature of 200 ° C. or higher in an oxygen atmosphere to form a NiO film containing the Ag or a laminated film of the NiO and Ag into a p-type NiO film.
A step of patterning the p-type NiO film and leaving it on the epitaxially grown p-type III nitride semiconductor.
It is characterized by including.

By adopting such a method for manufacturing a semiconductor device, it is possible to re-grow a group III nitride semiconductor containing a p-type dopant while suppressing crystal defects on the group III nitride semiconductor of the substrate. As a result, the contact resistance (contact resistance) between the regrown p-type III nitride semiconductor and the substrate and the contact resistance between the p-type III nitride semiconductor and the electrode are reduced to provide a high-performance transistor. Can be done.
Further, by using the p-type NiO film as a contact electrode in contact with the p-type III-nitride semiconductor, the contact resistance can be further reduced.

The method for manufacturing a semiconductor device according to the present invention is as follows.
After the fourth step, the substrate is immersed in a TMAH (tetramethylammonium hydroxide) solution of 50 [° C.] or higher.

By adopting such a method for manufacturing a semiconductor device, it becomes easy to remove the etching mask.
The reason for this is that TMAH has the characteristics that the etching rate of the GaN crystal with respect to the c-plane is low and the etching rates of the a-plane and m-plane are high. That is, the epitaxially grown GaN does not proceed with etching, and the polycrystalline GaN film deposited on the etching mask contains various crystal planes, so that etching proceeds preferentially. As a result, the etching mask of the lower layer is easily exposed and can be easily removed by phosphoric acid or the like.

The method for manufacturing a semiconductor device according to the present invention is as follows.
The semiconductor device is a transistor,
At least a region to be a source region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor is etched to obtain the first group. The first step of exposing the group III nitride semiconductor of No. 1 and
The second step of performing the nitrogen radical treatment and
After the second step, the n-type having a smaller electron affinity than the first group III nitride semiconductor is placed on the exposed first group III nitride semiconductor while being continuously irradiated with nitrogen radicals. The third step of forming the third group III nitride semiconductor by the PLD method and
It is characterized by including a fourth step of forming a contact electrode on the third group III nitride semiconductor.

In this way, by recovering crystal defects by heating in nitrogen radicals and re-growing a group III nitride semiconductor in the source region while suppressing the generation of defects by the PLD method, electrons are transferred from the source region to the channel region. It is possible to easily manufacture an n-channel transistor capable of increasing the electron velocity and increasing the on-current when injected.

The method for manufacturing a semiconductor device according to the present invention is as follows.
The semiconductor device is a transistor,
A region to be at least a drain region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor is etched to obtain the first group. The first step of exposing the group III nitride semiconductor of No. 1 and
The second step of performing the nitrogen radical treatment and
After the second step, while continuously irradiating the nitrogen radical, the n-type having a larger electron affinity than the first group III nitride semiconductor is placed on the exposed first group III nitride semiconductor. The third step of forming the fourth group III nitride semiconductor by the PLD method and
It is characterized by including a fourth step of forming a contact electrode on the third group III nitride semiconductor.

In this way, by recovering crystal defects by heating in nitrogen radicals and re-growing a group III nitride semiconductor in the drain region while suppressing the generation of defects by the PLD method, electrons are transferred from the channel region to the drain region. It is possible to easily manufacture an n-channel transistor capable of increasing the electron velocity and increasing the on-current when injected.

The method for manufacturing a semiconductor device according to the present invention is as follows.
The semiconductor device is a transistor,
A region serving as a source region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor is etched to obtain the first group. The first step of exposing the group III nitride semiconductor of
The second step of performing the nitrogen radical treatment and
After the second, the n-type third having a smaller electron affinity than the first group III nitride semiconductor is placed on the exposed first group III nitride semiconductor while being continuously irradiated with nitrogen radicals. In the third step of forming the group III nitride semiconductor of the above by the PLD method,
A fourth step of etching a region of the substrate to be a drain region to expose the first group III nitride semiconductor.
The fifth step of performing the nitrogen radical treatment and
After the fifth, while continuously irradiating the nitrogen radical, on the exposed first group III nitride semiconductor, the n-type fourth having a larger electron affinity than the first group III nitride semiconductor. In the sixth step of forming the group III nitride semiconductor of the above by the PLD method,
It is characterized by including a seventh step of forming a contact electrode on the third group III nitride semiconductor and the fourth group III nitride semiconductor.

By adopting such a method for manufacturing a semiconductor device, the speed of electrons increases when electrons are injected from the source region to the channel region, and when electrons are injected from the channel region to the drain region, the electron speed increases. By increasing the electron velocity, it is possible to provide an n-channel transistor capable of further increasing the on-current.

The method for manufacturing a semiconductor device according to the present invention is as follows.
The step of forming the contact electrode includes a step of forming a metal or a C12A7 film by the PLD method, a step of forming Ti by the PLD method, and a step of heating the substrate in a vacuum.
It is characterized by including in this order.

By adopting such a method for manufacturing a semiconductor device, the contact resistance between the source region and the drain region and the contact electrode is reduced, and the performance of the n-channel transistor is improved.

The method for manufacturing a semiconductor device according to the present invention is as follows.
The PLD method is characterized by being a PLD method using a pulse laser having a pulse width on the order of picoseconds.

In the PLD method, by using a pulse laser having a pulse width on the order of picoseconds, a film having good flatness and good crystallinity in a group III nitride semiconductor can be formed at a low temperature of 500 ° C. or lower. It is possible. Thereby, the generation of crystal defects due to nitrogen desorption can be effectively suppressed.
In this specification, it means a PLD method using a pulse laser having a pulse width on the order of picoseconds, that is, a pulse laser having a width of 1 picosecond or more and 1000 picoseconds or less.

The transistor according to the present invention is
A transistor using a group III nitride semiconductor,
A gate insulating film made of a silicon nitride film is provided on the group III nitride semiconductor.
A NiO gate electrode containing Ag is provided on the gate insulating film.

By using a transistor having such a configuration, by controlling the concentration of Ag in the NiO film, a gate electrode having a large work function can be realized, and an enhancement type transistor which has been difficult to manufacture in the past can be provided. ..

The transistor according to the present invention is
It is an n-channel transistor using a group III nitride semiconductor and includes an n-type group III nitride semiconductor epitaxially grown in the source region and the drain region.
An electrode is provided on the epitaxially grown n-type group III nitride semiconductor.
The electrode is characterized by having a C12A7 film in contact with the n-type group III nitride semiconductor that has been epitaxially grown.

By using a transistor having such a configuration, the contact resistance between the n-type III-nitride semiconductor in the source region and the drain region and the electrode can be reduced, and the on-current of the n-channel transistor can be improved.

The transistor according to the present invention is
It is a p-channel transistor using a group III nitride semiconductor and includes a p-type group III nitride semiconductor epitaxially grown in the source region and the drain region.
An electrode is provided on the p-type group III nitride semiconductor that has been epitaxially grown.
The electrode is characterized by comprising a NiO film containing Ag in contact with the p-type III-nitride semiconductor which has been epitaxially grown.

By using a transistor having such a configuration, the contact resistance between the p-type III nitride semiconductor in the source region and the drain region and the electrode can be reduced, and the on-current of the p-channel transistor can be improved.

The transistor according to the present invention is
It is an n-channel transistor using a group III nitride semiconductor.
It comprises a channel region having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor.
The source region in contact with the channel region has a third group III nitride semiconductor containing an n-type impurity having a smaller electron affinity than the first group III nitride semiconductor.
The third group III nitride semiconductor is characterized in that it is in contact with the first group III nitride semiconductor and the second group III nitride semiconductor.

By using a transistor having such a configuration, when electrons are injected from the source region to the channel region, the speed of the electrons increases and the on-current of the transistor can be improved.

The transistor according to the present invention is
It is an n-channel transistor using a group III nitride semiconductor.
It comprises a channel region having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor.
The drain region in contact with the channel region has a fourth group III nitride semiconductor containing an n-type impurity having a higher electron affinity than the first group III nitride semiconductor.
The fourth group III nitride semiconductor is a transistor characterized in that it is in contact with the first group III nitride semiconductor and the second group III nitride semiconductor.

By using a transistor having such a configuration, when electrons are injected from the channel region to the drain region, the speed of the electrons increases and the on-current of the transistor can be improved.
The regrowth source and drain regions are not limited to high-concentration Ge-doped GaN, but can be replaced with high-concentration Ge-doped AlGaN or high-concentration Ge-doped InGaN. Alternatively, it is possible to replace the source region and the drain region with group III nitride semiconductors having different band gaps. In this case, when electrons are transferred from the group III nitride semiconductor having a large bandgap to the group III nitride semiconductor, the effect of increasing the electron velocity can be obtained, so that the current can be further increased. become.

According to the transistor using the group III nitride semiconductor of the present invention and the method for manufacturing the same, crystal defects on the surface of the group III nitride semiconductor are suppressed, and the gate insulating film and source with few interface states, the drain region and the electrode are used. Low resistance contacts can be realized and high performance transistors can be obtained.

The conceptual diagram of the film forming apparatus used for manufacturing the semiconductor apparatus of this invention. The cross-sectional view which shows the main manufacturing process of Embodiment 1. FIG. The cross-sectional view which shows the main manufacturing process of Embodiment 1. FIG. The graph which shows the characteristic of an insulated gate transistor. The cross-sectional view which shows the main manufacturing process of Embodiment 2. Surface SEM photograph of the formed group III nitride semiconductor. The cross-sectional view which shows the main manufacturing process of Embodiment 2. The cross-sectional view which shows the main manufacturing process of Embodiment 3. The cross-sectional view which shows the main manufacturing process of Embodiment 3. The cross-sectional view which shows the main manufacturing process of Embodiment 3. The cross-sectional view which shows the main manufacturing process of Embodiment 4. The cross-sectional view which shows the main manufacturing process of Embodiment 5. The cross-sectional view which shows the main manufacturing process of Embodiment 5.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, none of the following embodiments give a limiting interpretation in finding the gist of the present invention. Further, the same or the same kind of members may be designated by the same reference numerals and the description thereof may be omitted.

Further, for the sake of simplicity, in the following description, GaN, AlGaN and the like may be described as typical examples of group III nitride semiconductors, but the present invention is not limited to GaN and AlGaN. For example, a mixed crystal of InN, GaN, AlN, BN and the like is also included in the group III nitride semiconductor.

(Embodiment 1)
FIG. 1 is a conceptual diagram showing a main configuration of a film forming apparatus used for manufacturing the group III nitride semiconductor apparatus of the present invention.

This film forming apparatus irradiates the surface of a target made of a film forming material with a pulsed laser by a PLD (PLD: Pulsed Laser Deposition) method to evaporate (ablate) the material and form a film on a substrate (hereinafter referred to as a film forming apparatus). , PLD device).

The PLD device includes a substrate support device 2 and a target support device 3 inside a chamber 1, which is an airtight vacuum container. A substrate 4, which is an object for forming a film, is placed on the substrate support device 2.
The substrate 4 is exemplified by a circular wafer having a GaN layer on the surface, but the substrate 4 is not limited thereto.

The substrate support device 2 can heat the substrate 4 and maintain it at a constant temperature by a built-in heating device.

A target container 5a is supported on the target support device 3. The target container 5a houses the target 6a, which is a film-forming material. Therefore, the target support device 3 supports the target 6a via the target container 5a.
Further, the target support device 3 includes a temperature control device. The temperature control device includes a heating or cooling device, and can maintain the temperature of the target 6a at a constant temperature via the target container 5a.

A plurality of target containers can be provided in the chamber 1. FIG. 1 shows an example in which different targets 6a and 6b are housed in two target containers 5a and 5b, respectively. Therefore, it becomes possible to continuously form a plurality of different types of films.
The number of target containers is not limited to two, and may be more than two, or may be one.

The chamber 1 includes a light transmitting window 7 for introducing a laser beam. The pulsed laser emitted from the laser irradiation device 8 installed outside the chamber 1 is focused by the lens 9, introduced into the chamber 1 through the light transmission window 7, and irradiated onto the target 6a.
The frequency of the laser pulse is set to be equal to or higher than the threshold value of the repetition frequency capable of maintaining continuous excitation with respect to the film-forming material on the surface of the target 6a as described later.
By setting the pulse width of the laser pulse to the order of picoseconds, it is possible to stably form a film having a flat surface.
When the pulse width is on the order of nanoseconds or more, it evaporates due to a thermal process and the crystallinity deteriorates, and when it is on the order of femtoseconds or less, the target material flies in a cluster shape and the flatness deteriorates.
The center wavelength of the pulsed laser and the energy of one pulse can be, for example, 1064 [nm] and 50 [μJ], respectively, but are not limited thereto. Further, the irradiation region (spot) diameter of the laser on the target 6a is focused to, for example, 100 [μm] or less, but is not limited to this.

The film-forming material evaporates at the portion of the surface of the target 6a irradiated with the laser beam. The film-forming material discharged from the surface of the target 6a forms a plume 11, and a film is formed by the film-forming material reaching the opposite substrate 4.

The chamber 1 includes a gas introduction port 12 and an exhaust port 13, and can control pressure and atmosphere.
A vacuum pump is connected to the exhaust port 13, and the inside of the chamber 1 can be exhausted to maintain a vacuum state.

Atmosphere control gas can be introduced from the gas introduction port 12 as needed. The pressure inside the chamber 1 can be kept constant by controlling the opening degree of the APC (Auto Pressure Controller) valve installed between the exhaust port 13 and the vacuum pump and the rotation speed of the vacuum pump.

In addition, this device has a load lock chamber for substrate replacement to prevent unnecessary oxidation of the target surface, and a turbo molecular pump is used for the exhaust of the chamber 1 for film formation, so that the base pressure is applied. ^{Can be 10-5} [Pa] or less.
Further, the nitrogen gas used is a high-purity gas compatible with semiconductors, for example, a gas purifier is used, and a gas having an oxygen concentration of 1 [ppb] or less is preferably used.

Further, the chamber 1 is equipped with a radical irradiation device 14, for example, a radical gun.
Radical irradiation device 14, MFC (mass flow controller) by the flow rate controlled nitrogen gas, for example, 2 [sccm] nitrogen _{(N 2)} gas is introduced, a high frequency, the power of example 13.56 [MHz] supplied .. The radical irradiation device 14 generates nitrogen radicals 18 from nitrogen gas by the supplied electric energy, and irradiates the surface of the substrate 4 with the generated nitrogen radicals 18 from the nozzle 15 which is an outlet. Since the nitrogen radical is active, it has a nitriding action on the film forming material flying from the surface of the substrate 4 and the target 6a to the substrate 4.
The frequency of the applied power is not limited to the above.

Hereinafter, a method for manufacturing a group III nitride semiconductor device using the PLD device will be described with reference to FIGS. 2 and 3.
2 and 3 show cross-sectional views of the main manufacturing process of the insulated gate FET of this embodiment.

Although one semiconductor transistor is drawn on the drawing for simplicity, a plurality of transistors may be formed on a group III nitride semiconductor substrate. Similarly, although the separation region for separating a plurality of transistors is omitted in the drawing, an inert region due to ion implantation may be provided as an element separation region, or a trench in which an insulating film is embedded may be provided. For example, with respect to FIGS. 2 and 3, an element separation region may be formed at a position perpendicular to the paper surface.
Ion implantation for element separation is performed with a photoresist mask, for example, N (nitrogen), Fe (iron), Zn (zinc) ions under the conditions of an acceleration voltage of 100 [keV] and a dose of 10 ¹⁵ [/ cm ² ]. It can be carried out.

First, as a group III nitride semiconductor substrate, a first group III nitride semiconductor layer 21, for example, a GaN layer is placed on a support substrate such as a (111) -plane silicon substrate, a C-plane silicon carbide, or a Ga-plane GaN template substrate. A substrate 20 is prepared in which a second group III nitride semiconductor layer 22, for example, Al _0.15 Ga _0.85 N is epitaxially grown by about 10 [nm], which is epitaxially grown by about [μm].
By combining the materials of the first group III nitride semiconductor layer 21 and the second group III nitride semiconductor layer 22 as described above, the first group III nitride semiconductor layer 21 and the second group III nitride are combined. The semiconductor layer 22 is heterojunctioned, and two-dimensional electrons are formed in the vicinity of the heterojunction interface.

In the following, in the region where the second group III nitride semiconductor layer 22 is formed on the first group III nitride semiconductor layer 21 and at least forms the gate insulating film, or in the channel region of the field effect transistor, the second group is formed. The description will be given to the substrate 20 in which the group III nitride semiconductor layer 22 of No. 2 is exposed, but the present invention is not limited thereto. It may be a substrate in which a group III nitride semiconductor layer is further formed in multiple layers or a substrate composed of a single layer of the group III nitride semiconductor layer.

As shown in FIG. 2A, in the PLD device 1 shown in FIG. 1, the substrate 20 is supported by the substrate support device 2, and a predetermined temperature is irradiated while irradiating the nitrogen radical 23 generated by the radical irradiation device 14. And hold for hours, for example, at a temperature of 200 [° C.] or higher for 1 [minute] or longer.
The holding conditions are merely examples, and the temperature and time are determined according to the state of the crystal defects of the substrate 20. The crystal state of the surface can be confirmed by, for example, a reflection high-speed electron diffraction method (RHEED) or the like. Therefore, an analyzer such as RHEED may be incorporated in the PLD device 1.

For example, when nitrogen pores are present near the surface of the second group III nitride semiconductor layer 22 due to possible damage in the manufacturing process, for example, the second group III nitride semiconductor layer 22 exposed on the substrate 20. Since the nitrogen radical 23 irradiated on the surface of the above is active nitrogen, it reacts so as to fill the nitrogen vacancies. Further, by heating the substrate 20, the reaction of nitrogen radicals is promoted, and crystal defects near the surface are effectively recovered.

When heated to recover crystal defects of a GaN-based crystal, nitrogen may be desorbed from the surface thereof and new crystal defects may be generated. However, as in the present embodiment, by heating the substrate 20 while irradiating the nitrogen radical 23, it is possible to recover the crystal defects and prevent the generation of crystal defects due to the desorption of nitrogen from the surface.

Next, as shown in FIG. 2B, while continuing the irradiation of the substrate 20 with the nitrogen radical 23, the evaporated silicon is supplied to the surface of the substrate 20 by the PLD method targeting silicon (Si). .. On the surface of the substrate 20, a silicon nitride film 24 serving as a gate insulating film, for example, a film thickness of 20 [nm], is formed on the second group III nitride semiconductor layer 22 by the reaction of Si and nitrogen radicals. NS. At this time, in order to promote the reaction between silicon and nitrogen, the temperature of the substrate 20 is set to, for example, 200 [° C.].

In this way, the second group III nitride is used to continuously form a silicon nitride film after recovering crystal defects while preventing nitrogen desorption from the surface of the second group III nitride semiconductor layer 22. It is possible to suppress the generation of interface levels between the semiconductor layer 22 and the silicon nitride film 24.
Further, the nitrogen radical is continuously supplied at a substrate temperature of 200 [° C.] or higher without interruption between the step shown in FIG. 2 (a) and the film forming step of the silicon nitride film shown in FIG. 2 (b). By continuing to do so, it is possible to effectively prevent nitrogen desorption at the start of film formation and at the time of film formation, and even for nitrogen defects that already existed, the defects are repaired beyond the activation energy for restoration. Can be done.

Next, as shown in FIG. 2 (c), a NiO film containing Ag is siliconized by a PLD method under an oxygen atmosphere as a target in which an acid nitride of Ag or Ag and an acid nitride of Ni or Ni are mixed. It is deposited on the nitride film 24. By forming a film in an oxygen atmosphere, the oxidation of NiO can be promoted and the hole concentration can be increased.
After that, oxygen gas is supplied to the radical irradiation device 14, oxygen radicals are generated, and heat treatment is performed at 200 ° C. or higher for, for example, 10 [minutes] while irradiating the NiO film surface with oxygen radicals.
By performing the heat treatment in an oxygen atmosphere, oxygen defects can be reduced and p-type conduction can be realized.

As a result, the Ag-doped p-type NiO film 25 can be formed. The content of Ag is, for example, 1 to 5 [mol%]. Further, the carrier concentration of the NiO film can be changed by changing the temperature and time of the heat treatment. By increasing the carrier concentration, it is possible to suppress the elongation of the depletion layer toward the NiO film side.
By providing a plurality of targets in the same PLD device, the process of FIG. 2 (c) can be continuously carried out without exposing the substrate 20 to the atmosphere after the process of FIG. 2 (b). .. As a result, unnecessary contamination and the like can be effectively removed from the silicon nitride film 24 which is the gate insulating film.

In the process of forming the NiO film, since it is covered with the silicon nitride film, nitrogen desorption of the second group III nitride semiconductor layer 22 can be prevented.
Further, since the silicon nitride film has oxygen impermeable property, it is possible to prevent the surface of the second group III nitride semiconductor layer 22 from being oxidized during the heat treatment in an oxidizing atmosphere after the formation of the NiO film. As a result, fluctuations in transistor characteristics due to surface oxidation can be prevented.

After depositing a NiO film containing Ag by the PLD method, heat treatment may be performed in an oxygen atmosphere in another device.

Further, after the NiO film is formed by the PLD method targeting NiO, the Ag is formed by the PLD method targeting Ag to form a laminated film of NiO and Ag, and the Ag is put into the NiO film by heat treatment. A p-type NiO film 25 that has diffused and is doped with Ag may be formed. The Ag concentration can be variably controlled by the film thickness of Ag to be formed.
In this case, the heat treatment for diffusing Ag does not need to be in an oxygen atmosphere, and in order to prevent the oxidation of Ag in the upper layer, the heat treatment may be performed in a vacuum or a nitrogen atmosphere. However, after diffusing Ag by heat treatment in a non-oxidizing atmosphere, heat treatment is performed in an oxygen atmosphere to increase the hole concentration of the NiO film and promote p-type formation.

The laminated film can be formed by a PLD method in which independent Ag and NiO targets are alternately used. Further, not limited to the above, the NiO film and Ag oxidation can be performed by the PLD method in an oxygen atmosphere targeting Ni or Ni oxynitrides and the PLD method in an oxygen atmosphere targeting Ag or Ag oxynitrides. A laminated film may be formed with the film.
By forming a NiO film by the PLD method in an oxidizing atmosphere, the oxidation of NiO can be promoted and the hole concentration can be increased.
Further, the laminated structure is not limited to the two-layer structure, and may be a multilayer film having three or more layers in which different films are alternately formed.

Although the NiO film is an oxide semiconductor having a large bandgap, it becomes a p-type semiconductor by doping Ag as described above, and the work function of the NiO film can be adjusted by the concentration of Ag to be doped.
The NiO film has the characteristics of an electron affinity of 2.5 [eV] and a band gap of 4.0 [eV]. The work function of a semiconductor is equal to the sum of electron affinity and the energy difference from the conduction band to the Fermi level, whereas in p-type semiconductors, the Fermi level is near the valence band, so the sum of electron affinity and bandgap. It becomes a value close to.
The work function of the p-type NiO film containing Ag increases the p-type carrier concentration by increasing the Ag concentration, and when the carrier concentration increases, the Fermi level approaches the valence band and exceeds the density of states. The energy difference from the conduction band to the Fermi level is equivalent to the bandgap because it shrinks when doped. Therefore, the work function of the p-type NiO film containing Ag is 6.5 [eV]. The value of this work function can be larger than 5.6 [eV] of Pt, which is the largest in metal.
As a result, by using a p-type NiO film containing Ag for the gate electrode, it is possible to realize an enhancement type FET, which has been difficult to manufacture in the past.
In addition to Ag, Li may be used as a p-type dopant for NiO. However, since Li is deliquescent, the use of Ag as a dopant facilitates the production of a film-forming target.

A p-type semiconductor may be formed by depositing an oxide semiconductor other than NiO and then doping it with Ag or other elements.
Further, in the above embodiment, the FET using the p-type NiO film as the gate electrode has been described, but a metal such as Ni or Pt may be used as the gate electrode. In this case, the gate electrode can be formed by forming a metal film on the silicon nitride film 24 which is a gate insulating film and patterning it by, for example, a PLD method targeting a metal such as Ni.

Next, as shown in FIG. 2 (d), the NiO film pattern 25a is formed by patterning the p-type NiO film 25. The p-type NiO film 25 can be patterned by dry etching by forming a photoresist by a lithography process and using the photoresist as a mask. However, since dry etching is performed on the silicon nitride film 24, the surface of the substrate 20 is dry etched. No damage is added.

When the p-type NiO film is wet-etched, the p-type NiO film can be etched by immersing the substrate in a mixed solution containing concentrated sulfuric acid and hydrogen peroxide solution raised to 60 [° C.] or higher. ..
As the above-mentioned mixed solution, for example, a commercially available concentrated sulfuric acid having a concentration of 90 [%] and a commercially available hydrogen peroxide solution having a concentration of 35 [%] are mixed at a volume ratio of concentrated sulfuric acid: hydrogen peroxide solution = 1: 1 to 3. The liquid can be used.

In the case of wet etching, a patterned silicon oxide film can be used as the etching mask. In this case, a silicon oxide film is formed on the p-type NiO film by a CVD method or the like, and a resist pattern is formed on the silicon oxide film by a lithography method. Then, by etching the silicon oxide film with hydrofluoric acid, a pattern of the silicon oxide film can be formed.
It is also possible to use a silicon nitride film instead of the silicon oxide film. When wet etching a silicon nitride film, thermal phosphoric acid may be used.

Next, as shown in FIG. 3A, for example, a silicon oxide film is formed by a CVD method or the like, and a mask 26 is formed by a combination of lithography and etching. Then, the silicon nitride film 24 is etched using the mask 26 as an etching mask to expose the source (cathode) and drain (anode) regions 27a and 27b of the second group III nitride semiconductor layer 22. At this time, the silicon nitride film 24 may not be removed and may be left on the element separation region (not shown).
Although the mask 26 is formed of a silicon oxide film, other materials may be used as long as the film can be used as a mask for the lift-off process.

When forming the mask 26, the silicon oxide film may be etched with the photoresist as the mask, and then the silicon nitride film 24 may be etched. However, by etching the silicon nitride film 24 using the mask 26 instead of the photoresist, it is possible to prevent the surface of the substrate 20 from being oxidized by the ashing treatment for removing the photoresist.

Next, as shown in FIG. 3B, a first metal film 28 for forming a contact electrode, for example, a laminated film of Ti and Al is formed in this order by a vapor deposition method or the like.
Then, the substrate 20 on which the first metal film 28 is formed is heat-treated and brought into ohmic contact. For example, as the first metal film 28, Ti / Au, Hf / Ni / Au, or Y / Ni / Au can be used in addition to Ti20 [nm] / Al200 [nm].

By heating the surface of the second group III nitride semiconductor layer 22 while irradiating it with nitrogen radicals before forming the first metal film 28, the second group III nitride semiconductor layer 22 is heated during dry etching. Crystal defects generated on the surface may be recovered. As a result, even lower resistance contact resistance can be realized.

Next, as shown in FIG. 3C, the mask 26 made of a silicon oxide film is removed by a wet etching method using, for example, hydrofluoric acid, and the first metal film 28 on the mask 26 is removed by a lift-off method. As a result, the first metal film 28 on the source and drain regions 27a and 27b is left behind.

Next, as shown in FIG. 3D, a second metal film 29 for gate wiring, for example, Ni20 [nm] / Au200 [nm], is formed on the NiO film pattern 25a by the lift-off method. Since the lift-off method is the same as the steps described with reference to FIGS. 3A, 3B, and 3C, details are omitted.

By the above steps, a gate-isolated FET can be obtained. After that, if necessary, an interlayer insulating film covering the FET is formed, and contact holes and wiring are formed.

The film thickness of the silicon nitride film may be appropriately determined in order to realize the desired withstand voltage and dielectric constant of the gate insulating film. Further, in the above embodiment, a silicon nitride film is used as the gate insulating film, but a silicon oxide film, an aluminum oxide film, a hafnium (Hf) oxide film, a zirconium (Zr) oxide film, and HfZr oxidation are used on the silicon nitride film. By forming another insulating film such as a film, the withstand voltage and the dielectric constant of the gate insulating film may be adjusted.

As the mask used in the lift-off method, a photoresist may be used in addition to the silicon oxide film.

In the above embodiment, the source and drain electrodes are formed after the gate electrode made of the NiO film is formed, but after the source and drain electrodes are formed by the lift-off method, the gate electrode made of the NiO film and the Ni / Au film are formed. Gate wiring may be formed.

Further, when the NiO film is directly formed on a group III nitride semiconductor and used as a gate electrode, the NiO film is a p-type semiconductor having a large bandgap, and a hetero-PN junction having many interface defects is formed. As a result, there arises a problem that the leakage current (off current) increases. However, the leakage current can be reduced by providing the silicon nitride film as in the above-described embodiment.

FIG. 4 shows the gate voltage (source-gate voltage) dependence of the drain current (Id) of the FET obtained by the present embodiment. FIG. 4 (a) shows the case where the substrate temperature at the time of film formation of the silicon nitride film 24 which is the gate insulating film is room temperature, and FIG. 4 (b) shows the case where the silicon nitride film 24 which is the gate insulating film is formed at room temperature. The drain current (Id) characteristic when the substrate temperature is 200 [° C.] is shown.

As shown in FIG. 4A, when the substrate temperature at the time of film formation of the silicon nitride film 24 is room temperature, there is hysteresis in the Id when the gate voltage is stepped up and down, and the gate voltage shift amount is 450 [mV]. ].
On the other hand, as shown in FIG. 4B, when the substrate temperature at the time of film formation of the silicon nitride film 24 is 200 [° C.], the hysteresis of Id at the time of stepping up and lowering the gate voltage is not confirmed, and the Id The gate voltage shift amount is as good as 100 [mV] or less. This result means that the interface state between the second group III nitride semiconductor layer 22 and the silicon nitride film 24 could be suppressed by forming the silicon nitride film 24 at a substrate temperature of 200 [° C.]. ..
Further, unlike the case where the film forming temperature of the silicon nitride film 24 is 200 [° C.], when the film forming temperature of the silicon nitride film 24 is room temperature, a clear hysteresis is observed, so that it is suitable for repairing crystal defects due to nitrogen radicals. Means that activation energy corresponding to a temperature of 200 [° C.] is required.

A p-type III nitride semiconductor may be formed between the gate insulating film 24 and the second group III nitride semiconductor layer 22 to form a so-called gate injection transistor which is a kind of FET in a broad sense.

In the above embodiment, the substrate is heat-treated while being irradiated with nitrogen radicals, and then the film is continuously formed on the substrate by the PLD method in the same chamber, but a multi-chamber device is used. It is also possible to process the substrate in different chambers and transfer the substrate between the chambers using a vacuum transfer system.

(Embodiment 2)
Hereinafter, other embodiments of the present invention will be described with reference to FIGS. 5, 6, and 7.
By utilizing the effect of preventing the generation of surface defects and recovering defects caused by nitrogen desorption of group III nitride semiconductors by heat treatment in a nitrogen radical atmosphere, the group III nitride is epitaxially grown in the source and drain regions of the FET. The performance of the FET can be improved.
Hereinafter, an N-channel Schottky gate FET will be described as an example, but the insulated gate FET disclosed in the first embodiment can also be suitably applied.

A substrate 20 on which a second group III nitride semiconductor layer 22, for example, an AlGaN layer is formed is prepared on a first group III nitride semiconductor layer 21, for example, a GaN layer, and as shown in FIG. 5 (a). , A silicon oxide film 30 is formed on the second group III nitride semiconductor layer 22 by a CVD method or the like.
Even if a silicon oxide film is formed while irradiating oxygen radicals using a Si as a target, after irradiating nitrogen radicals while heating using a PLD device to recover crystal defects on the surface of the substrate 20. good.

Next, as shown in FIG. 5B, by a combination of lithography and etching technology, the silicon oxide film 30 on the region to be the source region 31a and the drain region 31b of the FET is dry-etched using the photoresist as a mask, and then dry-etched. The photoresist is removed by an ashing treatment or the like to form a mask 30a. Next, using the mask 30a as a mask, the substrate 20 in the region to be the source region 31a and the drain region 31b is dry-etched to expose the first group III nitride semiconductor layer 21 to the surface.
The region sandwiched between the source region 31a and the drain region 31b becomes the channel region 31c. Strictly speaking, the channel region of the FET is a region in which electrical conduction is controlled by an electric field generated by the gate electrode, but in the present specification, the region sandwiched between the source region 31a and the drain region 31b is used as a channel for convenience. It is referred to as a region 31c.

Next, as shown in FIG. 5 (c), while irradiating the nitrogen radical 32, it is heated to, for example, 200 [° C.] to recover the crystal defects near the surface of the substrate 20.

Next, as shown in FIG. 5 (d), while irradiating with a nitrogen radical by the PLD method targeting Ga containing 2 [mol%] of a Group IV element such as germanium (Ge) as an n-type dopant, The third group III nitride semiconductors 33a and 33b, which are n-type GaN layers doped with Ge, are epitaxially grown in the source and drain regions 31a and 31b where the first group III nitride semiconductor layer 21 is exposed on the surface. .. On the other hand, since the mask 30a is composed of a silicon oxide film, a polycrystalline group III nitride semiconductor 33c, which is a polycrystalline GaN layer grown in an island shape without epitaxial growth on the mask 30a, is formed.

FIG. 6 is a surface SEM photograph after the step of FIG. 5 (d). Polycrystalline III-nitride semiconductors 33c with irregular surfaces are formed on the mask 30a, whereas the third group III nitride semiconductors 33a and 33b are epitaxial growth films having a smooth surface. Can be understood.

Next, as shown in FIG. 7A, the nitrogen radical irradiation is stopped, and C12A7 is targeted to form C12A7 films 34a, 34b, 34c by the PLD method, for example, having a film thickness of 10 to 20 [nm].
During the film formation of the C12A7 film by the PLD method, the oxygen atmosphere may be switched. It is also possible to continuously stack Ti by the PLD method after forming the C12A7 film.

After the step of FIG. 5D and before the step of FIG. 7A, the polycrystalline group III nitride semiconductor 33c may be etched with TMAH (tetramethylammonium hydroxide). As described below, the epitaxially grown third group III nitride semiconductors 33a and 33b are not etched by TMAH, and the polycrystalline group III nitride semiconductor 33c is selectively etched. Therefore, the mask 30a under the group III nitride semiconductor 33c is exposed, and the etching of the mask 30a in the lift-off step of the next step becomes easier.

TMAH (an aqueous solution having a weight concentration of 2.38 [%]) heated to 50 [° C.] or higher has an etching effect on the a-plane and m-plane of the GaN crystal, but has the property of not etching the c-plane. .. Since the surface of the epitaxially grown GaN (third group III nitride semiconductors 33a and 33b) is the c-plane, it is not etched. On the other hand, since the GaN film formed on the mask 30a (silicon oxide film) is polycrystalline (polycrystalline group III nitride semiconductor 33c), there are grains having a-plane and m-plane on the surface. As a result, only polycrystalline GaN (polycrystalline group III nitride semiconductor 33c) is selectively etched.

Next, as shown in FIG. 7B, the mask 30a is selectively removed by a wet etching method using, for example, hydrofluoric acid, and the polycrystalline group III nitride semiconductor 33c and the C12A7 film 34c on the mask 30a are removed. Then, the third group III nitride semiconductors 33a and 33b and the C12A7 films 34a and 34b are left in the source and drain regions 31a and 31b.

Next, as shown in FIG. 7 (c), for example, a Ti / Al film is vapor-deposited, and a third metal 35a, 35b containing Ti is formed on the C12A7 film 34a, 34b by a lift-off method. Then, heat treatment is performed in a vacuum at a temperature of 200 [° C.] or higher, and Ti is supplied from the third metals 35a and 35b to the C12A7 films 34a and 34b by thermal diffusion.
As described below, the C12A7 films 34a and 34b can have high electrical conductivity by supplying Ti and subjecting them to heat treatment.

The C12A7 film encapsulates free oxygen ions in a cage structure formed by a crystal lattice skeleton. By reducing the included free oxygen ions with Ti and replacing them with electrons, the C12A7 membrane can have high conductivity. Al can also function as a reducing agent.

The third metals 35a and 35b may be alloys containing Ti, but a laminated film having a Ti layer in the lower layer such as a Ti / Al film is more efficient for Ti on the C12A7 films 34a and 34b. Can be supplied.

C12A7 has a special effect of reducing contact resistance due to its high electrical conductivity and low work function of 2.4 [eV]. That is, since C12A7 has a small work function and is smaller than the electron affinity of the GaN surface, a potential barrier does not occur between C12A7 and GaN. As a result, the contact resistance has an effect that the contact resistance can be reduced as compared with the contact electrode made of a metal material conventionally used.

As the target of the C12A7 film to be vapor-deposited by the PLD method, C12A7 which has been previously heat-treated with a reducing agent such as Ti or Al may be used. As a result, it is possible to have high electrical conductivity without supplying a reducing agent from the third metals 35a and 35b.
In the case of the PLD method, free oxygen can be efficiently reduced by the energy of the laser beam.
Further, by depositing a C12A7 film by the PLD method and then performing a heat treatment while irradiating a hydrogen radical, or by vapor-depositing C12A7 while irradiating a hydrogen radical, free oxygen ions encapsulated by the reducing property of hydrogen are electronized. May be replaced with.

Next, as shown in FIG. 7 (d), a gate electrode 36 made of, for example, a Ni / Au film is formed by, for example, a lift-off method using a photoresist as a mask.

Before the formation of the Ti / Al film shown in FIG. 7 (c) and the film formation of the Ni / Au film shown in FIG. 7 (d), the substrate 20 is irradiated with nitrogen radicals using this PLD apparatus. You may heat the substrate while doing so. By forming a Ti / Al film or a Ni / Au film after recovering the crystal defects on the surface of the substrate 20, the contact resistance can be reduced and the threshold voltage can be stabilized.

In the present embodiment, since the group III nitride semiconductor is formed in the source and drain regions by the PLD method after recovering the crystal defects, the epitaxial growth can be performed while suppressing the generation of the crystal defects. Therefore, the contact resistance in the source and drain regions is lowered, and the on-resistance of the FET is reduced. As a result, the on-current of the FET increases.
Further, by using the C12A7 film which is in direct ohmic contact with the epitaxially grown group III nitride semiconductor as a contact electrode, the contact resistance with the group III nitride semiconductor can be further reduced, and the on-current of the FET can be reduced. It can be further increased.

The step shown in FIG. 7A is omitted, and a metal film such as a Ti / Al film is directly used as a source and drain regions 31a and 31b without interposing a C12A7 film. Ohmic contact may be made with the semiconductors 33a and 33b to serve as contact electrodes.
In this case, as compared with the above embodiment, the contact resistance is increased, but the manufacturing cost is reduced.

(Embodiment 3)
Although the N-channel FET has been described in the second embodiment, it is possible to manufacture a P-channel FET by using the film-forming pretreatment and the film-forming treatment of the present invention. Hereinafter, a method of manufacturing a P-channel FET will be described with reference to FIGS. 8, 9, and 10.

The first group III nitride semiconductor layer 21, for example, a GaN layer, the second group III nitride semiconductor layer 22, for example, an AlGaN layer, and the fourth group III nitride semiconductor layer 41, for example, a GaN layer were formed in this order. The substrate 40 is prepared.
The fourth group III nitride semiconductor layer 41 is heterojunctioned with the second group III nitride semiconductor layer 22, and a two-dimensional whole gas is formed in the fourth group III nitride semiconductor layer 41.

As shown in FIG. 8A, a silicon oxide film is formed on the fourth group III nitride semiconductor layer 41 by a CVD method or the like. After that, a mask 42 having an opening 43 is formed in a region to be a channel region of the P-channel FET by a combination of lithography technology and etching technology.

Next, as shown in FIG. 8 (b), while irradiating a nitrogen radical, a Ga target containing, for example, Mg as a p-type dopant is used by the PLD method, and a p-type III-nitride semiconductor is used on the substrate 40. The fifth group III nitride semiconductor 44, for example, Mg-containing GaN, is epitaxially grown. On the other hand, since it does not grow epitaxially on the mask 42, a polycrystalline group III nitride semiconductor 45, for example, a Mg-containing polycrystalline GaN is formed.

Next, as shown in FIG. 8 (c), the surface of the polycrystalline group III nitride semiconductor 45 is wet-etched to reduce the film thickness or remove fine crystals. For etching, for example, by using TMAH, the polycrystalline group III nitride semiconductor 45 is selectively etched, and the epitaxially grown fifth group III nitride semiconductor 44 is not etched. As a result, the exposed area of the mask 42 is increased, and the mask removal in the next step becomes easier.

Next, as shown in FIG. 8D, the mask 42 is wet-etched, and the fifth group III nitride semiconductor 45 on the mask 42 is removed by a lift-off method.

Next, as shown in FIG. 9A, a silicon oxide film is formed by a CVD method or the like, and a mask 46 is formed so as to cover the fifth group III nitride semiconductor 44 by a combination of lithography technology and etching technology. do.

Next, as shown in FIG. 9B, the substrate 40 is etched with the mask 46 as an etching mask to expose the surface of the first group III nitride semiconductor layer 21.

Next, as shown in FIG. 9 (c), the substrate 40 is heated to 200 [° C.] or higher while irradiating with nitrogen radicals to recover crystal defects, and then Ga containing 2 [mol%] of Mg is added. A sixth group III nitride semiconductor 47, which is a p-type group III nitride semiconductor, is epitaxially grown on the surface of the exposed first group III nitride semiconductor layer 21 by the target PLD method. At this time, a polycrystalline group III nitride semiconductor 48 is formed on the mask 46.

After that, the irradiation of the nitrogen radical is stopped, the target is changed, and for example, by the PLD method targeting NiO containing Ag, the sixth group III nitride semiconductor 47 and the polycrystalline group III nitride semiconductor 48 are applied. For example, a p-type contact conductive film 49, 50 made of a p-type NiO film doped with Ag is formed. After that, the conductive films 49 and 50 for contact can be subjected to a heat treatment of 200 [° C.] or more in an oxygen atmosphere to increase the electrical conductivity.

The heat treatment in the oxygen atmosphere can be performed in the PLD device, but the heat treatment may be performed in a separate heat treatment device.

Next, as shown in FIG. 9D, the mask 46 is wet-etched, and the polycrystalline group III nitride semiconductor 48 and the conductive film 50 for contact formed on the mask 46 are removed by a lift-off method.

Next, as shown in FIG. 10, a mask made of a photoresist is used to deposit a conductive film for electrodes, for example, Ni / Al, and a source, drain electrode 51 and a gate electrode 52 are formed by a lift-off method.

In the present embodiment, when the group III nitride semiconductor formed in the source and drain regions is formed, the crystal is recovered by performing a heat treatment while irradiating the nitrogen radical, and the p-type group III having good crystallinity is obtained. A sixth group III nitride semiconductor 47, which is a nitride semiconductor, can be formed.
Further, the group III nitride semiconductor 47 is brought into ohmic contact with the source and drain electrodes, and a conductive film 49 for contact of the p-type NiO film is interposed in order to reduce the contact resistance. The work function of the NiO film can be adjusted by the amount of doping of Ag, and the doping of Ag can reduce the contact resistance between the NiO film and the p-type group III nitride semiconductor 47.

Further, in the above embodiment, the p-type NiO film containing Ag was used as a contact electrode with the source and drain regions, but it was formed so as to be in contact with the fifth group III nitride semiconductor 44 and used as a gate electrode. You may use it.
After the step of FIG. 9D, the p-type NiO film containing Ag may be formed on the group III nitride semiconductor 44 again by the lift-off method. The method for forming the p-type NiO film containing Ag is the same as the step of FIG. 9 (c).
An enhancement type transistor can be realized by using a p-type NiO film containing Ag, which has a large work function and has conductivity, as a gate electrode of a Schottky type field effect transistor. Further, the threshold value of the transistor can be adjusted by adjusting the Ag concentration.

(Embodiment 4)
By combining the nitrogen radical irradiation according to the present invention and the film formation by the PLD method, it is possible to form a group III nitride having good crystallinity while suppressing crystal defects due to nitrogen vacancies.
In the following, a regrowth technique for a group III nitride semiconductor that can further reduce contact resistance will be described.

A substrate 20 on which a second group III nitride semiconductor layer 22, for example, an AlGaN layer is formed is prepared on a first group III nitride semiconductor layer 21, for example, a GaN layer. Then, through the steps of FIGS. 5A to 5C, the first group III nitride semiconductor layer 21 in the source and drain regions is exposed, and the substrate 20 is subjected to heat treatment while being irradiated with nitrogen radicals. Repairs surface defects.

Next, as shown in FIG. 11A, the n-type seventh group III nitride semiconductors 53a and 53b having a larger bandgap as compared with the first group III nitride semiconductor layer 21 are sourced in the source region, respectively. It is epitaxially grown in 31a and the drain region 31b to form a polycrystalline group III nitride semiconductor 54 on the mask 30a.
The seventh group III nitride semiconductors 53a and 53b and the polycrystalline group III nitride semiconductor 54 are formed by, for example, a PLD method targeting AlGaN containing Ge.

Next, as shown in FIG. 11B, the mask 30a is wet-etched, and the polycrystalline group III nitride semiconductor 54 is removed by a lift-off method.

Next, as shown in FIG. 11C, a source electrode 55a and a drain electrode 55b made of a Ti / Al film are formed by a lift-off method using, for example, a photoresist as a mask.

Next, as shown in FIG. 11D, a channel region in which the first group III nitride semiconductor layer 21 and the second group III nitride semiconductor layer 22 are heterojunctioned by, for example, a lift-off method using a photoresist as a mask. A gate electrode 56 made of a Ni / Au film is formed on 31c.
The channel region 31c is in contact with the source and drain regions 31a and 31b.

In the present embodiment, most of the two-dimensional electron gas is the first group III nitride semiconductor layer 21 due to the heterojunction between the first group III nitride semiconductor layer 21 and the second group III nitride semiconductor layer 22. Is generated in.
The seventh group III nitride semiconductor 53a formed in the source region 31a has a larger bandgap and electron affinity (energy from the vacuum level to the bottom of the conduction band) as compared with the first group III nitride semiconductor 21. ) Is small.
Therefore, an energy difference occurs between the conduction band of the seventh group III nitride semiconductor 53a in the source region 31a and the conduction band of the first group III nitride semiconductor 21 in the channel region 31c.
The electrons injected from the conduction band of the seventh group III nitride semiconductor 53a in the source region to the conduction band of the first group III nitride semiconductor 21 in the channel region are given kinetic energy corresponding to the above energy difference. , The speed increases.
Therefore, it is sufficient that the seventh group III nitride semiconductor 53a having a larger bandgap than the first group III nitride semiconductor 21 is formed in at least the source region 31a.

As a result, in the FET of the present embodiment, as compared with the case where the same group III nitride semiconductor as the first group III nitride semiconductor layer 21 is used as the seventh group III nitride semiconductor 53a in the source region 31a, The operating speed of the FET can be increased.

In the above embodiment, in the step shown in FIG. 11A, n-type 7th group III nitride semiconductors 53a and 53b having a larger band gap than the first group III nitride semiconductor layer 21 are used. However, as the n-type seventh group III nitride semiconductors 53a and 53b, a group III nitride semiconductor having a smaller band gap as compared with the first group III nitride semiconductor layer 21, for example, Ge. May be epitaxially grown by the PLD method targeting InGaN containing.
In this case, the electrons injected from the conduction band of the first group III nitride semiconductor 21 in the channel region 31c to the conduction band of the seventh group III nitride semiconductor 53b in the drain region 31b are the first group III nitrides. The kinetic energy corresponding to the energy difference between the conduction band of the semiconductor 21 and the conduction band of the seventh group III nitride semiconductor 53b is given, and the speed is increased.
As a result, the operating speed of the FET can be increased as compared with the case where the same group III nitride semiconductor as the first group III nitride semiconductor layer 21 is used as the seventh group III nitride semiconductor 53b in the drain region 31b. can.
Therefore, in this case, it is sufficient that the seventh group III nitride semiconductor 53b having a smaller bandgap than the first group III nitride semiconductor 21 is formed at least in the drain region 31b.

Although the Schottky gate type FET has been described in the above embodiment, it can also be applied to the group III nitride semiconductor in the source and drain regions of the insulated gate type FET, and is particularly suitable for the insulated gate type FET shown in the first embodiment. Applicable.

(Embodiment 5)
In the present embodiment, the high-speed operation of the FET can be enhanced by forming a group III nitride semiconductor having a small bandgap in the drain region.

As shown in FIG. 12A, the silicon oxide film 30 is combined with the lithography technique and the etching technique by the same method as the step of FIG. 5B so as to expose the region to be the source region 31a of the FET. Is patterned to form a mask 30b. After that, the substrate 20 in the region to be the source region 31a is dry-etched using the mask 30b as a mask to expose the first group III nitride semiconductor layer 21.

Next, as shown in FIG. 12 (b), while irradiating with nitrogen radicals, the cells are heated to, for example, 200 [° C.] to recover crystal defects near the surface of the substrate 20. Then, as compared with the first group III nitride semiconductor layer 21, an n-type seventh group III nitride semiconductor 53a having a large bandgap is epitaxially grown in the source region 31a, and the polycrystalline group III is formed on the mask 30b. The nitride semiconductor 54 is formed.
The seventh group III nitride semiconductor 53a and the polycrystalline group III nitride semiconductor 57 are formed by, for example, the PLD method targeting AlGaN.

Next, as shown in FIG. 12 (c), the mask 30b is wet-etched, and the polycrystalline group III nitride semiconductor 57 is removed by the lift-off method.

Next, as shown in FIG. 12 (d), the mask 58 that exposes the region to be the drain region 31b of the FET is formed by the same method as in FIG. 12 (a).

Next, as shown in FIG. 12 (e), the substrate 20 is etched with the mask 58 as a mask to expose the first group III nitride semiconductor layer 21 in the region to be the drain region 31b.
Then, while irradiating with nitrogen radicals, it is heated to, for example, 200 [° C.] to recover crystal defects on the surface of the substrate 20. Then, as compared with the first group III nitride semiconductor layer 21, an n-type eighth group III nitride semiconductor 59 having a small bandgap is epitaxially grown in the drain region 31b, and the polycrystalline group III is formed on the mask 58. The nitride semiconductor 60 is formed.
The eighth group III nitride semiconductor 59 and the polycrystalline group III nitride semiconductor 60 are formed by, for example, the PLD method targeting InGaN containing Ge.

Next, as shown in FIG. 13A, the mask 58 is wet-etched and the polycrystalline group III nitride semiconductor 60 is removed by the lift-off method.

Next, as shown in FIG. 13 (b), a source electrode 55a and a drain electrode 55b made of a Ti / Al film are formed by a lift-off method in the same manner as in the steps of FIGS. 11 (c) and 11 (d), and then lift-off is performed. By the method, a gate electrode 56 made of a Ni / Au film is formed on the channel region 31c.
The channel region 31c is in contact with the source and drain regions 31a and 31b.

In the present embodiment, the eighth group III nitride semiconductor 59 formed in the drain region has a smaller bandgap than the first group III nitride semiconductor 21 and has an electron affinity (from the vacuum level to the conduction band). Energy to the bottom) is large. Therefore, an energy difference occurs between the conduction band of the first group III nitride semiconductor 21 in the channel region and the conduction band of the eighth group III nitride semiconductor 59 in the drain region.
The electrons injected from the conduction band of the first group III nitride semiconductor 21 in the channel region to the conduction band of the eighth group III nitride semiconductor 59 in the drain region are given kinetic energy corresponding to the above energy difference. , The speed increases.
As a result, in the FET of the present embodiment, the operating speed of the FET can be further increased as compared with the fourth embodiment.

In the present embodiment, an example in which the seventh group III nitride semiconductor 53a is formed in the source region 31a and then the eighth group III nitride semiconductor 59 is formed in the drain region 31b is shown. After forming the eighth group III nitride semiconductor 59 in 31b, the seventh group III nitride semiconductor 53a may be formed in the source region 31a.

Although the Schottky gate type FET has been described above, it can also be applied to the insulated gate type FET, and particularly preferably to the insulated gate type FET shown in the first embodiment.

1 Chamber 2 Board support device 3 Target support device
4 Substrate 5a, 5b Target container 6a, 6b Target 7 Light transmission window 8 Laser irradiation device 20 Substrate 20
21 First Group III Nitride Semiconductor Layer 22 Second Group III Nitride Semiconductor Layer 23 Nitrogen Radical 24 Silicon Nitride Film 25 p-type NiO Film 25a NiO Film Pattern 26 Mask 27a Source Region 27b Drain Region 28 First Metal Film 29 Second metal film 30 Silicon oxide film 30a, 30b Mask 31a Source region 31b Drain region 31c Channel region 32 Nitrogen radicals 33a, 33b Third group III nitride semiconductor 33c Polycrystalline Group III nitride semiconductors 34a, 34b, 34c C12A7 film 35a, 35b Ti / Al film 36 Ni / Au film 40 Substrate 41 Fourth group III nitride semiconductor layer 42 Mask 43 Opening 44 Fifth group III nitride semiconductor 45 Polycrystalline group III nitride semiconductor 46 Mask 47 Group III Nitride Semiconductor 48 Polycrystalline Group III Nitride Semiconductor 49 Conductive Film for Contact 50 Conductive Film for Contact 51 Source, Drain Electrode 52 Gate Electrode 52
53a, 53b 7th Group III Nitride Semiconductor 54 Polycrystalline Group III Nitride Semiconductor 55a Source Electrode 55b Drain Electrode 56 Gate Electrode 57 Polycrystalline Group III Nitride Semiconductor 58 Mask 59 8th Group III Nitride Semiconductor 60 Polycrystalline Group III Nitride Semiconductor

Claims (20)

A method for manufacturing a semiconductor device, which comprises a step of performing a nitrogen radical treatment of heating a substrate having a group III nitride semiconductor on the surface while irradiating the surface of the substrate with nitrogen radicals.
The semiconductor device is a transistor,
The first step of performing the nitrogen radical treatment and
After the first step, a silicon nitride film is formed on the surface of the substrate by a PLD method targeting silicon while continuously irradiating the surface of the substrate with nitrogen radicals to form a gate insulating film. Step 2 and
The third step of forming the gate electrode on the silicon nitride film and
A method for manufacturing a semiconductor device, which comprises a fourth step of removing the silicon nitride film on a region to be a source region and a drain region to form a source electrode and a drain electrode. The method for manufacturing a semiconductor device according to claim 1, wherein the gate electrode formed in the third step is made of metal. In the third step, a NiO film containing Ag on the silicon nitride film by a PLD method under an oxygen atmosphere as a target in which an acid nitride of Ag or Ag and an acid nitride of Ni or Ni are mixed. NiO film and Ag oxide film by the PLD method in an oxygen atmosphere targeting Ni or Ni oxynitrides and the PLD method in an oxygen atmosphere targeting Ag or Ag oxynitrides. And the process of forming a laminated film with
A step of heat-treating the Ag-containing NiO film or the laminated film of the NiO film and the Ag oxide film at a temperature of 200 [° C.] or higher in an oxygen atmosphere to form a p-type NiO film.
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of patterning the p-type NiO film to form a gate electrode. In the step of patterning the p-type NiO film to form a gate electrode,
A claim comprising a step of etching the p-type NiO film by immersing the substrate in a mixed solution containing concentrated sulfuric acid and hydrogen peroxide solution at a temperature of 60 [° C.] or higher. 3. The method for manufacturing a semiconductor device according to 3. A method for manufacturing a semiconductor device, which comprises a step of performing a nitrogen radical treatment of heating a substrate having a group III nitride semiconductor on the surface while irradiating the surface of the substrate with nitrogen radicals.
The semiconductor device is a transistor,
The first step of forming an etching mask having a source region and a drain region on a substrate having a group III nitride semiconductor on the surface thereof.
A second step of etching the source region and the drain region of the substrate using the etching mask as a mask.
The third step of performing the nitrogen radical treatment and
After the third step, the n-type III nitride semiconductor becomes the source region and the drain region by the PLD method targeting the group III element containing the group IV element while continuously irradiating the nitrogen radical. The fourth step of epitaxial growth in the region and
A method for manufacturing a semiconductor device, which comprises a fifth step of forming a conductive film on the epitaxially grown n-type III-nitride semiconductor. The fifth step is a step of forming 12CaO / 7Al2O3 on the substrate by the PLD method.
The step of forming a film containing Ti on the substrate and
The method for manufacturing a semiconductor device according to claim 5, further comprising a step of heat-treating the substrate in a vacuum at a temperature of 200 [° C.] or higher. A method for manufacturing a semiconductor device, which comprises a step of performing a nitrogen radical treatment of heating a substrate having a group III nitride semiconductor on the surface while irradiating the surface of the substrate with nitrogen radicals.
The semiconductor device is a transistor,
The first step of forming an etching mask having a region to be a source region and a drain region on a substrate having a group III nitride semiconductor on the surface, and using the etching mask as a mask, the source region and the drain of the substrate. The second step of etching the region to be the region and
The third step of performing the nitrogen radical treatment and
After the third step, the p-type III nitride semiconductor is applied to the source region and the drain region by the PLD method targeting the Group III element containing Mg while continuously irradiating the nitrogen radical. 4th step of epitaxial growth and
A method for manufacturing a semiconductor device, which comprises a fifth step of forming a source electrode and a drain electrode on the p-type III nitride semiconductor that has been epitaxially grown. In the fifth step, a NiO film containing Ag is formed on the substrate by a PLD method targeting NiO containing Ag, or a PLD method targeting NiO and a PLD method targeting Ag. The process of forming a laminated film of NiO and Ag by
A step of heat-treating the substrate at a temperature of 200 [° C.] or higher in an oxygen atmosphere to form a NiO film containing the Ag or a laminated film of the NiO and Ag into a p-type NiO film.
A step of patterning the p-type NiO film and leaving it on the epitaxially grown p-type III nitride semiconductor.
7. The method for manufacturing a semiconductor device according to claim 7. The method for manufacturing a semiconductor device according to any one of claims 5 to 8, wherein the substrate is immersed in a TMAH solution having a temperature of 50 [° C.] or higher after the fourth step. A method for manufacturing a semiconductor device, which comprises a step of performing a nitrogen radical treatment of heating a substrate having a group III nitride semiconductor on the surface while irradiating the surface of the substrate with nitrogen radicals.
The semiconductor device is a transistor,
At least a region to be a source region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor is etched to obtain the first group. The first step of exposing the group III nitride semiconductor of No. 1 and
The second step of performing the nitrogen radical treatment and
After the second step, the n-type having a smaller electron affinity than the first group III nitride semiconductor is placed on the exposed first group III nitride semiconductor while being continuously irradiated with nitrogen radicals. The third step of forming the third group III nitride semiconductor by the PLD method and
A method for manufacturing a semiconductor device, which comprises a fourth step of forming a contact electrode on the third group III nitride semiconductor. A method for manufacturing a semiconductor device, which comprises a step of performing a nitrogen radical treatment of heating a substrate having a group III nitride semiconductor on the surface while irradiating the surface of the substrate with nitrogen radicals.
The semiconductor device is a transistor,
A region to be at least a drain region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor is etched to obtain the first group. The first step of exposing the group III nitride semiconductor of No. 1 and
The second step of performing the nitrogen radical treatment and
After the second step, while continuously irradiating the nitrogen radical, the n-type having a larger electron affinity than the first group III nitride semiconductor is placed on the exposed first group III nitride semiconductor. The third step of forming the fourth group III nitride semiconductor by the PLD method and
A method for manufacturing a semiconductor device, which comprises a fourth step of forming a contact electrode on the fourth group III nitride semiconductor. A method for manufacturing a semiconductor device, which comprises a step of performing a nitrogen radical treatment of heating a substrate having a group III nitride semiconductor on the surface while irradiating the surface of the substrate with nitrogen radicals.
The semiconductor device is a transistor,
A region serving as a source region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor is etched to obtain the first group. The first step of exposing the group III nitride semiconductor of
The second step of performing the nitrogen radical treatment and
After the second step, the n-type having a smaller electron affinity than the first group III nitride semiconductor is placed on the exposed first group III nitride semiconductor while being continuously irradiated with nitrogen radicals. The third step of forming the third group III nitride semiconductor by the PLD method and
A fourth step of etching a region of the substrate to be a drain region to expose the first group III nitride semiconductor.
The fifth step of performing the nitrogen radical treatment and
After the fifth step, while continuously irradiating the nitrogen radical, the n-type having a larger electron affinity than the first group III nitride semiconductor is placed on the exposed first group III nitride semiconductor. In the sixth step of forming the fourth group III nitride semiconductor by the PLD method,
A method for manufacturing a semiconductor device, which comprises a third step of forming a contact electrode on the third group III nitride semiconductor and the fourth group III nitride semiconductor. The step of forming the contact electrode includes a step of forming a metal or a C12A7 film by the PLD method, a step of forming Ti by the PLD method, and a step of heating the substrate in a vacuum.
The method for manufacturing a semiconductor device according to any one of claims 10 to 12, wherein the semiconductor device is included in this order. The method for manufacturing a semiconductor device according to any one of claims 1 to 13, wherein the PLD method is a PLD method using a pulse laser having a pulse width on the order of picoseconds. A transistor using a group III nitride semiconductor,
A gate insulating film made of a silicon nitride film is provided on the group III nitride semiconductor.
A transistor comprising a NiO gate electrode containing Ag on the gate insulating film. It is an n-channel transistor using a group III nitride semiconductor and includes an n-type group III nitride semiconductor epitaxially grown in the source region and the drain region.
An electrode is provided on the epitaxially grown n-type group III nitride semiconductor.
The electrode is an n-channel transistor provided with a C12A7 film in contact with the n-type group III nitride semiconductor that has been epitaxially grown. It is a p-channel transistor using a group III nitride semiconductor and includes a p-type group III nitride semiconductor epitaxially grown in the source region and the drain region.
An electrode is provided on the p-type group III nitride semiconductor that has been epitaxially grown.
The electrode is a p-channel transistor comprising a NiO film containing Ag in contact with the p-type III-nitride semiconductor that has been epitaxially grown. It is an n-channel transistor using a group III nitride semiconductor.
It comprises a channel region having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor.
The source region in contact with the channel region has a seventh group III nitride semiconductor containing an n-type impurity having a smaller electron affinity than the first group III nitride semiconductor.
The seventh group III nitride semiconductor is an n-channel transistor characterized in that it is in contact with the first group III nitride semiconductor and the second group III nitride semiconductor. It is an n-channel transistor using a group III nitride semiconductor.
It comprises a channel region having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned onto the first group III nitride semiconductor.
The source region in contact with the channel region has a seventh nitride semiconductor containing an n-type impurity having an electron affinity smaller than that of the first group III nitride semiconductor, and also has a seventh nitride semiconductor.
The drain region in contact with the channel region has an eighth group III nitride semiconductor containing an n-type impurity having a higher electron affinity than the first group III nitride semiconductor.
The eighth group III nitride semiconductor is an n-channel transistor characterized in that it is in contact with the first group III nitride semiconductor and the second group III nitride semiconductor. Nitrogen radical treatment in which a substrate having a group III nitride semiconductor on the surface is placed in a PLD device and the substrate is heated to 200 ° C. or higher while the surface of the substrate is irradiated with nitrogen radicals by a radical gun. A method for manufacturing a semiconductor device, which comprises a step of forming a silicon nitride film on the substrate by a PLD method targeting silicon while continuing irradiation with the nitrogen radical.

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