JP6948302B2 - 回路のパッケージ構造 - Google Patents
回路のパッケージ構造 Download PDFInfo
- Publication number
- JP6948302B2 JP6948302B2 JP2018195414A JP2018195414A JP6948302B2 JP 6948302 B2 JP6948302 B2 JP 6948302B2 JP 2018195414 A JP2018195414 A JP 2018195414A JP 2018195414 A JP2018195414 A JP 2018195414A JP 6948302 B2 JP6948302 B2 JP 6948302B2
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- Prior art keywords
- lead
- segment
- width
- connection portion
- bump connection
- Prior art date
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- 229910000679 solder Inorganic materials 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000012790 adhesive layer Substances 0.000 claims description 9
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 229920001721 polyimide Polymers 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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- 238000010304 firing Methods 0.000 description 1
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- 230000017525 heat dissipation Effects 0.000 description 1
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- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
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Description
に係る3つのリード37、38、39が占めるのと同じ領域上に、本発明に係る4つのリード32、33、35、36を形成することができる。
Claims (16)
- 回路のパッケージ構造であって、
基板と、
前記基板上に配置されており、かつ、第1リードおよび第2リードを含む、複数の金属層と、
複数のはんだマスク層と、
複数のバンプと、
接着層と、を備え、
前記第1リードは、第1バンプ接続部と、第1リードセグメントと、第2リードセグメントと、を備え、
前記第1リードセグメントは、前記第1バンプ接続部に接続されており、
前記第1リードセグメントの幅は、前記第1バンプ接続部の幅よりも狭く、
前記第1リードセグメントは、前記第1バンプ接続部と前記第2リードセグメントとの間に接続されており、
前記第2リードは、前記第1リードに隣り合っており、
前記第2リードと前記第1リードとの間には、リードギャップがあり、
第2バンプ接続部と、第1リードセグメントと、第2リードセグメントと、を備え、
前記第2リードの前記第1リードセグメントは、前記第2バンプ接続部に接続されており、
前記第1バンプ接続部および前記第2バンプ接続部は、スタガード配置されており、
前記第2バンプ接続部は、前記第1リードの前記第1リードセグメントに隣り合っており、
前記第2リードセグメントの前記第1リードセグメントは、前記第2バンプ接続部と前記第2リードセグメントとの間に接続されており、
前記複数のはんだマスク層は、前記第1リードの前記第2リードセグメントの一端および前記第2リードの前記第2リードセグメントの一端を覆うことなく、前記第1リードおよび前記第2リードの一部を覆っており、
前記複数のバンプは、チップの底部との接続のために、前記第1バンプ接続部上および前記第2バンプ接続部上に形成されており、
前記接着層は、前記基板と、前記複数の金属層と、前記複数のバンプと、を覆っている、回路のパッケージ構造。 - 前記第2リードの前記第1リードセグメントの幅は、前記第2バンプ接続部の幅よりも狭い、請求項1に記載の回路のパッケージ構造。
- 前記第1リードの前記第1リードセグメントは、前記第2リードの前記第1リードセグメントに隣り合っており、
前記第1リードの前記第1リードセグメントおよび前記第2リードの前記第1リードセグメントは、それらの間にギャップを形成し、
前記第1リードの前記第1リードセグメントの幅と前記ギャップとの合計は、14μmから18μmまでであり、かつ、18μm未満であり、
前記第2リードの前記第1リードセグメントの幅と前記ギャップとの合計は、14μmから18μmまでであり、かつ、18μm未満である、請求項1に記載の回路のパッケージ構造。 - 前記第2バンプ接続部は、前記第1リードの前記第1リードセグメントに隣り合っており、
前記第2バンプ接続部および前記第1リードの前記第1リードセグメントは、それらの間にギャップを形成し、
前記第1リードの前記第1リードセグメントの幅と前記ギャップとの合計は、14μmから18μmまでであり、かつ、18μm未満である、請求項1に記載の回路のパッケージ構造。 - 前記第1リードの前記第1リードセグメントの幅、および、前記第1リードの前記第2リードセグメントの幅は、前記第1バンプ接続部の幅よりも狭い、請求項1に記載の回路のパッケージ構造。
- 前記第2リードセグメントの幅は、前記第1バンプ接続部の幅と等しい、請求項1に記載の回路のパッケージ構造。
- 前記第2リードセグメントの幅は、前記第1リードの前記第1リードセグメントの幅と等しい、請求項1に記載の回路のパッケージ構造。
- 前記第2リードセグメントの幅は、
前記第1リードの前記第1リードセグメントの幅よりも広く、かつ、
前記第1バンプ接続部の幅よりも狭い、請求項1に記載の回路のパッケージ構造。 - 前記第2バンプ接続部は、前記第1リードの前記第1リードセグメントに隣り合っており、
前記第2バンプ接続部および前記第1リードの前記第1リードセグメントは、それらの間に第1ギャップを形成し、
前記第2リードの前記第1リードセグメントは、前記第1リードの前記第2リードセグメントに隣り合っており、
前記第2リードの前記第1リードセグメントおよび前記第1リードの前記第2リードセグメントは、それらの間に第2ギャップを形成し、
前記第1ギャップは、
前記第2ギャップと同一である、または、
前記第2ギャップとは異なる、請求項1に記載の回路のパッケージ構造。 - 前記第2リードの前記第1リードセグメントの幅、および、前記第2リードの前記第2リードセグメントの幅は、前記第2バンプ接続部の幅よりも狭い、請求項1に記載の回路のパッケージ構造。
- 前記第2リードセグメントの幅は、前記第2バンプ接続部の幅と等しい、請求項1に記載の回路のパッケージ構造。
- 前記第2リードセグメントの幅は、前記第2リードの前記第1リードセグメントの幅と等しい、請求項1に記載の回路のパッケージ構造。
- 前記第2リードセグメントの幅は、
前記第2リードの前記第1リードセグメントの幅よりも広く、かつ、
前記第2バンプ接続部の幅よりも狭い、請求項1に記載の回路のパッケージ構造。 - 第3リードをさらに備え、
前記第3リードは、前記第2リードと隣り合っており、
当該第3リードと前記第2リードとの間にはリードギャップがあり、
前記第3リードは、第3バンプ接続部および第1リードセグメントを備え、
前記第3リードの前記第1リードセグメントは、前記第3バンプ接続部に接続されており、
前記第3リードの前記第1リードセグメントの幅は、前記第3バンプ接続部の幅よりも狭く、
前記第3バンプ接続部および前記第2バンプ接続部は、スタガード配置されており、
前記第2バンプ接続部は、前記第1リードの前記第1リードセグメントおよび前記第3リードの前記第1リードセグメントと隣り合っている、請求項1に記載の回路のパッケージ構造。 - 前記第1リードの前記第1リードセグメントの側面は、湾曲しており、かつ、
前記第1リードの前記第1リードセグメントの側面に対応する前記第2バンプ接続部の側面は、湾曲している、請求項1に記載の回路のパッケージ構造。 - 前記第1リードの前記第1リードセグメントの側面は平坦であり、
前記第2バンプ接続部の側面は、前記第1リードの前記第1リードセグメントの側面と平行であり、かつ、平坦である、請求項1に記載の回路のパッケージ構造。
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