JP6805768B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a semiconductor element.

When the parasitic inductance in a semiconductor device having a semiconductor element such as a transistor is large, a large surge voltage may be generated. This surge voltage may adversely affect the operation of the semiconductor element. Therefore, the parasitic inductance in the semiconductor device should be as small as possible. Conventionally, semiconductor devices have been proposed in various ways in order to reduce parasitic inductance.

Patent Document 1 discloses a semiconductor device including a positive electrode bus bar and a negative electrode bus bar, which are electrically connected to each semiconductor module having a semiconductor element and a DC voltage is applied between them. According to Patent Document 1, a semiconductor module is composed of a large current semiconductor module capable of passing a large current and a small current semiconductor module capable of passing only a small current. Further, the large current substrate portion of the positive electrode bus bar and the large current substrate portion of the negative electrode bus bar are connected to the large current semiconductor module, and the small current substrate portion of the positive electrode bus bar and the small current substrate portion of the negative electrode bus bar are connected to the small current semiconductor module. Is connected. Each substrate portion has a portion connected to a capacitor. The distance between the large current substrate of the positive electrode bus bar and the large current substrate of the negative electrode bus bar at the connection to the capacitor is the small current substrate of the positive electrode bus bar and the small current substrate of the negative electrode bus bar at the connection to the capacitor. It is smaller than the distance between the parts. In this way, the distance between the large current substrate portion of the positive electrode bus bar and the large current substrate portion of the negative electrode bus bar is relatively small, so that the parasitic inductance of the large current substrate portion is reduced.

Patent Document 2 discloses a power conversion device including a power semiconductor module and a power board having a positive electrode conductor plate and a negative electrode conductor plate connected to the power semiconductor module. According to Patent Document 2, the positive electrode conductor plate and the negative electrode conductor plate of the power board are laminated and arranged. By such a laminated arrangement, a region is formed in which the positive electrode current flowing through the positive electrode conductor plate and the negative electrode current flowing through the negative electrode conductor plate flow in opposite directions to each other. Therefore, the inductances caused by the respective currents cancel each other out. As a result, the parasitic inductance on the power board is reduced.

Patent Document 3 describes a circuit unit having a first switching element and a second switching element connected in series, and a capacitor electrically connected in parallel to the first switching element and the second switching element. Discloses a plurality of semiconductor devices arranged side by side. According to Patent Document 3, since each circuit unit is provided with a capacitor, the parasitic inductance can be reduced as compared with the case where a plurality of circuit units are connected to one capacitor.

Japanese Unexamined Patent Publication No. 2015-015787 Japanese Unexamined Patent Publication No. 2014-171342 JP-A-2015-106646

(Problems to be solved by the invention)
According to Patent Document 1, although the parasitic inductance in the wiring connecting the semiconductor module and the capacitor can be reduced, the parasitic inductance in the semiconductor module cannot be reduced. Further, according to Patent Document 2, although the parasitic inductance generated in the power board connected to the semiconductor module can be reduced, the parasitic inductance in the semiconductor module cannot be reduced. Further, according to Patent Document 3, since it is necessary to provide a capacitor in each circuit unit, the cost of the semiconductor device increases.

An object of the present invention is to provide a semiconductor device in which the parasitic inductance in a semiconductor module is reduced while suppressing an increase in cost.

According to the present invention, between the positive electrode line (P) connected to the power supply side positive electrode terminal (VP) of the DC power supply (V) and the negative electrode line (N) connected to the power supply side negative electrode terminal (VN) of the DC power supply. A semiconductor device including a semiconductor module (10A, 10B, 10C) to be connected, wherein the semiconductor module is made of a conductive metal and is electrically connected to a positive electrode terminal on the power supply side of a DC power supply and in a predetermined direction ( It is composed of a positive electrode plate (14) on which a positive electrode surface (141) facing Z1) is formed and a conductive metal, and is electrically connected to a negative electrode terminal on the power supply side of a DC power supply and is oriented in the same direction as the positive electrode surface. A plurality of arm circuits (17a, 17b, 17c ) in which a facing negative electrode surface (151) is formed and are arranged in parallel with the negative electrode plate (15) arranged adjacent to the positive electrode plate and connected in parallel between the positive electrode plate and the negative electrode plate. , 17d, 17e), and each of the plurality of arm circuits is a surface (171a) on which the first electrode (D) is formed and a surface facing the opposite side to the one surface, and the second electrode ( A semiconductor element having the other surface (171b) on which S) is formed, the first semiconductor element (171) bonded to the positive electrode plate with one surface facing the positive electrode surface, and the first electrode. A semiconductor element having one surface (172a) on which (D) is formed and the other surface (172b) on which the second electrode (S) is formed, which is a surface facing the opposite side to the one surface, and the like. The second semiconductor element (172) bonded to the negative electrode plate with the direction facing the negative electrode surface, the other surface of the first semiconductor element facing the same direction, and one surface of the second semiconductor element are electrically connected. a conductive connecting member having a first connecting portion connecting (513) (51), have a conductive connection member of the plurality of arm circuits, the first conductive connection member provided in the arm circuit disposed adjacent Provided is a semiconductor device (1) including a partition piece (51) having a second connection portion (514) connected to the connection portion .

According to the present invention, the directions of the first semiconductor element and the second semiconductor element provided in the semiconductor module are opposite to each other. That is, one surface of the first semiconductor element and the other surface of the second semiconductor element face in the same direction, and the other surface of the first semiconductor element and one surface of the second semiconductor element face in the same direction. Therefore, the orientation of one surface of the first semiconductor element on which the first electrode is formed can be aligned with the orientation of the other surface of the second semiconductor element on which the second electrode is formed. Therefore, the orientation of the positive electrode surface of the positive electrode plate that is face-to-face connected to one surface of the first semiconductor element on which the first electrode is formed and the other surface of the second semiconductor element on which the second electrode is formed are face-to-face connected. The orientation of the negative electrode surface of the negative electrode plate can be matched. By matching the orientation of the positive electrode surface and the orientation of the negative electrode surface in this way, the positive electrode plate and the negative electrode plate can be arranged side by side in parallel. Therefore, the distance between the positive electrode plate and the negative electrode plate can be set short, and as a result, the parasitic inductance of the positive electrode plate and the negative electrode plate can be reduced.

Further, according to the present invention, since the first semiconductor element and the second semiconductor element are inverted and arranged as described above, the orientation of the other surface of the first semiconductor element on which the second electrode is formed and the first. The orientation of one surface of the second semiconductor device on which one electrode is formed can be matched. Therefore, the length of the first connecting portion connecting the other surface of the first semiconductor element on which the second electrode is formed and the one surface of the second semiconductor element on which the first electrode is formed is set short. As a result, the parasitic inductance of the conductive connecting member having the first connecting portion can also be reduced.

As described above, according to the present invention, the parasitic inductance of the positive electrode plate, the negative electrode plate, and the conductive connecting member can be reduced, and these members are members constituting the semiconductor module. That is, according to the present invention, the parasitic inductance in the semiconductor module can be reduced. Further, according to the present invention, by devising the arrangement of each configuration in the semiconductor module, the parasitic inductance can be reduced without adding a capacitor for reducing the parasitic inductance as in Patent Document 3, for example. That is, it is possible to reduce the parasitic inductance in the semiconductor module while suppressing the increase in cost.

Further, in the present invention, it is preferable that the positive electrode surface and the negative electrode surface are formed in the same plane. According to this, the region where the positive electrode plate and the negative electrode plate are arranged adjacent to each other, that is, the region where the positive electrode plate and the negative electrode plate are arranged adjacent to each other is the largest, so that the parasitic inductance of the positive electrode plate and the negative electrode plate can be further reduced. Regarding the above term "same plane", not only when the plane including the positive electrode surface and the plane including the negative electrode surface completely match, but also when the plane including the positive electrode surface and the plane including the negative electrode surface are included. If the difference in position in the normal direction is within the allowable error range, it can be considered that the positive electrode surface and the negative electrode surface are formed in the same plane.

Further, the first semiconductor element and the second semiconductor element are transistors (171, 172) having a third electrode (G), respectively, the first electrode is a drain electrode or a collector electrode, and the second electrode. Is a source electrode or an emitter electrode, and a third electrode may be a gate electrode or a base electrode. According to this, the semiconductor device according to the present invention can be applied to a power conversion device including an inverter circuit.

In the first semiconductor element and the second semiconductor element, the third electrode (gate electrode or base electrode) is formed on the other surface, that is, the surface on which the second electrode (source electrode or emitter electrode) is formed. The structure can be adopted. In this case, it is preferable that a recess (152) is formed in a portion of the negative electrode surface of the negative electrode plate facing the third electrode formed on the other surface of the second semiconductor element. The recess may be formed in a part of the facing portion of the third electrode and a part of the facing portion of the second electrode. When the third electrode is a gate electrode or a base electrode, a signal must be input to the third electrode via a signal line in order to switch the first semiconductor element and the transistor as the second semiconductor element. .. However, since the negative electrode surfaces arranged facing each other are bonded to the other surface on which the third electrode of the second semiconductor element is formed, when the other surface of the second semiconductor element and the negative electrode surface are in full contact with each other, No gap is formed for connecting the signal line to the third electrode of the second semiconductor element. In this regard, in the present invention, of the negative electrode surface of the negative electrode plate, a recess is formed in the facing portion of the third electrode formed on the other surface of the second semiconductor element, so that a signal is transmitted through the recess. The wire can be connected to the third electrode. When the recess is also formed in a part of the facing portion of the second electrode, the signal line can be connected to the second electrode through the recess.

In this case, the third electrode formed on the other surface of the first semiconductor element and the third electrode formed on the other surface of the second semiconductor element are via flexible wirings (61, 62) having flexibility. It is preferable that the device is connected to a control board (60) that outputs a signal to the third electrode. According to this, since the signal line connected to the third electrode formed on the other surface of the second semiconductor element is a flexible wiring having flexibility, the second electrode of the second semiconductor element faces the third electrode. The flexible wiring can be folded back in the recess formed in the portion. In this way, the end of the flexible wiring folded back in the recess can be reliably connected to the third electrode of the second semiconductor element. Further, for both the connection between the third electrode formed on the other surface of the first semiconductor element and the control board and the connection between the third electrode formed on the other surface of the second semiconductor element and the control board. By using flexible wiring, it is possible to eliminate the connection process such as wire bonding.

Further, the semiconductor module in which a semiconductor apparatus according to the present invention, a plurality of arm circuits connected in parallel between the positive and negative electrode plates (17a, 17b, 17c, 17d , 17e) Ru with a. Then, each of the plurality of arm circuits are, that Yusuke a first semiconductor element, and a second semiconductor element, and a conductive connection member. According to this, a large current can be taken out from the semiconductor device by taking out the current from each of a plurality of arm circuits connected in parallel between the positive and negative electrodes.

In this case, it is preferable that a plurality of arm circuits are aligned and arranged along a predetermined direction. Further, in this case, the first semiconductor element, the second semiconductor element, and the conductive connecting member each of the plurality of arm circuits may also be arranged and arranged along the predetermined direction. According to this, the semiconductor device can be compactly configured by arranging a plurality of arm circuits in an aligned manner.

The conductive connection member of the plurality of arm circuits are that Yusuke second connecting portion connecting the first connecting portion of the conductive connecting member provided in the arm circuit disposed adjacent the (514). According to this, the conductive connecting members of each arm circuit are connected by the second connecting portion. The configuration of such a conductive connecting member is such that one conductive connecting member provided so as to cross all the arm circuits along a predetermined direction is divided and assigned to each arm circuit. It can be said that. By assigning the conductive connecting member separately for each arm circuit in this way, the dimensional error of each arm circuit can be absorbed by the second connecting portion connecting between the arm circuits. Further, even if the arm circuit is thermally deformed due to thermal expansion due to heat generated by the operation of the first semiconductor element and the second semiconductor element included in the arm circuit, the deformation is connected between the arm circuits. (2) It can be absorbed by the connection part. Therefore, damage to the semiconductor device due to thermal deformation is effectively prevented, and as a result, the reliability of the semiconductor device can be improved.

Further, the semiconductor device according to the present invention may include a plurality of semiconductor modules (10A, 10B, 10C) connected in parallel between the positive electrode line and the negative electrode line. According to this, for example, by connecting each of the three semiconductor modules to the U-phase coil, V-phase coil, and W-phase coil of the three-phase DC brushless motor, the inverter circuit of the three-phase DC brushless motor is configured. Can be done.

It is a top view of the semiconductor device which concerns on this embodiment. It is a top view which shows the arrangement relation of the positive electrode plate, the negative electrode plate, and a conductive plate embedded and fixed in the bottom surface of a case. It is a top view of the arm unit. FIG. 3 is a sectional view taken along line IV-IV of FIG. It is a VV sectional view of FIG. It is a top view of the divided bus bar. It is a side view of the divided bus bar. It is a figure which shows the division piece. It is a figure which shows the terminal piece. It is a circuit diagram which shows the inverter circuit composed of the 1st semiconductor module, the 2nd semiconductor module, and the 3rd semiconductor module.

Hereinafter, the semiconductor device according to the embodiment of the present invention will be described with reference to the drawings. In this embodiment, a semiconductor device used as an inverter circuit of a three-phase DC brushless motor will be described. FIG. 1 is a plan view of the semiconductor device 1 according to the present embodiment. As shown in FIG. 1, the semiconductor device 1 includes a first semiconductor module 10A, a second semiconductor module 10B, a third semiconductor module 10C, and a case 40 accommodating these semiconductor modules.

The case 40 is made of an insulating material such as resin. Further, the case 40 includes a bottom wall 41 having a circular shape in a plan view, and a ring-shaped side wall 42 extending upward from the peripheral end of the bottom wall 41 along the central axis direction of the bottom wall 41. The tip of the side wall 42 is open. A control board or the like can be placed on this opening surface.

The first semiconductor module 10A, the second semiconductor module 10B, and the third semiconductor module 10C are arranged on the bottom wall 41 of the case 40. As can be seen from FIG. 1, the structures of the first semiconductor module 10A, the second semiconductor module 10B, and the third semiconductor module 10C are the same, and the respective semiconductor modules are arranged around the center of the bottom wall 41 at 120 ° intervals. Will be done.

The first semiconductor module 10A, the second semiconductor module 10B, and the third semiconductor module 10C have a positive electrode terminal 11, a negative electrode terminal 12, an output terminal 13, a positive electrode plate 14, a negative electrode plate 15, and a conductive plate 16, respectively. It includes an arm unit 17 composed of five arm circuits (17a, 17b, 17c, 17d, 17e).

Each of the positive electrode terminals 11, each negative electrode terminal 12, each output terminal 13, each positive electrode plate 14, each negative electrode plate 15, and each conductive plate 16 included in the respective semiconductor modules 10A, 10B, and 10C are made of a conductive metal. .. For example, copper, aluminum, molybdenum, and composite materials thereof can be exemplified. In this embodiment, they are formed of copper.

Each of the positive electrode terminals 11 included in the respective semiconductor modules 10A, 10B, and 10C has a cylindrical shape extending in a direction orthogonal to the paper surface of FIG. 1, and one end (upper end) thereof is the power supply side of the DC power supply. It is connected in parallel to the positive electrode terminal via the positive electrode line. Further, each negative electrode terminal 12 included in each of the semiconductor modules 10A, 10B, and 10C has a cylindrical shape extending in a direction orthogonal to the paper surface of FIG. 1, and one end (upper end) thereof is a DC power supply. It is connected in parallel to the negative electrode terminal on the power supply side via the negative electrode line. Here, the DC power supply is any device that has a power supply side positive electrode terminal and a power supply side negative electrode terminal and can apply a DC voltage between the power supply side positive electrode terminal and the power supply side negative electrode terminal. It may be. For example, as a DC power source, a battery, a battery, and a capacitor can be exemplified. Further, electric power smoothed by a smoothing capacitor after full-wave rectification or half-wave rectification of alternating current such as commercial alternating current, so-called intermediate DC power, can also be used as a DC power source.

Further, the other end (lower end) of the positive electrode terminal 11 is electrically connected to the positive electrode plate 14, and the other end (lower end) of the negative electrode terminal 12 is electrically connected to the negative electrode plate 15. Therefore, each of the positive electrode plates 14 included in the respective semiconductor modules 10A, 10B, 10C is electrically connected to the power supply side positive electrode terminal of the DC power supply via each positive electrode terminal 11 and the positive electrode line, and the respective semiconductor modules 10A, 10B are connected. Each of the negative electrode plates 15 included in the 10C is electrically connected to the power supply side negative electrode terminal of the DC power supply via each negative electrode terminal 12 and the negative electrode line.

Further, each output terminal 13 included in each of the semiconductor modules 10A, 10B, and 10C has a cylindrical shape extending in a direction orthogonal to the paper surface of FIG. 1 like each positive electrode terminal 11 and each negative electrode terminal 12. There is. Further, one end (upper end) of the output terminal 13 included in the first semiconductor module 10A is electrically connected to the U-phase coil of the three-phase DC brushless motor via an output line, and the output terminal included in the second semiconductor module 10B is provided. One end (upper end) of 13 is electrically connected to the V-phase coil of the three-phase DC brushless motor via an output line, and one end (upper end) of the output terminal 13 included in the third semiconductor module 10C is an output line. It is electrically connected to the W-phase coil of the 3-phase brushless motor via. Further, the other end (lower end) of each output terminal 13 included in each of the semiconductor modules 10A, 10B, 10C is connected to each conductive plate 16.

Each of the positive electrode plates 14, each negative electrode plate 15, and each conductive plate 16 included in the respective semiconductor modules 10A, 10B, and 10C are embedded and fixed in the bottom wall 41 of the case 40. FIG. 2 is a plan view showing the arrangement relationship of the positive electrode plate 14, the negative electrode plate 15, and the conductive plate 16 embedded and fixed in the bottom wall 41 of the case 40. The positive electrode plate 14 embedded in the bottom wall 41 of the case 40 is exposed from the bottom wall 41 at one end surface thereof. Similarly, the negative electrode plate 15 embedded in the bottom wall 41 of the case 40 is exposed from the bottom wall 41 at one end surface thereof, and the conductive plate 16 embedded in the bottom wall 41 of the case 40 is exposed at one end surface thereof. It is exposed from the bottom wall 41. The exposed surface of the positive electrode plate 14 constitutes the positive electrode surface 141, and the exposed surface of the negative electrode plate 15 constitutes the negative electrode surface 151. Therefore, FIG. 2 shows the positive electrode surface 141 of the positive electrode plate 14, the negative electrode surface 151 of the negative electrode plate 15, and the exposed surface 161 from the bottom wall 41 of the conductive plate 16, respectively.

As shown in FIG. 2, the positive electrode surface 141 of the positive electrode plate 14 is composed of a trapezoidal region 14a and a rectangular region 14b connected to the lower bottom of the trapezoidal region 14a. The other end of the positive electrode terminal 11 is connected to the trapezoidal region 14a. The negative electrode surface 151 of the negative electrode plate 15 is also composed of a trapezoidal region 15a and a rectangular region 15b connected to the lower bottom of the trapezoidal region 15a. The other end of the negative electrode terminal 12 is connected to the trapezoidal region 15a.

Further, in the positive electrode plate 14 and the negative electrode plate 15, the end side 142 of the rectangular region 14b of the positive electrode surface 141 and the end side 152 of the rectangular region 15b of the negative electrode surface 151 face each other with a certain minute distance α. It is embedded in the bottom wall 41 of the case 40. The minute distance α between the end side 142 and the end side 152 corresponds to the distance between the positive electrode plate 14 and the negative electrode plate 15. The smaller the minute distance α is, the better. For example, the minute distance α can be set to 0.05 mm to 1.0 mm. In this way, the positive electrode plate 14 and the negative electrode plate 15 are arranged adjacent to each other (closely arranged) with a minute distance α in a state of being embedded in the bottom wall 41 of the case 40.

Here, for convenience of explanation, the left-right direction in the plan view of FIG. 2 is defined as the X direction, the right side is defined as the X1 direction, and the left side is defined as the X2 direction. Further, the vertical direction (that is, the direction orthogonal to the X direction) in the plan view of FIG. 2 is defined as the Y direction. Further, the direction orthogonal to the X direction and the Y direction, that is, the vertical vertical direction is defined as the Z direction. When the direction is defined in this way, as can be seen from FIG. 2, the minute distance α represents the distance between the positive electrode plate 14 and the negative electrode plate 15 in the Y direction. Further, the positive electrode plate 14 and the negative electrode plate 15 are arranged adjacent to each other with the rectangular regions 14b and 15b facing each other and separated by a minute distance α along the Y direction.

Further, the positive electrode surface 141 of the positive electrode plate 14 and the negative electrode surface 151 of the negative electrode plate 15 are formed in line symmetry with respect to a straight line L passing through an intermediate point of a minute distance α in the Y direction and along the X direction. Further, the exposed surface 161 of the conductive plate 16 is formed in a region on the X1 direction side of the positive electrode surface 141 of the positive electrode plate 14 and the negative electrode surface 151 of the negative electrode plate 15 and in a region through which the straight line L passes.

Further, the first transistor 171 provided in each of the five arm circuits described later is connected to the rectangular region 14b of the positive electrode surface 141 of the positive electrode plate 14, and the rectangular region 15b of the negative electrode surface 151 of the negative electrode plate 15 will be described later. A second transistor 172 included in each of the five arm circuits is connected. As can be seen from FIG. 2, the first transistor 171 included in each of the five arm circuits is connected to the rectangular region 14b of the positive electrode surface 141 so as to be aligned linearly along the X direction. Similarly, the second transistor 172 included in each of the five arm circuits is also connected to the rectangular region 15b of the negative electrode surface 151 so as to be linearly aligned along the X direction.

Next, the arm unit 17 will be described. FIG. 3 is a plan view of the arm unit 17. In FIG. 3, the left-right direction is the X direction, the right side is the X1 direction, the left side is the X2 direction, and the vertical direction is the Y direction. As described above, the arm unit 17 is composed of five arm circuits (first arm circuit 17a, second arm circuit 17b, third arm circuit 17c, fourth arm circuit 17d, fifth arm circuit 17e). .. As can be seen from FIG. 3, each arm circuit is arranged so as to be aligned along the X direction. Specifically, the first arm circuit 17a, the second arm circuit 17b, the third arm circuit 17c, the fourth arm circuit 17d, and the fifth arm circuit 17e are arranged in this order in the X1 direction. .. The configuration of each arm circuit is basically the same. Typically, the configuration of the first arm circuit 17a will be described.

FIG. 4 is a sectional view taken along line IV-IV of FIG. 3, showing a sectional view of the first arm circuit 17a along the Y direction. The horizontal direction in FIG. 4 is the Y direction, and the vertical direction is the Z direction (vertical direction). Further, of the Z directions, the upward direction is defined as the Z1 direction, and the downward direction is defined as the Z2 direction. As shown in FIG. 4, the first arm circuit 17a includes a first transistor 171 and a second transistor 172, and a first division piece 51a of the division bus bar 50 described later. The first transistor 171 corresponds to the first semiconductor element of the present invention, and the second transistor 172 corresponds to the second semiconductor element of the present invention.

The first transistor 171 and the second transistor 172 are N-channel type power MOSFETs in this embodiment. The first transistor 171 has a thin plate shape, and one surface 171a and the other surface 171b facing the opposite side to the one surface 171a are formed along the plate thickness direction. The drain electrode D is formed on one surface 171a, and the source electrode S and the gate electrode G are formed on the other surface 171b. Similarly, the second transistor 172 also has a thin plate shape, and one surface 172a and the other surface 172b facing the opposite side to the one surface 172a are formed along the plate thickness direction. The drain electrode D is formed on one surface 172a, and the source electrode S and the gate electrode G are formed on the other surface 172b.

The first transistor 171 is arranged on the rectangular region 14b of the positive electrode surface 141 of the positive electrode plate 14 embedded in the bottom wall 41 of the case 40, and is bonded to the positive electrode plate 14 via a bonding material 191 such as solder. .. In this case, one surface 171a of the first transistor 171, that is, the surface on which the drain electrode D is formed is arranged to face the rectangular region 14b of the positive electrode surface 141 of the positive electrode plate 14, and the first transistor 171 is the positive electrode plate. It is joined to 14.

The second transistor 172 is arranged on the rectangular region 15b of the negative electrode surface 151 of the negative electrode plate 15 embedded in the bottom wall 41 of the case 40, and is bonded to the negative electrode plate 15 via a bonding material 192 such as solder. .. In this case, the other surface 172b of the second transistor 172, that is, the surface on which the source electrode S and the gate electrode G are formed, is arranged facing the rectangular region 15b of the negative electrode surface 151 of the negative electrode plate 15, and the second transistor is arranged. 172 is joined to the negative electrode plate 15.

As shown in FIG. 4, since both the positive electrode surface 141 of the positive electrode plate 14 and the negative electrode surface 151 of the negative electrode plate 15 are exposed surfaces from the bottom portion 41, they are in the same plane as the bottom surface (surface) of the bottom wall 41, that is, They are formed in the same plane and face the same direction. In FIG. 4, the positive electrode surface 141 of the positive electrode plate 14 and the negative electrode surface 151 of the negative electrode plate 15 face in the Z1 direction (upward direction). One surface (for example, the surface on which the drain electrode D is formed) is arranged to face one of the electrode surfaces (for example, the positive electrode surface 141 of the positive electrode plate 14) of the two electrode surfaces (141, 151) facing the same direction. One transistor (for example, the first transistor 171) is arranged in the other, and the other electrode surface (for example, the negative electrode surface 151 of the negative electrode plate 15) has the other surface (for example, the surface on which the source electrode S and the gate electrode G are formed). The other electrode (for example, the second electrode 172) is arranged so that the two electrodes face each other. That is, the two transistors (171 and 172) are arranged on the respective electrode plates (positive electrode plate 14 and negative electrode plate 15) so as to face each other in opposite directions. In other words, both transistors are arranged in a state where the other transistor is inverted with respect to one transistor. Therefore, the orientation of the surface (one surface 171a) on which the drain electrode D of the first transistor 171 is formed and the orientation of the surface (the other surface 172b) on which the source electrode S and the gate electrode G of the second transistor 172 are formed are different. The same direction, that is, downward (Z2 direction). Further, the orientation of the surface (the other surface 171b) on which the source electrode S and the gate electrode G of the first transistor 171 are formed is the same as the orientation of the surface (one surface 172a) on which the drain electrode D of the second transistor 172 is formed. The direction, that is, the upward direction (Z1 direction direction).

As can be seen from FIG. 4, the first transistor 171 and the second transistor 172 are electrically connected via the first partition piece 51a. As described above, the first divided piece 51a constitutes a part of the divided bus bar 50 which is a lead frame. Here, the divided bus bar 50 will be described.

FIG. 6 is a plan view of the divided bus bar 50, and FIG. 7 is a side view of the divided bus bar 50. In FIGS. 6 and 7, the left-right direction is the X direction, the right side is the X1 direction, and the left side is the X2 direction. Further, the vertical direction in FIG. 6 is the Y direction. Further, the vertical direction in FIG. 7 is the Z direction, the upper side is the Z1 direction, and the lower side is the Z2 direction. As shown in FIGS. 6 and 7, the divided bus bar 50 includes four divided pieces (first divided piece 51a, second divided piece 51b, third divided piece 51c, fourth divided piece 51d) and one. It has a terminal piece 52 and is configured by connecting these. The shape of each divided piece is the same. Each divided piece is generically called a divided piece 51. The split piece 51 and the terminal piece 52 correspond to the conductive connecting member of the present invention.

8A and 8B are views showing the divided pieces 51, FIG. 8A is a plan view of the divided pieces 51, and FIG. 8B is a side view of the divided pieces 51. 9A and 9B are views showing the terminal piece 52, FIG. 9A is a plan view of the terminal piece 52, and FIG. 9B is a side view of the terminal piece 52. The orientation of the split piece 51 shown in FIG. 8A and the orientation of the terminal piece 52 shown in FIG. 9A coincide with the orientation of the split piece 51 and the terminal piece 52 shown in FIG. The orientation of the divided piece 51 shown and the orientation of the terminal piece 52 shown in FIG. 9B coincide with the orientation of the divided piece 51 and the terminal piece 52 shown in FIG. 7. That is, the left-right direction of FIGS. 8A and 9A is the X direction, the right side is the X1 direction, the left side is the X2 direction, and the vertical direction is the Y direction. Further, the left-right direction of FIGS. 8 (b) and 9 (b) is the X direction, the right side is the X1 direction, the left side is the X2 direction, the vertical direction is the Z direction, the upper side is the Z1 direction, and the lower side is the Z2 direction. is there.

As is well shown in FIG. 8A, the divided piece 51 has a first joint portion 511, a second joint portion 512, an in-arm connection portion 513, and an arm-to-arm connection portion 514, and has elastic modulus such as copper. It is composed of a conductive metal with a high coefficient. Further, as shown well in FIG. 9A, the terminal piece 52 has a first joint portion 521, a second joint portion 522, an in-arm connection portion 523, and a terminal connection portion 524, and is made of copper or the like. It is composed of a conductive metal with a high elastic modulus. The in-arm connection portion 513 and 523 correspond to the first connection portion of the present invention, and the inter-arm connection portion 523 corresponds to the second connection portion of the present invention.

FIG. 4 shows a cross section of the first divided piece 51a as the divided piece 51. The divided piece 51 extends in the Y direction when viewed from the cross-sectional direction (X direction) shown in FIG. Further, an upwardly convex (convex in the Z1 direction) convex portion is formed at the central portion of the divided piece 51 in the Y direction. The portion extending to the left in the Y direction of FIG. 4 from the lower left end of the convex portion constitutes the first joint portion 511, and the portion extending to the right in the Y direction of FIG. 4 from the lower right end of the convex portion constitutes the second joint. The portion 512 is formed, and the convex portion constitutes the in-arm connecting portion 513. Therefore, the first joint portion 511, the in-arm connection portion 513, and the second joint portion 512 are formed in this order along the Y direction.

Further, as can be seen from FIG. 8A, the arm-to-arm connection portion 514 extends in the X1 direction from the in-arm connection portion 513. Further, as can be seen from FIG. 8B, an inclined portion 515 is formed between the in-arm connection portion 513 and the arm-to-arm connection portion 514. The inclined portion 515 is configured to be inclined obliquely upward as it goes from the in-arm connecting portion 513 to the inter-arm connecting portion 514 along the X direction. Then, the upper side portion of the convex in-arm connection portion 513 is connected to the lower end (left end) of the inclined portion 515, and the arm-to-arm connection portion 514 is connected to the upper end (right end) of the inclined portion 515. .. Therefore, the vertical position (Z direction position) of the arm-to-arm connection portion 514 when the divided piece 51 is viewed from the side surface is higher than the vertical position of the upper side portion of the arm-in-arm connecting portion 513. Specifically, the vertical position (Z direction position) of the lower surface 514a of the arm-to-arm connection portion 514 is substantially equal to the vertical position of the upper surface 513b of the in-arm connection portion 513.

As shown in FIG. 6, in the four divided pieces 51 having the above structure, each first joint portion 511 is arranged on a straight line along the X direction, and each second joint portion 512 is X. They are aligned so that they are arranged on a straight line along the direction. At this time, as shown in FIG. 7, the arm-to-arm connection portion 514 of the first division piece 51a is overlapped directly above the in-arm connection portion 513 of the second division piece 51b, and the arm-to-arm connection portion 514 of the second division piece 51b is overlapped. Is overlapped directly above the in-arm connection portion 513 of the third division piece 51c, and the inter-arm connection portion 514 of the third division piece 51c is overlapped directly above the in-arm connection portion 513 of the fourth division piece 51d. The four partition pieces 51 are aligned along the X direction. Then, the arm-to-arm connection portion 514 of one divided piece 51 and the in-arm connecting portion 513 of the other divided piece 51 are joined by a joining member such as solder. In this way, the four divided pieces 51 are connected. Further, of the four divided pieces 51 connected, the terminal piece 52 is connected to the arm-to-arm connection portion 514 of the fourth divided piece 51d.

The shapes of the first joint portion 521, the second joint portion 522, and the in-arm connection portion 523 of the terminal piece 52 are the first joint portion 511, the second joint portion 512, and the in-arm connection portion 513 of the divided piece 51, respectively. It is almost the same as the shape of. That is, the terminal piece 52 extends in the Y direction when viewed from the X direction, like the divided piece 51 shown in FIG. 4, and an upwardly convex convex portion is formed in the central portion thereof. This convex portion constitutes the in-arm connection portion 523, the first joint portion 521 extends to the left from the left lower end of the in-arm connection portion 523, and the second joint portion 522 extends from the right lower end of the in-arm connection portion 523. Is extended to the right. Further, as shown in FIG. 9A, the terminal connection portion 524 of the terminal piece 52 extends from the in-arm connection portion 523 in the X1 direction. Further, as can be seen from FIG. 9B, a vertical portion 525 is formed between the in-arm connection portion 523 and the terminal connection portion 524. The vertical portion 525 extends in the vertical direction (Z direction), and the upper end portion of the convex in-arm connection portion 523 is connected to the upper end thereof, and the terminal connection portion 524 is connected to the lower end portion thereof. Therefore, the vertical position (Z direction position) of the terminal connecting portion 524 when the terminal piece 52 is viewed from the side surface is lower than the vertical position of the upper side portion of the connecting portion 513 in the arm. The vertical position (Z direction position) of the lower surface 524a of the terminal connection portion 524 is equal to the vertical position of the lower surface 521a (and the lower surface of the second joint portion 522) of the first joint portion 521.

The terminal pieces 52 are aligned with the four divided pieces 51 connected as shown in FIG. At this time, the terminal piece 52 has the first joint portion 521 arranged on a straight line along the X direction together with the first joint portion 511 of the four divided pieces 51 connected, and the second joint portion 522 , Together with the second joint 512 of the four connected pieces 51, are arranged with respect to the four connected pieces 51 so as to be arranged on a straight line along the X direction. Further, as shown in FIG. 7, the in-arm connection portion 523 of the terminal piece 52 is connected to the four division pieces 51 so as to be overlapped directly under the arm-to-arm connection portion 514 of the fourth division piece 51d. It is arranged against. Then, the in-arm connection portion 523 of the terminal piece 52 and the arm-to-arm connection portion 514 of the fourth divided piece 51d arranged immediately above the terminal piece 52 are joined via a joining material such as solder. In this way, the in-arm connection portion 523 of the terminal piece 52 is connected to the fourth division piece 51d.

In the divided bus bar 50 having the above configuration, as shown in FIG. 6, the first divided piece 51a, the second divided piece 51b, the third divided piece 51c, the fourth divided piece 51d, and the terminal piece 52 are arranged along the X direction. It is configured to be aligned in a row. Then, as shown in FIG. 3, the divided bus bar 50 has the connecting directions of the divided pieces 51 and the terminal pieces 52 (that is, the alignment directions of the divided pieces 51 and the terminal pieces 52) coincident with the X direction and the X direction. It is arranged in the case 40 so as to cross the five arm circuits (17a, 17b, 17c, 17d, 17e) aligned with the above. By disposing the split bus bar 50 for the five arm circuits in this way, the first split piece 51a is assigned to the first arm circuit 17a, and the second split piece 51b is assigned to the second arm circuit 17b. The third division piece 51c is assigned to the third arm circuit 17c, the fourth division piece 51d is assigned to the fourth arm circuit 17d, and the terminal piece 52 is assigned to the fifth arm circuit 17e.

As shown in FIG. 4, the source electrode S and the gate electrode G of the first transistor 171 are formed in the first junction 511 of the partition piece 51 (first partition piece 51a) assigned to the first arm circuit 17a. It faces the other surface 171b, which is a surface, and the second junction 512 of the divided piece 51 faces the one surface 172a, which is the surface on which the drain electrode D of the second transistor 172 is formed. Then, the first joint portion 511 of the divided pieces 51 arranged facing each other and the other surface 171b of the first transistor 171 are joined via a bonding material 193 such as solder, and the second joint portion 512 of the divided pieces 51 arranged facing each other is joined. One side 172a of the second transistor 172 is joined via a bonding material 194 such as solder.

The connection configuration of the dividing piece 51 and the terminal piece 52 assigned to the second to fifth arm circuits and the first transistor 171 and the second transistor 172 is the same as described above.

FIG. 5 is a sectional view taken along line VV of FIG. 3, showing a sectional view of the divided bus bar 50 along the Y direction. As shown in FIG. 5, the inter-arm connection portion 514 of the first partition piece 51a assigned to the first arm circuit 17a is connected to the in-arm connection portion 513 of the second partition piece 51b assigned to the second arm circuit 17b. Be connected. Further, the arm-to-arm connection portion 514 of the second division piece 51b assigned to the second arm circuit 17b is connected to the in-arm connection portion 513 of the third division piece 51c assigned to the third arm circuit 17c. Further, the arm-to-arm connection portion 514 of the third division piece 51c assigned to the third arm circuit 17c is connected to the in-arm connection portion 513 of the fourth division piece 51d assigned to the fourth arm circuit 17d. Then, the arm-to-arm connection portion 514 of the fourth division piece 51d assigned to the fourth arm circuit 17d is connected to the in-arm connection portion 523 of the terminal piece 52 assigned to the fifth arm circuit 17e. Further, the terminal connection portion 524 of the terminal piece 52 assigned to the fifth arm circuit 17e is connected to the exposed surface 161 of the conductive plate 16 embedded in the bottom wall 41 of the case 40. The output terminal 13 is connected to the conductive plate 16 as described above. Therefore, the divided bus bar 50 is connected to the output terminal 13 via the conductive plate 16.

Further, as shown in FIG. 4, a first junction portion is formed in a part of the other surface 171b of the first transistor 171 where the gate electrode G is formed and the part where the source electrode S is formed. 511 (521) is not joined. Then, one end of the flexible wiring 61, which is a flexible electric wire, is connected to the portion of the other surface 171b of the first transistor 171 where the gate electrode G is formed, and the other surface 171b of the first transistor 171 is connected. One end of the flexible wiring 63, which is a flexible electric wire, is connected to the portion where the source electrode S is formed. Further, one end of the flexible wiring 62, which is a flexible electric wire, is also connected to the portion of the other surface 172b of the second transistor 172 where the gate electrode G is formed, and the other surface 172b of the second transistor 172 is connected. One end of the flexible wiring 64, which is a flexible electric wire, is also connected to the portion of which the source electrode S is formed. Here, the other surface 172b of the second transistor 172 is a downward surface, and when the entire surface thereof is in face-to-face contact with the negative electrode surface 151 of the negative electrode plate 15, the flexible wirings 62 and 64 are connected to the other surface of the second transistor 172. Cannot connect to 172b. Regarding this point, in the present embodiment, the internal space of the case 40 is located in the portion of the negative electrode surface 151 of the negative electrode plate 15 facing the gate electrode G and the source electrode S formed on the other surface 172b of the second transistor 172. A recess 152 is formed so as to communicate with the second transistor 172, and one end of the flexible wirings 62 and 64 is connected to the other surface 172b (lower surface) of the second transistor 172 via the recess 152. Here, since the flexible wirings 62 and 64 have flexibility, by folding back the flexible wirings 62 and 64 in the recess 152 as shown in FIG. 4, one end of the flexible wirings 62 and 64 is surely seconded. It can be connected to the gate electrode G and the source electrode S formed on the other surface 172b of the transistor 172. The other end of the flexible wiring 61, 62, 63, 64 is connected to a control board (not shown).

FIG. 10 is a circuit diagram showing an inverter circuit including the first semiconductor module 10A, the second semiconductor module 10B, and the third semiconductor module 10C having the above configuration. As shown in FIG. 10, the positive electrode terminals 11 of the semiconductor modules 10A, 10B, and 10C are connected in parallel to the positive electrode line P connected to the power supply side positive electrode terminal VP of the DC power supply V, and each semiconductor module 10A, The negative electrode terminals 12 of 10B and 10C are connected in parallel to the negative electrode line N connected to the power supply side negative electrode terminal VN of the DC power supply V. Therefore, the semiconductor device 1 (inverter circuit) according to the present embodiment includes a positive electrode line P connected to the power supply side positive electrode terminal VP of the DC power supply V and a negative electrode line N connected to the power supply side negative electrode terminal VN of the DC power supply V. It is a semiconductor device including a plurality of semiconductor modules (first semiconductor module 10A, second semiconductor module 10B, third semiconductor module 10C) connected in parallel between the two.

Further, the five arm circuits (first arm circuit 17a, second arm circuit 17b, third arm circuit 17c, fourth arm circuit 17d, fifth arm circuit 17e) included in each semiconductor module 10A, 10B, 10C are The positive electrode plate 14 connected to the positive electrode terminal 11 and the negative electrode plate 15 connected to the negative electrode terminal 12 are connected in parallel. Further, the dividing piece 51 and the terminal piece 52 assigned to the five arm circuits connected in parallel are connected in series to the conductive plate 16 connected to the output terminal 13. Then, the output terminal 13 of the first semiconductor module 10A is connected to the U-phase coil of the three-phase DC brushless motor M via the first output line 71, and the output terminal 13 of the second semiconductor module 10B is connected to the second output line. It is connected to the V-phase coil of the 3-phase DC brushless motor M via 72, and the output terminal 13 of the third semiconductor module 10C is connected to the W-phase coil of the 3-phase DC brushless motor M via the third output line 73. To.

The five first transistors 171 and the five second transistors 172 provided in the semiconductor modules 10A, 10B, and 10C, respectively, function as switching elements. In this case, when a signal is input from the control board 60 to the gate electrodes G of the transistors 171 and 172 in a predetermined pattern, the transistors 171 and 172 are switched. Further, in the present embodiment, the five first transistors 171 included in the semiconductor modules 10A, 10B, and 10C each operate at the same time. That is, the ON operation and the OFF operation of the five first transistors 171 are all performed at the same timing. Similarly, the five second transistors 172 included in each of the semiconductor modules 10A, 10B, and 10C operate at the same time. That is, the ON operation and the OFF operation of the five second transistors 172 are all performed at the same timing.

In the inverter circuit shown in FIG. 10, for example, when the first transistor 171 of the first semiconductor module 10A and the second transistor 172 of the third semiconductor module 10C are turned on and the other transistors are turned off, the inside of the inverter circuit The current flows as follows. That is, the current from the positive electrode line P flows in this order to the positive electrode terminal 11, the positive electrode plate 14, the first transistor 171 and the split bus bar 50, the conductive plate 16, and the output terminal 13 of the first semiconductor module 10A. Then, a current is supplied from the output terminal 13 of the first semiconductor module 10A to the U-phase coil of the three-phase DC brushless motor M via the first output line 71. Further, the current from the W-phase coil of the three-phase DC brushless motor M flows to the output terminal 13 of the third semiconductor module 10C via the third output line 73, and further, the conductive plate 16 of the third semiconductor module 10C, The current flows through the split bus bar 50, the second transistor 172, the negative electrode plate 15, and the negative electrode terminal 12 in this order. Then, a current flows from the negative electrode terminal 12 of the third semiconductor module 10C to the negative electrode line N.

Further, for example, when the first transistor 171 of the second semiconductor module 10B and the second transistor 172 of the first semiconductor module 10A are turned on and the other transistors are turned off, the current in the inverter circuit is as follows. Flow like. That is, the current from the positive electrode line P flows in this order to the positive electrode terminal 11, the positive electrode plate 14, the first transistor 171 and the split bus bar 50, the conductive plate 16, and the output terminal 13 of the second semiconductor module 10B. Then, a current is supplied from the output terminal 13 of the second semiconductor module 10B to the V-phase coil of the three-phase DC brushless motor M via the second output line 72. Further, the current from the U-phase coil of the three-phase DC brushless motor M flows to the output terminal 13 of the first semiconductor module 10A via the first output line 71, and further, the conductive plate 16 of the first semiconductor module 10A, The current flows through the split bus bar 50, the second transistor 172, the negative electrode plate 15, and the negative electrode terminal 12 in this order. Then, a current flows from the negative electrode terminal 12 of the first semiconductor module 10A to the negative electrode line N.

As in the above example, when the first transistor 171 of each semiconductor module 10A, 10B, 10C is turned on, a current flows from the positive electrode plate 14 to the first transistor 171. On the other hand, when the second transistor 172 of each semiconductor module 10A, 10B, 10C is turned on, a current flows from the second transistor 172 to the negative electrode plate 15. When the flow of these currents is shown in FIG. 4, the direction of the current flowing through the positive electrode plate 14 is upward (Z1 direction) as shown by arrow A, and the direction of the current flowing through the negative electrode plate 15 is shown by arrow B. Downward (Z2 direction). That is, the direction of the current flowing through the positive electrode plate 14 and the direction of the current flowing through the negative electrode plate 15 are opposite.

Mutual inductance increases when members in which currents flow in opposite directions are placed close to each other. Therefore, the inductances cancel each other out, and the parasitic inductance can be reduced. According to this embodiment, the positive electrode surface 141 of the positive electrode plate 14 (the surface connected to one surface 171a of the first transistor 171) and the negative electrode surface 151 of the negative electrode plate 15 (the other surface 172b of the second transistor 172) are connected. By making the surface) in the same direction, it is realized that the positive electrode plate 14 and the negative electrode plate 15 in which the current flows in opposite directions are arranged side by side in parallel. Therefore, the distance (minute distance α) between the positive electrode plate 14 and the negative electrode plate 15 arranged adjacent to each other can be made as small as possible. As a result, the parasitic inductance of the positive electrode plate 14 and the negative electrode plate 15 can be reduced.

Further, the positive electrode surface 141 of the positive electrode plate 14 (the surface connected to one surface 171a of the first transistor 171) and the negative electrode surface 151 of the negative electrode plate 15 (the surface connected to the other surface 172b of the second transistor 172) are formed. In order to have the same orientation, the orientation of the first transistor 171 and the orientation of the second transistor 172 are reversed. As a result, the other surface 171b of the first transistor 171 and the one surface 172a of the second transistor 172 are oriented in the same direction (upward). Therefore, the other surface 171b of the first transistor 171 and the one surface 172a of the second transistor 172 can be linearly connected, and therefore, the other surface 171b of the first transistor 171 and one 172a of the second transistor 172 can be connected. The length of the connecting portion (connecting portion 513, 524 in the arm) to be connected can be shortened. As a result, the parasitic inductance of the connection portion can be reduced.

As described above, the semiconductor device 1 according to the present embodiment has a positive electrode line P connected to the power supply side positive electrode terminal VP of the DC power supply V and a negative electrode line N connected to the power supply side negative electrode terminal VN of the DC power supply V. It is a semiconductor device including semiconductor modules (10A, 10B, 10C) connected between them. Further, the semiconductor modules (10A, 10B, 10C) are electrically connected to the positive electrode plate 14, the negative electrode plate 15, the first transistor 171 as the first semiconductor element, and the second transistor 172 as the second semiconductor element. A split piece 51 or a terminal piece 52 of the split bus bar 50 as a member is provided. The positive electrode plate 14 is made of a conductive metal and is electrically connected to the power supply side positive electrode terminal VP of the DC power supply V via the positive electrode terminal 11. A positive electrode surface 141 facing a predetermined direction (Z1 direction) is formed on the positive electrode plate 14. The negative electrode plate 15 is made of a conductive metal and is electrically connected to the power supply side negative electrode terminal VN of the DC power supply V via the negative electrode terminal 12. The negative electrode plate 15 is formed with a negative electrode surface 151 facing in the same direction as the positive electrode surface 141. The positive electrode plate 14 and the negative electrode plate 15 are arranged in parallel and adjacent to each other in a state of facing each other. The first transistor 171 is a surface facing the one side 171a on which the first electrode (drain electrode D) is formed and the side opposite to the one side 171a on which the second electrode (source electrode S) is formed. It has a direction 171b, and one surface 171a is joined to the positive electrode plate 14 in a state of being arranged facing the positive electrode surface 141. The second transistor 172 is a surface facing the one side 172a on which the first electrode (drain electrode D) is formed and the side opposite to the one side 172a on which the second electrode (source electrode S) is formed. It has a direction 172b and is joined to the negative electrode plate 15 in a state where the other direction 172b is arranged facing the negative electrode surface 151. Further, the divided piece 51 or the terminal piece 52 of the divided bus bar 50 is an in-arm connection portion (513) that electrically connects the other surface 171b of the first transistor 171 and the one surface 172a of the second transistor 172 facing the same direction. .523).

According to the semiconductor device 1 according to the present embodiment, since the directions of the first transistor 171 and the second transistor 172 are opposite to each other, they are face-to-face connected to one surface 171a of the first transistor 171 on which the drain electrode D is formed. The orientation of the positive electrode surface 141 of the positive electrode plate 14 and the orientation of the negative electrode surface 151 of the negative electrode plate 15 which is face-to-face connected to the other surface 172b of the second transistor 172 on which the source electrode is formed can be matched. By aligning the orientation of the positive electrode surface 141 and the orientation of the negative electrode surface 151 in this way, the positive electrode plate 14 and the negative electrode plate 15 can be arranged side by side. Therefore, the distance between the positive electrode plate 14 and the negative electrode plate 15 (small distance α) can be set short, and as a result, the parasitic inductance of the positive electrode plate 14 and the negative electrode plate 15 can be reduced.

Further, by inverting the arrangement of the first transistor 171 and the second transistor 172, the orientation of the other surface 171b of the first transistor 171 on which the source electrode S is formed and the orientation of the second transistor 172 on which the drain electrode D is formed are formed. On the other hand, the orientation of the surface 172a can be matched. Therefore, the length of the in-arm connection portion (513, 523) connecting these surfaces (the other surface 171b of the first transistor 171 and the one surface 172a of the second transistor 172) can be set short, and as a result, the length can be set short. The parasitic inductance of the in-arm connection (513, 523) can also be reduced.

Further, the positive electrode plate 14, the negative electrode plate 15, and the in-arm connection portion (513, 523) are members constituting the semiconductor module. Therefore, according to this embodiment, the parasitic inductance in the semiconductor module can be reduced. Further, the parasitic inductance is reduced without adding a capacitor for reducing the parasitic inductance as in Patent Document 3, for example. That is, it is possible to reduce the parasitic inductance in the semiconductor module while suppressing the increase in cost.

Further, in the present embodiment, both the positive electrode surface 141 of the positive electrode plate 14 and the negative electrode surface 151 of the negative electrode plate 15 are surfaces exposed on the bottom wall 41 of the case 40, and these surfaces are the bottom walls of the case 40. It is formed in the same plane as the bottom surface of 41. By forming the positive electrode surface 141 and the negative electrode surface 151 on the same surface in this way, the region where the positive electrode plate 14 and the negative electrode plate 15 are arranged adjacent to each other (the region where the positive electrode plate 14 and the negative electrode plate 15 are arranged adjacent to each other) becomes the largest. Therefore, the parasitic inductance of the positive electrode plate and the negative electrode plate can be further reduced.

Further, since the positive electrode plate 14 and the negative electrode plate 15 can be arranged next to each other, even when a thick copper substrate is used for them in order to improve heat dissipation, the thickness only increases in one direction. On the other hand, when the positive electrode plate 14 and the negative electrode plate 15 are arranged so as to sandwich the first transistor 171 and the second transistor 172, if a thick copper substrate is used for these, the thickness increases in one direction and the opposite direction. To do. From this, according to the present embodiment, the semiconductor device 1 can be compactly configured even when the positive electrode plate 14 and the negative electrode plate 15 are made of a thick copper substrate to improve heat dissipation.

Further, according to the present embodiment, the other surface 172b of the second transistor 172 on which the gate electrode G and the source electrode S are formed is in face-to-face contact with the negative electrode surface 151 of the negative electrode plate 15, but of the negative electrode surfaces 151. A recess 152 is formed in a part of the facing portion of the gate electrode G and the source electrode S formed on the other surface 172b of the second transistor 172. Therefore, the signal line can be connected to the gate electrode G and the source electrode S of the second transistor 172 via the recess 152.

Further, the gate electrode G formed on the other surface 171b of the first transistor 171 and the gate electrode G formed on the other surface 172b of the second transistor 172 are gated via flexible wirings 61 and 62 having flexibility. Each is connected to a control board 60 that outputs a signal to the electrode G. Further, the source electrode S formed on the other surface 171b of the first transistor 171 and the source electrode S formed on the other surface 172b of the second transistor 172 are also controlled via the flexible wirings 63 and 64 having flexibility. Each is connected to the substrate 60. According to this, since the signal lines connected to the gate electrode G and the source electrode S formed on the other surface 172b of the second transistor 172 are the flexible wirings 62 and 64 having flexibility, the second transistor 172 The flexible wirings 62 and 64 can be folded back in the recess 152 formed in the facing portion of the gate electrode G and the source electrode S. In this way, one end of the flexible wirings 62 and 64 folded back in the recess 152 can be reliably connected to the gate electrode G and the source electrode S of the second transistor 172. Further, the connection between the gate electrode G and the control board 60 formed on the other surface 171b of the first transistor 171 and the other surface 172b of the second transistor 172, respectively, and the other surface 171b and the second transistor 172 of the first transistor 171. By using flexible wiring for connecting the source electrode S formed on the other surface 172b and the control substrate 60, a connection step such as wire bonding can be eliminated.

Further, the semiconductor modules (10A, 10B, 10C) included in the semiconductor device 1 according to the present embodiment have a plurality of arm circuits (17a, 17b, 17c, 17d) connected in parallel between the positive electrode plate 14 and the negative electrode plate 15. , 17e). Each of the plurality of arm circuits has a first transistor 171 and a second transistor 172, and a division piece 51 or a terminal piece 52 of the division bus bar 50 as a conductive connecting member. According to this, a large current can be taken out from the semiconductor device 1 by taking out the current from each of the plurality of arm circuits connected in parallel.

Further, the flexible wirings 61 and 63 are attached to the gate electrode G and the source electrode S of the first transistor 171 of each of the plurality of arm circuits constituting the arm unit 17, and the flexible wirings 62 and 64 constitute the arm unit 17. It is attached to the gate electrode G and the source electrode S of the second transistor 172 of each of the plurality of arm circuits. In this case, by arranging the flexible wiring 61 and the flexible wiring 63, and the flexible wiring 62 and the flexible wiring 64 in parallel with each other in each arm circuit, the parasitic inductance in these signal wirings can be reduced. As a result, the generation of surge voltage in the signal wiring can be suppressed. Further, according to this configuration, it is not necessary to provide the case 40 with external connection terminals connected to the gate electrode G and the source electrode S, and the signal wiring is directly taken out of the case by the flexible wirings 61, 62, 63, 64. be able to.

Further, in the plurality of arm circuits, the first transistor 171 included in each of them is linearly arranged along the X direction as shown in FIG. 2, and the second transistor 172 included in each of them is shown in FIG. It is aligned along a predetermined direction (X direction) so as to be aligned linearly along the X direction as shown. The semiconductor device 1 can be compactly configured by arranging the plurality of arm circuits in an aligned manner.

Further, among the plurality of arm circuits, the divided pieces 51 as conductive connecting members included in the first arm circuit 17a, the second arm circuit 17b, the third arm circuit 17c, and the fourth arm circuit 17d are arm circuits arranged adjacent to each other. It has an arm-to-arm connection portion 514 as a second connection portion to be connected to the in-arm connection portion 513 of the split piece 51 or the in-arm connection portion 523 of the terminal piece 52. It can be said that such a configuration is a configuration in which a conductive connecting member (lead frame) common to all arm circuits is divided and assigned to each arm circuit. By assigning the conductive connecting member separately for each arm circuit in this way, the dimensional error of each arm circuit can be absorbed by the arm-to-arm connecting portion 514 connecting between the arm circuits. Further, even when the split bus bar 50 is thermally deformed so as to warp in the X direction due to thermal expansion due to heat generated by the operation of the first transistor 171 and the second transistor 172 included in the arm circuit, for example. , The deformation can be absorbed by the arm-to-arm connection portion 514 that connects the arm circuits. Therefore, damage to the semiconductor device 1 due to thermal deformation is effectively prevented, and as a result, the reliability of the semiconductor device 1 can be improved. In addition, the electrode plates (positive electrode plate 14, negative electrode plate 15), semiconductor elements (first transistor 171 and second transistor 172), and lead frame (divided bus bar 50) can be joined by a single reflow step.

Further, since a plurality of arm circuits (17a, 17b, 17c, 17d, 17e) provided in each of the semiconductor modules 10A, 10B, and 10C are aligned and arranged along a predetermined direction (X direction), the arms are arranged between the arms. The length of the connecting portion 514 can also be shortened. As a result, the parasitic inductance of the arm-to-arm connection portion 514 can be reduced.

Further, as can be seen from FIG. 4, the in-arm connection portion (513, 523) of the divided piece 51 or the terminal piece 52 constituting the divided bus bar 50 has an upwardly convex convex shape in FIG. Therefore, the distance between the in-arm connection portion (513,523) and the positive electrode plate 14 and the distance between the in-arm connection portion (513,523) and the negative electrode plate 15 can be increased. Therefore, due to the small distance between them, a short circuit between the split piece 51 and the positive and negative electrodes and a short circuit between the terminal piece 52 and the positive and negative electrodes are prevented.

Further, the semiconductor device 1 according to the present embodiment includes three semiconductor modules (10A, 10B, 10C) connected in parallel between the positive electrode line P and the negative electrode line N. Therefore, by connecting each of the three semiconductor modules to the U-phase coil, V-phase coil, and W-phase coil of the three-phase DC brushless motor, the inverter circuit of the three-phase DC brushless motor can be configured.

Although the embodiments of the present invention have been described above, the present invention should not be limited to the above embodiments. For example, in the above embodiment, the example in which the first semiconductor element and the second semiconductor element are N-channel type power MOSFETs has been described, but a P-channel type MOSFET may also be used. Further, in the above embodiment, the example in which the first semiconductor element and the second semiconductor element are MOSFETs has been described, but a bipolar transistor such as an IGBT may be used, or a semiconductor element other than the transistor may be used. As described above, the present invention is deformable as long as it does not deviate from the gist thereof.

1 ... Semiconductor device, 10A ... First semiconductor module, 10B ... Second semiconductor module, 10C ... Third semiconductor module, 11 ... Positive terminal, 12 ... Negative terminal, 13 ... Output terminal, 14 ... Positive plate, 14a ... Trapezoidal region , 14b ... rectangular region, 141 ... positive electrode surface, 142 ... end edge, 15 ... negative electrode plate, 15a ... trapezoidal region, 15b ... rectangular region, 151 ... negative electrode surface, 152 ... end edge, 152 ... recess, 16 ... conductive plate, 161 ... Exposed surface, 17 ... Arm unit, 17a ... First arm circuit, 17b ... Second arm circuit, 17c ... Third arm circuit, 17d ... Fourth arm circuit, 17e ... Fifth arm circuit, 171 ... First transistor (First semiconductor element), 171a ... One side, 171b ... The other side, 172 ... Second transistor (second semiconductor element), 172a ... One side, 172b ... The other side, 40 ... Case, 41 ... Bottom wall, 42 ... Side wall, 50 ... split bus bar (conductive connecting member), 51 ... split piece (conductive connecting member), 51a ... first split piece, 51b ... second split piece, 51c ... third split piece, 51d ... fourth split One piece, 511 ... 1st joint, 512 ... 2nd joint, 513 ... In-arm connection (first connection), 513b ... Top surface, 514 ... Arm-to-arm connection (second connection), 514a ... Bottom surface, 515 ... Inclined portion, 52 ... Terminal piece (conductive connection member) 521 ... First joint portion 521a ... Bottom surface 522 ... Second joint portion 523 ... In-arm connection portion (first connection portion) 524 ... Terminal Connection part, 524a ... Bottom surface, 525 ... Vertical part, 60 ... Control board, 61, 62, 63, 64 ... Flexible wiring, D ... Drain electrode (first electrode), S ... Source electrode (second electrode), G ... Gate electrode (third electrode), V ... DC power supply, VP ... Power supply side positive electrode terminal, VN ... Power supply side negative electrode terminal, P ... Positive electrode line, N ... Negative electrode line,

Claims (8)

A semiconductor device including a semiconductor module connected between a positive electrode line connected to a positive electrode terminal on the power supply side of a DC power supply and a negative electrode line connected to a negative electrode line on the power supply side of the DC power supply.
The semiconductor module
A positive electrode plate made of a conductive metal, electrically connected to a positive electrode terminal on the power supply side of a DC power supply, and having a positive electrode surface facing a predetermined direction.
A negative electrode composed of a conductive metal, electrically connected to the power supply side negative electrode terminal of the DC power supply, formed with a negative electrode surface facing the same direction as the positive electrode surface, and arranged adjacent to the positive electrode plate. Board and
A plurality of arm circuits connected in parallel between the positive electrode plate and the negative electrode plate are provided.
Each of the plurality of arm circuits
A semiconductor device having one surface on which the first electrode is formed and a surface facing the opposite side to the one surface and the other surface on which the second electrode is formed, wherein the one surface is the positive electrode surface. The first semiconductor element bonded to the positive electrode plate in a state of facing each other,
A semiconductor device having one surface on which the first electrode is formed and a surface facing the opposite side to the one surface and the other surface on which the second electrode is formed, and the other surface is the negative electrode surface. A second semiconductor element bonded to the negative electrode plate in a state of facing each other,
Possess a conductive connecting member having a first connecting portion for electrically connecting with the other surface of the first semiconductor device facing the same direction and the one surface of the second semiconductor element, a,
A semiconductor device in which the conductive connecting member of the plurality of arm circuits includes a divided piece having a second connecting portion connected to the first connecting portion of the conductive connecting member provided in the arm circuit arranged adjacent to the arm circuit . In the semiconductor device according to claim 1,
A semiconductor device in which the positive electrode surface and the negative electrode surface are formed in the same plane. In the semiconductor device according to claim 1 or 2.
The first semiconductor element and the second semiconductor element are transistors having a third electrode, respectively.
A semiconductor device in which the first electrode is a drain electrode or a collector electrode, the second electrode is a source electrode or an emitter electrode, and the third electrode is a gate electrode or a base electrode. In the semiconductor device according to claim 3,
The third electrode is formed on the other surface, and the third electrode is formed on the other surface.
A semiconductor device in which a recess is formed in a portion of the negative electrode surface facing the third electrode formed on the other surface of the second semiconductor element. In the semiconductor device according to claim 4,
The third electrode formed on the other surface of the first semiconductor element and the third electrode formed on the other surface of the second semiconductor element are provided via flexible wiring having flexibility. A semiconductor device connected to a control board that outputs a signal to the third electrode. In the semiconductor device according to any one of claims 1 to 5 .
A semiconductor device in which the plurality of arm circuits are aligned and arranged along a predetermined direction. In the semiconductor device according to any one of claims 1 to 6 .
A semiconductor device including a plurality of the semiconductor modules connected in parallel between the positive electrode line and the negative electrode line. In the semiconductor device according to any one of claims 1 to 7 .
The second connection portion of the division piece of the arm circuit and the first connection portion of the division piece of the arm circuit arranged adjacent to the arm circuit are overlapped in a direction in which the positive electrode surface and the negative electrode surface face. A semiconductor device that is connected by being arranged in such a manner.

Images