JP6884569B2 - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP6884569B2 JP6884569B2 JP2016245624A JP2016245624A JP6884569B2 JP 6884569 B2 JP6884569 B2 JP 6884569B2 JP 2016245624 A JP2016245624 A JP 2016245624A JP 2016245624 A JP2016245624 A JP 2016245624A JP 6884569 B2 JP6884569 B2 JP 6884569B2
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description
本実施の形態では、半導体装置の一形態を、図1乃至図9を用いて説明する。
以下では、本発明の一態様に係るトランジスタの一例について説明する。図1(A)、図1(B)、および図1(C)は、本発明の一態様に係るトランジスタの上面図および断面図である。図1(A)は上面図であり、図1(B)は、図1(A)に示す一点鎖線X1−X2、図1(C)は、一点鎖線Y1−Y2に対応する断面図である。なお、図1(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
図2には、トランジスタ200に適応できる構造の一例を示す。図2(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図2(A)において一部の膜は省略されている。また、図2(B)は、図2(A)に示す一点鎖線X1−X2に対応する断面図であり、図2(C)はY1−Y2に対応する断面図である。
図3には、トランジスタ200に適応できる構造の一例を示す。図3(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図3(A)において一部の膜は省略されている。また、図3(B)は、図3(A)に示す一点鎖線X1−X2に対応する断面図であり、図3(C)はY1−Y2に対応する断面図である。
図4には、トランジスタ200に適応できる構造の一例を示す。図4(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図4(A)において一部の膜は省略されている。また、図4(B)は、図4(A)に示す一点鎖線X1−X2に対応する断面図であり、図4(C)はY1−Y2に対応する断面図である。
図5には、トランジスタ200に適応できる構造の一例を示す。図5(A)はトランジスタ200の上面を示す。なお、図の明瞭化のため、図5(A)において一部の膜は省略されている。また、図5(B)は、図5(A)に示す一点鎖線X1−X2に対応する断面図であり、図5(C)はY1−Y2に対応する断面図である。
以下に、図1に示した半導体装置の作製方法の一例を図6乃至図9を参照して説明する。
本実施の形態では、半導体装置の一形態を、図10乃至図29を用いて説明する。
本発明の一態様であるトランジスタを使用した、半導体装置(記憶装置)の一例を図10乃至図16に示す。なお、図10(A)は、図11乃至図14を回路図で表したものである。図15、および図16は、図11乃至図14に示す半導体装置が形成される領域の端部を示す。
図10(A)、および図11乃至図14に示す半導体装置は、トランジスタ300と、トランジスタ200、および容量素子100を有している。
図10(B)に示す半導体装置は、トランジスタ300を有さない点で図10(A)に示した半導体装置と異なる。この場合も図10(A)に示した半導体装置と同様の動作により情報の書き込みおよび保持動作が可能である。
本発明の一態様の半導体装置は、図11に示すようにトランジスタ300、トランジスタ200、容量素子100を有する。トランジスタ200はトランジスタ300の上方に設けられ、容量素子100はトランジスタ300、およびトランジスタ200の上方に設けられている。
また、本実施の形態の変形例として、図12に示すように、導電体244を形成してもよい。つまり、絶縁体282にプラグを埋め込み、プラグ上に、配線となる導電体、およびバリア層245を積層構造で設けてもよい。この場合、導電体244を構成する導電体において、配線として機能する導電体は、耐酸化性が高い導電体を用いることが好ましい。
また、本実施の形態の変形例として、容量素子100において、必ずしも導電体112を有する必要はない。
また、本実施の形態の変形例の一例を、図14に示す。図14は、図13と、トランジスタ300、およびトランジスタ200の構成が異なる。
また、本実施の形態の変形例の一例を、図17に示す。図17(A)、および図17(B)はそれぞれ、一点鎖線A1−A2を軸とした、トランジスタ200のチャネル長、およびチャネル幅方向の断面を示す。
また、本実施の形態の変形例の一例を、図18に示す。図18は、図13と、容量素子の構成が異なる。
また、本実施の形態の変形例の一例を、図19に示す。図19(A)は、図10(A)に示す半導体装置を、マトリクス状に配置した場合における、行の一部を抜き出した回路図である。また、図19(B)は、図19(A)の回路図と対応した半導体装置の断面図である。
また、本実施の形態の変形例の一例を、図20に示す。図20は、図19に示す半導体装置において、トランジスタ201、およびトランジスタ202を集積した場合の半導体装置の断面図である。
本実施の形態では、上記構成例で示した半導体装置の作製方法の一例について、図11、および図21乃至図29を用いて説明する。
本実施の形態においては、先の実施の形態で例示したトランジスタを有する酸化物半導体について、図33乃至図38を用いて以下説明を行う。
以下では、酸化物半導体の構造について説明する。
まずは、CAAC−OSについて説明する。
次に、nc−OSについて説明する。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。
次に、酸化物半導体のキャリア密度について、以下に説明を行う。
本実施の形態においては、本発明の一態様に係るトランジスタや上述した記憶装置などの半導体装置を含むCPUの一例について説明する。
図39は、上述したトランジスタを一部に用いたCPUの一例の構成を示すブロック図である。
本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した表示装置について、図41および図42を用いて説明する。
表示装置に用いられる表示素子としては液晶素子(液晶表示素子ともいう。)、発光素子(発光表示素子ともいう。)などを用いることができる。発光素子は、電流または電圧によって輝度が制御される素子をその範疇に含んでおり、具体的には無機EL(Electroluminescence)、有機ELなどを含む。以下では、表示装置の一例としてEL素子を用いた表示装置(EL表示装置)および液晶素子を用いた表示装置(液晶表示装置)について説明する。
本実施の形態においては、本発明の一態様に係るトランジスタなどを利用した電子機器について説明する。
本発明の一態様に係る半導体装置は、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置(代表的にはDVD:Digital Versatile Disc等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置)に用いることができる。その他に、本発明の一態様に係る半導体装置を用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図43に示す。
以下では、本発明の一態様に係る試料1A、試料1B、試料1C、試料1D、試料1E、試料1F、および試料1Gについて説明する。試料1A乃至試料1Gは、基板5000と、基板5000上の酸化物5001と、酸化物5001上の絶縁体5002と、を有する。
続いて、絶縁体5002、および酸化物5001に含有される水素濃度の評価を行った。なお、水素濃度評価は、二次イオン質量分析(Secondary Ion Mass Spectrometry:SIMS)により行い、分析装置としてアルバック・ファイ社製ダイナミックSIMS装置PHI ADEPT−1010を用いた。
101 容量素子
102 容量素子
105 容量素子
110 絶縁体
112 導電体
112a 導電体
112b 導電体
116 導電体
124 導電体
130 絶縁体
132 絶縁体
134 絶縁体
150 絶縁体
200 トランジスタ
201 トランジスタ
202 トランジスタ
205 導電体
205a 導電体
205A 導電体
205b 導電体
205B 導電体
210 絶縁体
212 絶縁体
213 絶縁体
214 絶縁体
216 絶縁体
218 導電体
218a 導電体
218b 導電体
218c 導電体
220 絶縁体
222 絶縁体
224 絶縁体
230 酸化物
230a 酸化物
230A 酸化物
230b 酸化物
230B 酸化物
230c 酸化物
230d 酸化物
240a 導電体
240A 導電膜
240b 導電体
240B 導電層
241a 導電体
241b 導電体
244 導電体
244a 導電体
244A 導電膜
244b 導電体
244B 導電膜
244c 導電体
244d 導電体
244e 導電体
245 バリア層
245a バリア層
245A バリア膜
245b バリア層
245c バリア層
245d バリア層
245e バリア層
250 絶縁体
260 導電体
260a 導電体
260A 導電膜
260b 導電体
260c 導電体
280 絶縁体
282 絶縁体
283 絶縁体
284 絶縁体
285 絶縁体
286 絶縁体
290 レジストマスク
292 レジストマスク
294 レジストマスク
296 レジストマスク
300 トランジスタ
301 トランジスタ
302 トランジスタ
311 基板
312 半導体領域
314 絶縁体
316 導電体
318a 低抵抗領域
318b 低抵抗領域
320 絶縁体
322 絶縁体
324 絶縁体
326 絶縁体
328 導電体
328a 導電体
328b 導電体
328c 導電体
330 導電体
330a 導電体
330b 導電体
330c 導電体
350 絶縁体
352 絶縁体
354 絶縁体
356 導電体
356a 導電体
356b 導電体
356c 導電体
358 絶縁体
700 基板
701 絶縁体
702 絶縁体
703 半導体
704 導電体
705 導電体
705a 領域
706 絶縁体
707a 導電体
707b 導電体
708 絶縁体
709 絶縁体
710 絶縁体
714a 導電体
714b 絶縁体
714c 導電体
716 絶縁体
719 発光素子
720 絶縁体
721 絶縁体
731 端子
732 FPC
733a 配線
734 シール材
735 駆動回路
736 駆動回路
737 画素
741 トランジスタ
742 容量素子
743 スイッチ素子
744 信号線
750 基板
751 トランジスタ
752 容量素子
753 液晶素子
754 走査線
755 信号線
781 導電体
782 発光層
783 導電体
784 隔壁
791 導電体
792 絶縁体
793 液晶層
794 絶縁体
795 スペーサ
796 導電体
797 基板
901 筐体
902 筐体
903 表示部
904 表示部
905 マイクロフォン
906 スピーカー
907 操作キー
908 スタイラス
911 筐体
912 筐体
913 表示部
914 表示部
915 接続部
916 操作キー
921 筐体
922 表示部
923 キーボード
924 ポインティングデバイス
931 筐体
932 冷蔵室用扉
933 冷凍室用扉
941 筐体
942 筐体
943 表示部
944 操作キー
945 レンズ
946 接続部
951 車体
952 車輪
953 ダッシュボード
954 ライト
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
1200 記憶素子
1201 回路
1202 回路
1203 スイッチ
1204 スイッチ
1206 論理素子
1207 容量素子
1208 容量素子
1209 トランジスタ
1210 トランジスタ
1213 トランジスタ
1214 トランジスタ
1220 回路
3001 配線
3002 配線
3003 配線
3004 配線
3005 配線
5000 基板
5001 酸化物
5002 絶縁体
Claims (8)
- 基板上に酸素、及び水素に対してバリア性を有する第1のバリア層と、
前記第1のバリア層上の第1の絶縁体と、
前記第1の絶縁体上の第2の絶縁体と、
前記第2の絶縁体上の第3の絶縁体と、
前記第3の絶縁体上の酸化物半導体を有するトランジスタと、
前記トランジスタ上の過剰酸素領域を有する第4の絶縁体と、
前記第4の絶縁体上の酸素、及び水素に対してバリア性を有する第2のバリア層と、を有し、
前記トランジスタは、耐酸化性を有する第1の導電体、耐酸化性を有する第2の導電体、および耐酸化性を有する第3の導電体を有し、
前記第2の絶縁体はhigh−k材料を有し、
前記トランジスタが設けられた領域の外縁において、前記第1のバリア層と、前記第2のバリア層とが接することにより、前記トランジスタは、前記第1のバリア層、及び前記第2のバリア層とに包囲されていることを特徴とする半導体装置。 - 請求項1において、
前記第1の導電体、前記第2の導電体、および前記第3の導電体は、窒化タンタルであることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第1のバリア層、および前記第2のバリア層は、TDS分析により、50℃から500℃の範囲において、水素原子に換算した水素の脱離量が、10×1015atoms/cm2以下である窒化シリコンであることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第1のバリア層、および前記第2のバリア層は、酸化アルミニウムであることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記第1のバリア層は、酸化アルミニウムであり、
前記第2のバリア層は、TDS分析により、50℃から500℃の範囲において、水素原子に換算した水素の脱離量が、10×1015atoms/cm2以下である窒化シリコンの積層構造であることを特徴とする半導体装置。 - 基板上に酸素、及び水素に対してバリア性を有する第1のバリア層を形成し、
前記第1のバリア層上に、第1の導電体を形成し、
前記第1の導電体上に、第1の絶縁体を形成し、
前記第1の絶縁体上に、high−k材料を用いて第2の絶縁体を形成し、
前記第2の絶縁体上に、第3の絶縁体を形成し、
前記第3の絶縁体上に、第1の酸化物半導体を形成し、
前記第1の酸化物半導体上に、耐酸化性を有する第2の導電体を形成し、
前記第2の導電体を、島状に加工し、
前記島状の第2の導電体をマスクとして、前記第1の酸化物半導体、前記第3の絶縁体を、島状に加工し、加熱処理を行った後、前記島状の第2の導電体を加工することで、第3の導電体、および第4の導電体を形成し、
前記第1の酸化物半導体、第3の導電体、および第4の導電体上に、第2の酸化物半導体を形成し、
前記第2の酸化物半導体上に、第4の絶縁体を形成し、
前記第4の絶縁体上に、耐酸化性を有する島状の第5の導電体を形成し、
前記第4の絶縁体、および前記第5の導電体上に、第5の絶縁体を形成し、
前記第5の絶縁体に、前記第3の導電体、前記第4の導電体、および前記第5の導電体に達する開口を形成し、
前記開口に第6の導電体を形成し、
前記第6の導電体上に、酸素、及び水素に対してバリア性を有する第2のバリア層を形成し、
前記第2のバリア層、および前記第5の絶縁体に対して、酸素プラズマ処理を行った後、前記第2のバリア層、および前記第5の絶縁体上に、酸素、及び水素に対してバリア性を有する第3のバリア層を形成することを特徴とする半導体装置の作製方法。 - 請求項6において、
前記第1のバリア層、および前記第3のバリア層は、スパッタリング法により形成することを特徴とする半導体装置の作製方法。 - 請求項6または請求項7において、
前記第5の導電体は、ALD法により形成された窒化タンタルと、スパッタリング法により形成された窒化タンタルの積層構造であることを特徴とする半導体装置の作製方法。
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JP6488124B2 (ja) * | 2013-12-27 | 2019-03-20 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US9577110B2 (en) | 2013-12-27 | 2017-02-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including an oxide semiconductor and the display device including the semiconductor device |
JP6506961B2 (ja) | 2013-12-27 | 2019-04-24 | 株式会社半導体エネルギー研究所 | 液晶表示装置 |
JP6559444B2 (ja) | 2014-03-14 | 2019-08-14 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
WO2015159179A1 (en) * | 2014-04-18 | 2015-10-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device |
TWI772799B (zh) | 2014-05-09 | 2022-08-01 | 日商半導體能源研究所股份有限公司 | 半導體裝置 |
KR102437450B1 (ko) | 2014-06-13 | 2022-08-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치, 및 반도체 장치를 포함하는 전자 기기 |
US9455337B2 (en) | 2014-06-18 | 2016-09-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US10460984B2 (en) | 2015-04-15 | 2019-10-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating electrode and semiconductor device |
KR102549926B1 (ko) | 2015-05-04 | 2023-06-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치, 반도체 장치의 제작 방법, 및 전자기기 |
WO2017081579A1 (en) | 2015-11-13 | 2017-05-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US9923001B2 (en) * | 2016-01-15 | 2018-03-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10741587B2 (en) * | 2016-03-11 | 2020-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, semiconductor wafer, module, electronic device, and manufacturing method the same |
-
2016
- 2016-12-19 JP JP2016245624A patent/JP6884569B2/ja active Active
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