JP6715312B2 - Display device - Google Patents

Description

The present invention relates to a display device, and more particularly to an active matrix display device in which an EL (Electro Luminescence) element is a display pixel and a TFT for driving the EL element is provided for each pixel.

In a conventional active matrix type organic EL display device (OLED), an LTPS-TFT (low temperature polysilicon TFT) using low temperature polysilicon as an active layer is used as a driving transistor.

However, in the active matrix type organic EL display device, the cost of the LTPS-TFT for driving the organic EL element is high in the whole cost, and the LTPS-TFT in particular has a problem that the cost required for manufacturing is large.

For this reason, the use of a-Si TFTs (amorphous silicon TFTs) has been studied, but since a-Si has low mobility and the threshold voltage Vt of the TFTs easily shifts (changes), the organic EL of the organic EL display device can be used. It is difficult to use an a-Si TFT for driving the device.

As a method for solving this problem, a TFT using an oxide semiconductor has been studied as shown in Patent Documents 2 and 3.

In addition, Patent Document 1 discloses an organic EL display device using an oxide semiconductor TFT.

JP, 2006-186319, A JP, 2006-165532, A JP, 2007-150157, A

In a conventional organic EL display device, a drive transistor that drives an organic EL element, a capacitor that stores electric charge for holding a voltage level of a gate electrode of the drive transistor at a predetermined level for one frame period, and a video signal to the capacitor. And a switching transistor for writing is provided at least for each pixel. With this configuration, a current is written in the capacitor via the switching transistor every one frame period and a current corresponding to the amount of charge is flowed by the drive transistor, and the organic EL element emits light.

On the other hand, as shown in Patent Documents 1 to 3, when a transistor is formed of an amorphous oxide semiconductor, as shown in the gate voltage-drain current characteristics of FIG. Although decreasing, the current decreases gradually near 0 V because electrons with low mobility remain.

For this reason, when a conventional amorphous oxide semiconductor is used as a switching transistor for writing a video signal in a capacitor, the amount of charge stored in the capacitor decreases with the passage of time. That is, there is a problem that a leak occurs between the source and the drain, the charge of the capacitor cannot be maintained for one frame period, and light emission with the same light amount cannot be maintained for one frame period.

An object of the present invention is to provide a display device in which leakage current when the oxide semiconductor transistor is off is reduced.

Another object of the present invention is to provide a display device capable of displaying an image without display unevenness with a simple pixel circuit.

In order to solve the above-mentioned problems, the invention according to claim 1 is characterized in that a light emitting element that emits light in response to a current, a first transistor that applies a drive voltage to the light emitting element, and at least one frame period of the first transistor. A display device in which pixel circuits each including at least a capacitive element that applies a predetermined voltage to a gate terminal and a second transistor that writes an image signal to the capacitive element based on a selection signal are arranged in a matrix. The first and second transistors are formed of an oxide semiconductor, and the first and second transistors cover the source and drain wirings of the first and second transistors and the active layer exposed between the source and drain wirings. The second transistor includes a gate insulating film, and the second transistor includes two gate electrodes formed in parallel so as to overlap an active layer region of the same transistor, and the same selection signal is input to the two gate electrodes . It said gate electrode is a Ru display device is formed with a thickness of more than twice the level difference of the gate insulating film serving as a base.

In order to solve the problem, the invention according to claim 2 is the display device according to claim 1, wherein the first and second transistors are N-type oxide semiconductors.

In order to solve the above problems, the invention according to claim 3 is the display device according to claim 1 or 2, wherein a part of one of the two gate electrodes is superposed on the source electrode. And a part of the other gate electrode overlaps the drain electrode.

In order to solve the above problems, the invention according to claim 4 is the display device according to any one of claims 1 to 3, wherein the first and second transistors are formed of an InGaZnOx-based oxide semiconductor. Is.

In order to solve the above problems, the invention according to claim 5 is the display device according to any one of claims 1 to 4, wherein the first and second transistors have a gate insulating film formed of a silicon oxide film. Is done.

According to a sixth aspect of the present invention, in the display device according to the fifth aspect, the silicon oxide film is an annealed film.

In order to solve the above-mentioned problems, the invention according to claim 7 is the display device according to any one of claims 1 to 4, wherein the first and second transistors have a gate insulating film formed of a SiN film. Is.

In order to solve the above problems, the invention according to claim 8 is the display device according to any one of claims 1 to 7, wherein the light emitting element is an EL element.

In order to solve the above problems, the invention according to claim 9 is the display device according to any one of claims 1 to 8, wherein the display device is a top emission type.

In order to solve the above-mentioned problems, the invention according to claim 10 is the display device according to any one of claims 1 to 8, wherein the second transistor is driven by a selection signal of 0 V or more.

In the display device of the present invention, since two gate electrodes are formed in parallel in the same semiconductor region of the second transistor and the same selection signal is input to the two gate electrodes, By stopping the carrier from the source electrode at the first gate electrode and reducing the carrier density between the gate electrodes, the effect more than doubling the resistance of the transistor can be obtained.

As a result, even when the second transistor which is an oxide semiconductor is used for the pixel circuit of the display device, the leakage current when the second transistor is off can be reduced.

In addition, since the leak current when the second transistor is off can be reduced, a silicon oxide film which can further stabilize the threshold voltage can be used as the gate insulating film. As a result, it is possible to display an image without display unevenness with a simple pixel circuit.

Other effects of the present invention will be clarified from the entire description of the specification.

FIG. 3 is a cross-sectional view illustrating a schematic configuration of an amorphous oxide semiconductor transistor in an organic EL display device which is a display device according to an embodiment of the present invention. FIG. 6A is a process diagram for describing the manufacturing method of the first and second transistors in the organic EL display device of the embodiment of the present invention. FIG. 6A is a process diagram for describing the manufacturing method of the first and second transistors in the organic EL display device of the embodiment of the present invention. FIG. 6A is a process diagram for describing the manufacturing method of the first and second transistors in the organic EL display device of the embodiment of the present invention. FIG. 6A is a process diagram for describing the manufacturing method of the first and second transistors in the organic EL display device of the embodiment of the present invention. FIG. 6A is a process diagram for describing the manufacturing method of the first and second transistors in the organic EL display device of the embodiment of the present invention. FIG. 6A is a process diagram for describing the manufacturing method of the first and second transistors in the organic EL display device of the embodiment of the present invention. FIG. 6A is a process diagram for describing the manufacturing method of the first and second transistors in the organic EL display device of the embodiment of the present invention. FIG. 6A is a process diagram for describing the manufacturing method of the first and second transistors in the organic EL display device of the embodiment of the present invention. FIG. 6A is a process diagram for describing the manufacturing method of the first and second transistors in the organic EL display device of the embodiment of the present invention. It is a circuit diagram for explaining a schematic structure of a pixel circuit of an organic EL display device of an embodiment of the present invention. FIG. 6 is a diagram for explaining the operation of the pixel circuit of the organic EL display device according to the embodiment of the present invention. FIG. 6A is a plan view for explaining the manufacturing method of the pixel circuit in the organic EL display device of the embodiment of the present invention. FIG. 6A is a plan view for explaining the manufacturing method of the pixel circuit in the organic EL display device of the embodiment of the present invention. FIG. 6A is a plan view for explaining the manufacturing method of the pixel circuit in the organic EL display device of the embodiment of the present invention. FIG. 6A is a plan view for explaining the manufacturing method of the pixel circuit in the organic EL display device of the embodiment of the present invention. FIG. 6A is a plan view for explaining the manufacturing method of the pixel circuit in the organic EL display device of the embodiment of the present invention. FIG. 6A is a plan view for explaining the manufacturing method of the pixel circuit in the organic EL display device of the embodiment of the present invention. It is a perspective view for explaining a schematic structure of an organic EL display device which is a display device according to an embodiment of the present invention. It is sectional drawing in the AA line of FIG. It is a figure for demonstrating operation|movement of the pixel circuit of the organic EL display device of other embodiment of this invention. It is a figure for demonstrating the gate voltage-drain current characteristic at the time of forming a transistor with the conventional amorphous oxide semiconductor.

Hereinafter, an example of an embodiment to which the present invention is applied will be described with reference to the drawings. However, in the following description, the same components will be denoted by the same reference numerals and repeated description will be omitted.

(Embodiment 1)
<Overall structure>
19 is a perspective view for explaining a schematic configuration of an organic EL display device which is a display device according to an embodiment of the present invention, and FIG. 20 is a sectional view taken along line AA of FIG.

As shown in FIG. 19, the organic EL display device of this embodiment includes a TFT substrate (first substrate) 19-1 on which an OLED layer is formed and a sealing glass (second substrate) 19-2. There is. The TFT substrate 19-1 and the sealing glass 19-2 are fixed by a sealing sealing material 19-3, and a vacuum is held between the TFT substrate 19-1 and the sealing glass 19-2. Has become.

In addition, an OLED (organic light emitting diode, organic electroluminescence element, light emitting layer) that emits R (red), G (green), and B (blue) that becomes pixels in a region surrounded by the sealing material 19-3. Are formed, and the pixels are arranged in a matrix in the x direction and the y direction in the drawing to form a pixel region 19-4.

Furthermore, the electrode lines formed on the TFT substrate 19-1 and connected to each pixel extend beyond the sealing material 19-3 to the outside of the pixel region 19-4. A terminal portion 19-5 is formed at an end portion of the electrode line so that a control signal is externally input to the pixel formed on the TFT substrate 19-1.

Further, in the present embodiment, the control signal input from the outside is a video signal corresponding to the light emission amount of each pixel, a gate signal that specifies writing of the video signal to each pixel and is a power source for one of the light emission, and the other. And a power supply for supplying a power supply voltage of 6V. Therefore, in the organic EL display device of the present embodiment, the video signal line for inputting the video signal, the gate signal line for inputting the gate signal, and the power supply line for supplying the power supply exceed the sealing sealing material 19-3 to the outside. It is configured to be pulled out to. The detailed configuration of the pixel circuit (circuit for one pixel cell) of this embodiment will be described later.

When a signal line that specifies writing of a video signal to each pixel and a power supply line that supplies one of the power supplies are separately formed as in the conventional pixel circuit, electrode lines and terminals corresponding to each are formed. The present invention can be applied by forming the portion 19-5.

As shown in FIG. 20, the organic EL display device of this embodiment has a configuration in which pixels are formed in the region between the TFT substrate 19-1 and the sealing glass 19-2. Further, since the light emitting material used for the light emitting layer has a property of being extremely weak against humidity, in the present embodiment, the well-known transparent desiccant 20-5 is formed inside the sealing glass 19-2, that is, on the pixel forming side. It is configured to.

Further, a cathode electrode 20-2 of a light emitting layer (OLED) and a pixel separation film 20-1 are formed on the upper surface side (pixel formation side) of the TFT substrate 19-1. A light emitting layer (OLED, light emitting portion) 20-3 and an anode electrode 20-4 made of a known transparent electrode material are formed on the pixel separation film 20-1. As will be described later, since the organic EL display device of the present invention has a configuration using an oxide semiconductor FET that is an n-type semiconductor, each pixel has a top anode type configuration. Note that the pixel of the present invention can be configured by combining with a top cathode type light emitting layer (OLED), but in this case, the driving voltage of the peripheral circuit needs to be higher by several V than that of the top anode type. There is.

The distance between the TFT substrate 19-1 and the sealing glass 19-2 is determined by the thickness of the transparent desiccant 20-5. In the present embodiment, part of the transparent desiccant 20-5 is the anode. It is configured to be in contact with the electrode 20-4. The entire surface of the transparent desiccant 20-5 may come into contact with the anode electrode 20-4.

Furthermore, since the organic EL display device of the present embodiment is a so-called top emission type display device, each RGB light emitted from the OLED layer 20-3 of each pixel is transparent to the anode electrode 20-4. The light is emitted in the direction of arrow 20-6 through the desiccant 20-5 and the sealing glass 19-2. The present invention can be applied to a so-called bottom emission type organic EL display device.

In the present embodiment, the sealing and sealing material 19-3 has a configuration using a known epoxy resin, and the transparent desiccant 20-5 has a configuration using a known aluminum alkoxide of a polymer alcohol. The sealing and sealing material 19-3 and the transparent desiccant 20-5 are not limited to the above materials, and other materials may be used.

<Pixel circuit configuration>
FIG. 11 is a circuit diagram for explaining the schematic configuration of the pixel circuit of the organic EL display device of the present invention, and FIG. 12 is a diagram for explaining the operation of the pixel circuit of the organic EL display device of the present invention. Note that the structure of the pixel circuit is not limited to this, and the pixel circuit can be applied to a pixel circuit having a circuit or the like for compensating for variations in transistors in each pixel circuit. The pixel circuit shown in FIG. 11 shows a pixel circuit for 4 pixels of 2×2.

As shown in FIG. 11, the pixel circuit of the present invention includes a light emitting layer (OLED) which is a diode D, and a power supply line (common electrode line) which supplies the light emitting layer (OLED) with a power supply voltage of 6 V which is one power supply voltage. ) V1, a first transistor T1 that controls the current flowing through the diode D, that is, the amount of light emitted from the light emitting layer (OLED), a gate signal line VSS that also functions as the other power supply line, and a drain-source terminal of the first transistor T1. It comprises a capacitor C connected in parallel between them, a second transistor T2 for writing a video signal for at least one frame into the capacitor C, and a video signal line DATA for supplying a video signal to the second transistor T2. There is.

Hereinafter, the configuration of the pixel circuit of this embodiment shown in FIG. 11 will be described in detail.

A power supply voltage of 6 V is applied to the anode side of the diode D via the power supply line V1. The cathode side of the diode D is connected to the gate signal line VSS via the first transistor T1, and a current corresponding to the voltage applied to the gate terminal of the first transistor T1 causes the diode D to pass through the diode. The amount of light emitted from the light emitting element is controlled.

A capacitor C is formed between the gate and the source of the first transistor T1. One end of the capacitor C, that is, the gate terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2. It is configured to. On the other hand, the source terminal of the second transistor T2 is connected to the video signal line DATA that supplies a video signal, and the video signal is written in the capacitor C. At this time, since one end of the capacitor C is connected to the gate terminal of the first transistor T1, the voltage corresponding to the video signal written in the capacitor C is applied to the gate of the first transistor T1 for at least one frame period. Will be applied. The details of the video signal writing operation will be described later.

Further, the gate terminal of the second transistor T2 is connected to the gate signal line VSS, and the video signal line DATA connected to the source terminal of the second transistor T2 is connected to the source terminal according to the write signal applied to the gate signal line VSS. The video signal is written in the condenser C.

Next, the operation of the pixel circuit of this embodiment will be described in detail with reference to FIG. However, in the following description, only the operation of the upper left pixel circuit in FIG. 11 will be described. Further, the voltage waveforms shown in FIG. 12 are voltage waveforms applied to the gate signal line VSS and the video signal line DATA connected to the upper left pixel circuit in FIG.

In the period t1 to t2, since the voltage of 0 V is applied to the gate terminal of the second transistor T2, the second transistor T2 is in the off state. Therefore, the charge accumulated in the writing operation one frame before is held in the capacitor C, and a voltage corresponding to the charge of the capacitor C is applied to the gate terminal of the first transistor T1. Therefore, the first transistor T1 causes a current corresponding to the charge of the capacitor C to flow through the diode D, and the diode D continues to emit light with a light emission amount corresponding to the current. At this time, in the organic EL display device of the present embodiment, two gate electrodes are formed in parallel in the same active layer of the second transistor T2 to form a second oxide film formed of an amorphous oxide semiconductor. Since the leak current between the source and drain of the transistor T2 is significantly reduced, the electric charge written in the capacitor C can be retained for one frame period.

In the periods t2 to t3, the write voltage V2 is applied to the gate terminal of the second transistor T2, and the second transistor T2 is turned on. Therefore, the video signal Vd1 supplied to the video signal line DATA in the period is applied (written) to the capacitor C via the second transistor T2. Therefore, the video signal Vd1 is applied to the gate terminal of the first transistor T1, the first transistor T1 passes a current corresponding to the applied voltage Vd1 to the diode D, and the diode D continues to emit light according to the current. It emits light.

In the period t3 to t4, since the voltage of 0 V is applied to the gate terminal of the second transistor T2 again, the second transistor T2 is turned off. The applied voltage Vd1 stored in the write operation in the periods t2 to t3 is held in the capacitor C, and the applied voltage Vd1 is applied to the gate terminal of the first transistor T1. Therefore, the first transistor T1 causes a current corresponding to the applied voltage Vd1 written in the capacitor C to flow in the diode D, and the diode D continues to emit light with a light emission amount corresponding to the current.

Note that in the period after t4, the same operation as in the periods t3 to t4 is performed until the next writing period, and the pixel circuit continues to emit light with a light emission amount corresponding to the applied voltage Vd1. In addition, since the same light emitting operation is performed in other pixel circuits, it is possible to display a desired image.

Furthermore, in the organic EL display device of the present embodiment, the first transistor T1 is also formed of an amorphous oxide semiconductor, so that the diode D can stably emit light.

<Structure of transistor>
FIG. 1 is a sectional view for explaining a schematic configuration of an amorphous oxide semiconductor transistor in the organic EL display device of this embodiment.

As shown in FIG. 1, in the transistor of this embodiment, a barrier layer 2 made of aluminum oxide is formed on the surface of a glass substrate 1, and an InGaZnOx film 3 serving as an active layer of an oxide semiconductor is formed on the barrier layer 2. It is configured to. With this structure, impurities are prevented from entering the InGaZnOx film 3 from the glass substrate 1 which may cause the threshold voltage Vth of the transistor to shift.

On the upper layer of the InGaZnOx film 3, SD wirings 4 made of a Mo film to be the source or drain of the amorphous oxide semiconductor transistor are formed so as to be spaced apart so as to sandwich the channel portion to be the active layer. The SD wiring 4 made of the Mo film has a shape with rounded corners.

A gate insulating film 5 made of a silicon oxide film (SiOx film, silicon oxide film) is formed on the upper layer of the SD wiring 4, and the thickness of the channel portion is about 50 nm. Further, in the present embodiment, in order to prevent the shift of the threshold voltage, which is a defect when the SiOx film is used as the gate insulating film 5, the SiOx film annealed at a high temperature is used as the gate insulating film 5. ..

A gate wiring 6 having a three-layer structure of Mo/Al/Mo is formed on the gate insulating film 5 in the channel portion. At this time, in the present embodiment, the gate wiring 6 is formed with a thickness that is at least twice the step of the underlying layer, as a structure for preventing disconnection of the gate wiring 6. Further, in this embodiment, in the contact hole portion of the gate insulating film 5 provided on the upper portion of the SD wiring 4 on the side to be the drain electrode, the same layer as the gate wiring 6 and the same thin film as the gate wiring material are formed. A thin film layer made of a material is formed. It should be noted that this thin film layer is electrically connected to the wiring on the side of the SD wiring 4 which will be the drain electrode.

On the upper layer of the gate wiring 6, a function of a flattening film for flattening unevenness on the front surface of the glass substrate 1 due to formation of a transistor and a wiring layer (not shown), and a function as a protective film for the transistor and a wiring layer (not shown) Insulating film 7 made of a photosensitive polyimide resin having is formed.

An electrode layer 8 of a light emitting layer (OLED, diode) made of an ITO/Ag/ITO laminated film is formed on the insulating film 7, and a pixel separation film 9 made of photosensitive polyimide is formed on the electrode layer 8. Has been done.

The present embodiment is a TFT substrate configured to use the amorphous oxide semiconductor transistor having such a configuration for driving a light emitting layer.

<Transistor manufacturing method>
2 to 10 are process diagrams for explaining the method for manufacturing the first and second transistors in the organic EL display device according to the present embodiment. Hereinafter, the manufacturing method will be described in the order of processes based on FIGS. 2 to 10. To do. Since the formation of the thin film including the formation of the electrodes in each step can be performed by a known photolithography technique, detailed description thereof will be omitted.

Step 1. (Fig. 2)
First, an aluminum oxide film is formed as a barrier layer 2 on the surface of a glass substrate 1 by a sputtering method, and subsequently, an InGaZnOx film 3 to be an active layer of an oxide semiconductor and a source wiring or a drain wiring of a transistor (hereinafter, A Mo film, which will be abbreviated as SD wiring) 4, is continuously formed. At this time, the thickness of the aluminum oxide film is about 70 nm, the thickness of the InGaZnOx film 3 is about 60 nm, and the thickness of the Mo film is about 180 nm.

Step 2. (Figure 3)
Next, a pattern for forming the source or drain wiring (SD wiring) 4 (SD pattern) by molding the Mo film and a pattern for forming a channel portion which becomes an active layer in the InGaZnOx film 3 are formed by the photoresist 10. Form. However, this pattern is formed by exposure using a photomask formed like a half mirror so that the channel portion is formed thin. In the pattern of the photoresist 10, the resist film thickness in the SD portion is 1.4 μm and the channel portion is 0.4 μm.

Step 3. (Fig. 4)
Next, the Mo film (both sides in the figure) which becomes the SD wiring 4 and the InGaZnOx film 3 (both sides in the figure) are etched by wet etching using the photoresist 10 formed in the step 2. At this time, the Mo film is wet-etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. The InGaZnOx film 3 is wet-etched using oxalic acid. After that, the photoresist 10 is removed by plasma ashing to a thickness of about 0.6 μm to expose the Mo film in the channel portion, and the photoresist 10 in the SD wiring portion is also thinned in the drawing. After that, the Mo film is wet-etched again with a mixed acid of phosphoric acid, acetic acid, and nitric acid to remove the Mo film in the channel portion, and both sides in the figure of the Mo film are removed to remove the Mo film from the InGaZnOx film 3. The width of the pattern is reduced in the figure.

With such a shape, it is possible to eliminate a portion where the SD wiring 4 crosses over the InGaZnOx film 3 (oxide semiconductor layer), and it is possible to avoid disconnection of the SD wiring 4 due to a step. Further, by forming the SD wiring 4 smaller than the InGaZnOx film 3 (oxide semiconductor layer), it is possible to easily cover this laminated portion (portion of the SD wiring 4) with a gate insulating film described later.

Further, in the present embodiment, in order to further facilitate the covering with the gate insulating film, first, ashing is performed after the photoresist 10 is peeled off to oxidize the corners of the SD wiring 4 formed of the Mo film. Then, by washing with water, the corners of the SD wiring 4 are rounded.

Step 4. (Figure 5)
Next, the gate insulating film 5 is formed, and the contact hole 11 is formed in the gate insulating film 5 by photolithography. The gate insulating film 5 is formed by decomposing TEOS (4 ethyloxysilane) gas and oxygen by a plasma CVD method to form a SiOx film. The contact hole 11 is formed by wet etching, and buffered hydrofluoric acid is used as an etching solution. In this way, the gate insulating film 5 having a film thickness of about 50 nm is formed. Further, an inclined region 12a is formed at the edge portion (upper end of the edge portion) of the gate wiring formation region 12. The formation of the inclined region 12a is such that, when a gate wiring is formed in a later step, both end portions of the gate wiring and the end portion of the SD wiring are overlapped with each other with the gate insulating film 5 interposed therebetween. This is to make the formation of the channel region between the source and gate smooth.

However, since the deep defect level in the SiOx film formed by the plasma CVD method can be eliminated by high temperature annealing, also in this embodiment, by annealing at 400° C. or higher, preferably 450° C. to 550° C. , It is reduced to the extent that there is practically no problem. Note that the deep defect level in the gate insulating film is a fixed charge because electrons gathered at the interface between the gate insulating film 5 and the InGaZnOx film 3 (oxide semiconductor layer) enter when the transistor is turned on. This causes a shift in the threshold voltage of the transistor.

Step 5. (Fig. 6)
Next, the gate wiring 6 is formed. At this time, the gate wiring 6 is formed so that both ends of the gate wiring 6 and the end of the SD wiring 4 overlap with each other with the gate insulating film 5 interposed therebetween. The gate wiring 6 of this embodiment has a three-layer structure of Mo/Al/Mo, and has a total film thickness of 500 nm of Mo:50 nm, Al:400 nm, and Mo:50 nm in order to prevent disconnection due to a step. In this embodiment, since the step difference of the base is 240 nm, the thickness of the gate wiring 6 is set to about twice the thickness to prevent disconnection. Therefore, the thickness of the gate wiring 6 is not limited to 500 nm. For example, when the thickness of the InGaZnOx film 3 (oxide semiconductor layer) is 40 nm and the thickness of the SD wiring 4 is 120 nm, Even if the film thickness of the wiring layer 6 is about 350 nm, disconnection can be prevented. Further, the gate wiring material 6a in the contact hole portion is left in order to make the contact hole 11 shallow so that it can be easily opened.
Step 6. (Figure 7)
Next, the insulating film 7 for insulating the wiring of the transistor and the electrode of the light emitting layer (OLED, diode) is formed. The insulating film 7 is formed by applying photosensitive polyimide to the upper layer by a well-known spin coating method or the like, and then exposing and developing it. After forming the insulating film 7, a contact hole 13 for electrically connecting the electrode of the light emitting layer (OLED, diode) and the SD wiring 4 is formed on the gate insulating material 6a by known photolithography. By using the coating type insulating film 7, the unevenness of the substrate surface due to the formation of the transistor and the wiring can be smoothed, so that it is possible to obtain the effect of eliminating the corners that cause light scattering. .. The film thickness of this polyimide, that is, the film thickness of the insulating layer 7 is about 1.5 μm.

Step 7. (Figure 8)
Next, an ITO/Ag/ITO laminated film to be the electrode 8 of the light emitting layer (OLED, diode) is formed. The ITO/Ag/ITO laminated film is formed by sequentially sputtering ITO, Ag, and ITO, and then forming the ITO/Ag/ITO laminated film into a predetermined pattern by known photolithography. The etching of ITO can be performed with oxalic acid, and the etching of Ag can be performed with a mixed acid of phosphoric acid, acetic acid, and nitric acid, but the etching method is not limited to this. Further, from the bottom (the glass substrate 1 side), the thickness of each ITO layer is about 50 nm, the thickness of the Ag layer is about 150 nm, and the thickness of the ITO layer is about 30 nm.

Step 8. (Figure 9)
Next, the pixel separation film 9 is formed. The pixel separation film 9 is formed by applying a photosensitive polyimide by a well-known spin coating method, exposing and developing, and then forming an opening on the electrode 8.

Through the above steps 1 to 8, a transistor array substrate for actively driving the light emitting layer (OLED, diode) is completed.

However, in the organic EL display device of the present embodiment, the first transistor and the second transistor have different gate electrode configurations. Hereinafter, a method of manufacturing the second transistor will be described.

As shown in FIG. 10, the second transistor has a configuration in which two gate wirings 14a and 14b are formed in parallel between the SD wirings 4 formed apart from each other, that is, in the same active layer region.

The formation of such a gate wiring is performed by etching Mo layer, Al layer, and Mo layer in the above-described step 5 when forming the gate wiring having the three-layer structure of Mo/Al/Mo. By forming the two gate wirings 14a and 14b, the subsequent steps are the same steps as the manufacturing method of the first transistor described above.

At this time, in the present embodiment, the gate wiring 6 of the first transistor shown in FIG. 9 is divided into a source side and a drain side, so that one gate wiring 14a has an end portion of the source wiring. The end portion of the other gate wiring 14b overlaps with the end portion of the drain wiring.

With such a structure, the effect of doubling the resistance of the transistor in the oxide semiconductor can be obtained, and leakage current between the source and the drain can be significantly reduced. That is, two transistors connected in series have the effect of doubling the resistance, but oxide transistors have the property of decreasing mobility when the number of carriers decreases, and carrier leakage from the source is observed. As a result, the carrier concentration in the channel portion that should be depleted originally increases, so that the mobility also rises and the leak current increases. Therefore, in this embodiment, the gates are continuously provided (two gate wirings are arranged in parallel) so that carriers from the source are stopped at the first gate and the carrier density between the gate electrodes is lowered. Thus, the effect more than doubling the resistance of the transistor can be obtained, and the leak current between the source and drain can be significantly reduced. Furthermore, in the present embodiment, since the respective end portions of the two gate wirings 14a and 14b are overlapped with either end portion of the source wiring or the drain wiring, the second semiconductor wiring is made of an oxide semiconductor. The effect that the increase in the ON resistance of the two transistors can be minimized is also obtained.

<Method of manufacturing pixel circuit>
13 to 18 are plan views for explaining the method for manufacturing the pixel circuit in the organic EL display device of the present embodiment, and the manufacturing method will be described below in order based on FIGS. 13 to 18. Since the formation of the thin film including the formation of the electrodes in each step can be performed by a known photolithography technique, detailed description thereof will be omitted.

Step 1. (Figure 13)
First, after forming an oxide semiconductor layer (InGaZnOx layer) for forming an active layer of an oxide semiconductor on the upper surface (TFT element formation) side of a glass substrate (not shown) on which a barrier layer is formed on the substrate surface, SD An electrode layer pattern to be a wiring layer and a signal line (video signal wiring layer) is formed. In FIG. 13, the SD wiring layer pattern 13-1 to be the SD electrode of the first transistor and the pixel are provided in a region between two adjacent signal line patterns 13-3 that apply a write voltage to each pixel capacitor. An electrode layer pattern, which is one of the capacitor electrode patterns 13-2 and serves as the SD electrode pattern of the second transistor, is formed.

As apparent from FIG. 13, the oxide semiconductor layer pattern 13-5 and the SD wiring layer pattern 13-1 are almost overlapped with each other, and the SD wiring layer pattern 13-1 is the oxide semiconductor layer pattern 13-. 5, the SD wiring layer pattern 13-1 is not broken at the step of the oxide semiconductor layer pattern 13-5. Further, in the portion where the gate wiring layer pattern described later crosses over the SD wiring layer pattern 13-1, unevenness 13-4 is provided in the SD wiring layer pattern. By forming the concavities and convexities 13-4 in this way, the crossover line is formed into a curved shape, and it is possible to avoid a phenomenon in which the etching liquid permeates between the resist and the gate wiring material when the gate wiring is etched to cause a disconnection.

Step 2. (Figure 14)
Next, the gate insulating film pattern 14-2 is formed on the upper surface of the glass substrate (not shown). At a location electrically connecting a gate wiring layer pattern and an SD wiring layer pattern 13-1 described later, and at a location electrically connecting the SD wiring layer pattern 13-1 and an electrode of a light emitting layer (OLED, diode). Form a contact hole 14-1.

Step 3. (Figure 15)
Next, a gate wiring pattern and a signal line pattern are formed. In this step, the gate electrode pattern 15-1 of the first transistor T1, the gate electrode pattern 15-4 of the second transistor T2, and the other electrode pattern 15-2 of the pixel capacitor C are formed. Further, a wiring pattern 15-3 is formed to supply power to the light emitting layer (OLED, diode) and send an open/close signal (gate signal) to the second transistor (writing transistor). In particular, in the present embodiment, as the gate electrode pattern 15-5 of the second transistor T2, a double gate electrode pattern 15-5, that is, two adjacent gate electrode patterns 15-5 are formed.

Further, in the formation of the capacitor, the electrode pattern 13-2 in the same layer as the SD wiring layer and the electrode pattern 15-2 in the same layer as the gate wiring layer are formed to overlap with each other through the gate insulating film pattern 14-2. .. In the present embodiment, the pattern on the gate wiring layer side (electrode pattern 15-2 in the same layer as the gate wiring layer) is replaced with the pattern on the SD wiring layer side (electrode pattern 13-2 in the same layer as the SD wiring layer). Inside, that is, by forming the pattern on the gate wiring layer side smaller than the pattern on the SD wiring layer side so that it does not protrude from the pattern on the SD wiring layer side, a short circuit occurs at the step on the outer peripheral portion of the SD wiring pattern. It avoids waking up.

Further, in this embodiment, the contact hole portion 14-1 is raised by forming the gate electrode pattern 15-4 in the contact hole portion 14-1 of the gate insulating film pattern 14-2. In the process described below, the photosensitive polyimide coating film in the contact hole portion provided in the photosensitive polyimide layer is thinned so that the contact hole is surely opened.

Step 4. (Figure 16)
Next, a photosensitive polyimide layer pattern 16-2 for smoothing unevenness on the surface of the glass substrate (not shown) is formed. After forming the photosensitive polyimide layer pattern 16-2, a contact hole pattern 16-1 for electrically connecting the electrode of the light emitting layer (OLED, diode) and the SD wiring layer pattern 13-1 is formed with the gate electrode pattern 15. -4 part is formed.

Step 5. (Figure 17)
Next, the electrode pattern 17-1 of the light emitting layer (OLED, diode) is formed in the region between the two adjacent signal line patterns 13-3. The light emitting layer (OLED, diode) electrode pattern 17-1 is electrically connected to the SD wiring layer pattern 13-1 through the contact hole 16-1 provided in the photosensitive polyimide layer pattern 16-2.

Step 6. (Figure 18)
Next, after forming a photosensitive polyimide layer on the surface of a glass substrate (not shown), an opening 18-1 is formed above the light emitting layer (OLED, diode) electrode pattern 17-1 to form a pixel separation film pattern. .. However, when forming the opening 18-1, the opening 18-1 is formed so that the peripheral portion of the light emitting layer (OLED, diode) electrode pattern 17-1 and the contact hole 16-1 are covered with the photosensitive polyimide layer. By forming it, the light emitting layer (OLED, diode) electrode pattern (cathode) 17-1 and the anode are not short-circuited.

The transistor array substrate is manufactured as described above.

Next, a procedure for forming a light emitting layer (OLED, diode) on this transistor array substrate will be described.

First, the electron transporting first substance and the second substance are co-deposited on the opening 18-1 of the light emitting layer (OLED, diode) electrode pattern (cathode) 17-1 provided on the transistor array substrate. Then, an electron injection layer is formed.

Next, the first material is deposited on the electron injection layer to form an electron transport layer. The film thickness of the electron transport layer varies depending on each emission color, and is 130 nm for red, 100 nm for green, and 70 nm for blue.

Next, a light emitting layer is formed on the electron injection layer. At this time, the thickness of the red light emitting layer is 60 nm, the thickness of the green light emitting layer is 60 nm, and the thickness of the blue light emitting layer is 60 nm. ..

Next, a hole transport layer is formed on the light emitting layer by using a third substance.

Next, a hole injection layer is formed on the hole transport layer. The thickness of the hole injection layer is 10 nm.

Next, an organic EL device is formed by forming an anode electrode having a film thickness of 30 nm on the hole injection layer by sputtering IZO. The organic EL device emits light by applying a negative voltage to the cathode electrode and a positive voltage to the upper anode electrode.

Note that the first substance is not particularly limited as long as it has an electron-transporting property and easily forms a charge-transfer complex by co-evaporation with an alkali metal, and examples thereof include tris(8-quinolinolato)aluminum and tris(4-). Methyl-8-quinolinolato)aluminum, bis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum, metal complexes such as bis[2-[2-hydroxyphenyl]benzoxazolate]zinc and 2- (4-Biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole, 1,3-bis[5-(p-tert-butylphenyl)-1,3,4- Oxadiazol-2-yl]benzene or the like can be used.

The second substance is not particularly limited as long as it is a material that exhibits an electron donating property to the electron transporting substance, and examples thereof include alkali metals such as lithium and cesium, alkaline earth metals such as magnesium and calcium, and the like. Further, it is possible to use a metal exhibiting an electron donating property selected from metals such as rare earth metals, or oxides, halides, and carbonates thereof.

The third substance is a substance having a hole-transporting property, and includes, for example, a tetraarylbenzidine compound (triphenyldiamine:TPD), an aromatic tertiary amine, a hydrazone derivative, a carbazole derivative, a triazole derivative, an imidazole derivative, An oxadiazole derivative having an amino group, a polythiophene derivative, a copper phthalocyanine derivative, or the like can be used.

Further, as the substance used for the hole injection layer, inorganic materials such as MoO ₃ , WO ₃ , and V ₂ O ₅ can be used. By using such a substance as the hole injecting layer, it is possible to obtain the effect of avoiding the deterioration of the organic material even when the anode electrode IZO is sputtered.

The light-emitting material used for the light-emitting layer is a host material having electron and hole transporting ability, to which a dopant that emits fluorescence or phosphorescence by recombination of them is added, and can be formed as a third layer by co-evaporation. There is no particular limitation as long as it is one, and examples of the host include tris(8-quinolinolato)aluminum, bis(8-quinolinolato)magnesium, bis(benzo{f}-8-quinolinolato)zinc, bis(2-methyl-8). -Quinolinolato) aluminum oxide, tris(8-quinolinolato)indium, tris(5-methyl-8-quinolinolato)aluminum, 8-quinolinolatolithium, tris(5-chloro-8-quinolinolato)gallium, bis(5-chloro) -8-quinolinolato)calcium, 5,7-dichloro-8-quinolinolato aluminum, tris(5,7-dibromo-8-hydroxyquinolinolato)aluminum, poly[zinc(II)-bis(8-hydroxy-). 5-quinolinyl)methane], anthracene derivatives, carbazole derivatives, and the like can be used.

As the dopant, a substance that captures electrons and holes in the host and recombines them to emit light, and for example, a substance that emits fluorescence such as a pyran derivative in red, a coumarin derivative in green, and an anthracene derivative in blue can be used. Further, or a substance emitting phosphorescence such as an iridium complex or a pyridinate derivative can be used.

For the uppermost layer, that is, the anode electrode, ITO or IZO, which is a transparent conductive film, is used to extract light.

Since the light emitting layer is vulnerable to moisture, it is necessary to seal it by enclosing dry nitrogen or the like. Alternatively, in consideration of moisture entering from the outside, a desiccant can be placed inside as in the present embodiment. Further, it may be sealed with frit glass or the like so that no moisture enters. Further, in the top emission type organic EL display device as in the present embodiment, the sealing glass is transparent, and light is emitted through the sealing glass.

Further, in the organic EL display device of the present embodiment, the silicon oxide film that has been annealed is used as the gate insulating film of the amorphous oxide semiconductor forming the first and second transistors, but the invention is not limited to this. Alternatively, for example, a SiN film formed by plasma CVD may be used as the gate insulating film.

Further, when the first and second transistors are formed of an amorphous oxide semiconductor using a silicon oxide film as the gate insulating film, when the SiN film is used as the passivation film, the SiN film is formed outside the gate insulating film, that is, above the gate insulating film. There is a need to.

As described above, in the organic EL display device of this embodiment, when forming the second transistor which is the switching transistor as shown in FIG. 10, two gate electrodes 14a are formed in the same semiconductor region, that is, in the same channel portion. , 14b are arranged side by side. At this time, since the same selection signal (gate signal) is input to the two gate electrodes as shown in FIG. 15, carriers from the source electrode are stopped at the first gate electrode 13b, and carrier density between the gate electrodes is reduced. By lowering, the effect more than doubling the resistance of the transistor can be obtained. As a result, even when the second transistor, which is an oxide semiconductor, is used in the pixel circuit of the organic EL display device, the leak current when the second transistor is off can be reduced.

In addition, since the leak current when the second transistor is off can be reduced, a silicon oxide film which can further stabilize the threshold voltage can be used as the gate insulating film. As a result, even in the organic EL display device, it is possible to display an image without display unevenness with a simple pixel circuit.

In the organic EL display device of the embodiment of the present invention, the gate electrode of the second transistor is formed of two gate electrodes arranged in parallel, but the gate electrode of the second transistor is the gate electrode of the first transistor. In the case of forming one electrode like the electrode, as shown in FIG. 21, the gate voltage when the second transistor is off may be made negative to promote depletion of the channel.

DESCRIPTION OF SYMBOLS 1... Glass substrate, 2... Barrier layer, 3... InGaZnOx film 4... SD wiring, 5... Gate insulating film, 6... Gate wiring 6a... Gate wiring material, 7 ... Insulating film, 8... Electrode of light emitting layer 9... Pixel separating film, 10... Photoresist, 11... Contact hole 12... Gate wiring formation region, 12a... Inclined region , 13... Contact holes 14a, 14b... Gate wiring, 13-1... SD wiring layer pattern 13-2... Pixel capacitor electrode pattern, 13-3... Signal line pattern 13-4 ... Wiring pattern unevenness, 13-5... Oxide semiconductor layer pattern 14-1... Contact hole, 14-2... Gate insulating film pattern 15-1... Gate electrode pattern, 15- 2... Electrode pattern of pixel capacitor 15-3... Wiring pattern, 15-4... Gate electrode pattern 15-5... Gate electrode pattern, 16-1... Contact hole pattern 16-2. .. Photosensitive polyimide layer pattern, 17-1... Electrode pattern of light emitting layer 18-1... Opening, 19-1... TFT substrate, 19-2... Sealing glass 19-3. ..Sealing sealing material, 19-4... Pixel region, 19-5... Terminal part 20-1... Pixel separation film, 20-2... Cathode electrode, 20-3... OLED Layer 20-4... Anode electrode, 20-5... Transparent desiccant T1... First transistor, T2... Second transistor, C... Capacitor D... Diode, V1... Power line (common electrode line), DATA... Video signal line VSS... Gate signal line

Claims (10)

A light emitting element that emits light in response to an electric current
A first transistor for applying a driving voltage to the light emitting element;
A capacitive element that applies a predetermined voltage to the gate terminal of the first transistor for at least one frame period;
A display device in which pixel circuits each including at least a second transistor for writing an image signal into the capacitive element based on a selection signal are arranged in a matrix,
The first and second transistors are formed of an oxide semiconductor,
The first and second transistors include a gate insulating film covering the source and drain wirings of the first and second transistors and the active layer exposed between the source and drain wirings.
The second transistor includes two gate electrodes formed in parallel so as to overlap with an active layer region of the same transistor, and the same selection signal is input to the two gate electrodes,
The gate electrode is a display device according to claim Rukoto formed by more than twice the thickness of the step of the gate insulating film serving as a base.
The display device according to claim 1,
The display device, wherein the first and second transistors are N-type oxide semiconductors. The display device according to claim 1 or 2,
Of the two gate electrodes,
Part of one of the gate electrodes is formed to overlap the source electrode,
A display device, wherein a part of the other gate electrode is formed so as to overlap the drain electrode. The display device according to any one of claims 1 to 3,
The display device, wherein the first and second transistors are formed of an InGaZnOx-based oxide semiconductor. The display device according to any one of claims 1 to 4,
The display device according to claim 1, wherein the first and second transistors have a gate insulating film formed of a silicon oxide film. The display device according to claim 5,
The display device, wherein the silicon oxide film is an annealed film. The display device according to any one of claims 1 to 4,
A display device, wherein the first and second transistors have a gate insulating film formed of a SiN film. The display device according to any one of claims 1 to 7,
The display device, wherein the light emitting element is an EL element. The display device according to any one of claims 1 to 8,
The display device is a top emission type display device. The display device according to any one of claims 1 to 8,
The display device is characterized in that the second transistor is driven by a selection signal of 0V or more.

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