JP5770236B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to an active matrix display device in which an EL (Electro Luminescence) element is used as a display pixel and a driving TFT for the EL element is provided for each pixel.

  In a conventional active matrix organic EL display device (OLED), an LTPS-TFT (low temperature polysilicon TFT) using low temperature polysilicon as an active layer is used as a driving transistor.

  However, in the active matrix organic EL display device, the cost of the LTPS-TFT for driving the organic EL element is high, and the LTPS-TFT has a problem that the cost required for manufacturing is particularly high.

  For this reason, the use of a-Si TFTs (amorphous silicon TFTs) has been studied. However, since a-Si has low mobility and the threshold voltage Vt of the TFT is likely to shift (fluctuate), the organic EL of the organic EL display device can be used. It is difficult to use an a-Si TFT for driving the element.

  As a method for solving this problem, as shown in Patent Document 2 and Patent Document 3, a TFT using an oxide semiconductor has been studied.

  Patent Document 1 discloses an organic EL display device using an oxide semiconductor TFT.

JP 2006-186319 A JP 2006-165532 A JP 2007-150157 A

  In a conventional organic EL display device, a driving transistor that drives an organic EL element, a capacitor that accumulates charges for holding the voltage level of the gate electrode of the driving transistor at a predetermined level for one frame period, and a video signal in the capacitor A switching transistor for writing is provided at least for each pixel. With this configuration, the current is written to the capacitor via the switching transistor for each frame period, and a current corresponding to the amount of electric charge is caused to flow by the driving transistor, so that the organic EL element emits light.

On the other hand, as shown in Patent Documents 1 to 3, when a transistor is formed in an amorphous oxide semiconductor, a gate voltage of 22 - as shown in the drain current characteristics, the drain current is brought close to 0V gate voltage from the positive side However, since the electrons with low mobility remain in the vicinity of 0 V, the current decrease gradually becomes gentle.

  For this reason, when a conventional amorphous oxide semiconductor is used as a switching transistor to write a video signal to a capacitor, the amount of charge stored in the capacitor decreases with the passage of time. That is, there is a problem that leakage occurs between the source and the drain, the capacitor charge cannot be maintained for one frame period, and light emission with the same light quantity cannot be maintained for one frame period.

  An object of the present invention is to provide a display device in which leakage current when an oxide semiconductor transistor is off is reduced.

  Another object of the present invention is to provide a display device capable of displaying an image without display unevenness with a simple pixel circuit.

In order to solve the above-mentioned problem, the invention according to claim 1 is a light-emitting element that emits light in response to a current, a first transistor that applies a driving voltage to the light-emitting element, and at least one frame period. A display device in which a pixel circuit including at least a capacitor element that applies a predetermined voltage to a gate terminal and a second transistor that writes an image signal to the capacitor element based on a selection signal is arranged in a matrix. 1 and the second transistor has a source electrode and a drain electrode, and a gate electrode are coplanar type thin film transistor disposed on the same side of the semi-conductor layer, the semiconductor layer of the first and second transistors, oxide The second transistor is formed of a semiconductor, and the two transistors formed in parallel so as to overlap the active layer region of the same transistor. Comprising a gate electrode, a display device where the same selection signal to the gate electrodes of the two said is input.

In order to solve the above problem, according to a second aspect of the present invention, in the display device according to the first aspect, the semiconductor layers of the first and second transistors are formed of an N-type oxide semiconductor.

In order to solve the above problem, the invention according to claim 3, superimposed in the display device according to claim 1 or 2, of the two gate electrodes, the portion of the source electrode of one of the gate electrode it is to form, in which a part of the other gate electrode is formed to overlap the drain electrode.

In order to solve the above problem, according to a fourth aspect of the present invention, in the display device according to any one of the first to third aspects, the semiconductor layer of the first and second transistors is an N-type oxide semiconductor. Is formed.

In order to solve the above problem, forming an invention according to claim 5, in the display device according to any one of claims 1 to 4, wherein the first and second transistors with a gate insulating film is a silicon oxide film Is formed .

In order to solve the above problem, according to a sixth aspect of the present invention, in the display device according to the fifth aspect , the silicon oxide film is an annealed film .

In order to solve the above-mentioned problem, according to a seventh aspect of the present invention, in the display device according to any one of the first to fourth aspects, the first and second transistors have a gate insulating film formed of a SiN film. It is.

In order to solve the above-mentioned problem, the invention according to claim 8 is the display device according to any one of claims 1 to 7, wherein the light emitting element is an EL element .

In order to solve the above-mentioned problem, the invention according to claim 9 is the display device according to any one of claims 1 to 8, wherein the display device is a top emission type .

In order to solve the above-mentioned problem, according to a tenth aspect of the present invention, in the display device according to any one of the first to eighth aspects, the second transistor is driven by a selection signal of 0V or higher.

  In the display device of the present invention, two gate electrodes are formed in parallel in the same semiconductor region of the second transistor, and the same selection signal is input to the two gate electrodes. By stopping carriers from the source electrode at the first gate electrode and lowering the carrier density between the gate electrodes, an effect more than double the resistance of the transistor can be obtained. As a result, even when the second transistor that is an oxide semiconductor is used for a pixel circuit of a display device, leakage current when the second transistor is off can be reduced.

  In addition, since the leakage current when the second transistor is off can be reduced, a silicon oxide film that can further stabilize the threshold voltage can be used as the gate insulating film. As a result, it is possible to perform image display without display unevenness with a simple pixel circuit.

  Other effects of the present invention will become apparent from the description of the entire specification.

It is sectional drawing for demonstrating schematic structure of the amorphous oxide semiconductor transistor in the organic electroluminescence display which is a display apparatus of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is process drawing for demonstrating the manufacturing method of the 1st and 2nd transistor in the organic electroluminescence display of embodiment of this invention. It is a circuit diagram for demonstrating schematic structure of the pixel circuit of the organic electroluminescence display of embodiment of this invention. It is a figure for demonstrating operation | movement of the pixel circuit of the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a top view for demonstrating the manufacturing method of the pixel circuit in the organic electroluminescence display of embodiment of this invention. It is a perspective view for demonstrating schematic structure of the organic electroluminescence display which is a display apparatus of embodiment of this invention. It is sectional drawing in the AA of FIG. It is a figure for demonstrating operation | movement of the pixel circuit of the organic electroluminescence display of other embodiment of this invention. It is a figure for demonstrating the gate voltage-drain current characteristic at the time of forming a transistor with the conventional amorphous oxide semiconductor.

  Hereinafter, an example of an embodiment to which the present invention is applied will be described with reference to the drawings. However, in the following description, the same components are denoted by the same reference numerals, and repeated description is omitted.

(Embodiment 1)
<Overall configuration>
FIG. 19 is a perspective view for explaining a schematic configuration of an organic EL display device which is a display device according to an embodiment of the present invention, and FIG. 20 is a cross-sectional view taken along line AA of FIG.

  As shown in FIG. 19, the organic EL display device of this embodiment is composed of a TFT substrate (first substrate) 19-1 on which an OLED layer is formed and a sealing glass (second substrate) 19-2. Yes. The TFT substrate 19-1 and the sealing glass 19-2 are fixed by a sealing sealant 19-3, and the TFT substrate 19-1 and the sealing glass 19-2 are held in a vacuum. It has become.

  In addition, OLEDs (organic light emitting diodes, organic electroluminescent elements, light emitting layers) that emit light to R (red), G (green), and B (blue) that become pixels within the region surrounded by the sealing material 19-3 Each pixel is arranged in a matrix in the x and y directions in the figure, and a pixel region 19-4 is formed.

  Furthermore, an electrode line formed on the TFT substrate 19-1 and connected to each pixel extends beyond the sealing seal material 19-3 to the outside of the pixel region 19-4. A terminal portion 19-5 is formed at the end of the electrode line, and a control signal is input from the outside to the pixel formed on the TFT substrate 19-1.

  Further, in the present embodiment, the control signal input from the outside is a video signal corresponding to the light emission amount of each pixel, a video signal writing to each pixel, a gate signal serving as one power source during light emission, and the other And a power supply that supplies a power supply voltage of 6V. Therefore, in the organic EL display device of the present embodiment, the video signal line for inputting the video signal, the gate signal line for inputting the gate signal, and the power supply line for supplying the power supply are provided outside the sealing seal material 19-3. It becomes the structure pulled out to. The detailed configuration of the pixel circuit of this embodiment (a circuit for one pixel cell) will be described later.

  In addition, when a signal line for designating writing of a video signal to each pixel and a power supply line for supplying one power supply are formed separately as in a conventional pixel circuit, electrode lines and terminals corresponding to each are formed. The present invention can be applied by forming the portion 19-5.

  As shown in FIG. 20, the organic EL display device of the present embodiment has a configuration in which pixels are formed in a region between the TFT substrate 19-1 and the sealing glass 19-2. In addition, since the light emitting material used for the light emitting layer has a very weak property to humidity, a known transparent desiccant 20-5 is formed inside the sealing glass 19-2, that is, on the pixel forming side in this embodiment. It is the composition which becomes.

  Further, a cathode electrode 20-2 and a pixel separation film 20-1 of the light emitting layer (OLED) are formed on the upper surface side (pixel formation side) of the TFT substrate 19-1, and this cathode electrode 20-2. In addition, a light emitting layer (OLED, light emitting portion) 20-3 and an anode electrode 20-4 made of a known transparent electrode material are formed on the pixel separation film 20-1. As will be described later, since the organic EL display device of the present invention is configured to use an oxide semiconductor FET which is an n-type semiconductor, each pixel has a top anode type configuration. It is possible to configure the pixel of the present invention in combination with a top cathode type light emitting layer (OLED). In this case, however, the driving voltage of the peripheral circuit needs to be several V higher than the configuration of the top anode type. There is.

  The distance between the TFT substrate 19-1 and the sealing glass 19-2 is determined by the thickness of the transparent desiccant 20-5. In this embodiment, a part of the transparent desiccant 20-5 is an anode. It is the structure which contacts the electrode 20-4. Note that the entire surface of the transparent desiccant 20-5 may be in contact with the anode electrode 20-4.

  Furthermore, since the organic EL display device of this embodiment is a so-called top emission type display device, each RGB light emitted from the OLED layer 20-3 of each pixel is transparent to the anode electrode 20-4. It becomes the structure radiate | emitted in the arrow 20-6 direction through the desiccant 20-5 and the sealing glass 19-2. The present invention can also be applied to a so-called bottom emission type organic EL display device.

  In this embodiment, the sealing seal material 19-3 is configured using a known epoxy resin, and the transparent desiccant 20-5 is configured using a known aluminum alkoxide of a polymer alcohol. In addition, the sealing sealing material 19-3 and the transparent desiccant 20-5 are not limited to the said material, Other materials may be sufficient.

<Configuration of pixel circuit>
FIG. 11 is a circuit diagram for explaining the schematic configuration of the pixel circuit of the organic EL display device of the present invention, and FIG. 12 is a diagram for explaining the operation of the pixel circuit of the organic EL display device of the present invention. Note that the structure of the pixel circuit is not limited to this, and the present invention can also be applied to a pixel circuit having a circuit that compensates for variations in transistors in each pixel circuit. Further, the pixel circuit shown in FIG. 11 is a pixel circuit for 4 pixels of 2 × 2.

  As shown in FIG. 11, the pixel circuit of the present invention has a light emitting layer (OLED) that is a diode D, and a power supply line (common electrode line) that supplies a power supply voltage of 6V that is one power supply voltage to the light emitting layer (OLED). ) V1, the first transistor T1 that controls the current flowing through the diode D, that is, the light emission amount of the light emitting layer (OLED), the gate signal line VSS that also functions as the other power supply line, and the drain-source terminal of the first transistor T1 A capacitor C connected in parallel, a second transistor T2 for writing a video signal for at least one frame to the capacitor C, and a video signal line DATA for supplying a video signal to the second transistor T2. Yes.

  Hereinafter, the configuration of the pixel circuit of this embodiment shown in FIG. 11 will be described in detail.

  The power supply voltage of 6V is applied to the anode side of the diode D through the power supply line V1. The cathode side of the diode D is connected to the gate signal line VSS via the first transistor T1, and a current corresponding to the voltage applied to the gate terminal of the first transistor T1 causes the diode D to pass through the diode D. The light emission amount of the light emitting element is controlled.

  Further, a capacitor C is formed between the gate and source of the first transistor T1, and the drain terminal of the second transistor T2 is connected to one end of the capacitor C, that is, the gate terminal of the first transistor T1. It is the composition which becomes. On the other hand, the source terminal of the second transistor T2 is connected to the video signal line DATA that supplies the video signal, and the video signal is written to the capacitor C. At this time, since one end of the capacitor C is connected to the gate terminal of the first transistor T1, the voltage corresponding to the video signal written to the capacitor C is applied to the gate of the first transistor T1 for at least one frame period. Will be applied. The details of the video signal writing operation will be described later.

  Further, the gate terminal of the second transistor T2 is connected to the gate signal line VSS, and the video signal line DATA connected to the source terminal in accordance with the write signal applied to the gate signal line VSS. The video signal is written to the capacitor C.

  Next, the operation of the pixel circuit of this embodiment will be described in detail based on FIG. However, in the following description, only the operation of the upper left pixel circuit in FIG. 11 will be described. 12 shows the voltage waveform applied to the gate signal line VSS and the video signal line DATA connected to the upper left pixel circuit in FIG.

  In the period t1 to t2, since the voltage of 0 V is applied to the gate terminal of the second transistor T2, the second transistor T2 is in an off state. For this reason, the electric charge stored in the writing operation one frame before is held in the capacitor C, and a voltage corresponding to the electric charge of the capacitor C is applied to the gate terminal of the first transistor T1. Accordingly, the first transistor T1 passes a current corresponding to the electric charge of the capacitor C to the diode D, and the diode D continuously emits light with a light emission amount corresponding to the current. At this time, in the organic EL display device of the present embodiment, the second transistor T2 formed of an amorphous oxide semiconductor has a configuration in which two gate electrodes are formed in parallel in the same active layer of the second transistor T2. Since the leakage current between the source and drain of the transistor T2 is greatly reduced, the charge written in the capacitor C can be held for one frame period.

  In the period t2 to t3, the write voltage V2 is applied to the gate terminal of the second transistor T2, and the second transistor T2 is turned on. For this reason, the video signal Vd1 supplied to the video signal line DATA during this period is applied (written) to the capacitor C via the second transistor T2. Accordingly, the video signal Vd1 is applied to the gate terminal of the first transistor T1, and the first transistor T1 causes a current corresponding to the applied voltage Vd1 to flow through the diode D, and the diode D continues with a light emission amount corresponding to the current. Emits light.

  In the period t3 to t4, since the voltage of 0V is applied again to the gate terminal of the second transistor T2, the second transistor T2 is turned off. The applied voltage Vd1 stored in the writing operation in the period t2 to t3 is held in the capacitor C, and the applied voltage Vd1 is applied to the gate terminal of the first transistor T1. Accordingly, the first transistor T1 causes a current corresponding to the applied voltage Vd1 written in the capacitor C to flow through the diode D, and the diode D continuously emits light with a light emission amount corresponding to the current.

  Note that in the period after t4, until the next writing period, the same operation as in the period t3 to t4 is performed, and the pixel circuit continues to emit light with the light emission amount corresponding to the applied voltage Vd1. In addition, since the same light emission operation is performed in other pixel circuits, a desired image display can be performed.

  Furthermore, in the organic EL display device of the present embodiment, since the first transistor T1 is also formed of an amorphous oxide semiconductor, the diode D can emit light stably.

<Structure of transistor>
FIG. 1 is a cross-sectional view for explaining a schematic configuration of an amorphous oxide semiconductor transistor in the organic EL display device of the present embodiment.

  As shown in FIG. 1, in the transistor of this embodiment, an aluminum oxide barrier layer 2 is formed on the surface of a glass substrate 1, and an InGaZnOx film 5 serving as an active layer of an oxide semiconductor is formed on the barrier layer 2. It is the composition which becomes. By adopting such a configuration, impurities are prevented from entering the InGaZnOx film 3 from the glass substrate 1 which causes the threshold voltage Vth of the transistor to shift.

  On the InGaZnOx film 3, an SD wiring 4 of a Mo film that becomes the source or drain of the amorphous oxide semiconductor transistor is formed so as to be separated with a channel portion that becomes an active layer interposed therebetween. The SD wiring 4 made of this Mo film has a shape with rounded corners.

  A gate insulating film 5 made of a silicon oxide film (SiOx film, silicon oxide film) is formed on the SD wiring 4 and the channel portion is formed to have a film thickness of about 50 nm. In the present embodiment, the SiOx film annealed at a high temperature is used as the gate insulating film 5 in order to prevent a threshold voltage shift, which is a drawback when the SiOx film is used as the gate insulating film 5. .

  A gate wiring 6 having a three-layer structure of Mo / Al / Mo is formed on the gate insulating film 5 in the channel portion. At this time, in the present embodiment, the gate wiring 6 is formed with a thickness that is at least twice as large as the step of the base layer as a configuration for preventing the disconnection of the gate wiring 6. In the present embodiment, the contact hole portion of the gate insulating film 5 provided above the wiring on the side that becomes the drain electrode in the SD wiring 4 is the same layer as the gate wiring 6 and the same thin film as the gate wiring material. A thin film layer made of a material is formed. The thin film layer is configured to be electrically connected to the wiring on the side that becomes the drain electrode in the SD wiring 4.

  On the upper layer of the gate wiring 6, a function of a flattening film for flattening irregularities on the front surface of the glass substrate 1 due to formation of a transistor and a wiring layer (not shown) and a function as a protective film for the transistor and a wiring layer (not shown) An insulating film 7 made of a photosensitive polyimide resin having is formed.

  An electrode layer 8 of a light emitting layer (OLED, diode) made of ITO / Ag / ITO laminated film is formed on the insulating film 7, and a pixel separation film 9 made of photosensitive polyimide is formed on the electrode layer 8. Has been.

  This embodiment is a TFT substrate having a configuration in which an amorphous oxide semiconductor transistor having such a configuration is used for driving a light emitting layer.

<Manufacturing method of transistor>
2 to 10 are process diagrams for explaining a method of manufacturing the first and second transistors in the organic EL display device of the present embodiment. Hereinafter, the manufacturing method will be described in order of steps based on FIGS. 2 to 10. To do. In addition, since formation of the thin film including formation of the electrode in each process is possible by a well-known photolithography technique, detailed description is abbreviate | omitted.

Step 1. (Figure 2)
First, an aluminum oxide film is formed as a barrier layer 2 on the surface of the glass substrate 1 by a sputtering method, and subsequently, an InGaZnOx film 3 that becomes an active layer of an oxide semiconductor and a source wiring or a drain wiring (hereinafter referred to as a transistor wiring) of a transistor. The Mo film to be 4) (abbreviated as SD wiring) is continuously formed. The film thickness at this time is about 70 nm for the aluminum oxide film, about 60 nm for the InGaZnOx film 3, and about 180 nm for the Mo film.

Step 2. (Figure 3)
Next, a pattern for forming a source or drain wiring (SD wiring) 4 by forming a Mo film (SD pattern) and a pattern for forming a channel portion serving as an active layer in the InGaZnOx film 3 are formed with a photoresist 10. Form. However, this pattern is formed by exposing using a photomask made like a half mirror so that the channel portion is formed thin. In the pattern of the photoresist 10, the resist film thickness in the SD portion is 1.4 μm, and the channel portion is 0.4 μm.

Step 3. (Fig. 4)
Next, the Mo film (both sides in the figure) to be the SD wiring 4 and the InGaZnOx film 3 (both sides in the figure) are etched by wet etching using the photoresist 10 formed in step 2. At this time, the Mo film is wet-etched using a mixed acid of phosphoric acid, acetic acid, and nitric acid. The InGaZnOx film 3 is wet etched using oxalic acid. Thereafter, the photoresist 10 is removed by a thickness of about 0.6 μm by plasma ashing to expose the Mo film in the channel portion, and the photoresist 10 in the SD wiring portion is also narrowed in the drawing. Thereafter, the Mo film is wet-etched again using a mixed acid of phosphoric acid, acetic acid, and nitric acid to remove the Mo film in the channel portion and remove both sides of the Mo film in the drawing to remove the Mo film from the InGaZnOx film 3. Reduce the width of the pattern in the figure.

  By adopting such a shape, it is possible to eliminate a portion where the SD wiring 4 goes over the InGaZnOx film 3 (oxide semiconductor layer), and it is possible to avoid disconnection of the SD wiring 4 due to a step. In addition, with the configuration in which the SD wiring 4 is formed smaller than the InGaZnOx film 3 (oxide semiconductor layer), it is possible to easily cover the stacked portion (the SD wiring 4 portion) with a gate insulating film described later.

  Furthermore, in this embodiment, in order to further facilitate the cover with the gate insulating film, first, the corner portion of the SD wiring 4 formed of the Mo film is oxidized by performing ashing after the photoresist 10 is peeled off. Then, it is set as the shape which rounded the corner | angular part of SD wiring 4 by washing with water.

Step 4. (Fig. 5)
Next, a gate insulating film 5 is formed, and a contact hole 11 is formed in the gate insulating film 5 by photolithography. The gate insulating film 5 is formed by decomposing TEOS (4 ethyloxysilane) gas and oxygen by plasma CVD to form a SiOx film. The contact hole 11 is formed by wet etching, and buffered hydrofluoric acid is used as an etchant. In this way, the gate insulating film 5 having a thickness of about 50 nm is formed. In addition, an inclined region 12a is formed at the edge of the gate wiring formation region 12 (the upper end of the edge). The inclined region 12a is formed in such a manner that when a gate wiring is formed in a later process, both ends of the gate wiring and the end of the SD wiring overlap with each other through the gate insulating film 5. This is because the channel region between the source and the gate is formed smoothly.

  However, deep defect levels in the SiOx film prepared by the plasma CVD method can be eliminated by high-temperature annealing. Therefore, in this embodiment, annealing is performed at 400 ° C. or higher, preferably 450 ° C. to 550 ° C. Reduce to an extent that is practically acceptable. Note that the deep defect level in the gate insulating film is that electrons gathered at the interface between the gate insulating film 5 and the InGaZnOx film 3 (oxide semiconductor layer) enter the fixed charge when the transistor is turned on. This causes the threshold voltage of the transistor to shift.

Step 5. (Fig. 6)
Next, the gate wiring 6 is formed. At this time, the gate wiring 6 is formed so that both ends of the gate wiring 6 and the end of the SD wiring 4 overlap with each other with the gate insulating film 5 interposed therebetween. The gate wiring 6 of this embodiment has a three-layer structure of Mo / Al / Mo, and has a thickness of 500 nm in total of Mo: 50 nm, Al: 400 nm, and Mo: 50 nm in order to prevent disconnection due to a step. In the present embodiment, since the base level difference is 240 nm, the thickness of the gate wiring 6 is approximately doubled to prevent disconnection. Therefore, the thickness of the gate wiring 6 is not limited to 500 nm. For example, when the InGaZnOx film 3 (oxide semiconductor layer) has a thickness of 40 nm and the SD wiring 4 has a thickness of 120 nm, Even if the thickness of the wiring layer 6 is about 350 nm, disconnection can be prevented. In addition, in order to make the contact hole 11 shallow and easily open, the gate wiring material 6a in the contact hole portion is left.
Step 6. (Fig. 7)
Next, an insulating film 7 is formed to insulate the wiring of the transistor and the electrode of the light emitting layer (OLED, diode). The insulating film 7 is formed by applying a photosensitive polyimide to the upper layer by a known spin coating method or the like and then developing it by exposure. After the formation of the insulating film 7, a contact hole 13 for electrically connecting the electrode of the light emitting layer (OLED, diode) and the SD wiring 4 is formed on the gate insulating material 6a by well-known photolithography. In addition, since the unevenness of the substrate surface accompanying the formation of the transistor and the wiring can be smoothed by using the coating type insulating film 7, the effect of eliminating corners that cause light scattering can be obtained. . The film thickness of this polyimide, that is, the film thickness of the insulating layer 7 is about 1.5 μm.

Step 7. (Fig. 8)
Next, an ITO / Ag / ITO laminated film to be the electrode 8 of the light emitting layer (OLED, diode) is formed. The ITO / Ag / ITO laminated film is formed by sequentially sputtering ITO, Ag, and ITO in order, and then forming the ITO / Ag / ITO laminated film into a predetermined pattern by well-known photolithography. Etching of ITO can be performed with oxalic acid, and etching of Ag can be performed with a mixed acid of phosphoric acid, acetic acid, and nitric acid, but is not limited thereto. From the bottom (from the glass substrate 1 side), the thickness of the ITO layer is about 50 nm, the thickness of the Ag layer is about 150 nm, and the thickness of the ITO layer is about 30 nm.

Step 8. (Fig. 9)
Next, the pixel separation film 9 is formed. The pixel separation film 9 is formed by forming an opening in the upper part of the electrode 8 after applying photosensitive polyimide by a known spin coating method or the like, exposing and developing it.

  Through the above steps 1 to 8, a transistor array substrate for actively driving the light emitting layer (OLED, diode) is completed.

  However, in the organic EL display device of the present embodiment, the configuration of the gate electrode is different between the first transistor and the second transistor. Hereinafter, a method for manufacturing the second transistor will be described.

  As shown in FIG. 10, the second transistor has a configuration in which two gate wirings 14a and 14b are formed in parallel between the SD wirings 4 formed apart from each other, that is, in the same active layer region.

  Such gate wiring is formed by etching the Mo layer, etching the Al layer, and etching the Mo layer when forming the gate wiring having the three-layer structure of Mo / Al / Mo in Step 5 described above. By forming the two gate wirings 14a and 14b, the subsequent steps are the same as those of the first transistor manufacturing method described above.

  At this time, in this embodiment, the gate wiring 6 of the first transistor shown in FIG. 9 is divided into two parts on the source side and the drain side, so that one gate wiring 14a has an end portion of the source wiring. The other gate wiring 14b is configured to overlap with the end of the drain wiring.

  With such a structure, the oxide semiconductor can achieve an effect that is more than double the resistance of the transistor, and can significantly reduce the leakage current between the source and the drain. In other words, since two transistors are connected in series, the resistance alone doubles, but the oxide transistor has the characteristic that the mobility decreases when the number of carriers decreases, so that the carrier leaks from the source. As a result, the carrier concentration in the channel portion that should be depleted originally increases, so that the mobility increases and the leakage current increases. For this reason, in this embodiment, the gates are continuously provided (two gate wirings are formed side by side) to stop carriers from the source at the first gate and to reduce the carrier density between the gate electrodes. As a result, the effect more than double the transistor resistance can be obtained, and the leakage current between the source and drain can be greatly reduced. Furthermore, in this embodiment, each end portion of the two gate wirings 14a and 14b is overlapped with either end portion of the source wiring or the drain wiring. The effect that the increase in the ON resistance of the two transistors can be minimized is also obtained.

<Manufacturing method of pixel circuit>
FIGS. 13 to 18 are plan views for explaining a method of manufacturing a pixel circuit in the organic EL display device of the present embodiment. Hereinafter, the manufacturing method will be described in order based on FIGS. In addition, since formation of the thin film including formation of the electrode in each process is possible by a well-known photolithography technique, detailed description is abbreviate | omitted.

Step 1. (Fig. 13)
First, after forming an oxide semiconductor layer (InGaZnOx layer) for forming an active layer of an oxide semiconductor on the upper surface (TFT element formation) side of a glass substrate (not shown) on which a barrier layer is formed on the substrate surface, SD An electrode layer pattern to be a wiring layer and a signal line (video signal wiring layer) is formed. In FIG. 13, the SD electrode pattern 13-1 of the first transistor and one electrode of the pixel capacitor are disposed in the region between two adjacent signal line patterns 13-3 for applying a write voltage to each pixel capacitor. An electrode layer pattern which is the pattern 13-2 and becomes the SD electrode pattern of the second transistor is formed.

  As is apparent from FIG. 13, the oxide semiconductor layer pattern 13-5 and the SD wiring layer pattern 13-1 are almost overlapped, and the SD wiring layer pattern 13-1 is the oxide semiconductor layer pattern 13-. Therefore, the SD wiring layer pattern 13-1 is not disconnected at the level difference of the oxide semiconductor layer pattern 13-5. Further, in a portion where a gate wiring layer pattern to be described later crosses over the SD wiring layer pattern 13-1, the SD wiring layer pattern is provided with unevenness 13-4. By forming the projections and depressions 13-4 in this way, it is possible to avoid a phenomenon in which the overpass line has a curved shape and the etching solution penetrates between the resist and the gate wiring material to cause disconnection when the gate wiring is etched.

Step 2. (Fig. 14)
Next, a gate insulating film pattern 14-2 is formed on the upper surface of a glass substrate (not shown). A portion where a gate wiring layer pattern and an SD wiring layer pattern 13-1 described later are electrically connected, and a portion where the SD wiring pattern 13-1 and an electrode of a light emitting layer (OLED, diode) are electrically connected are The contact hole 14-1 is formed.

Step 3. (Fig. 15)
Next, a gate wiring pattern and a signal line pattern are formed. In this step, the gate electrode pattern 15-1 of the first transistor T1, the gate electrode pattern 15-4 of the second transistor T2, and the other electrode pattern 15-2 of the pixel capacitor C are formed. Furthermore, the power supply of the light emitting layer (OLED, diode) and the wiring pattern 15-3 for sending an open / close signal (gate signal) to the second transistor (write transistor) are formed. In particular, in the present embodiment, as the gate electrode pattern 15-5 of the second transistor T2, a double gate electrode pattern 15-5, that is, two gate electrode patterns 15-5 provided side by side are formed.

  Further, in the formation of the capacitor, the electrode pattern 13-2 in the same layer as the SD wiring layer and the electrode pattern 15-2 in the same layer as the gate wiring layer are formed so as to overlap with each other through the gate insulating film 14-2. In the present embodiment, the pattern on the gate wiring layer side (electrode pattern 15-2 in the same layer as the gate wiring layer) is changed to the pattern on the SD wiring layer side (electrode pattern 13-2 in the same layer as the SD wiring layer). In other words, the pattern on the gate wiring layer side is formed smaller than the pattern on the SD wiring layer side so as not to protrude from the pattern on the SD wiring layer side. Avoiding that happening.

  Further, in the present embodiment, the contact hole portion 14-1 of the gate insulating film 14-2 is formed by leaving all the gate wiring material pattern 15-4 in the contact hole portion 14-1, thereby increasing the contact hole portion 14-1. The coating thickness of the photosensitive polyimide in the contact hole portion provided in the photosensitive polyimide layer in the later-described process is reduced, and the contact hole is surely opened.

Step 4. (Fig. 16)
Next, a photosensitive polyimide layer pattern 16-2 for smoothing irregularities on the surface of the glass substrate (not shown) is formed. After the formation of the photosensitive polyimide layer pattern 16-2, a contact hole pattern 16-1 for electrically connecting the electrode of the light emitting layer (OLED, diode) and the SD wiring pattern 13-1 is formed as a gate wiring material pattern 15 -4 part.

Step 5. (Fig. 17)
Next, an electrode pattern 17-1 of a light emitting layer (OLED, diode) is formed in a region between two adjacent signal line patterns 13-3. The light emitting layer (OLED, diode) electrode pattern 17-1 is electrically connected to the SD wiring pattern 13-1 through a contact hole 16-1 provided in the photosensitive polyimide layer pattern 16-2.

Step 6. (Fig. 18)
Next, after forming a photosensitive polyimide layer on a glass substrate surface (not shown), an opening 18-1 is formed above the light emitting layer (OLED, diode) electrode pattern 17-1, thereby forming a pixel separation film pattern. . However, when the opening 18-1 is formed, the opening 18-1 so that the peripheral part of the light emitting layer (OLED, diode) electrode pattern 17-1 and the contact hole 16-1 are covered with the photosensitive polyimide layer. Is formed so that the light emitting layer (OLED, diode) electrode pattern (cathode) 17-1 and the anode are not short-circuited.

  The transistor array substrate is manufactured as described above.

  Next, a procedure for creating a light emitting layer (OLED, diode) on the transistor array substrate will be described.

  First, a first substance and a second substance having an electron transporting property are co-deposited on the upper portion of the opening 18-1 of the light emitting layer (OLED, diode) electrode pattern (cathode) 17-1 provided on the transistor array substrate. Thus, an electron injection layer is formed.

  Next, a first material is deposited on the electron injection layer to form an electron transport layer. The film thickness of the electron transport layer varies depending on each emission color, and is 130 nm for red, 100 nm for green, and 70 nm for blue.

  Next, a light emitting layer is formed on the electron injection layer. At this time, when forming the red light emitting layer, the film thickness is 60 nm, when forming the green light emitting layer, the film thickness is 60 nm, and when forming the blue light emitting layer, the film thickness is also 60 nm. .

  Next, a hole transport layer is formed with a third substance on the light emitting layer.

  Next, a hole injection layer is formed on the hole transport layer. The thickness of the hole injection layer is 10 nm.

  Next, an organic EL device is configured by forming an anode electrode having a thickness of 30 nm on the hole injection layer by sputtering of IZO. The organic EL device emits light when a negative voltage is applied to the cathode electrode and a positive voltage is applied to the upper anode electrode.

  The first substance is not particularly limited as long as it exhibits electron transport properties and can be easily formed into a charge transfer complex by co-evaporation with an alkali metal. For example, tris (8-quinolinolato) aluminum, tris (4- Metal complexes such as methyl-8-quinolinolato) aluminum, bis (2-methyl-8-quinolinolato) -4-phenylphenolate-aluminum, bis [2- [2-hydroxyphenyl] benzoxazolate] zinc and 2- (4-Biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole, 1,3-bis [5- (p-tert-butylphenyl) -1,3,4- Oxadiazol-2-yl] benzene and the like can be used.

  The second substance is not particularly limited as long as it is a material that exhibits an electron donating property with respect to the electron transporting substance. For example, alkali metals such as lithium and cesium, alkaline earth metals such as magnesium and calcium, Further, a metal exhibiting an electron donating property selected from metals such as rare earth metals, or oxides, halides, carbonates and the like thereof can be used.

  The third substance is a substance exhibiting hole transport properties, such as a tetraarylbenzidine compound (triphenyldiamine: TPD), an aromatic tertiary amine, a hydrazone derivative, a carbazole derivative, a triazole derivative, an imidazole derivative, An oxadiazole derivative having an amino group, a polythiophene derivative, a copper phthalocyanine derivative, or the like can be used.

As the material used for the hole injection layer may be an inorganic material such as MoO _{3 or, WO 3, V 2 O 5} . By using such a substance as the hole injection layer, it is possible to avoid deterioration of the organic material even when the anode electrode IZO is sputtered.

  The light-emitting material used for the light-emitting layer is a host material having the ability to transport electrons and holes to which a dopant that emits fluorescence or phosphorescence is added by recombination thereof, and can be formed as a third layer by co-evaporation. The host is not particularly limited, and examples of the host include tris (8-quinolinolato) aluminum, bis (8-quinolinolato) magnesium, bis (benzo {f} -8-quinolinolato) zinc, bis (2-methyl-8). -Quinolinolato) aluminum oxide, tris (8-quinolinolato) indium, tris (5-methyl-8-quinolinolato) aluminum, 8-quinolinolatolithium, tris (5-chloro-8-quinolinolato) gallium, bis (5-chloro) -8-quinolinolato) calcium, 5,7-dichloro-8-quinolinolato Luminium, tris (5,7-dibromo-8-hydroxyquinolinolato) aluminum, complexes such as poly [zinc (II) -bis (8-hydroxy-5-quinolinyl) methane], anthracene derivatives, carbazole derivatives, etc. Can be used.

  The dopant captures electrons and holes in the host and recombines to emit light. For example, a red light emitting substance such as a pyran derivative, a green coumarin derivative, and a blue anthracene derivative can be used. . In addition, a phosphorescent substance such as an iridium complex or a pyridinate derivative may be used.

  The uppermost layer, that is, the anode electrode uses ITO or IZO, which is a transparent conductive film, to extract light.

  Note that since the light emitting layer is vulnerable to moisture, it is necessary to enclose and seal it with dry nitrogen or the like. Or, considering that moisture enters from the outside, it is also possible to place a desiccant inside as in this embodiment. Furthermore, it may be sealed with frit glass or the like so that moisture does not enter at all. Further, in the top emission type organic EL display device as in the present embodiment, the sealing glass is transparent, and light is emitted through the sealing glass.

  In the organic EL display device of the present embodiment, the annealed silicon oxide film is used as the gate insulating film of the amorphous oxide semiconductor forming the first and second transistors. However, the present invention is not limited to this. For example, a SiN film formed by plasma CVD may be used as the gate insulating film.

  In addition, when the first and second transistors are formed of an amorphous oxide semiconductor using a silicon oxide film as the gate insulating film, when the SiN film is used as the passivation film, the SiN film is formed on the outer side, that is, the upper layer than the gate insulating film. There is a need to.

  As described above, in the organic EL display device of this embodiment, when forming the second transistor as the switching transistor as shown in FIG. 10, the two gate electrodes 14a are formed in the same semiconductor region, that is, in the same channel portion. , 14b are arranged side by side. At this time, since the same selection signal (gate signal) is input to the two gate electrodes as shown in FIG. 15, the carrier from the source electrode is stopped at the first gate electrode 13b, and the carrier density between the gate electrodes. By reducing the value, the effect more than double the transistor resistance can be obtained. As a result, even when the second transistor that is an oxide semiconductor is used in a pixel circuit of an organic EL display device, the leakage current when the second transistor is off can be reduced.

  In addition, since the leakage current when the second transistor is off can be reduced, a silicon oxide film that can further stabilize the threshold voltage can be used as the gate insulating film. As a result, even in the organic EL display device, it is possible to perform image display without display unevenness with a simple pixel circuit.

  In the organic EL display device according to the embodiment of the present invention, the gate electrode of the second transistor is formed by two gate electrodes arranged in parallel. However, the gate electrode of the second transistor is the gate of the first transistor. In the case of forming a single electrode as in the case of the electrode, as shown in FIG. 21, the channel voltage may be depleted by setting the gate voltage when the second transistor is OFF to be negative.

DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2 ... Barrier layer, 3 ... InGaZnOx film | membrane 4 ... SD wiring, 5 ... Gate insulating film, 6 ... Gate wiring 6a ... Gate wiring material, 7 ... Insulating film, 8 ... Electrode of light emitting layer 9 ... Pixel isolation film, 10 ... Photoresist, 11 ... Contact hole 12 ... Gate wiring formation region, 12a ... Inclined region , 13 ... contact holes 14a, 14b ... gate wiring, 13-1 ... SD electrode pattern 13-2 ... pixel capacitor electrode pattern, 13-3 ... signal line pattern 13-4 ..Concavities and convexities of the wiring pattern, 13-5... Oxide semiconductor layer pattern 14-1... Contact hole, 14-2... Gate insulating film pattern 15-1. ... Pixel capacitors Electrode pattern 15-3 ... Wiring pattern, 15-4 ... Gate electrode pattern 15-5 ... Gate electrode pattern, 16-1 ... Contact hole pattern 16-2 ... Photosensitive polyimide Layer pattern, 17-1 ... Electrode pattern of light emitting layer 18-1 ... Opening, 19-1 ... TFT substrate, 19-2 ... Sealing glass 19-3 ... Sealing seal Material: 19-4: Pixel region, 19-5: Terminal portion 20-1: Pixel separation film, 20-2: Cathode electrode, 20-3: OLED layer 20-4, ..Anode electrode, 20-5 ... transparent desiccant T1 ... first transistor, T2 ... second transistor, C ... capacitor D ... diode, V1 ... power supply line (common electrode) Line), DATA ... Video signal line VSS ... G Door signal line

Claims (10)

A light emitting element that emits light in response to an electric current;
A first transistor for applying a driving voltage to the light emitting element;
A capacitive element that applies a predetermined voltage to the gate terminal of the first transistor for at least one frame period;
A display device in which pixel circuits each including at least a second transistor that writes an image signal to the capacitive element based on a selection signal are arranged in a matrix,
It said first and second transistors, a thin film transistor of a coplanar type source and drain electrodes, and the gate electrode are arranged on the same side of the semi-conductor layer,
The semiconductor layers of the first and second transistors are formed of an oxide semiconductor;
The second transistor includes two gate electrodes formed side by side so as to overlap an active layer region of the same transistor, and the same selection signal is input to the two gate electrodes. Display device. The display device according to claim 1,
The display device , wherein the semiconductor layers of the first and second transistors are formed of an N-type oxide semiconductor. The display device according to claim 1 or 2,
Of the two gate electrodes,
A part of one gate electrode is formed so as to overlap the source electrode,
A part of the other gate electrode is formed so as to overlap with the drain electrode. The display device according to any one of claims 1 to 3,
The display device , wherein the semiconductor layers of the first and second transistors are formed of an InGaZnOx-based oxide semiconductor. The display device according to any one of claims 1 to 4,
The display device, wherein the first and second transistors have a gate insulating film formed of a silicon oxide film. The display device according to claim 5,
The display device, wherein the silicon oxide film is an annealed film. The display device according to any one of claims 1 to 4,
The display device according to claim 1, wherein the first and second transistors have a gate insulating film formed of a SiN film. The display device according to claim 1,
The display device, wherein the light emitting element is an EL element. The display device according to any one of claims 1 to 8,
The display device is a top emission type display device. The display device according to any one of claims 1 to 8,
The display device, wherein the second transistor is driven by a selection signal of 0 V or more.

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