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JP6626639B2 - Method of manufacturing substrate for semiconductor device - Google Patents

Method of manufacturing substrate for semiconductor device Download PDF

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Publication number
JP6626639B2
JP6626639B2 JP2015109407A JP2015109407A JP6626639B2 JP 6626639 B2 JP6626639 B2 JP 6626639B2 JP 2015109407 A JP2015109407 A JP 2015109407A JP 2015109407 A JP2015109407 A JP 2015109407A JP 6626639 B2 JP6626639 B2 JP 6626639B2
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semiconductor device
resist layer
semiconductor element
substrate
metal
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JP2016225430A (en
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佑也 五郎丸
佑也 五郎丸
真幸 林田
真幸 林田
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Maxell Ltd
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Maxell Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、底部に電極等の金属部が露出する形態の半導体装置を製造するのに用いる半導体装置用基板に関する。   The present invention relates to a semiconductor device substrate used for manufacturing a semiconductor device in which a metal portion such as an electrode is exposed at the bottom.

半導体素子規制用の基板上に半導体素子を搭載し、半導体素子と外部導出用の金属端子とを配線接続した上で、樹脂等の保護材で半導体素子を含む基板全体を被覆した旧来の構造の半導体装置は、その構造上、小型化には限界があった。これに対し、半導体素子搭載部分や電極部分となる金属部を形成し、この金属部上に半導体素子を搭載し、配線等の処理後、半導体素子や配線等のある金属部の表面側を樹脂等の封止材で封止し、金属部が底部に一部露出した構成とされる半導体装置は、その高さを低くして省スペース化が図れる他、露出した金属部を通じて半導体素子で生じた熱を外部に放出でき、放熱の面で優れるといった特長を有しており、チップサイズなど超小型の半導体装置の分野で利用が進んでいる。   A semiconductor element is mounted on a substrate for regulating semiconductor elements, a wiring connection is made between the semiconductor element and a metal terminal for external derivation, and the entire substrate including the semiconductor element is covered with a protective material such as a resin. Semiconductor devices have a limit in miniaturization due to their structure. On the other hand, a metal part to be a semiconductor element mounting part and an electrode part is formed, a semiconductor element is mounted on this metal part, and after processing of wiring and the like, the surface side of the metal part with the semiconductor element and wiring is coated with a resin. The semiconductor device, which is sealed with a sealing material such as the above, has a configuration in which the metal part is partially exposed at the bottom, can reduce the height to save space, and can be generated in the semiconductor element through the exposed metal part. It has the feature of being able to emit heat to the outside and being excellent in heat dissipation, and is increasingly used in the field of ultra-compact semiconductor devices such as chip sizes.

こうした半導体装置は、主に、導電性を有する母型基板上に半導体素子搭載部分や電極部分となる金属部を、メッキを厚く形成する手法、いわゆる電鋳により、半導体装置の所望個数分まとめて形成し、半導体素子が搭載され配線等の処理を経た金属部の表面側を封止材で封止した後、母型基板のみを除去し、一体にまとまった状態の多数の半導体装置を個別に切り分ける、といった製造過程を経て製造される。このような半導体装置の製造方法の一例として、特開２００２−９１９６号公報や特開２００４−２１４２６５号公報に開示されるものがある。   Such a semiconductor device is mainly composed of a desired number of semiconductor devices by a technique of forming a metal portion serving as a semiconductor element mounting portion or an electrode portion on a conductive mother substrate with a thick plating, so-called electroforming. After forming and sealing the surface side of the metal part where the semiconductor element is mounted and processed wiring etc. with a sealing material, only the mother substrate is removed, and a large number of semiconductor devices in an integrated state are individually It is manufactured through a manufacturing process such as cutting. As an example of a method for manufacturing such a semiconductor device, there are those disclosed in JP-A-2002-9196 and JP-A-2004-214265.

特開２００２−９１９６号公報JP-A-2002-9196 特開２００４−２１４２６５号公報JP 2004-214265 A

従来の半導体装置の製造方法は前記特許文献に示される構成となっており、母型基板上への金属部の形成にあたり、母型基板における金属部の形成位置に対応するようにレジスト層をあらかじめ形成して、金属部が電解メッキの手法により適切な位置に形成するようにしていた。この金属部には、メッキによる形成に適したニッケル等の金属が使用されており、導電性や配線用ワイヤの接合性を高めるために、金属部表面には一般に金メッキや銀メッキが施されていた。このメッキに対しても、レジスト層が必要箇所以外へのメッキの付着を防ぐ役割を果していた。そして、このレジスト層を溶剤等で除去した上で、母型基板とその表面に形成された金属部が、半導体装置用基板として供給された。この半導体装置用基板を用いて、実際の半導体装置の製造工程において、半導体素子の搭載や配線、封止材による封止等を行うようにしていた。   The conventional method of manufacturing a semiconductor device has a configuration disclosed in the above-mentioned patent document, and in forming a metal portion on a master substrate, a resist layer is previously formed so as to correspond to a formation position of the metal portion on the mother substrate. Then, the metal part is formed at an appropriate position by an electrolytic plating technique. The metal portion is made of a metal such as nickel suitable for forming by plating, and the surface of the metal portion is generally gold-plated or silver-plated in order to enhance the conductivity and the bonding property of the wiring wire. Was. Also for this plating, the resist layer played a role of preventing the plating from adhering to places other than the necessary places. Then, after removing the resist layer with a solvent or the like, the mother substrate and the metal part formed on the surface thereof were supplied as a substrate for a semiconductor device. Using the semiconductor device substrate, mounting of semiconductor elements, wiring, sealing with a sealing material, and the like are performed in an actual semiconductor device manufacturing process.

近年、上記半導体装置用基板を用いて製造される半導体装置には、該半導体装置が用いられる電子機器のさらなる小型化を実現するために、低背化の要求がますます高まりつつあるが、これまでの構造では、半導体装置からの半導体素子搭載部分や電極部分の脱落を防止するために、半導体素子搭載部分や電極部分をなす金属部の薄型化には限界があり、さらに半導体素子自体も所定の強度を与えるために一定の厚さを確保する必要があり、さらなる薄型化、低背化が困難であるという課題を有していた。なお、半導体素子搭載部分をなくす構造も考えられるが、そうすると、半導体素子を搭載する際に、半導体素子の位置ズレが避けられなかった。   In recent years, semiconductor devices manufactured using the above-described semiconductor device substrate have been increasingly required to be reduced in height in order to further reduce the size of electronic devices in which the semiconductor devices are used. In the structures described above, there is a limit to the reduction of the thickness of the metal part forming the semiconductor element mounting part and the electrode part in order to prevent the semiconductor element mounting part and the electrode part from falling off from the semiconductor device. It is necessary to secure a certain thickness in order to give a sufficient strength, and there is a problem that it is difficult to further reduce the thickness and height. In addition, although a structure in which the semiconductor element mounting portion is eliminated is also conceivable, in that case, when the semiconductor element is mounted, a positional shift of the semiconductor element cannot be avoided.

本発明は前記課題を解消するためになされたもので、適切な箇所に規制部を設けて、得られる半導体装置各部の構造を最適化できると共に、効率よく半導体装置を製造できる、半導体装置用基板と当該基板の製造方法、並びに、この半導体装置用基板を用いて製造される半導体装置、及びその製造方法を提供することを目的とする。   The present invention has been made in order to solve the above-mentioned problems, and a semiconductor device substrate capable of optimizing a structure of each part of a semiconductor device to be obtained by providing a regulating part at an appropriate place and efficiently manufacturing a semiconductor device. And a method for manufacturing the substrate, a semiconductor device manufactured using the semiconductor device substrate, and a method for manufacturing the same.

本発明の開示に係る半導体装置用基板は、母型基板１０上に少なくとも電極部１１ｂとなる金属部１１が形成される半導体装置用基板において、母型基板１０上には、半導体素子１４を規制する規制部１１ａが設けられたものである。   The semiconductor device substrate according to the disclosure of the present invention is a semiconductor device substrate in which at least the metal portion 11 serving as the electrode portion 11 b is formed on the master substrate 10, wherein the semiconductor element 14 is regulated on the master substrate 10. This is provided with a regulating portion 11a.

このように本発明の開示によれば、母型基板１０上に半導体素子１４を規制するための規制部１１ａが設けられることにより、半導体装置用基板を用いた半導体装置の製造にあたり、半導体素子１４を搭載する際に、半導体素子１４の位置ズレを防止することができる。   As described above, according to the disclosure of the present invention, the regulation part 11 a for regulating the semiconductor element 14 is provided on the mother substrate 10, so that when the semiconductor device is manufactured using the semiconductor device substrate, When mounting the semiconductor device, misalignment of the semiconductor element 14 can be prevented.

また、本発明の開示に係る半導体装置用基板は、規制部１１ａが前記金属部１１に貫通孔１１ｅを形成することで設けられたものである。係る貫通孔１１ｅの形状は、半導体素子１４が収容可能な大きさとしている。   Further, in the substrate for a semiconductor device according to the disclosure of the present invention, the regulating portion 11 a is provided by forming the through hole 11 e in the metal portion 11. The shape of the through hole 11 e is set to a size that can accommodate the semiconductor element 14.

このように本発明の開示によれば、規制部１１ａが金属部１１に貫通孔１１ｅを形成することで設けられたものであり、該貫通孔貫通孔１１ｅの形状（大きさ）として、半導体素子１４が収容可能な大きさとなるようにすることにより、半導体装置製造の際に、半導体素子１４を貫通孔１１ｅ（規制部１１ａ）内に配設した場合、半導体素子１４の位置ズレを防止できるだけでなく、従来のように半導体素子搭載部の上面に搭載される場合と比べて、配設位置を下げることができ、半導体素子１１上面や、電極部１１ｂと半導体素子１４とを接合するワイヤ等の高さも下がる分、半導体装置の厚さを小さくして製造することができ、半導体装置の低背化を実現できる。また、半導体素子１４の位置が下がって、ワイヤ１５が接合する半導体素子１４と電極部１１ｂの各上面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ１５の使用量を削減してコストを低減できる。なお、貫通孔１１ｅの形状は、半導体素子１４と同形状とするのが好ましい。   As described above, according to the disclosure of the present invention, the regulating portion 11a is provided by forming the through hole 11e in the metal portion 11, and the shape (size) of the through hole 11e is determined by the semiconductor element. When the semiconductor element 14 is disposed in the through hole 11e (the regulating portion 11a) during the manufacture of the semiconductor device, it is possible to prevent the semiconductor element 14 from being misaligned by setting the size of the semiconductor element 14 such that the semiconductor element 14 can be accommodated. The arrangement position can be lowered as compared with the conventional case where the semiconductor device is mounted on the upper surface of the semiconductor device mounting portion, and the upper surface of the semiconductor device 11 and the wires for bonding the electrode portion 11b and the semiconductor device 14 can be reduced. Since the height is reduced, the semiconductor device can be manufactured with a reduced thickness, and the height of the semiconductor device can be reduced. In addition, since the position of the semiconductor element 14 is lowered and the upper surfaces of the semiconductor element 14 and the electrode portion 11b to which the wire 15 is bonded come closer to each other, the wire length can be shortened, and the amount of the wire 15 used can be reduced to reduce the cost. Can be reduced. It is preferable that the shape of the through hole 11 e is the same as that of the semiconductor element 14.

また、本発明の開示に係る半導体装置用基板は、規制部１１ａの高さ寸法が半導体素子１４の厚み寸法以上に設定されたものである。   Further, in the semiconductor device substrate according to the disclosure of the present invention, the height dimension of the regulating portion 11 a is set to be equal to or greater than the thickness dimension of the semiconductor element 14.

このように本発明の開示によれば、規制部１１ａの高さ寸法を半導体素子１４の厚み寸法以上に設定することにより、半導体装置製造の際に収容される半導体素子１４の側面全体を規制部１１ａによって規制することができるので、半導体素子１４の位置ズレを防止することができる。さらに、該規制部１１ａが貫通孔１１ｅから成るものであり、貫通孔１１ｅの深さ寸法を半導体素子１４の厚み寸法以上に設定することにより、半導体素子１４の側面全面が規制部１１ａに囲まれて規制されることになるので、半導体素子１４の位置ズレをより確実に防止することができる。   As described above, according to the disclosure of the present invention, by setting the height of the restricting portion 11a to be equal to or greater than the thickness of the semiconductor element 14, the entire side surface of the semiconductor element 14 accommodated in the manufacture of the semiconductor device is restricted. 11a, it is possible to prevent the semiconductor element 14 from being displaced. Further, the regulating portion 11a is formed of a through hole 11e, and by setting the depth dimension of the through hole 11e to be equal to or greater than the thickness dimension of the semiconductor element 14, the entire side surface of the semiconductor element 14 is surrounded by the regulating section 11a. Therefore, the displacement of the semiconductor element 14 can be more reliably prevented.

また、本発明の開示に係る半導体装置用基板の製造方法は、母型基板１０上に電極部１１ｂ及び半導体素子１４を規制する規制部１１ａとなる金属部１１が設けられた半導体装置用基板の製造方法において、母型基板１０上に金属部１１の形成位置に対応する第一レジスト層１２を形成する工程と、母型基板１０表面の第一レジスト層１２で覆われていない露出領域に金属部１１を形成する工程とを有し、第一レジスト層１２の設定により所定形状の金属部１１を得るものである。   Further, the method for manufacturing a semiconductor device substrate according to the disclosure of the present invention relates to a method for manufacturing a semiconductor device substrate in which a metal portion 11 serving as a regulation portion 11 a for regulating an electrode portion 11 b and a semiconductor element 14 is provided on a mother substrate 10. In the manufacturing method, a step of forming a first resist layer 12 corresponding to a formation position of a metal part 11 on a master substrate 10, and a step of forming a metal on an exposed region of the surface of the mother substrate 10 which is not covered with the first resist layer 12. Forming a metal portion 11 having a predetermined shape by setting the first resist layer 12.

このように本発明の開示によれば、金属部１１の形成において、第一レジスト層１２を設定することにより、電極部１１ｂ及び規制部１１ａとなる金属部１１を母型基板１０上に正確且つ容易に配置形成することができる。   As described above, according to the disclosure of the present invention, in forming the metal portion 11, by setting the first resist layer 12, the metal portion 11 serving as the electrode portion 11 b and the regulation portion 11 a can be accurately and accurately placed on the master substrate 10. It can be easily arranged and formed.

また、本発明の開示に係る半導体装置用基板の製造方法は、第一レジスト層１２が、半導体素子１４の配置箇所に形成され、金属部１１の形成終了後、最終的に第一レジスト層１２を除去することで、半導体素子配置箇所における、第一レジスト層１２が存在していた部位に貫通孔１１ｅを生じさせるものである。   Further, in the method of manufacturing a substrate for a semiconductor device according to the present disclosure, the first resist layer 12 is formed at the position where the semiconductor element 14 is disposed, and after the formation of the metal part 11 is completed, the first resist layer 12 is finally formed. Is removed, a through-hole 11e is formed in the portion where the first resist layer 12 was present in the semiconductor element arrangement location.

このように本発明の開示によれば、第一レジスト層１２を半導体素子１４の配置位置となる部位に配設して、最終的に形成された金属部１１の半導体素子配置位置における第一レジスト層１２の形状に応じた貫通孔１１ｅを生じさせることにより、得られた半導体装置用基板を用いて半導体装置を製造する際に、半導体素子１４を貫通孔１１ｅ内に配置することができ、半導体素子の側面全体を規制することが可能となる。   As described above, according to the disclosure of the present invention, the first resist layer 12 is disposed at the position where the semiconductor element 14 is disposed, and the first resist layer 12 is disposed at the position where the finally formed metal portion 11 is disposed at the semiconductor element. By forming the through-holes 11e according to the shape of the layer 12, the semiconductor element 14 can be arranged in the through-holes 11e when a semiconductor device is manufactured using the obtained semiconductor device substrate. It is possible to regulate the entire side surface of the element.

また、本発明の開示に係る半導体装置用基板の製造方法は、母型基板１０上に第一レジスト層１２を形成した後、少なくとも第一レジスト層１２上に、第二レジスト層１６を形成し、第一レジスト層１２の厚さを越える一方、第二レジスト層１６を越えない厚さで金属部１１を形成することにより、第一レジスト層１２寄りの金属部１１上端周縁には第一レジスト層１２側に張出した略庇状の張出部１１ｃが形成されるものである。   Further, the method for manufacturing a substrate for a semiconductor device according to the present disclosure includes forming the first resist layer 12 on the master substrate 10 and then forming the second resist layer 16 on at least the first resist layer 12. By forming the metal portion 11 so as to exceed the thickness of the first resist layer 12 but not to exceed the second resist layer 16, the first resist layer 12 An overhang-like overhang 11c is formed on the layer 12 side.

このように本発明の開示によれば、半導体装置を構成する金属部１１のうち、第一レジスト層１２寄りの金属部１１上端周縁には張出部１１ｃが形成されていることにより、得られた半導体装置用基板を用いて半導体装置を製造する際の封止材１９による封止状態において、封止材１９は張出部１１ｃがくい込み状に位置した状態で硬化しているため、この喰い付き効果により、半導体装置から母型基板１０を引き剥がし除去する時に、金属部１１は封止材１９側に確実に残留し、母型基板１０とともにくっついて引き離されることはなく、金属部１１のズレや欠落等が効果的に防止でき、製造工程時の歩留まりを向上できる。その一方で、第二レジスト層１６寄りの金属部１１上端周縁には張出部１１ｃが形成されていないので、貫通孔１１ｅ内への半導体素子１４の配設をスムーズに行うことができる。   As described above, according to the disclosure of the present invention, of the metal parts 11 constituting the semiconductor device, the overhanging part 11c is formed at the periphery of the upper end of the metal part 11 near the first resist layer 12. When the semiconductor device is manufactured by using the semiconductor device substrate, the sealing material 19 is hardened in a state where the overhang portion 11c is located in the shape of a bite. Due to the sticking effect, when the master substrate 10 is peeled off from the semiconductor device and removed, the metal portion 11 is securely left on the sealing material 19 side, and is not adhered to the mother substrate 10 and separated from the semiconductor device. Deviations and omissions can be effectively prevented, and the yield in the manufacturing process can be improved. On the other hand, since the overhang portion 11c is not formed on the periphery of the upper end of the metal portion 11 near the second resist layer 16, the semiconductor element 14 can be smoothly disposed in the through hole 11e.

また、本発明の開示に係る半導体装置は、半導体素子１４と電気的に接続する電極部１１ｂを有し、半導体素子１４の搭載、半導体素子１４と電極部１１ｂとの電気的接続、封止材１９による封止がなされ、装置底部に電極部１１ｂの裏面側が露出される半導体装置において、半導体素子１４を規制する規制部１１ａが設けられているものである。   Further, the semiconductor device according to the present disclosure includes an electrode portion 11b electrically connected to the semiconductor element 14, mounting the semiconductor element 14, electrically connecting the semiconductor element 14 to the electrode portion 11b, and sealing material. In a semiconductor device which is sealed by 19 and the back surface of the electrode portion 11b is exposed at the bottom of the device, a regulating portion 11a for regulating the semiconductor element 14 is provided.

このように本発明の開示によれば、半導体素子１４を規制する規制部１１ａが設けられていることにより、半導体素子１４を規制部１１ａによって規制することができ、半導体素子１４の位置ズレを防止することができる。   As described above, according to the disclosure of the present invention, the provision of the regulating portion 11a for regulating the semiconductor element 14 enables the semiconductor element 14 to be regulated by the regulating portion 11a, thereby preventing the semiconductor element 14 from being displaced. can do.

また、本発明の開示に係る半導体装置は、規制部１１ａが半導体素子１４と電極部１１ｂとを接合するワイヤ１５のループ頂部１５’の直下位置に設けられたものである。   Further, in the semiconductor device according to the present disclosure, the regulating portion 11a is provided at a position directly below the loop top 15 'of the wire 15 joining the semiconductor element 14 and the electrode portion 11b.

このように本発明の開示によれば、規制部１１ａをワイヤ１５のループ頂部１５’の直下位置と重なるように配置することにより、規制部１１ａによる半導体素子１４の位置ズレを防止することができ、しかも、規制部１１ａとワイヤ１５とが最も離れた位置関係とすることができるので、規制部１１ａとワイヤ１５との接触を可及的に防止することができる。   Thus, according to the disclosure of the present invention, it is possible to prevent the displacement of the semiconductor element 14 due to the restricting portion 11a by disposing the restricting portion 11a so as to overlap the position immediately below the loop top 15 'of the wire 15. Moreover, since the restricting portion 11a and the wire 15 can be in the most distant positional relationship, the contact between the restricting portion 11a and the wire 15 can be prevented as much as possible.

本発明の第１実施形態に係る半導体装置用基板の要部拡大図である。FIG. 2 is an enlarged view of a main part of the semiconductor device substrate according to the first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。FIG. 4 is an explanatory view of a step in the method for manufacturing a semiconductor device substrate according to the first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。FIG. 4 is an explanatory view of a step in the method for manufacturing a semiconductor device substrate according to the first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。FIG. 4 is an explanatory view of a step in the method for manufacturing a semiconductor device substrate according to the first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。FIG. 4 is an explanatory view of a step in the method for manufacturing a semiconductor device substrate according to the first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置の断面図及び底面図である。FIG. 2 is a cross-sectional view and a bottom view of the semiconductor device according to the first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置の別実施例の断面図及び底面図である。It is sectional drawing and a bottom view of another example of the semiconductor device concerning a 1st embodiment of the present invention. 本発明の第２実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and a bottom view of a semiconductor device concerning a 2nd embodiment of the present invention. 本発明の第３実施形態に係る半導体装置の断面図及び底面図である。It is a sectional view and a bottom view of a semiconductor device according to a third embodiment of the present invention. 本発明の第４実施形態に係る半導体装置の断面図及び底面図である。It is a sectional view and a bottom view of a semiconductor device according to a fourth embodiment of the present invention. 本発明の第５実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and a bottom view of a semiconductor device concerning a 5th embodiment of the present invention. 本発明の第５実施形態に係る半導体装置の別実施例の断面図及び底面図である。It is sectional drawing and a bottom view of another example of the semiconductor device concerning a 5th embodiment of the present invention. 本発明の第６実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and a bottom view of a semiconductor device concerning a 6th embodiment of the present invention. 本発明に係る規制部と半導体素子の配置状態説明図である。FIG. 4 is an explanatory diagram of an arrangement state of a regulating portion and a semiconductor element according to the present invention.

（第１実施形態）
以下、本発明の第１の実施形態に係る半導体装置用基板を図１ないし図７に基づいて説明する。前記各図において本実施形態に係る半導体装置用基板１は、導電性を有する材質からなる母型基板１０と、この母型基板１０上に形成され、本基板を用いて製造される半導体装置７０の少なくとも電極部１１ｂとなる金属部１１と、金属部１１表面にメッキにより形成される表面金属層１３とを備える構成である。 (1st Embodiment)
Hereinafter, a semiconductor device substrate according to a first embodiment of the present invention will be described with reference to FIGS. In each of the drawings, the semiconductor device substrate 1 according to the present embodiment includes a matrix substrate 10 made of a conductive material, and a semiconductor device 70 formed on the matrix substrate 10 and manufactured using the substrate. And a surface metal layer 13 formed on the surface of the metal portion 11 by plating.

この半導体装置用基板１を用いて製造される半導体装置７０は、図６に示すように、半導体装置用基板１から得られる金属部１１及び表面金属層１３に加えて、金属部１１のうちの電極部１１ｂと電気的に接続する半導体素子１４と、この半導体素子１４と電極部１１ｂとを接合するワイヤ１５と、半導体素子１４やワイヤ１５を含む金属部１１の表面側を覆って封止する封止材１９とを備える構成である。   As shown in FIG. 6, a semiconductor device 70 manufactured using the semiconductor device substrate 1 has a metal portion 11 and a surface metal layer 13 obtained from the semiconductor device substrate 1, The semiconductor element 14 electrically connected to the electrode part 11b, the wire 15 joining the semiconductor element 14 and the electrode part 11b, and the metal element 11 including the semiconductor element 14 and the wire 15 are covered and sealed. This is a configuration including a sealing material 19.

この半導体装置７０では、底部に金属部１１の裏面側が電極や放熱パッド等として露出した状態となり（図６（Ｂ）参照）、この露出する金属部１１の裏面側と、装置外装の一部として現れる封止材１９の裏面側とが略同一平面上に位置する構成である。半導体装置７０における底部以外の各面は、装置外装をなす封止材１９のみがそれぞれ現れた状態となっている。   In the semiconductor device 70, the back surface of the metal portion 11 is exposed at the bottom as an electrode, a heat radiation pad, or the like (see FIG. 6B). In this configuration, the back surface side of the encapsulating material 19 appears on substantially the same plane. Each surface other than the bottom of the semiconductor device 70 is in a state where only the sealing material 19 forming the device exterior has appeared.

前記半導体装置用基板１は、母型基板１０上に、金属部１１の配置部分が露出されるように第一レジスト層１２に引き続き第二レジスト層１６を形成した後、メッキにより金属部１１を形成し、さらに、金属部１１表面にメッキにより表面金属層１３を形成した後、第一レジスト層１２及び第二レジスト層１６を除去することで製造されるものである。   The semiconductor device substrate 1 is formed by forming a second resist layer 16 subsequent to the first resist layer 12 on the mother substrate 10 so that the arrangement portion of the metal portion 11 is exposed, and then plating the metal portion 11. It is manufactured by forming a surface metal layer 13 by plating on the surface of the metal portion 11 and then removing the first resist layer 12 and the second resist layer 16.

また、この半導体装置用基板１を用いた半導体装置の製造の際は、この半導体装置用基板１に対し、半導体素子１４の搭載及び配線、封止材１９による封止がなされ、封止の後、半導体装置部分から母型基板１０を除去して半導体装置７０を得る仕組みである。   When a semiconductor device is manufactured using the semiconductor device substrate 1, the semiconductor device substrate 1 is mounted with a semiconductor element 14, wiring, and sealing with a sealing material 19. This is a mechanism for obtaining the semiconductor device 70 by removing the mother substrate 10 from the semiconductor device portion.

母型基板１０は、ステンレス（ＳＵＳ４３０等）やアルミニウム、銅等の導電性の金属板（厚さ約０．１ｍｍ）で形成され、半導体装置の製造工程で除去されるまで、半導体装置用基板１の要部をなすものであり、半導体装置用基板製造工程の各段階で、表面側に第一レジスト層１２、金属部１１が形成され、また裏面側にレジスト層１８が配設される。金属部１１の形成の際には、この母型基板１０を介した通電がなされることで、母型基板１０表面の第一レジスト層１２に覆われない通電可能な部分（露出領域）に電解メッキで金属部１１が形成されることとなる。また、表面金属層１３のメッキの際も、電解メッキとする場合には、母型基板１０を介して通電がなされる。   The matrix substrate 10 is formed of a conductive metal plate (thickness: about 0.1 mm) such as stainless steel (SUS430 or the like), aluminum, copper, or the like, and the semiconductor device substrate 1 is removed until it is removed in a semiconductor device manufacturing process. In each stage of the semiconductor device substrate manufacturing process, the first resist layer 12 and the metal part 11 are formed on the front side, and the resist layer 18 is provided on the back side. When the metal portion 11 is formed, an electric current is applied through the master substrate 10 so that an electroconductive portion (exposed region) of the surface of the mother substrate 10 that is not covered by the first resist layer 12 is exposed. The metal part 11 is formed by plating. Also, when plating the surface metal layer 13, in the case of electrolytic plating, power is supplied via the master substrate 10.

一方、半導体装置用基板１を用いた半導体装置の製造工程では、母型基板１０上の金属部１１表面側が封止材１９で覆われ（図５（Ｂ）参照）、母型基板１０で金属部１１及び封止材１９を支持しなくても十分な強度が得られたら、母型基板１０が除去される（図５（Ｃ）参照）。母型基板１０がステンレスの場合には、力を加えて半導体装置側から物理的に引き剥がして除去する方法が採られ、また、母型基板１０が銅等の場合、薬液を用いて溶解除去するエッチングの方法が用いられる。エッチングの場合、母型基板１０は溶解するが金属部１１のニッケル等の材質が冒されないような選択エッチング性を有するエッチング液を用いることとなる。この母型基板１０が除去されると、半導体装置底部に、金属部１１（電極部１１ｂ）及び封止材１９の各裏面が同一平面上に露出した状態が得られる。   On the other hand, in the process of manufacturing a semiconductor device using the semiconductor device substrate 1, the surface of the metal portion 11 on the mother substrate 10 is covered with a sealing material 19 (see FIG. 5B). When sufficient strength is obtained without supporting the portion 11 and the sealing material 19, the matrix substrate 10 is removed (see FIG. 5C). When the matrix substrate 10 is made of stainless steel, a method of applying force and physically peeling it off from the semiconductor device side to remove it is adopted. When the matrix substrate 10 is made of copper or the like, it is dissolved and removed using a chemical solution. Etching method is used. In the case of etching, an etching solution having a selective etching property that dissolves the matrix substrate 10 but does not affect the material such as nickel of the metal portion 11 is used. When the matrix substrate 10 is removed, a state is obtained in which the back surfaces of the metal portion 11 (electrode portion 11b) and the sealing material 19 are exposed on the same plane at the bottom of the semiconductor device.

前記金属部１１は、電解メッキに適したニッケルや銅、又はニッケル−コバルト等のニッケル合金からなり、母型基板１０上の第一レジスト層１２から露出する部分に、電解メッキで形成される構成である。半導体装置用基板１において、金属部１１は、母型基板１０表面で、一又は複数配置される電極部１１ｂを一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなる。   The metal portion 11 is made of nickel or copper suitable for electrolytic plating or a nickel alloy such as nickel-cobalt, and is formed by electrolytic plating on a portion exposed from the first resist layer 12 on the matrix substrate 10. It is. In the semiconductor device substrate 1, the metal portions 11 are arranged on the surface of the matrix substrate 10 in such a manner that one or a plurality of electrode portions 11 b are arranged as one unit in a number of semiconductor devices to be manufactured. Will be formed.

この金属部１１は、第一レジスト層１２の厚さを越える厚さ（例えば、厚さ約６０〜８０μｍ）で、且つ上端周縁には第一レジスト層１２表面側に張出した略庇状の張出し部１１ｃを有する形状として形成される。張出し部１１ｃは、電解メッキの際、金属部１１を第一レジスト層１２の厚さまで形成した後も電解メッキを継続して、金属部の成長を厚さ方向に加えて第一レジスト層１２による制限のない他の向きにも進行させることで、第一レジスト層１２を越えた金属部１１上端部から第一レジスト層１２側へ張出した形状として得られるものである。この張出し部１１ｃは、封止材１９による封止に伴って、封止材１９で挟まれて固定された状態（アンカー効果）となる。   The metal portion 11 has a thickness exceeding the thickness of the first resist layer 12 (for example, a thickness of about 60 to 80 μm), and has a substantially eaves-shaped protrusion on the periphery of the upper end toward the surface of the first resist layer 12. It is formed as a shape having a portion 11c. In the case of electrolytic plating, the overhang portion 11c continues the electrolytic plating even after forming the metal portion 11 to the thickness of the first resist layer 12, and adds the growth of the metal portion in the thickness direction to form the first resist layer 12. By proceeding in any other unrestricted direction, a shape protruding from the upper end of the metal portion 11 beyond the first resist layer 12 toward the first resist layer 12 can be obtained. The overhanging portion 11c is sandwiched and fixed by the sealing material 19 (anchor effect) with the sealing by the sealing material 19.

この他、金属部１１として、半導体装置製造の際に半導体素子１４を規制するための規制部１１ａが設けられる。具体的には、半導体素子１４の配置箇所にあたる金属部１１に貫通孔１１ｅを形成することで規制部１１ａとしている。この規制部１１ａは、第一レジスト層１２を形成した後、規制部１１ａに対応する箇所に第二レジスト層１６を配設し、係る個所の第一レジスト層１２及び第二レジスト層１６を除去することで貫通孔１１ｅが生じ、規制部１１ａとなるものであり、半導体素子１４を規制するのに必要な強度を維持する厚さとされる。係る規制部１１ａによって半導体素子１４を規制することができ、半導体素子１４を搭載する際に、半導体素子１４の位置ズレを防止することができる。この規制部１１ａの裏面も、電極部１１ｂと同様に、封止材１９の裏面と同一平面上に露出されることになる。   In addition, a regulating portion 11a for regulating the semiconductor element 14 at the time of manufacturing the semiconductor device is provided as the metal portion 11. Specifically, a through-hole 11e is formed in the metal part 11 corresponding to the position where the semiconductor element 14 is arranged, thereby forming the regulating part 11a. After forming the first resist layer 12, the restricting portion 11a arranges the second resist layer 16 at a position corresponding to the restricting portion 11a, and removes the first resist layer 12 and the second resist layer 16 at such a position. As a result, a through-hole 11e is formed, which serves as a regulating portion 11a, and has a thickness that maintains the strength necessary for regulating the semiconductor element 14. The semiconductor element 14 can be restricted by the restricting portion 11a, and the semiconductor element 14 can be prevented from being displaced when the semiconductor element 14 is mounted. The back surface of the regulating portion 11a is also exposed on the same plane as the back surface of the sealing material 19, similarly to the electrode portion 11b.

金属部１１は、大部分を電解メッキに適したニッケルやニッケル合金等で形成されるが、金属部１１の裏面側には、半導体装置実装時のハンダ付けを適切に行えるようにするために、ニッケル等の主材質部よりハンダぬれ性の良好な金属、例えば金や銀、錫、パラジウム、ハンダ等の薄膜１１ｄが配設される構成である。この薄膜１１ｄの厚さは０．０１〜１μｍ程度とするのが好ましい。   The metal part 11 is mostly formed of nickel or a nickel alloy suitable for electrolytic plating, but on the back side of the metal part 11, in order to appropriately perform soldering when mounting a semiconductor device, In this configuration, a thin film 11d of a metal having better solder wettability than a main material portion such as nickel, for example, gold, silver, tin, palladium, or solder is provided. It is preferable that the thickness of the thin film 11d is about 0.01 to 1 μm.

金属部１１形成の際には、あらかじめ薄膜１１ｄが母型基板１０上の第一レジスト層１２のない部分（露出領域）にメッキ等により形成された後、この薄膜１１ｄ上にさらにメッキ等によりニッケル等の主材質部が形成されることとなる（図４（Ｂ）参照）。この薄膜１１ｄには、母型基板１０のエッチングによる除去の際に、エッチング液による金属部１１の侵食劣化を防ぐ機能を与えることもできる。   In forming the metal part 11, a thin film 11d is formed in advance on a portion (exposed region) of the mother substrate 10 where the first resist layer 12 is not formed by plating or the like, and nickel is further formed on the thin film 11d by plating or the like. Is formed (see FIG. 4B). The thin film 11d may have a function of preventing the metal part 11 from being eroded and deteriorated by the etchant when the matrix substrate 10 is removed by etching.

なお、この金属部１１裏面側の薄膜形成は、前記ハンダ付け対策を目的とする場合、メッキで金属部１１主材質部を形成する前に限られるものではなく、半導体装置７０の完成後、封止材１９から露出した金属部１１の裏面にメッキにより薄膜を形成するようにしてもかまわない。   The formation of the thin film on the back side of the metal part 11 is not limited to the formation of the main material part of the metal part 11 by plating when the soldering countermeasure is intended. A thin film may be formed on the back surface of the metal portion 11 exposed from the stopper 19 by plating.

前記第一レジスト層１２は、金属部１１の電解メッキや表面金属層１３のメッキで使用するメッキ液に対する耐溶解性を備えた絶縁性材で形成され、母型基板１０上にあらかじめ設定される金属部１１の配置部分を露出するように対応させて配設され、金属部１１及び表面金属層１３の形成後には除去されるものである（図４（Ｃ）参照）。   The first resist layer 12 is formed of an insulating material having resistance to dissolution against a plating solution used for electrolytic plating of the metal part 11 and plating of the surface metal layer 13, and is set in advance on the mother substrate 10. The metal portion 11 is disposed so as to correspond to the exposed portion, and is removed after the formation of the metal portion 11 and the surface metal layer 13 (see FIG. 4C).

この第一レジスト層１２は、母型基板１０上に金属部１１の形成に先立って配設され、詳細には、アルカリ現像タイプの感光性レジスト材を母型基板１０に所定の厚さ、例えば約５０μｍの厚さとなるようにして密着配設し、半導体装置７０の金属部１１位置に対応する所定パターンのマスクフィルム５０を載せた状態で紫外線照射による露光での硬化（図２（Ｃ）参照）、非照射部分のレジスト材を除去する現像等の処理を経て、金属部１１の配置部分が露出されるような形状で形成される。   The first resist layer 12 is provided on the master substrate 10 prior to the formation of the metal part 11. Specifically, a photosensitive resist material of an alkali development type is formed on the mother substrate 10 to a predetermined thickness, for example, Hardened by exposure to ultraviolet light with the mask film 50 having a predetermined pattern corresponding to the position of the metal part 11 of the semiconductor device 70 mounted thereon, which is closely attached so as to have a thickness of about 50 μm (see FIG. 2C). ), Through processing such as development for removing the resist material in the non-irradiated portion, the metal portion 11 is formed in such a shape as to expose the disposed portion.

また、第二レジスト層１６は、前記第一レジスト層１２同様にメッキ液に対する耐溶解性を備えた絶縁性材で形成され、第一レジスト層１２を形成した後で、あらかじめ設定される金属部１１の規制部１１ａに対応させて配設され、金属部１１及び表面金属層１３の形成後には除去されるものである。この第二レジスト層１６としては、第一レジスト層１２の場合と同様、アルカリ現像タイプの感光性レジスト材等を用いることができる。このレジスト材を母型基板１０や第一レジスト層１２の各表面に所定の厚さ、例えば約３０μｍを超える厚さとなるように形成し、金属部１１の規制部１１ａ配置位置に対応する所定パターンのマスクフィルム５１を載せた状態で、紫外線照射による露光で硬化させる処理を経ると、母型基板１０や第一レジスト層１２上に固定状態の第二レジスト層１６が形成されることとなる。これら第一レジスト層１２及び第二レジスト層１６により、金属部１１の規制部１１ａに相当する部分で電解メッキが進行せず、金属部１１の欠けた部分、すなわち貫通孔１１ｅの規制部１１ａが設けられる。   The second resist layer 16 is formed of an insulating material having resistance to dissolution against a plating solution similarly to the first resist layer 12, and after the first resist layer 12 is formed, a predetermined metal part is formed. The metal parts 11 and the surface metal layer 13 are removed after the metal parts 11 and the surface metal layer 13 are formed. As the second resist layer 16, as in the case of the first resist layer 12, an alkali developing type photosensitive resist material or the like can be used. This resist material is formed on each surface of the matrix substrate 10 and the first resist layer 12 so as to have a predetermined thickness, for example, a thickness exceeding about 30 μm, and a predetermined pattern corresponding to the position of the regulating portion 11 a of the metal portion 11. In the state where the mask film 51 is placed on the substrate, a process of curing by exposure to ultraviolet irradiation is performed, so that the fixed second resist layer 16 is formed on the matrix substrate 10 and the first resist layer 12. Due to the first resist layer 12 and the second resist layer 16, electrolytic plating does not proceed in a portion corresponding to the regulating portion 11 a of the metal portion 11, and the lacking portion of the metal portion 11, that is, the regulating portion 11 a of the through hole 11 e is formed. Provided.

なお、この第一レジスト層１２や第二レジスト層１６については、感光性レジストに限られるものではなく、メッキ液に対し変質せず強度の高い塗膜が得られる塗料を、母型基板１０上における金属部１１の配置部分が露出されるように、電着塗装等により必要な塗膜厚さとなるように塗装して形成することもできる。   Note that the first resist layer 12 and the second resist layer 16 are not limited to the photosensitive resist, and a paint capable of obtaining a high-strength coating film without being deteriorated by a plating solution is coated on the master substrate 10. Can be formed by electrodeposition coating or the like so as to have a required coating film thickness so that the portion where the metal part 11 is disposed is exposed.

一方、この表面側の第一レジスト層１２や第二レジスト層１６とは別に、母型基板１０の裏面側にも、レジスト層１８が形成される構成である（図２参照）。裏面側のレジスト層１８は、硬化状態でメッキ液への耐性のある材質で、且つ不要となったら容易に溶解除去可能なレジスト材、例えば厚さ約５０μｍのアルカリ現像タイプの感光性フィルムレジストを熱圧着等により配設し、そのままマスクなしに紫外線照射による露光等の処理を経て、裏面全面にわたり硬化形成されるものとすることができる。なお、レジスト層１８については、レジストに限られるものではなく、例えばカバーフィルムであっても良く、要は絶縁性を有するものであれば良い。   On the other hand, in addition to the first resist layer 12 and the second resist layer 16 on the front side, a resist layer 18 is also formed on the back side of the matrix substrate 10 (see FIG. 2). The resist layer 18 on the back side is made of a material that is resistant to a plating solution in a cured state and that can be easily dissolved and removed when unnecessary, for example, an alkali developing type photosensitive film resist having a thickness of about 50 μm. It can be provided by thermocompression bonding or the like, and can be cured and formed over the entire rear surface without exposure through a process such as exposure to ultraviolet light without using a mask. Note that the resist layer 18 is not limited to a resist, and may be, for example, a cover film.

表面金属層１３は、配線用のワイヤ１５をなす金線等との接合性に優れる金や銀、パラジウム等からなるメッキ膜として形成される。この表面金属層１３は、母型基板１０ごとのメッキにより金属部１１の表面に所定の厚さ、例えば、金メッキの場合は約０．１〜１μｍ、銀メッキの場合は約１〜１０μｍの厚さのメッキとして形成される。この表面金属層１３のメッキの際、母型基板１０の裏面側はレジスト層１８で覆われていることから、メッキの付着等は生じない（図４（Ｂ）参照）。なお、この表面金属層１３へのメッキに際しては、金属部１１のメッキの場合とはメッキ液を異ならせるなど、メッキの金属に対応するメッキ液を使用することとなる。   The surface metal layer 13 is formed as a plating film made of gold, silver, palladium, or the like, which has excellent bondability with a gold wire or the like forming the wiring wire 15. The surface metal layer 13 has a predetermined thickness on the surface of the metal part 11 by plating for each matrix substrate 10, for example, about 0.1 to 1 μm in the case of gold plating, and about 1 to 10 μm in the case of silver plating. It is formed as a plating. At the time of plating of the front surface metal layer 13, since the back surface side of the mother substrate 10 is covered with the resist layer 18, there is no adhesion of plating or the like (see FIG. 4B). When plating the surface metal layer 13, a plating solution corresponding to the metal to be plated is used, for example, by using a different plating solution from the case of plating the metal portion 11.

この表面金属層１３のメッキを形成する際は、金属部１１がニッケルの場合、メッキが密着しにくいため、通常、表面金属層１３のメッキの前にあらかじめ金属部１１表面に下地メッキ（銅ストライク、ニッケルストライク、銀ストライク、又は金ストライク）を行い、表面金属層１３の金属部１１への密着性を高めることが望ましい。   When plating the surface metal layer 13, if the metal portion 11 is nickel, the plating is difficult to adhere to. Therefore, usually, the surface of the metal portion 11 is preliminarily plated (copper strike) before plating the surface metal layer 13. , Nickel strike, silver strike, or gold strike) to improve the adhesion of the surface metal layer 13 to the metal portion 11.

半導体素子１４は、微細な電子回路が形成されたいわゆるチップであり、金、銅等の導電性線材からなる配線（ボンディング）用のワイヤ１５が、半導体素子１４表面に設けられた電極と金属部１１のうちの電極部１１ｂとにそれぞれ接合され、半導体素子１４と電極部１１ｂとを電気的に接続することとなる。   The semiconductor element 14 is a so-called chip on which a fine electronic circuit is formed, and a wiring (bonding) wire 15 made of a conductive wire material such as gold or copper is provided with an electrode provided on the surface of the semiconductor element 14 and a metal part. The semiconductor element 14 and the electrode portion 11b are electrically connected to the electrode portion 11b of the semiconductor device 11, respectively.

この時、半導体素子１４は規制部１１ａによって規制された状態となっていることから、半導体素子の位置ズレを防止することができる。しかも、規制部１１ａは金属部１１に貫通孔１１ｅを形成することで得ることができ、この貫通孔１１ｅ内に半導体素子１４を配置させれば、半導体素子１４は規制部１１ａに囲まれた状態で配置されることになるので、半導体素子１４の位置ズレをより確実に防止することができる。また、従来のように半導体素子搭載部の上面に搭載される場合と比べて、配設位置を下げることができ、半導体素子１４上面や接合されるワイヤ１５も下がる分、半導体装置７０の厚さを小さくして製造することができ、半導体装置７０の低背化を実現できる。また、半導体素子１４の位置が下がって、ワイヤ１５が接合する半導体素子１４と電極部１１ｂの各上面が近付く分、ワイヤ１５の長さも短くすることができ、ワイヤ１５の使用量を削減してコストを低減できる。なお、貫通孔１１ｅ内に半導体素子１４を配置するようにした場合には、半導体素子１４の裏面も半導体装置７０の底部から露出されることになる。   At this time, since the semiconductor element 14 is in a state of being regulated by the regulation section 11a, it is possible to prevent the semiconductor element from being displaced. Moreover, the restricting portion 11a can be obtained by forming the through-hole 11e in the metal portion 11, and if the semiconductor element 14 is arranged in the through-hole 11e, the semiconductor element 14 is surrounded by the restricting portion 11a. Therefore, the displacement of the semiconductor element 14 can be prevented more reliably. Further, compared with the conventional case where the semiconductor device is mounted on the upper surface of the semiconductor device mounting portion, the disposition position can be lowered, and the upper surface of the semiconductor device 14 and the wire 15 to be bonded are also lowered, so that the thickness of the semiconductor device 70 is reduced. , And the height of the semiconductor device 70 can be reduced. In addition, since the position of the semiconductor element 14 is lowered and the upper surfaces of the semiconductor element 14 to which the wire 15 is bonded and the upper surfaces of the electrode portions 11b are closer to each other, the length of the wire 15 can be shortened, and the amount of use of the wire 15 can be reduced. Cost can be reduced. When the semiconductor element 14 is arranged in the through hole 11e, the back surface of the semiconductor element 14 is also exposed from the bottom of the semiconductor device 70.

前記封止材１９は、物理的強度の高い熱硬化性エポキシ樹脂等であり、金属部１１表面側の半導体素子１４やワイヤ１５を覆った状態で封止し、半導体素子１４やワイヤ１５等の構造的に弱い部分を外部から隔離した保護状態とするものである。なお、半導体素子１４がＬＥＤ等の発光素子の場合、透光性の材質が用いられる。   The sealing material 19 is a thermosetting epoxy resin or the like having a high physical strength, and seals the semiconductor element 14 and the wire 15 on the surface of the metal part 11 while covering the same. This is a protection state in which a structurally weak portion is isolated from the outside. When the semiconductor element 14 is a light emitting element such as an LED, a light transmitting material is used.

この封止材１９を用いる封止工程は、半導体装置用基板１に対して行われ、母型基板１０の表面側における金属部１１等のある半導体装置となる範囲を、上型となる金型で覆った上で、この金型と母型基板１０の間に封止材１９を圧入し、封止材１９を硬化させることで封止が完了となる。ただし、封止工程では、一つの半導体装置となる半導体素子搭載部１１ａや複数の電極部１１ｂが多数整列状態のままで一様に封止されるため、半導体装置は封止材１９を介して多数つながった状態となっている。   The sealing step using the sealing material 19 is performed on the semiconductor device substrate 1, and the area of the semiconductor device including the metal portion 11 on the front side of the mother substrate 10 is changed to an upper mold. Then, the sealing material 19 is press-fitted between the mold and the mother substrate 10, and the sealing material 19 is cured to complete the sealing. However, in the sealing step, since the semiconductor element mounting portion 11a and the plurality of electrode portions 11b to be one semiconductor device are uniformly sealed in a state where many are aligned, the semiconductor device is interposed via the sealing material 19. Many are connected.

この封止材１９は、十分な物理的強度を有しており、半導体装置７０の外装の一部として十分に内部を保護する機能を果し、母型基板１０を半導体装置側から引き剥がすなど力を加えて物理的に除去する場合にも、割れ等の破損もなく金属部１１との一体化状態を維持することとなる。   The sealing material 19 has a sufficient physical strength, and has a function of sufficiently protecting the inside as a part of the exterior of the semiconductor device 70, such as peeling the mother substrate 10 from the semiconductor device side. Even in the case of physically removing by applying force, the integrated state with the metal part 11 is maintained without damage such as cracks.

次に、本実施形態に係る半導体装置用基板の製造及び半導体装置用基板を用いた半導体装置製造の各工程について説明する。   Next, the steps of manufacturing the semiconductor device substrate and manufacturing the semiconductor device using the semiconductor device substrate according to the present embodiment will be described.

半導体装置用基板の製造工程として、まず、母型基板１０を用意し（図２（Ａ）、母型基板１０上にあらかじめ設定される金属部１１の非配置部分に対応させて第一レジスト層１２を配設する。具体的には、母型基板１０の表面側に、形成する金属部１１の形状や高さ（例えば約５０μｍ）に対応するように、感光性レジスト材１２ａを配設する（図２（Ｂ）参照）。感光性レジスト材１２ａに対しては、金属部１１の配置位置に対応する所定パターンのマスクフィルム５０を載せた状態で、紫外線照射による露光での硬化（図２（Ｃ）参照）、非照射部分のレジスト剤を除去する現像等の処理を行い、金属部１１の配置部分が露出する第一レジスト層１２を形成する（図３（Ａ）参照）。また、母型基板１０の裏面側にも感光性レジスト材を表面側同様に配設し、このレジスト材全面に対して露光等の処理を経て、裏面全面にわたりレジスト層１８を形成する（図２（Ｃ）参照）。   As a manufacturing process of a substrate for a semiconductor device, first, a master substrate 10 is prepared (FIG. 2A), and a first resist layer is formed on the master substrate 10 in correspondence with a non-arranged portion of the metal portion 11 set in advance. Specifically, a photosensitive resist material 12a is provided on the front side of the matrix substrate 10 so as to correspond to the shape and height (for example, about 50 μm) of the metal part 11 to be formed. (See FIG. 2 (B).) The photosensitive resist material 12a is cured by exposure to ultraviolet light while the mask film 50 having a predetermined pattern corresponding to the position of the metal part 11 is placed thereon (FIG. 2). (See FIG. 3C), a process such as development for removing the resist agent in the non-irradiated portion is performed to form the first resist layer 12 in which the metal portion 11 is exposed (see FIG. 3A). A photosensitive resist material is also provided on the back side of the matrix substrate 10. Surface side similarly arranged, through a process such as exposure to this resist material is formed over the entire surface of the resist layer 18 over the entire back surface (see FIG. 2 (C)).

第一レジスト層１２を形成したら、所定厚さまで形成された第一レジスト層１２の上に、金属部１１における規制部１１ａに対応させて第二レジスト層１６を配設する。具体的には、母型基板１０と第一レジスト層１２の表面側に、感光性レジスト材１６ａを、貫通孔１１ｅを有する規制部１１ａの高さ（深さ）より大きい所定厚さ（例えば約３０μｍ）となるようにして密着配設する（図３（Ｂ）参照）。この感光性レジスト材に対し、規制部１１ａ（貫通孔１１ｅ）の配置位置に対応する所定パターンのマスクフィルム５１を載せた状態で、紫外線照射による露光（図３（Ｃ）参照）、非照射部分のレジスト剤を除去する現像等の処理を行い、規制部１１ａ（貫通孔１１ｅ）を生じさせる箇所に対応させた第二レジスト層１６を形成する（図４（Ａ）参照）。なお、貫通孔１１ｅは、第一レジスト層１２及び第二レジスト層１６を形成することで設けられているが、第二レジスト層１６のみの形成で設けることもできる。具体的には、第一レジスト層１２を形成する工程において、貫通孔１１ｅを生じさせる箇所における感光性レジスト材１２ａの露光を行わず、第二レジスト層１６を形成する工程において、貫通孔１１ｅを生じさせる箇所における感光性レジスト材１６ａを露光・現像することで貫通孔１１ｅを設けることができる。また、貫通孔１１ｅの大きさが規制部１１ａの第一レジスト層１２側への張出し量に比べて十分大きい場合には、第二レジスト層１６を設けずに第一レジスト層１２のみを貫通孔１１ｅを設ける位置に形成するようにしてもよい。   After the first resist layer 12 is formed, the second resist layer 16 is disposed on the first resist layer 12 formed to a predetermined thickness so as to correspond to the regulation part 11a of the metal part 11. Specifically, the photosensitive resist material 16a is provided on the front surface side of the matrix substrate 10 and the first resist layer 12 by a predetermined thickness (for example, about a predetermined thickness larger than the height (depth) of the regulating portion 11a having the through hole 11e. 30 μm) (see FIG. 3B). With this photosensitive resist material on which a mask film 51 having a predetermined pattern corresponding to the arrangement position of the regulating portion 11a (through hole 11e) is placed, exposure by ultraviolet irradiation (see FIG. 3C), non-irradiation portion Then, a process such as development for removing the resist agent is performed to form the second resist layer 16 corresponding to the location where the restriction portion 11a (through hole 11e) is generated (see FIG. 4A). The through-hole 11e is provided by forming the first resist layer 12 and the second resist layer 16, but may be provided by forming only the second resist layer 16. Specifically, in the step of forming the first resist layer 12, the photosensitive resist material 12 a is not exposed at a position where the through-hole 11 e is formed, and the through-hole 11 e is formed in the step of forming the second resist layer 16. The through-hole 11e can be provided by exposing and developing the photosensitive resist material 16a at the location where it is generated. When the size of the through hole 11e is sufficiently large compared to the amount of the protrusion of the regulating portion 11a to the first resist layer 12, the second resist layer 16 is not provided and only the first resist layer 12 is formed. 11e may be formed at a position to be provided.

こうして、金属部１１のメッキで使用するメッキ液に対する耐溶解性を備えたレジスト層１２・１６を形成したら、母型基板１０表面の第一レジスト層１２及び第二レジスト層１６で覆われていない露出部分に対し、必要に応じて表面酸化被膜除去や表面活性化処理を行う。具体的には、母型基板１０及び金属部１１（薄膜１１ｄ）の材質によって、脱脂、酸浸漬、化学エッチング、電解処理、ストライクメッキなどを選択して行う。なお、化学エッチングは、母型基板１０自体を溶解して、その表面の酸化被膜（不活性膜）を除去するものであり、係る表面は粗面となる。   In this manner, when the resist layers 12 and 16 having the resistance to the plating solution used for plating the metal portion 11 are formed, the resist layers 12 and 16 are not covered with the first resist layer 12 and the second resist layer 16 on the surface of the matrix substrate 10. The exposed portion is subjected to a surface oxide film removal and a surface activation treatment as necessary. Specifically, degreasing, acid immersion, chemical etching, electrolytic treatment, strike plating, or the like is selected and performed depending on the material of the mother substrate 10 and the metal portion 11 (thin film 11d). The chemical etching dissolves the matrix substrate 10 itself and removes an oxide film (inactive film) on the surface, and the surface becomes rough.

その後、この露出部分にメッキ等によりハンダぬれ性改善用の金の薄膜１１ｄを、例えば０．０１〜１μｍ厚で形成する（図４（Ｂ）参照）。そして、この薄膜１１ｄ上に、電解メッキによりニッケルを積層して金属部１１を形成する（図４（Ｂ）参照）。   Thereafter, a gold thin film 11d for improving solder wettability is formed on the exposed portion with a thickness of, for example, 0.01 to 1 [mu] m (see FIG. 4B). Then, nickel is laminated on the thin film 11d by electrolytic plating to form the metal part 11 (see FIG. 4B).

この金属部１１の形成工程で、金属部１１は、第一レジスト層１２の厚さを越える一方、第二レジスト層１６の上面を越えない厚さとして形成され、第二レジスト層１６の側面に接する部位を伴う一方、第一レジスト層１２寄りの金属部１１上端周縁には第一レジスト層１２側に張出した略庇状の張出し部１１ｃが形成され、第二レジスト層１６の配置された箇所に金属部１１は形成されない。金属部１１は、母型基板１０表面において、一又は複数配置される電極部１１ｂを一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなる。   In the step of forming the metal portion 11, the metal portion 11 is formed to have a thickness exceeding the thickness of the first resist layer 12 but not exceeding the upper surface of the second resist layer 16. On the periphery of the upper end of the metal portion 11 near the first resist layer 12, a substantially eaves-like overhang 11 c projecting toward the first resist layer 12 is formed, and the portion where the second resist layer 16 is disposed No metal part 11 is formed. The metal parts 11 are formed on the surface of the matrix substrate 10 in such a manner that one or a plurality of electrode parts 11b are arranged as one unit, and as many as the number of semiconductor devices to be manufactured.

所望の厚さ及び形状の金属部１１が得られたら、母型基板１０ごとのメッキ浴浸漬により、金属部１１の表面に、表面金属層１３を所定の厚さ、例えば銀メッキの場合、厚さ約０．１〜０．５μｍとなるように形成する（図４（Ｂ）参照）。メッキ浴に用いられるメッキ液に対し、第一レジスト層１２及び第二レジスト層１６は十分な耐性を有しているため、変質等が生じることはなく、レジスト層としての機能を維持し、必要箇所以外へのメッキ付着を防ぐことができる。また、この表面金属層１３のメッキの際、母型基板１０の裏面側はレジスト層１８で覆われていることから、メッキの付着はない。   When the metal part 11 having a desired thickness and shape is obtained, the surface metal layer 13 is formed on the surface of the metal part 11 by a predetermined thickness, for example, in the case of silver plating, by immersion in a plating bath for each mother substrate 10. It is formed to have a thickness of about 0.1 to 0.5 μm (see FIG. 4B). The first resist layer 12 and the second resist layer 16 have sufficient resistance to the plating solution used in the plating bath, so that the first resist layer 12 and the second resist layer 16 do not deteriorate, maintain the function as the resist layer, and It is possible to prevent plating from adhering to places other than the place. Further, when plating the front surface metal layer 13, since the back surface of the mother substrate 10 is covered with the resist layer 18, there is no adhesion of plating.

表面金属層１３を形成後、母型基板１０表面側の第一レジスト層１２、第二レジスト層１６、及び裏面側のレジスト層１８をそれぞれ除去（溶解除去、膨潤除去）すると（図４（Ｃ）参照）、半導体装置用基板１が完成する。この時、第二レジスト層１６及びその下に形成されている第一レジスト層１２が除去することで、貫通孔１１ｅを有する規制部１１ａが現れる。   After the front surface metal layer 13 is formed, the first resist layer 12, the second resist layer 16 on the front side of the matrix substrate 10 and the resist layer 18 on the back side are removed (dissolution removal and swelling removal) (FIG. 4C )), The semiconductor device substrate 1 is completed. At this time, by removing the second resist layer 16 and the first resist layer 12 formed thereunder, the regulating portion 11a having the through hole 11e appears.

続いて、得られた半導体装置用基板１を用いた半導体装置の製造について説明すると、まず、半導体装置用基板１における貫通孔１１ｅ内に、半導体素子１４を挿入搭載し、規制部１１ａによって半導体素子１４を規制固定状態とする。そして、半導体素子１４表面の電極と、これに対応する各電極部１１ｂとに、金線等のワイヤ１５を接合し、半導体素子１４と各電極部１１ｂとを電気的接続状態とする（図５（Ａ）参照）。この配線による電気的接続は、超音波ボンディング装置等により実施される。電極部１１ｂの表面には表面金属層１３が形成されているため、ワイヤ１５との接合を確実なものとすることができ、接続の信頼性を高められる。なお、ワイヤ１５によって半導体素子１４と電極部１１ｂとを接続する時に、半導体素子１４がその配置箇所から脱落するおそれがあるが、これを防ぐために、半導体素子１４の裏面や半導体素子１４の配置箇所に予め仮接着剤（ダイアタッチフィルム、樹脂フィルム、樹脂ペーストなど）を設けておくと良い。   Next, the manufacture of a semiconductor device using the obtained semiconductor device substrate 1 will be described. First, the semiconductor element 14 is inserted and mounted in the through hole 11e of the semiconductor device substrate 1, and the semiconductor element 14 is 14 is set in the regulation fixed state. Then, a wire 15 such as a gold wire is bonded to the electrode on the surface of the semiconductor element 14 and each of the corresponding electrode parts 11b, and the semiconductor element 14 and each of the electrode parts 11b are electrically connected (FIG. 5). (A)). The electrical connection by the wiring is performed by an ultrasonic bonding device or the like. Since the surface metal layer 13 is formed on the surface of the electrode portion 11b, the connection with the wire 15 can be ensured, and the connection reliability can be improved. When the semiconductor element 14 and the electrode portion 11b are connected to each other by the wire 15, the semiconductor element 14 may fall off from the place where the semiconductor element 14 is arranged. It is preferable to provide a temporary adhesive (a die attach film, a resin film, a resin paste, etc.) in advance.

半導体素子１４と各電極部１１ｂとの接続が完了したら、母型基板１０の表面側における金属部１１等のある半導体装置となる範囲を、熱硬化性エポキシ樹脂等の封止材１９で封止し、半導体素子１４やワイヤ１５を外部から隔離した保護状態とする（図５（Ｂ）参照）。詳細には、母型基板１０の表面側を上型となるモールド金型に装着し、母型基板１０に下型の役割を担わせつつ、モールド金型内に封止材１９となるエポキシ樹脂を圧入するという過程で封止が実行され、母型基板１０上では、一つの半導体装置となる複数の電極部１１ｂが多数整列状態のままで一様に封止され、半導体装置が多数つながった状態で現れることとなる。   When the connection between the semiconductor element 14 and each of the electrode portions 11b is completed, the semiconductor device including the metal portion 11 on the surface side of the mother substrate 10 is sealed with a sealing material 19 such as a thermosetting epoxy resin. Then, the semiconductor element 14 and the wire 15 are brought into a protection state in which they are isolated from the outside (see FIG. 5B). In detail, the front surface side of the mother substrate 10 is attached to a mold die serving as an upper mold, and an epoxy resin serving as a sealing material 19 is provided in the mold die while the mother substrate 10 plays a role of a lower mold. Is sealed in the process of press-fitting, a plurality of electrode portions 11b to be one semiconductor device are uniformly sealed on the mother substrate 10 in a state where many are aligned, and a large number of semiconductor devices are connected. Will appear in a state.

この多数つながった状態の半導体装置が得られたら、母型基板１０を除去し、各半導体装置の底部に金属部１１の裏面側及び半導体素子１４の裏面側が露出した状態を得る（図５（Ｃ）参照）。ステンレス製である母型基板１０の除去には、半導体装置側から母型基板１０を物理的に引き剥がして除去する方法を用いる。母型基板１０に強度及び剥離性に優れるステンレスを用いることで、半導体装置側から母型基板１０を引き剥がして速やかに分離除去することができる。   When the semiconductor devices in a multi-connected state are obtained, the mother substrate 10 is removed to obtain a state in which the back surface of the metal part 11 and the back surface of the semiconductor element 14 are exposed at the bottom of each semiconductor device (see FIG. )reference). The method of removing the master substrate 10 made of stainless steel by physically peeling the master substrate 10 from the semiconductor device side is used. By using stainless steel having excellent strength and releasability for the matrix substrate 10, the matrix substrate 10 can be peeled off from the semiconductor device side and quickly separated and removed.

この他、母型基板１０を除去する方法として、母型基板１０をエッチング（溶解）させる方法を用いることもできる。このエッチングの場合、母型基板１０は溶解するが薄膜１１ｄや金属部１１の材質が冒されないような選択エッチング性を有するエッチング液を用いることとなる。溶解させて除去する場合では、半導体装置側に過大な力が加わらないため、母型基板１０の除去に伴う悪影響が生じる確率を小さくできる。   In addition, as a method of removing the mother substrate 10, a method of etching (dissolving) the mother substrate 10 can be used. In the case of this etching, an etching solution having a selective etching property that dissolves the matrix substrate 10 but does not affect the material of the thin film 11d or the metal portion 11 is used. In the case of dissolving and removing, since an excessive force is not applied to the semiconductor device side, it is possible to reduce the probability of causing an adverse effect due to the removal of the master substrate 10.

母型基板１０を除去された半導体装置の底部では、露出する金属部１１の裏面側と、封止材１９の裏面側とが略同一平面上に位置する状態となっている。母型基板１０の除去後、多数つながった状態の半導体装置を一つ一つ切り離せば、一つの半導体装置７０としての完成品となる。   At the bottom of the semiconductor device from which the mother substrate 10 has been removed, the back surface side of the exposed metal part 11 and the back surface side of the sealing material 19 are positioned substantially on the same plane. After the removal of the mother substrate 10, a large number of connected semiconductor devices are cut off one by one to obtain a completed product as one semiconductor device 70.

得られた半導体装置７０内部において、金属部１１の上端周縁を張出し部１１ｃとして略庇状に張り出し形成し、封止材１９による封止状態で、この張出し部１１ｃが封止材１９に囲まれて固定されていることから、樹脂同士で密着し強固に一体化した封止材１９に張出し部１１が食込んで、金属部１１に加わる外力に対する抵抗体の役割を果たすこととなり、母型基板１０にステンレス等を用い、半導体装置側から母型基板１０を物理的に引き剥がして除去する場合など、金属部１１裏面側に装置外装から引離そうとする外力が加わっても、該張出し部１１が金属部１１の移動を妨げ、金属部１１の他部分に対するズレ等をなくすことができ、製造時における歩留りを向上させられると共に、半導体装置としての強度を高められ、使用時の耐久性や半導体装置動作の信頼性も高められる。   Inside the obtained semiconductor device 70, the peripheral edge of the upper end of the metal portion 11 is formed as an overhang 11 c so as to extend in a substantially eaves-like manner, and the overhang 11 c is surrounded by the encapsulant 19 in a state of being sealed by the encapsulant 19. The protrusion 11 penetrates into the sealing material 19, which is tightly integrated with the resin, and plays a role of a resistor against an external force applied to the metal part 11. For example, when stainless steel or the like is used as the base 10 and the mother substrate 10 is physically peeled off from the semiconductor device side and removed, even if an external force is applied to the back side of the metal portion 11 to separate it from the exterior of the device, the overhang portion 11 can prevent the movement of the metal portion 11 and can eliminate the displacement of the metal portion 11 with respect to other portions, thereby improving the yield during manufacturing, increasing the strength as a semiconductor device, and improving the performance during use. Reliability of durability and semiconductor device operation is also enhanced.

このように、本実施形態に係る半導体装置用基板１は、母型基板１０上に規制部１１ａを設けることから、この半導体装置用基板１を用いた半導体装置７０の製造にあたり、半導体素子１４の位置ズレを防止することができる。そして、規制部１１ａを半導体装置製造工程で半導体素子１４を挿入、規制可能な大きさの貫通孔１１ｅとすることから、この半導体装置用基板１を用いた半導体装置７０の製造にあたり、従来のように半導体素子搭載部の上面に搭載される場合と比べて、半導体素子１４の搭載位置を下げることができ、半導体素子１４上面や、電極部１１ｂと半導体素子１４とを接合するワイヤ１５等の高さも下がる分、半導体装置７０の厚さを小さくして製造することができ、半導体装置７０の低背化を実現できる。また、半導体素子１４の位置が下がって、ワイヤ１５が接合する半導体素子１４と電極部１１ｂの各上面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量を削減してコスト低減にも寄与できる。   As described above, the semiconductor device substrate 1 according to the present embodiment is provided with the restricting portions 11 a on the master substrate 10. Therefore, when manufacturing the semiconductor device 70 using the semiconductor device substrate 1, Position displacement can be prevented. In the manufacturing process of the semiconductor device 70 using the semiconductor device substrate 1, the regulating portion 11 a is a through hole 11 e having a size that allows the semiconductor element 14 to be inserted and regulated in the semiconductor device manufacturing process. The mounting position of the semiconductor element 14 can be lowered as compared with the case where the semiconductor element 14 is mounted on the upper surface of the semiconductor element mounting portion, and the height of the upper surface of the semiconductor element 14 or the wire 15 for joining the electrode portion 11b and the semiconductor element 14 can be increased. As a result, the semiconductor device 70 can be manufactured with a reduced thickness, and the height of the semiconductor device 70 can be reduced. In addition, since the position of the semiconductor element 14 is lowered and the upper surfaces of the semiconductor element 14 and the electrode portion 11b to which the wire 15 is bonded are closer to each other, the wire length can be shortened, and the wire usage can be reduced to reduce cost. Can also contribute.

ここで、本実施形態の半導体装置用基板１は、貫通孔１１ｅの形状をストレート状としているが、テーパ状としても良い。このテーパ状の貫通孔として、母型基板の表面側（半導体装置の裏面側）に向かって拡がるテーパ状の貫通孔とすれば、半導体装置の製造にあたり、係る貫通孔内に半導体素子を挿入後、半導体素子が脱落しにくい構造とすることができる。また、母型基板の表面側（半導体装置の裏面側）に向かって窄まるテーパ状の貫通孔とすれば、半導体装置の製造にあたり、係る貫通孔内への半導体素子の挿入がしやすい構造とすることができる。   Here, in the semiconductor device substrate 1 of the present embodiment, the shape of the through hole 11e is straight, but may be tapered. If the tapered through-hole is a tapered through-hole that expands toward the front surface side (the back surface side of the semiconductor device) of the mother substrate, the semiconductor device is manufactured after the semiconductor element is inserted into the through-hole. In addition, a structure in which the semiconductor element does not easily fall can be provided. Further, if a tapered through hole narrowing toward the front surface side (back surface side of the semiconductor device) of the master substrate is used, a structure in which a semiconductor element can be easily inserted into the through hole in manufacturing a semiconductor device is provided. can do.

また、図７に示すように、母型基板１０の表面側（半導体装置７１の裏面側）に向かって窄まるテーパ状の貫通孔１１ｅの中途（壁面）に半導体素子１４を配設することもできる。係る構造によっても、半導体素子１４の位置ズレの防止及び半導体装置の低背化の実現が可能となる。このテーパ状の貫通孔１１ｅは、第一レジスト層１２及び第二レジスト層１６を所望のテーパ形状に対応させて形成することで、容易に得ることができる。なお、図７に示す半導体装置７１は、その底部から半導体素子１４が露出されているが、半導体素子１４の底部とテーパ状の貫通孔内壁とで囲まれる空間に封止材１９を封入させることで、半導体装置の底部から半導体素子１４が露出されない構成（半導体素子１４の裏面が封止材１９で覆われた構成）とすることもできる。   In addition, as shown in FIG. 7, the semiconductor element 14 may be provided in the middle (wall surface) of the tapered through hole 11e narrowing toward the front surface side (the back surface side of the semiconductor device 71) of the matrix substrate 10. it can. With such a structure as well, it is possible to prevent displacement of the semiconductor element 14 and to reduce the height of the semiconductor device. The tapered through-hole 11e can be easily obtained by forming the first resist layer 12 and the second resist layer 16 so as to correspond to a desired tapered shape. In the semiconductor device 71 shown in FIG. 7, the semiconductor element 14 is exposed from the bottom, but the sealing material 19 is sealed in a space surrounded by the bottom of the semiconductor element 14 and the inner wall of the tapered through hole. Thus, a configuration in which the semiconductor element 14 is not exposed from the bottom of the semiconductor device (a configuration in which the back surface of the semiconductor element 14 is covered with the sealing material 19) can be adopted.

（第２実施形態）
第２実施形態に係る半導体装置用基板は、上記第１実施形態同様に、母型基板１０と、電極部１１ｂと、規制部１１ａとを備えるものである。図８は、係る構成の半導体装置用基板を用いて製造した半導体装置７２を示している。図８に示すように、規制部１１ａの高さ（貫通孔１１ｅの深さ）が半導体素子１４の厚さ以上に設定されているものである。 (2nd Embodiment)
The semiconductor device substrate according to the second embodiment includes a matrix substrate 10, an electrode portion 11b, and a regulating portion 11a, as in the first embodiment. FIG. 8 shows a semiconductor device 72 manufactured using the semiconductor device substrate having such a configuration. As shown in FIG. 8, the height of the regulating portion 11a (the depth of the through hole 11e) is set to be equal to or greater than the thickness of the semiconductor element 14.

このように、規制部１１ａの高さ寸法を半導体素子１４の厚さ寸法以上に設定されていることで、半導体素子１４の側面全体を規制部１１ａによって規制することができるので、半導体素子１４の位置ズレを防止することができる。また、該規制部１１ａが貫通孔１１ｅから成るものであると、半導体素子１４の側面全面が規制部１１ａに覆われて規制されることになるので、より確実に半導体素子１４の位置ズレを防止することができる。また、半導体素子１４の側面が規制部１１ａと対向配置されることになるので、放熱性を向上することができる。   Since the height of the regulating portion 11a is set to be equal to or greater than the thickness of the semiconductor element 14, the entire side surface of the semiconductor element 14 can be regulated by the regulating portion 11a. Position displacement can be prevented. Further, when the regulating portion 11a is formed of the through hole 11e, the entire side surface of the semiconductor element 14 is covered and regulated by the regulating portion 11a, so that the positional deviation of the semiconductor element 14 can be more reliably prevented. can do. In addition, since the side surface of the semiconductor element 14 is arranged to face the restricting portion 11a, heat dissipation can be improved.

なお、所望の高さ（深さ）の規制部１１ａ（貫通孔１１ｅ）を得るためには、上記第１実施形態における半導体装置用基板の製造工程の第一レジスト層１２・第二レジスト層１６を形成する工程（図２（Ｂ）〜図４（Ａ）参照）において、母型基板１０上に形成される第一レジスト層１２及び／又は第二レジスト層１６の厚さを調整、すなわち、第一レジスト層１２及び／又は第二レジスト層１６の厚さを半導体素子１４の厚さ以上に設定することで容易に得られる。   In order to obtain the regulation portion 11a (through hole 11e) having a desired height (depth), the first resist layer 12 and the second resist layer 16 in the manufacturing process of the semiconductor device substrate in the first embodiment are required. (See FIGS. 2B to 4A), the thickness of the first resist layer 12 and / or the second resist layer 16 formed on the master substrate 10 is adjusted, that is, It can be easily obtained by setting the thickness of the first resist layer 12 and / or the second resist layer 16 to be equal to or larger than the thickness of the semiconductor element 14.

（第３実施形態）
上記実施形態における半導体装置用基板においては、母型基板１０上に電極部１１ｂと規制部１１ａとを別々に設け、この半導体装置用基板を用いた半導体装置の製造工程にて、規制部１１ａに規制されるように半導体素子１４を搭載しているが、第３実施形態に係る半導体装置用基板は、電極部１１ｂに規制部１１ａを兼ねさせる構成としているものである。 (Third embodiment)
In the semiconductor device substrate in the above embodiment, the electrode portion 11b and the regulating portion 11a are separately provided on the master substrate 10, and the regulating portion 11a is provided in the process of manufacturing a semiconductor device using the semiconductor device substrate. Although the semiconductor element 14 is mounted so as to be regulated, the substrate for a semiconductor device according to the third embodiment is configured so that the electrode portion 11b also serves as the regulation portion 11a.

本実施形態に係る半導体装置用基板は、上記実施形態同様、母型基板１０と、電極部１１ｂとを備えるものであり、異なる点として、電極部１１ｂが上記実施形態における規制部１１ａを兼ねている。そして、各電極部１１ｂ間が貫通孔１１ｅに相当することになり、この電極部１１ｂ間に半導体素子１４を配設する。係る電極部１１は、後の半導体装置製造工程で行われる半導体素子１４の配置予定箇所であって、半導体素子１４の外径以上の間隔をあけて母型基板１０上に形成されるものである。図９は、係る構成の半導体装置用基板を用いて製造した半導体装置７３を示している。   The semiconductor device substrate according to the present embodiment includes a matrix substrate 10 and an electrode portion 11b, similarly to the above-described embodiment. The difference is that the electrode portion 11b also serves as the regulating portion 11a in the above-described embodiment. I have. The space between the electrode portions 11b corresponds to the through hole 11e, and the semiconductor element 14 is provided between the electrode portions 11b. The electrode portion 11 is a place where the semiconductor element 14 is to be arranged in a later semiconductor device manufacturing process, and is formed on the matrix substrate 10 with an interval larger than the outer diameter of the semiconductor element 14. . FIG. 9 shows a semiconductor device 73 manufactured using the semiconductor device substrate having such a configuration.

このように、電極部１１ｂに規制部１１ａを兼ねさせた構成とすることで、電極部と規制部とを別々に形成した構成と比べて、規制部の形成を省略することができるので、半導体装置の構成をよりコンパクトにすることができる。また、規制部の形成を省略することにより、規制部の形成領域分だけ母型基板１０上に形成される一つの半導体装置としての取り数を増やすことが可能となり、コストダウンが図れる。   As described above, by employing the configuration in which the electrode portion 11b also serves as the regulating portion 11a, the formation of the regulating portion can be omitted as compared with a configuration in which the electrode portion and the regulating portion are separately formed. The configuration of the device can be made more compact. In addition, by omitting the formation of the restricting portion, it is possible to increase the number of semiconductor devices formed on the mother substrate 10 by the forming region of the restricting portion, thereby achieving cost reduction.

なお、本実施形態に係る半導体装置用基板の製造工程について説明すると、上記第１実施形態における半導体装置用基板の製造工程において、母型基板１０上に第一レジスト層１２（及び第二レジスト層１６）を形成する工程での規制部１１ａに対応するレジストパターンの形成を省略することで形成できる。その他の点は、上記第１実施形態と同様である。また、続く半導体装置用基板を用いた半導体装置の製造工程についても、上記第１実施形態と同様である。   The manufacturing process of the semiconductor device substrate according to the present embodiment will be described. In the manufacturing process of the semiconductor device substrate in the first embodiment, the first resist layer 12 (and the second resist layer 16) can be formed by omitting the formation of a resist pattern corresponding to the regulating portion 11a in the step of forming (16). The other points are the same as in the first embodiment. Further, the manufacturing process of the semiconductor device using the semiconductor device substrate is the same as that of the first embodiment.

（第４実施形態）
第４実施形態に係る半導体装置用基板は、上記実施形態同様に、母型基板１０と、電極部１１ｂと、規制部１１ａとを備えるものである。図１０は、係る構成の半導体装置用基板を用いて製造した半導体装置７４を示している。該規制部１１ａは、ワイヤ１５のループ頂部１５’の直下位置に重なるように配設されている。つまり、規制部１１ａとワイヤ１５のループ頂部１５’とは、半導体装置（半導体装置用基板）の高さ方向において、直線上に位置している。ここで、ループ頂部１５’とは、半導体素子１４の電極と金属電極部１１ｂとを接続するワイヤ１４の最頂点の部分を言う。 (Fourth embodiment)
The semiconductor device substrate according to the fourth embodiment includes a matrix substrate 10, an electrode portion 11b, and a regulation portion 11a, as in the above embodiment. FIG. 10 shows a semiconductor device 74 manufactured using the semiconductor device substrate having such a configuration. The restricting portion 11a is disposed so as to overlap immediately below the loop top 15 'of the wire 15. That is, the regulating portion 11a and the loop top 15 'of the wire 15 are located on a straight line in the height direction of the semiconductor device (substrate for semiconductor device). Here, the loop apex 15 'refers to the topmost portion of the wire 14 connecting the electrode of the semiconductor element 14 and the metal electrode 11b.

このように、規制部１１ａをワイヤ１５のループ頂部１５’の直下位置に配置させることで、半導体素子１４の位置ズレを防止することができるとともに、規制部１１ａとワイヤ１５とが接触することを可及的に防止することができる。   By arranging the restricting portion 11a directly below the loop top 15 'of the wire 15 as described above, it is possible to prevent the semiconductor element 14 from being misaligned and to prevent the restricting portion 11a from coming into contact with the wire 15. It can be prevented as much as possible.

なお、係る構成の半導体装置用基板を得るためには、上記第１実施形態における半導体装置用基板の製造工程において、母型基板１０上に配設される半導体素子１４の配置領域部分に対応する第一レジスト層１２及び／又は第二レジスト層１６の形状や厚さを調整することで容易に得られる。   In order to obtain a semiconductor device substrate having such a configuration, in the manufacturing process of the semiconductor device substrate according to the first embodiment, the semiconductor device substrate corresponds to the arrangement region of the semiconductor element 14 disposed on the master substrate 10. It can be easily obtained by adjusting the shape and thickness of the first resist layer 12 and / or the second resist layer 16.

（第５実施形態）
第５実施形態に係る半導体装置用基板は、母型基板１０と、電極部１１ｂと、規制部１１ａとを備えるものであり、規制部１１ａとして貫通孔１１ｅが形成されており、該貫通孔１１ｅと重なるように凹部１１ｆが設けられているものである。この凹部１１ｆの底面（底面積）は貫通孔１１ｅの開口（開口面積）より大きいものである。図１１は、係る構成の半導体装置用基板を用いて製造した半導体装置７５を示している。 (Fifth embodiment)
The substrate for a semiconductor device according to the fifth embodiment includes a mother substrate 10, an electrode portion 11b, and a regulating portion 11a. A through hole 11e is formed as the regulating portion 11a. And a concave portion 11f is provided so as to overlap. The bottom surface (bottom area) of the recess 11f is larger than the opening (opening area) of the through hole 11e. FIG. 11 shows a semiconductor device 75 manufactured using the semiconductor device substrate having such a configuration.

このように、貫通孔１１ｅと重なるように凹部１１ｆを設けた構成とすることで、凹部１１ｆの内面による半導体素子１４の位置ズレ防止や半導体装置の低背化ができる。しかも、貫通孔１１ｅを覆うように凹部１１ｆの底面上に半導体素子１４を配設することで、半導体素子１４を半導体装置７０の底部（封止材１９の裏面）から奥まった位置に配置させることができ、半導体素子１４を外力から保護することができる。   As described above, by providing the concave portion 11f so as to overlap the through hole 11e, it is possible to prevent the semiconductor element 14 from being displaced by the inner surface of the concave portion 11f and to reduce the height of the semiconductor device. In addition, by disposing the semiconductor element 14 on the bottom surface of the concave portion 11f so as to cover the through hole 11e, the semiconductor element 14 is disposed at a position that is recessed from the bottom of the semiconductor device 70 (the back surface of the sealing material 19). Accordingly, the semiconductor element 14 can be protected from external force.

なお、係る構成の半導体装置用基板を得るためには、上記第１実施形態における半導体装置用基板の製造工程において、母型基板１０上に形成される規制部１１ａ（貫通孔１１ｅ）に対応する第一レジスト層１２及び／又は第二レジスト層１６の形状や厚さを調整することで容易に得られる。   In order to obtain a semiconductor device substrate having such a configuration, in the manufacturing process of the semiconductor device substrate according to the first embodiment, the semiconductor device substrate corresponds to the regulating portion 11a (through hole 11e) formed on the master substrate 10. It can be easily obtained by adjusting the shape and thickness of the first resist layer 12 and / or the second resist layer 16.

半導体装置７５の底部において、貫通孔１１ｅからは半導体素子１４の裏面が露出されるが、上記第１実施形態のように、貫通孔１１ｅ内に封止材１９を封入させることで、図１２に示すように、底部から半導体素子１４が露出されない構成（半導体素子１４の裏面が封止材１９で覆われた構成）の半導体装置７６とすることもできる。   At the bottom of the semiconductor device 75, the back surface of the semiconductor element 14 is exposed from the through hole 11e. By encapsulating the sealing material 19 in the through hole 11e as in the first embodiment, as shown in FIG. As shown, the semiconductor device 76 may be configured such that the semiconductor element 14 is not exposed from the bottom (the back surface of the semiconductor element 14 is covered with the sealing material 19).

（第６実施形態）
第６実施形態に係る半導体装置用基板は、母型基板１０と、電極部１１ｂとを備えるものであり、電極部１１ｂが規制部１１ａを兼ねており（電極部１１間が貫通孔１１ｅに相当）、電極部１１ｂの上部には、延設部２０が一体的に設けられているものである。図１３は、係る構成の半導体装置用基板を用いて製造した半導体装置７７を示している。延設部２０は、半導体素子１４に向かって延びるように設けられており、延設部２０と半導体素子１４の電極とが電気的に接続されている。 (Sixth embodiment)
The semiconductor device substrate according to the sixth embodiment includes a mother substrate 10 and an electrode portion 11b, and the electrode portion 11b also serves as a regulating portion 11a (a space between the electrode portions 11 corresponds to a through hole 11e). ), The extension portion 20 is integrally provided above the electrode portion 11b. FIG. 13 shows a semiconductor device 77 manufactured using the semiconductor device substrate having such a configuration. The extension 20 is provided so as to extend toward the semiconductor element 14, and the extension 20 and the electrode of the semiconductor element 14 are electrically connected.

このように、電極部１１ｂ（規制部１１ａ）の上部に延設部２０が設けられた構成とすることで、電極部１１ｂ（規制部１１ａ）によって半導体素子１４の側面を規制するだけでなく、延設部２０によって半導体素子１４の上面も規制することができるので、半導体素子１４の各面から位置ズレを抑制できる。   As described above, the configuration in which the extending portion 20 is provided above the electrode portion 11b (the regulating portion 11a) allows not only the side surface of the semiconductor element 14 to be regulated by the electrode portion 11b (the regulating portion 11a), but also Since the upper surface of the semiconductor element 14 can also be regulated by the extension 20, positional deviation from each surface of the semiconductor element 14 can be suppressed.

なお、係る構成の半導体装置用基板を得るためには、上記第１実施形態における半導体装置用基板の製造工程において、母型基板１０上に電極部１１ｂ（規制部１１ａ）を形成し、電極部１１ｂ間に半導体素子１４を配置させた後、延設部２０を形成するために、電極部１１ｂ（規制部１１ａ）上面及び半導体素子１４上面が露出されるようにレジスト層を形成した後にメッキすることで得られる。   In order to obtain the semiconductor device substrate having such a configuration, in the manufacturing process of the semiconductor device substrate according to the first embodiment, the electrode portion 11b (the regulating portion 11a) is formed on the master substrate 10 and the electrode portion 11b is formed. After disposing the semiconductor element 14 between 11b, in order to form the extension part 20, plating is performed after forming a resist layer so that the upper surface of the electrode part 11b (regulator 11a) and the upper surface of the semiconductor element 14 are exposed. It can be obtained by:

上記実施形態においては、図１４（Ａ）に示すように、規制部１１ａの半導体素子１４と対向する側（第二レジスト層１６の側面に接する側）の上端周縁には張出部１１ｃが形成されていないが、図１４（Ｂ）に示すように、規制部１１ａの半導体素子１４と対向する側にも張出部１１ｃを形成しても良い。この場合、第一レジスト層１２上に形成していた第二レジスト層１６の形成を省略する、つまり、図３（Ａ）に示すように、母型基板１０上に第一レジスト層１２を形成した後に、第二レジスト層１６を形成せずに、第一レジスト層１２の厚さを越えるまでメッキすると良い。また、金属部１１（規制部１１ａ、電極部１１ｂ）の上端周縁に張出部１１ｃを形成しないストレート状にしても良い（図１４（Ｃ）参照）。この場合、図３（Ａ）に示すように、母型基板１０上に第一レジスト層１２を形成後、第一レジスト層１２の厚さを越えないようにメッキすると良い。   In the above embodiment, as shown in FIG. 14A, an overhang portion 11c is formed on the upper edge of the side of the regulating portion 11a facing the semiconductor element 14 (the side in contact with the side surface of the second resist layer 16). Although not shown, as shown in FIG. 14B, an overhang portion 11c may be formed on the side of the regulating portion 11a facing the semiconductor element 14. In this case, the formation of the second resist layer 16 formed on the first resist layer 12 is omitted, that is, the first resist layer 12 is formed on the master substrate 10 as shown in FIG. After that, plating is preferably performed until the thickness exceeds the thickness of the first resist layer 12 without forming the second resist layer 16. Alternatively, the metal portion 11 (the regulating portion 11a and the electrode portion 11b) may be formed in a straight shape without the protruding portion 11c formed on the peripheral edge of the upper end (see FIG. 14C). In this case, as shown in FIG. 3A, after forming the first resist layer 12 on the matrix substrate 10, it is preferable to perform plating so as not to exceed the thickness of the first resist layer 12.

また、上記実施形態において、第一レジスト層１２及び第二レジスト層１６を形成する際には、感光性レジスト材１２ａを配設して露光・現像を行った後に感光性レジスト材１６ａを配設しているが、感光性レジスト材１２ａを配設して露光した後に、現像を行わないまま感光性レジスト材１６ａを配設し、露光してから、感光性レジスト材１２ａと感光性レジスト材１６ａとを一緒に現像するようにしても良い。また、第一レジスト層１２及び第二レジスト層１６を形成するにあたり、マスクフィルム５０・５１を用いて露光しているが、直描装置によって露光しても良い。   In the above embodiment, when the first resist layer 12 and the second resist layer 16 are formed, the photosensitive resist material 12a is provided, and after performing exposure and development, the photosensitive resist material 16a is provided. However, after the photosensitive resist material 12a is provided and exposed, the photosensitive resist material 16a is provided without performing development and exposed, and then the photosensitive resist material 12a and the photosensitive resist material 16a are exposed. May be developed together. In forming the first resist layer 12 and the second resist layer 16, the exposure is performed using the mask films 50 and 51. However, the exposure may be performed using a direct drawing apparatus.

また、上記実施形態において、貫通孔１１ｅ内に半導体素子１４を配設する場合に、貫通孔１１ｅ内面と半導体素子１４外面との間に隙間があっても良いし、貫通孔１１ｅ内面と半導体素子１４外面との間に隙間がなく、規制部１１ａと半導体素子１４とが密接して配設されてあっても良い。   Further, in the above embodiment, when the semiconductor element 14 is disposed in the through hole 11e, a gap may be provided between the inner surface of the through hole 11e and the outer surface of the semiconductor element 14, or the inner surface of the through hole 11e may be connected to the semiconductor element. There may be no gap between the outer surface of the semiconductor device 14 and the regulating portion 11a and the semiconductor element 14 may be arranged closely.

また、アースをとるために、規制部１１ａを接地電極として兼用させ、アースワイヤ（グランドワイヤ）を規制部１１ａと接続するようにしても良い。   Further, in order to take the ground, the regulating portion 11a may be used also as a ground electrode, and an earth wire (ground wire) may be connected to the regulating portion 11a.

１ 半導体装置用基板
１０ 母型基板
１１ 金属部
１１ａ 規制部
１１ｂ 電極部
１１ｃ 張出し部
１１ｄ 薄膜
１１ｅ 貫通孔
１１ｆ 凹部
１２ 第一レジスト層
１２ａ レジスト材
１３ 表面金属層
１４ 半導体素子
１５ ワイヤ
１６ 第二レジスト層
１６ａ レジスト材
１８ レジスト層
１９ 封止材
２０ 延設部
７０〜７７ 半導体装置 REFERENCE SIGNS LIST 1 semiconductor device substrate 10 master substrate 11 metal portion 11a regulating portion 11b electrode portion 11c overhang portion 11d thin film 11e through hole 11f concave portion 12 first resist layer 12a resist material 13 surface metal layer 14 semiconductor element 15 wire 16 second resist layer Reference Signs List 16a Resist material 18 Resist layer 19 Sealing material 20 Extension 70-77 Semiconductor device

Claims (1)

母型基板上に少なくとも電極部となる金属部と、半導体素子を規制する規制部とが設けられ、該規制部の上端に張出し部が形成された半導体装置用基板の製造方法において、At least a metal part serving as an electrode part on the mother substrate and a regulating part for regulating the semiconductor element are provided, and in a method of manufacturing a semiconductor device substrate in which an overhang is formed at the upper end of the regulating part,
前記母型基板上に、前記金属部および前記規制部の形成位置に対応する第一レジスト層を形成する工程と、Forming a first resist layer corresponding to the formation position of the metal part and the regulation part on the mother substrate;
少なくとも前記第一レジスト層上に、前記規制部の形成位置に対応する第二レジスト層を形成する工程と、Forming a second resist layer at least on the first resist layer corresponding to the formation position of the regulating portion,
前記母型基板表面の前記第一レジスト層および第二レジスト層で覆われていない露出領域に、前記金属部および前記規制部を形成する工程とを有し、Forming the metal part and the regulating part in an exposed area of the surface of the matrix substrate that is not covered with the first resist layer and the second resist layer,
前記規制部は前記第一レジスト層の厚さを越える一方、前記第二レジスト層を越えない厚さで形成することを特徴とする半導体装置用基板の製造方法。The method for manufacturing a substrate for a semiconductor device according to claim 1, wherein the regulating portion is formed to have a thickness exceeding the thickness of the first resist layer but not exceeding the second resist layer.
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