JP6536187B2 - Array substrate and liquid crystal display device provided with the array substrate - Google Patents

Description

  The present invention relates to a wiring structure and a display device, and more particularly, to a wiring structure including a plurality of lead wirings and a display device using the same.

  A liquid crystal display panel constituting a liquid crystal display device has a plurality of gate lines (scanning signal lines) and a plurality of source lines (image signal lines) arranged in a matrix. In the display area of the liquid crystal display panel, a plurality of display pixels are formed corresponding to respective intersections of the gate lines and the source lines. The plurality of gate signal lines are driven by a gate driver IC, and the plurality of source lines are driven by a source driver IC.

  The gate wiring and the source wiring are formed on the liquid crystal surface side of the liquid crystal display panel. The routing to each wire is routed from the display area to the driver IC mounted outside the display area. This wiring arrangement is performed using a space around the display area (hereinafter, this space may be referred to as a frame). Therefore, the routing distance of each routing wire routed to the display area differs depending on the mounting position of the driver IC. Therefore, the electrical resistances of the respective lead-out lines also differ, and display unevenness occurs due to the resistance difference between the lines. In order to keep the wiring resistance difference low, a vacant space of a frame is used to control the wiring length and the wiring width. However, it is difficult to adjust the resistance difference and it is difficult to suppress the occurrence of display unevenness.

  The routing distance of the routing wiring changes depending on the layout and wiring layout of the driver IC and the number of outputs from the driver IC to the signal line in the display area. For example, the lead wiring length may be different between the clockwise rotation and the counterclockwise rotation of the display area. In a liquid crystal display panel having a large panel outer size and a small number of display pixels, there is a space for a frame space in which each wire connected from the driver IC to the display surface is routed. Therefore, for example, when the routing distance of the source wiring is different between the left and right of the display as in the arrangement of the source driver IC, the resistance between the respective wirings can be adjusted by adjusting the wiring width and length. . (Patent Document 1, 2)

  However, it has become difficult to secure a sufficient space for the frame with the recent increase in display definition and narrowing of the frame of the panel. Therefore, it has become necessary to form routed wiring with a wiring width as narrow as the manufacturing limit. In this case, the surplus space is narrowed, which makes it difficult to adjust the resistance in the wiring width. Therefore, it becomes necessary to adjust the resistance only by the wiring length. In this case, as described above, since the wiring length is determined by the arrangement of the driver IC and the number of outputs, it is difficult to suppress the display unevenness due to the resistance difference between the wirings.

  In such a situation, by providing a conductor pattern overlapping with the wiring through the insulating film in the frame, the difference in the wiring load distribution caused by the difference in the length of each wiring, that is, the difference in RC delay is reduced. Technology is known. (Patent Document 3)

Patent Document 1: Japanese Patent Application Publication No. 2007-047259 Japanese Patent Application Laid-Open No. 7-134305 Japanese Patent Publication No. 2005-529360 publication gazette (Figure 2)

  In the conventional liquid crystal display device, there is a problem that a difference in resistance occurs between the wires because the lead distances of the wires are different, and display unevenness having a wire load distribution occurs in the entire wire region. Although there is known a technique for improving the difference in RC delay by providing a conductor pattern overlapping with the wiring and the insulating film in order to solve the problem, fine adjustment is difficult and adjustment range is narrow by itself. A problem has arisen.

  The present invention has been made to solve such problems, and a wiring structure and a display device capable of adjusting a wiring load difference to be constant by performing a wiring load adjustment using a wiring capacitance for a resistance difference of lead wiring. Intended to provide.

  The array substrate according to the present invention has a display area and a frame area outside the display area on an insulating substrate, and in the display area, a gate wiring, and a source wiring intersecting the gate wiring via an insulating film. And a switching element formed in the vicinity of the intersection of the gate wiring and the source wiring, and a pixel electrode electrically connected to the switching element are formed, and the frame region is connected to the A first conductive pattern having an extended gate lead-out wiring and at least a region overlapping with the gate lead-out wiring via an insulating film, a capacitive insulating film on the first conductive pattern, and at least a capacitive insulating film and an insulating film And an array substrate having a second conductive pattern having a region overlapping with the gate lead-out wiring via the first conductive pattern and the gate lead-out distribution. The area where each of the second and third conductive patterns overlap with each other is smaller as the wiring resistance of the gate lead-out wiring is higher. The area where each of the second conductive patterns and each gate lead-out wiring overlap each other is the wiring for the gate lead-out wiring. The array substrate is characterized in that it is disposed to be smaller as the resistance is higher.

  Provided are an array substrate and a display device capable of adjusting a difference in wiring load to a constant value by performing wiring load adjustment using wiring capacitance for a difference in resistance of routed wiring.

FIG. 1 is a plan view showing an array substrate according to Embodiment 1 of the present invention. FIG. 6A is a plan view and a cross-sectional view of a display area of the array substrate according to Embodiment 1 of the present invention. It is sectional drawing of the frame part of the array substrate which concerns on Embodiment 1 of this invention. It is a top view which shows the array substrate which concerns on Embodiment 2 of this invention. FIG. 16 is a plan view showing an array substrate according to a modification of the second embodiment of the present invention.

Embodiment 1
FIG. 1 shows a plan view of an array substrate used in a liquid crystal display panel according to the present invention. An array substrate 1 in which elements and the like described later are formed on an insulating substrate and an opposing substrate 2 are bonded to be opposed to each other. A color filter including, for example, three RGB colors may be formed on the counter substrate 2 as necessary. Although not shown, liquid crystal is sealed between the array substrate 1 and the counter substrate 2 and sealed with a seal or the like so as not to leak.

  Next, the array substrate 1 will be described. The array substrate 1 has a display area 11 composed of a plurality of pixels arranged in a matrix and a frame area 12 which is an outer peripheral area thereof. That is, the non-display area surrounding the outer periphery of the display area 11 is the frame area 12.

  In the display area 11, on the array substrate 1, a plurality of source wirings 132 and a plurality of gate wirings 131 cross each other and are arranged in a matrix. That is, the array substrate 1 is a wiring substrate on which a plurality of wirings are formed. In the display area 11, each of the gate lines 131 is formed to extend in the lateral direction in the drawing. A plurality of gate wirings 131 formed to extend in the lateral direction are arranged side by side in the longitudinal direction. In the display area 11, gate wirings 131 having the same width are formed at the same intervals.

  On the other hand, each of the source lines 132 is formed to extend along the vertical direction in the drawing. A plurality of source wirings 132 formed to extend in the longitudinal direction are arranged side by side in the lateral direction in the drawing. In FIG. 1, source interconnections 132 having the same width are formed at the same intervals.

  An area divided by the source wiring 132 and the gate wiring 131 is a pixel. Each pixel includes a pixel electrode for applying a voltage to the liquid crystal, and a switching element for controlling the application of the voltage. The switching element is often provided in the vicinity of the intersection of the source wiring 132 and the gate wiring 131, and is typically a TFT (Thin Fi lm t s i s t o r), which will be described in detail below.

  FIG. 2 shows a plan view and a sectional view of the periphery of a pixel in the display area. The cross-sectional view is a cross-sectional view at a point described by D-D in the plan view. A gate insulating film 21 is formed on the insulating substrate 20 so as to cover the gate wiring 131 and the gate electrode extended from the gate wiring 131. The gate insulating film 21 can be made of silicon oxide, silicon nitride or the like. In the present embodiment, since the structure in which the gate lead-out wiring and the gate wiring 131 described later are integrally formed is dealt with, the gate lead-out wiring is also formed simultaneously with the gate wiring.

  Next, the semiconductor film 22 is formed on the gate insulating film 21. As the semiconductor film 22, an oxide semiconductor film such as an a-Si (amorphous silicon) film, a p-Si (polycrystalline silicon film) film, or In-Ga-Zn-O can be used. A source electrode 23 extended from the source wiring 132 is formed on the semiconductor film 22. Thus, the source voltage can be supplied to the source region of the semiconductor film 22.

  Furthermore, the drain electrode 24 is formed on the drain region of the semiconductor film 22. The source electrode 23 and the drain electrode 24 can be formed in the same process as the source wiring 132.

  For the gate wiring 131 and the source wiring 132, for example, a low-resistance metal material such as Al, Cr, or Mo can be used. As described above, the gate wiring 131 and the source wiring 132 are formed in different wiring layers. That is, the source wiring 132 and the gate wiring 131 are disposed so as to intersect at substantially right angles with each other via the gate insulating film 21, and a TFT having a gate electrode, a semiconductor film, a drain electrode, and a source electrode near the intersection It will be arranged.

  Then, an interlayer insulating film 25 is formed on the TFT including the drain electrode 24. Furthermore, the pixel electrode 26 is formed on the interlayer insulating film 25. The drain electrode 24 is connected to the pixel electrode 26 through a contact hole CH provided in the interlayer insulating film 25. Therefore, the voltage transmitted to the drain electrode 24 is also applied to the pixel electrode 26.

  When the liquid crystal display panel is of a transmissive type, the pixel electrode 26 is formed of a transparent conductive film such as ITO. Further, in the lateral electric field type or FFS type liquid crystal panel, the capacitive insulating film 27 is provided on the upper layer of the pixel electrode 26 and the common electrode 28 is provided to face the pixel electrode 26 via the capacitive insulating film 27. The common electrode 28 is formed of a transparent conductive film and has a slit-shaped opening. That is, the slit-shaped portion is a region where the common electrode 28 is not formed, and the pixel electrode 26 in the lower layer is exposed through the capacitive insulating film 27.

  Although the common electrode 28 is described as a strip-like pattern extending laterally across the plurality of pixels in the drawing, it may not be such a pattern shape. The common electrode 28 is generally formed over almost the entire surface of the display area 11 in many cases, but an opening may be provided as needed, for example, not provided above the TFT. Further, as described later, a common potential is applied to the common electrode 28.

  In the TFT completed as described above, when a gate signal is supplied to the gate wiring 131, a gate voltage is applied to a predetermined gate electrode. Thus, the TFT is turned on, and an image display signal voltage is supplied from the source wiring to the pixel electrode through the source electrode and the drain electrode.

  Returning to FIG. 1, of the frame area 12, the portion on the right side of the display area 11 in the drawing is taken as the right portion 12 a of the frame area 12. Further, in the frame area 12, a lower portion in the drawing than the display area 11 is taken as the lower side 12 b of the frame area 12. Further, in the frame area 12, the upper part of the display area 11 in the drawing is referred to as the upper part 12 c of the frame area 12 and the left part is similarly referred to as the left part 12 d of the frame area 12. Therefore, the display area 11 is surrounded by the right side portion 12a, the lower portion 12b, the upper portion 12c, and the left side portion 12d of the frame area 12.

  In FIG. 1, the source driver IC 142 is disposed on the lower side of the display area 11, ie, in the lower portion 12b, and the gate driver IC 141 is disposed on the right side, ie, in the right side 12a. The gate driver IC 141 is connected to the gate wiring 131 via the gate lead-out wiring 133. Further, the source driver IC 142 is connected to the source wiring 132 via the source lead wiring 134. That is, the gate lead-out lines 133 are each connected to the gate line 131 and extend to an external terminal (not shown). The same applies to the source lead wiring 134.

  The gate driver IC 141 and the source driver IC 142 each supply a gate signal to the gate wiring 131 or supply an image display signal voltage to the source wiring 132 based on control signals and display data supplied from the outside. Do. By this supply, the TFT is turned on as described above, and the image display signal voltage is supplied to the pixel electrode. On the other hand, since a common potential is applied to the common electrode 28 opposed to the pixel electrode 26, a fringe electric field is generated between the pixel electrode 26 and the common electrode 28 according to the potential difference of both, thereby aligning the liquid crystal. Changes, and a desired amount of transmitted light can be obtained and displayed in each pixel.

  In FIG. 1, the gate lead-out wiring 133 and the gate wiring 131 are provided in one-to-one correspondence. Although both may be formed of mutually different members, they may be integrally formed of the same material. The relationship between the source lead wiring 134 and the source wiring 132 is also the same. In the present embodiment, in order to explain the case where both are integrally formed of the same material, there are cases where the gate wiring 131 includes the gate lead-out wiring 133 and the parts are distinguished by the both names.

  Further, in FIG. 1, the gate lead-out line 133a is a gate lead-out line closer to the upper portion 12c, and the gate lead-out line 133c is a gate lead-out wire closer to the lower portion 12b. The gate lead-out line 133b is a gate lead-out line located near the center of the right side 12a. As can be seen from FIG. 1, the gate lead-out lines 133a and 133c are longer than the gate lead-out line 133b. In addition, the length of the gate lead-out line increases with distance from the center of the right side 12a in the vertical direction in the drawing. At this time, if the width of the lead wiring is constant, the wiring resistance also increases.

  Therefore, the line resistances of the gate lead-out lines 133a and 133c in the right side portion 12a become higher than the line resistance of the gate lead-out line 133b in the central portion of the driver IC 141. When a liquid crystal display panel using an array substrate having such a resistance difference is displayed, display unevenness having a low resistance distribution of the gate routing wiring 133 in the vicinity of the connection portion between the gate routing wiring 133 and the gate wiring 131 Is easier to see as described above.

  The patterns provided to improve such display unevenness are the first conductive pattern 160 and the second conductive pattern 161. The first conductive pattern and the second conductive pattern may be collectively referred to simply as a conductive pattern. The first conductive pattern 160 has a triangular shape in a plan view, and is roughly an isosceles triangle, and is hatched in the figure. The base of this isosceles triangle is along the boundary between the gate wiring 131 and the gate lead-out wiring 133, and the apex angle is arranged near the gate lead-out wiring 133b.

  By such an arrangement, the overlapping length of the first conductive pattern 160 and the gate lead-out line 133 is longest in the vicinity of the gate lead-out line 133 b. The overlapping length becomes shorter as it is separated from the central portion of the right side portion 12a in the vertical direction in the drawing. As described above, the overlapping length is not the same in each gate lead-out wiring, but in more accurate expression, the overlapping lengths are arranged so as to be different in area than the length. About the point from which an overlapping area differs, the effect is mentioned later and it mentions later.

  On the other hand, the shape of the second conductive pattern 161 is a triangle that encloses the first conductive pattern 160, and is roughly an isosceles triangle. In addition, the size relationship of the overlapping area of the second conductive pattern 161 and the gate lead-out lines is substantially the same as in the case of the first conductive pattern 160.

  Next, these conductive patterns will be further described with reference to FIG. FIG. 3 is a cross-sectional view in FIG. 1, and cross-sectional views of portions shown by AA, BB and CC in FIG. 1 are respectively shown in FIG. 3 (a), FIG. 3 (b) and FIG. Corresponds to c). Specifically, FIG. 3A is a cross-sectional view in a region where the gate lead-out wiring 133 b and the conductive pattern overlap. FIG. 3B is a cross-sectional view in a region where the region including the end portion of the first conductive pattern 160 and the gate routing wiring 133 overlap. Further, FIG. 3C is a cross-sectional view in a region where the region including the end portion of the second conductive pattern 161 and the gate routing wiring 133 overlap.

  Each drawing will be described below. In FIG. 3A, the gate lead-out wiring 133 formed on the insulating substrate 2 is covered with the gate insulating film 21 and the interlayer insulating film 25, and the first conductive pattern 160 is formed thereon. The upper layer is further covered with a capacitive insulating film 27, and a second conductive pattern 161 is formed in the upper layer. That is, the gate lead-out wiring 133, the first conductive pattern, and the second conductive pattern overlap. This area is referred to as an area A as a first area.

  In the present embodiment, the first conductive pattern 160 and the pixel electrode 26 are formed in the same layer, and the second conductive pattern 161 and the common electrode 28 are formed in the same layer. There is no need to limit to layers. The conductive pattern may be formed of the same material as the pixel electrode 26 and the common electrode 28 or may be formed of a transparent conductive film. The transparent conductive film may have a higher resistance than the gate lead wiring. As will be described later, the conductive pattern mainly affects the capacitance, and the direct influence on the electrical resistance is small. The conductive pattern may be formed in the same layer as the source electrode 23.

  In FIG. 3B, there is a region where the first conductive pattern 160 is not formed. In that region, the second conductive pattern 161 is superimposed on the gate lead-out wiring 133 with the gate insulating film 21, the interlayer insulating film 25, and the capacitive insulating film 27 stacked. That is, the gate lead-out wiring 133 and the second conductive pattern 161 overlap. However, it does not overlap with the first conductive pattern 160. This area is called area B as a second area.

  In FIG. 3C, the first conductive pattern 160 is not formed, and in addition, a region in which the second conductive pattern 161 is not formed is partially present. In that region, only the gate insulating film 21, the interlayer insulating film 25 and the capacitive insulating film 27 are stacked on the gate lead-out wiring 133, and the gate lead-out wiring 133 and the conductive pattern do not overlap. This region is referred to as a region C as a third region.

  Here, the difference in capacitance between the gate wiring and the conductive pattern in the regions A to C will be described. In the region A, a capacitance is formed between the gate lead-out wire 133 and the first conductive pattern 160. On the other hand, in the region B, a capacitance is formed between the gate lead-out wiring 133 and the second conductive pattern 161, but the point that the capacitance insulating film 27 is also interposed is different from the region A. Therefore, the capacitance between the gate lead-out line and the conductive pattern is smaller in the region B than in the region A. Furthermore, since there is no conductive pattern in the region C, the capacitance is almost negligible. Therefore, the magnitude relationship of the capacity per unit area in the overlapping region is region A> region B> region C.

  By the way, this capacitance becomes a wiring load in synergy with the wiring resistance. That is, the wiring load is determined by the product of the wiring resistance and the wiring capacitance. Although the wiring resistance and the capacitance include not only the frame region 12 but also the portions formed in the display region 11, the resistance and the capacitance of the gate wiring in the display region 11 may be regarded as almost the same in each gate wiring. On the other hand, in the frame area 12, since the lengths of the gate lead-out lines 133 are different from each other, a difference occurs in the line load to cause display unevenness.

  As shown in FIGS. 1 and 3, the first conductive pattern 160 and the second conductive pattern 161 are formed in a region overlapping a part of the gate lead-out wiring 133. Further, as shown in FIG. 1, the length of overlapping with the gate lead-out wiring differs depending on the position. However, in the present invention, as will be described later, since the difference in area to be superimposed is important, hereinafter, expression focused on the area is used. Note that if the widths of the gate lead-out lines are the same, the difference in overlapping length can be regarded as the same as the difference in overlapping area.

  As shown in FIG. 1, the length of the gate lead-out line 133b drawn from the center of the right side 12a of the gate driver IC 141 is shorter than that of the gate lead-out lines 133a and 133c. Therefore, the line resistance of the gate lead-out line 133b is also lower than the line resistance of the gate lead-out lines 133a and 133c. Moreover, as the distance from the center of the right side 12a in the vertical direction in the drawing increases, the gate lead-out wire becomes longer and the wire resistance also increases.

  On the other hand, as can be seen from FIGS. 1 and 3, since the conductive pattern is triangular, the overlapping area of the gate wiring 133b and the conductive pattern is greater than the overlapping area of the gate wiring 133a, 133c and the conductive pattern. growing. Then, the overlapping area of the gate lead-out line and the conductive pattern decreases as the center of the right side 12a is separated in the vertical direction in the drawing.

  From the above, it can be seen that the area in which the conductive pattern and each gate lead wiring overlap each other is smaller as the wiring resistance of the gate lead wiring is higher. And, by arranging in this way, it is possible to compensate for the difference in wiring load caused by the difference in wiring resistance with the difference in capacitance, so it is possible to reduce display unevenness.

  Furthermore, it is necessary to consider not only the difference in mere overlapping area as described above, but also the difference in capacity per unit area between the region A and the region B. That is, the region A having a larger capacity per unit area than the region B is overlapped particularly in a wide range by the gate lead-out line 133b. Therefore, the difference between the capacitance formed between the gate lead-out line 133b and the conductive pattern and the capacitance between the gate lead-out lines 133a and 133c and the conductive pattern is larger than the difference in area.

  That is, in the embodiment of the present invention, compensation is performed with a more precise adjustment in a wider range than the case where there is only one conductive pattern in the embodiment of the present invention. Can. When there is only one layer, for example, the overlapping area for forming a capacitance needs to be small in the vicinity of the portion where the wiring length is the longest among the gate lead-out interconnections 133a and 133c, while in the vicinity of the gate lead-out interconnection 133b. It was necessary to provide a large overlapping area. Therefore, depending on the balance between the two, the overlapping area is insufficient in the gate lead-out wiring 133b, or the area is so small that pattern processing can not be controlled near the portion of the gate lead-out wirings 133a and 133c having the longest wiring length. I also had to

  In the embodiment according to the present invention, by forming the conductive pattern overlapping the gate lead-out wiring for each different layer, display unevenness is reduced by compensating by precise adjustment even when the difference in wiring resistance is significant. Can.

  Next, a method of determining the size of the area in which the gate lead-out wiring 133 and the conductive pattern are overlapped will be described.

  First, the pattern and number of gate lead-out lines 133 are determined. Then, the resistance value of each gate lead-out line 133 is calculated. Then, a difference in resistance value between the plurality of gate lead-out lines 133 is obtained. From the difference in resistance value and the wiring resistance of the gate wiring 131 in the display area 11, the capacitance required to compensate for the difference in each wiring resistance is determined. For the conductive pattern required to realize this capacitance, the overlapping area with each gate lead-out line and the layer to be formed are determined.

  This makes it possible to reduce the difference in resistance value among the lead wirings with precise adjustment in a wider range as compared with the case where the conductive film pattern of only one layer is formed on the wirings via the insulating film. Further, in the case of the FFS liquid crystal display device, since the pixel electrode 26 and the common electrode 28 are formed on the array substrate via the capacitive insulating film, as described above, the first conductive pattern and the first conductive pattern are formed. The formation of the second conductive pattern is performed simultaneously with each of the pixel electrode and the common electrode, so that there is no need to add a manufacturing process.

  In the present embodiment, as shown in FIG. 1, both the first conductive pattern 160 and the second conductive pattern 161 form an approximately isosceles triangle, but the present invention is not limited to this shape. . Further, the shape of the conductive pattern is axisymmetrical with respect to a line crossing the central portion of the gate driver IC 141, but may not be axisymmetric. The conductive pattern may be separated into a plurality of patterns. The important thing is to compensate for the difference in gate line resistance with capacitance.

  Further, the number of conductive patterns is not limited to two, and may be three or more. In this embodiment, for example, a conductive pattern formed of a metal film in the same layer as the source electrode 23 may be additionally formed. The number of steps may be increased to add a new conductive pattern.

  Furthermore, the conductive pattern may be a pattern separated from other patterns. However, in the case where the conductive pattern is a separated pattern, the potential applied to the conductive pattern is also changed due to the voltage applied to the gate lead wiring, and the capacitance formed between the gate lead wiring and the conductive pattern is reduced. It will In that case, the above-described compensation effect is also reduced. Therefore, it is more preferable to apply a potential different from that for the gate lead wiring to the conductive pattern.

  For example, a common potential may be applied to the conductive pattern. In this case, the conductive pattern may be formed so as to be electrically connected to a terminal (not shown) for applying a common potential from the outside or a wire connected to the terminal. The second conductive pattern 162 may be integrally formed to extend from the common electrode 28 in the display area 11.

  Also, the pattern extending from the common electrode 28 on the capacitive insulating film 27 may be connected to the first conductive pattern 161. In this case, a contact hole (not shown) may be opened in the capacitive insulating film 27 and both may be connected via the contact hole.

  Furthermore, in the first embodiment, the embodiment in which the range in which the wiring resistance can be compensated is expanded by providing the first conductive pattern 160 and the second conductive pattern 161 has been described. It is also possible to achieve the same effect by mixing the isolated pattern and the pattern to which the common potential is applied.

Second Embodiment
The configuration of the liquid crystal display panel according to the second embodiment will be described with reference to FIG. FIG. 4 is a plan view for explaining the frame area. A plurality of gate lines 131 extend in the horizontal direction in the drawing in the display area 11, and gate lead-out lines 133 are formed in the frame area 12 as in the first embodiment, but there are also differences. .

  The first difference is that the driver IC is formed on only one side. Specifically, in the second embodiment, the gate driver IC 141 and the source driver IC 142 described in the first embodiment are integrated into a common driver IC 150 and formed on one side. Therefore, the driver IC 150 is connected to both the source wiring and the gate lead-out wiring.

  Furthermore, the gate lead-out lines are disposed at different positions according to the distance from the driver IC 150. Specifically, for the gate wiring close to the driver IC 150, the gate lead-out wiring 133d is disposed on the left side 12d of the frame area. On the other hand, for the gate wiring far from the driver IC 150, the gate lead-out wiring 133e is disposed on the right side 12a of the frame area.

  The arrangement shown in FIG. 4 is used to achieve miniaturization and narrowing of the display device by narrowing, in particular, the right side 12a and the left side 12d of the frame area 12, but even in such a configuration, the arrangement shown in FIG. There is a difference in wiring resistance of each gate wiring. Therefore, by arranging the first conductive pattern 160 and the second conductive pattern 161 as shown in FIG. 4 as in the first embodiment, the difference in wiring resistance can be compensated, and display unevenness is suppressed. It is possible. Although FIG. 4 is provided so as to overlap with the gate lead-out line 133e, a conductive pattern may be separately provided to overlap with the gate lead-out line 133d.

  By the way, in the configuration as shown in FIG. 4, since the wiring load of the gate wiring on the upper side of the display area 11 is heavy, the boundary between the upper side and the lower side of the display area 11, that is, the gate lead-out wiring 133 d and the gate In some cases, display unevenness may easily occur at the boundary with the lead wiring 133e. This will be described as a modification of the second embodiment with reference to FIG. FIG. 5 is also a plan view for explaining the frame area as in FIG.

  A first conductive pattern 160 and a second conductive pattern 161 are formed so as to overlap with the gate lead-out wiring 133 d. In FIG. 5, the first conductive pattern 160 is triangular. Furthermore, a rectangular second conductive pattern 161 is formed in the upper layer. In the configuration of FIG. 5, the second conductive pattern 161 compensates for the wiring resistance difference between the lead wiring 133e of the gate wiring far from the driver IC 150 and the lead wiring 133d of the gate wiring near the driver IC 150, and further the first conductive pattern. By means of 160, it is possible to compensate for each wiring resistance difference between the gate lead wirings 133d. Of course, the shape of the conductive pattern is determined after determining which wire resistance is effective to compensate for display unevenness, and the form as shown in FIGS. 4 and 5 is used. It is not limited. In FIG. 5, the compensation targets of the first conductive pattern and the second conductive pattern may be interchanged, or the pattern shape may be changed as appropriate.

  As described in the first embodiment, the conductive pattern may be an isolated pattern. It is more preferable to apply a potential different from that for the gate lead wiring to the conductive pattern.

  A display device can be manufactured by a known method using the array substrate according to the first and second embodiments. For example, after bonding is performed so that liquid crystal is sealed between the array substrate and the opposite substrate to seal the periphery of the substrate, an external circuit is connected to the terminals of the array substrate or the opposite substrate and a light source is installed behind Thus, the liquid crystal display device can be manufactured.

  In addition, after forming a light emitting layer which emits light by applying an electric field on the pixel electrode of the array substrate, an electroluminescent display device can be manufactured by covering it with an insulating film and forming a common electrode. Furthermore, it is possible to manufacture an electrophoretic display device in which microcapsules containing white and black pigment particles are driven by an electric field generated by an array substrate and an external circuit, and an electronic powder fluid display device. . Although different from the display device, by providing a photoelectric conversion element instead of the pixel electrode in the array substrate according to the present invention, it is also possible to manufacture an image sensor of visible light, ultraviolet light or radiation.

1 array substrate, 11 display areas, 12 frame areas,
21 gate insulating film, 22 semiconductor film, 23 source electrode, 24 drain electrode,
25 interlayer insulating film, 26 pixel electrodes, 27 capacitance insulating films, 28 common electrodes,
131 gate wiring 132 source wiring 133 gate routing wiring 134 source routing wiring 141 gate driver IC 142 source driver IC,
150 drivers I c,
160 first conductive pattern, 161 second conductive pattern

Claims (5)

A display area and a frame area outside the display area on an insulating substrate;
In the display area, gate wiring,
A source line intersecting the gate line via a first insulating film;
A switching element formed in the vicinity of an intersection of the gate wiring and the source wiring;
A pixel electrode electrically connected to the switching element;
A first conductive pattern having a gate lead-out wiring connected to the gate wiring and extending to an external terminal and a region overlapping with the gate lead-out wiring via at least the first insulating film in the frame region;
A capacitive insulating film above the first conductive pattern,
A second conductive pattern having a region overlapping with the gate lead-out line via at least the capacitive insulating film and the first insulating film;
An array substrate having
The area in which the first conductive pattern and each gate lead wiring overlap each other is arranged to be smaller as the wiring resistance of the gate lead wiring is higher,
An array substrate, wherein the area in which the second conductive pattern and each gate lead wiring overlap each other is smaller as the lead resistance of the gate lead wiring is higher. A first region that form a capacitance at least the first conductive pattern and said gate lead-out wiring and superposition,
The second conductive pattern and said gate lead-out line to form a capacitor by superposition, and a second region where said first conductive pattern and said gate lead-out line is not superimposed,
Wherein the capacitance per unit area in the first region, an array substrate according to claim 1, wherein greater than the capacitance per unit area in the second region. The array substrate of claim 1 or 2, characterized in that said said pixel electrode the first conductive pattern is the same layer. A common electrode facing the pixel electrode via the capacitive insulating film in the display region;
The array substrate according to any one of claims 1 to 3, wherein the common electrode is the same layer as the second conductive pattern. A liquid crystal display device comprising the array substrate according to any one of claims 1 to 4 .

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