JP2017003660A - Array substrate and liquid crystal display including the array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring structure and a display that can adjust a difference in wiring load to a fixed value by performing wiring load adjustment of adjusting a difference in resistance between lead wirings with wiring capacity.SOLUTION: In a frame area 12a of an array substrate 1, a first conductive pattern 160 is formed on an insulating film covering gate lead wirings 133a to 133c, and a second conductive pattern 161 is formed on the first conductive pattern 160 with a capacitive insulating film.EFFECT: A capacity between the conductive patterns and the gate lead wirings can be adjusted according to the length of the gate lead wirings.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring structure and a display device, and more particularly to a wiring structure including a plurality of lead wirings and a display device using the wiring structure.

  A liquid crystal display panel constituting a liquid crystal display device has a plurality of gate lines (scanning signal lines) and a plurality of source lines (image signal lines) arranged in a matrix. In the display area of the liquid crystal display panel, a plurality of display pixels are formed corresponding to the intersections of these gate lines and source lines. The plurality of gate signal lines are driven by a gate driver IC, and the plurality of source lines are driven by a source driver IC.

  The gate wiring and the source wiring are formed on the liquid crystal surface side of the liquid crystal display panel. The wiring to each wiring is routed from the display area to the driver IC mounted outside the display area. This wiring is performed using a space around the display area (hereinafter, this space may be referred to as a frame). Therefore, the routing distance of each routing wiring routed to the display area varies depending on the mounting position of the driver IC. Therefore, the electrical resistance of each routing wiring also differs, and display unevenness occurs due to the resistance difference between the wirings. In order to suppress this wiring resistance difference, the frame space is used and the wiring length and width are controlled. However, it is difficult to adjust the resistance difference and it is difficult to suppress the occurrence of display unevenness.

  The routing distance of the routing wiring varies depending on the arrangement of the driver IC, the wiring arrangement, and the number of outputs output from the driver IC to the signal lines in the display area. For example, the lead wiring length may be different between turning the display area clockwise and counterclockwise. In a liquid crystal display panel having a large panel outer size and a small number of display pixels, there is a space in a frame space for routing each wiring connected from the driver IC to the display surface. Therefore, for example, when the source wiring routing distances are different on the left and right of the display as in the arrangement of the source driver ICs, the resistance adjustment between the wirings can be performed by adjusting the wiring width and length. . (Patent Documents 1 and 2)

  However, it has become difficult to secure a sufficient space in the frame with the recent high-definition display and the narrow frame of the panel. For this reason, it has become necessary to form the lead wiring with a narrow wiring width close to the manufacturing limit. In this case, the surplus space becomes narrow and it becomes difficult to adjust the resistance with the wiring width. Therefore, it becomes necessary to adjust the resistance only with the wiring length. In this case, as described above, the wiring length is determined by the arrangement of the driver ICs and the number of outputs, and thus it is difficult to suppress display unevenness due to the resistance difference between the wirings.

  For this situation, by providing a conductor pattern that overlaps the wiring via an insulating film in the frame, the difference in wiring load distribution due to the difference in length of each wiring, that is, the difference in RC delay is reduced. The technology to do is known. (Patent Document 3)

Japanese Unexamined Patent Publication No. 2007-047259 Japanese Unexamined Patent Publication No. 7-134305 Special table 2005-529360 publication gazette (FIG. 2)

  The conventional liquid crystal display device has a problem in that since the wiring distance of each wiring is different, a resistance difference is generated between the wirings, and display unevenness having a wiring load distribution in the entire wiring region occurs. In order to improve the problem, a technique for improving the difference in RC delay by providing a conductor pattern that overlaps with the wiring and the insulating film is known. However, it is difficult to make fine adjustments and the adjustment range is narrow. Problems have arisen.

  The present invention has been made in order to solve such problems, and a wiring structure and a display device capable of adjusting a wiring load difference to a constant by adjusting a wiring load based on a wiring capacitance by adjusting a wiring load resistance difference. The purpose is to provide.

  The array substrate according to the present invention has a display region on the insulating substrate and a frame region outside the display region, and the display region has a gate wiring and a source wiring crossing the gate wiring through an insulating film. And a switching element formed in the vicinity of the intersection of the gate wiring and the source wiring, and a pixel electrode electrically connected to the switching element, and connected to the gate wiring in the frame region to the external terminal. A first conductive pattern having a region overlapping with the extended gate routing wiring and at least the gate routing wiring through the insulating film; a capacitive insulating film in an upper layer of the first conductive pattern; and at least a capacitive insulating film and an insulating film; A second conductive pattern having a region overlapping with the gate routing wiring via the first conductive pattern and each gate routing layout. Are arranged so that the higher the wiring resistance of the gate routing wiring is, the smaller the area where the second conductive pattern and each gate routing wiring overlap is the wiring of the gate routing wiring. The array substrate is arranged such that the higher the resistance is, the smaller the resistance is.

  Provided are an array substrate and a display device capable of adjusting a wiring load difference to be constant by adjusting a wiring load by adjusting a wiring load resistance difference.

It is a top view which shows the array substrate which concerns on Embodiment 1 of this invention. It is the top view and sectional drawing of a display area of an array substrate concerning Embodiment 1 of the present invention. It is sectional drawing of the frame part of the array substrate which concerns on Embodiment 1 of this invention. It is a top view which shows the array substrate which concerns on Embodiment 2 of this invention. It is a top view which shows the array board | substrate which concerns on the modification of Embodiment 2 of this invention.

Embodiment 1 FIG.
FIG. 1 shows a plan view of an array substrate used in the liquid crystal display panel according to the present invention. An array substrate 1 on which elements and the like to be described later are formed on an insulating substrate and an opposing substrate 2 are bonded to face each other. For example, a color filter including three colors of RGB may be formed on the counter substrate 2 as necessary. Although not shown, liquid crystal is sealed between the array substrate 1 and the counter substrate 2, and is sealed with a seal or the like so as not to leak.

  Next, the array substrate 1 will be described. The array substrate 1 has a display area 11 composed of a plurality of pixels arranged in a matrix and a frame area 12 which is an outer peripheral area thereof. That is, the non-display area surrounding the outer periphery of the display area 11 becomes the frame area 12.

  In the display region 11, a plurality of source lines 132 and a plurality of gate lines 131 are arranged in a matrix on the array substrate 1 so as to intersect each other. That is, the array substrate 1 is a wiring substrate on which a plurality of wirings are formed. In the display area 11, each of the gate lines 131 is formed to extend in the horizontal direction on the drawing. A plurality of gate wirings 131 formed so as to extend in the horizontal direction are arranged side by side in the vertical direction. In the display area 11, gate lines 131 having the same width are formed at the same interval.

  On the other hand, each of the source lines 132 is formed so as to extend along the vertical direction in the drawing. A plurality of source wirings 132 formed so as to extend in the vertical direction are arranged side by side in the horizontal direction on the drawing. In FIG. 1, source wirings 132 having the same width are formed at the same interval.

  A region divided by the source wiring 132 and the gate wiring 131 is a pixel. Each pixel includes a pixel electrode for applying a voltage to the liquid crystal and a switching element for controlling the application of the voltage. The switching element is often provided in the vicinity of the intersection of the source wiring 132 and the gate wiring 131, and is typically a TFT (ThinFilmRassistor). Details will be described below.

  FIG. 2 shows a plan view and a cross-sectional view around the pixel in the display area. The cross-sectional view is a cross-sectional view taken along the line DD in the plan view. On the insulating substrate 20, the gate insulating film 21 is formed so as to cover the gate wiring 131 and the gate electrode extending from the gate wiring 131. As the gate insulating film 21, silicon oxide, silicon nitride, or the like can be used. In this embodiment, since a structure in which a gate routing wiring and a gate wiring 131 described later are integrally formed is handled, the gate routing wiring is formed simultaneously with the gate wiring.

  Next, a semiconductor film 22 is formed on the gate insulating film 21. As the semiconductor film 22, an a-Si (amorphous silicon) film, a p-Si (polycrystalline silicon film) film, or an oxide semiconductor film such as In—Ga—Zn—O can be used. A source electrode 23 extending from the source wiring 132 is formed on the semiconductor film 22. Thereby, a source voltage can be supplied to the source region of the semiconductor film 22.

  Furthermore, a drain electrode 24 is formed on the drain region of the semiconductor film 22. The source electrode 23 and the drain electrode 24 can be formed in the same process as the source wiring 132.

  For the gate wiring 131 and the source wiring 132, for example, a low-resistance metal material such as Al, Cr, or Mo can be used. Thus, the gate wiring 131 and the source wiring 132 are formed with different wiring layers. That is, the source wiring 132 and the gate wiring 131 are arranged so as to intersect each other at a substantially right angle through the gate insulating film 21, and a TFT having a gate electrode, a semiconductor film, a drain electrode, and a source electrode is located near the intersection. Will be placed.

  An interlayer insulating film 25 is formed on the TFT including the drain electrode 24. Further, a pixel electrode 26 is formed on the interlayer insulating film 25. The drain electrode 24 is connected to the pixel electrode 26 through a contact hole CH provided in the interlayer insulating film 25. Therefore, the voltage transmitted to the drain electrode 24 is also applied to the pixel electrode 26.

  When the liquid crystal display panel is a transmissive type, the pixel electrode 26 is formed of a transparent conductive film such as ITO. Further, in a horizontal electric field type or FFS type liquid crystal panel, a capacitor insulating film 27 is provided above the pixel electrode 26, and a common electrode 28 is provided so as to face the pixel electrode 26 through the capacitor insulating film 27. The common electrode 28 is formed of a transparent conductive film and has a slit-shaped opening. That is, the slit-shaped portion is a region where the common electrode 28 is not formed, and the lower pixel electrode 26 is exposed through the capacitive insulating film 27.

  Although the common electrode 28 is illustrated as a strip-like pattern extending in the lateral direction across a plurality of pixels in the drawing, the common electrode 28 may not have such a pattern shape. In general, the common electrode 28 is often formed over almost the entire surface of the display region 11, but an opening may be appropriately provided as necessary, for example, not provided above the TFT. As will be described later, a common potential is applied to the common electrode 28.

  In the TFT completed as described above, when a gate signal is supplied to the gate wiring 131, a gate voltage is applied to a predetermined gate electrode. As a result, the TFT is turned on, and an image display signal voltage is supplied from the source wiring to the pixel electrode via the source electrode and the drain electrode.

  Returning to FIG. 1, in the frame area 12, a portion on the right side of the display area 11 in the drawing is a right portion 12 a of the frame area 12. Further, in the frame area 12, a lower part in the drawing than the display area 11 is a lower side portion 12 b of the frame area 12. Further, in the frame area 12, the upper part of the display area 11 in the drawing is the upper part 12 c of the frame area 12, and similarly the left part is the left part 12 d of the frame area 12. Accordingly, the display area 11 is surrounded by the right side part 12a, the lower part 12b, the upper part 12c, and the left side part 12d of the frame area 12.

  In FIG. 1, a source driver IC 142 is disposed on the lower side of the display area 11, that is, the lower portion 12b, and a gate driver IC 141 is disposed on the right side, that is, the right side 12a. The gate driver IC 141 is connected to the gate wiring 131 through the gate routing wiring 133. Further, the source driver IC 142 is connected to the source wiring 132 through the source routing wiring 134. That is, the gate routing wiring 133 is connected to the gate wiring 131 and extends to an external terminal (not shown). The same applies to the source routing wiring 134.

  The gate driver IC 141 and the source driver IC 142 respectively supply a gate signal to the gate wiring 131 or supply an image display signal voltage to the source wiring 132 based on a control signal and display data supplied from the outside. To do. By this supply, the TFT is turned on as described above, and the image display signal voltage is supplied to the pixel electrode. On the other hand, since a common potential is applied to the common electrode 28 facing the pixel electrode 26, a fringe electric field corresponding to the potential difference between the pixel electrode 26 and the common electrode 28 is generated, thereby causing the alignment direction of the liquid crystal. Changes, it is possible to obtain and display a desired amount of transmitted light in each pixel.

  In FIG. 1, the gate routing wiring 133 and the gate wiring 131 are provided in a one-to-one correspondence. Both may be formed of different members, but may be integrally formed of the same material. The relationship between the source routing wiring 134 and the source wiring 132 is the same. In this embodiment mode, the case where both are integrally formed of the same material will be described. Therefore, there are cases where the gate wiring 131 includes the gate lead-out wiring 133 and where the parts are distinguished by their names.

  In FIG. 1, a gate routing wiring 133a is a gate routing wiring closer to the upper portion 12c, and a gate routing wiring 133c is a gate routing wiring closer to the lower portion 12b. The gate routing wiring 133b is a gate routing wiring near the center of the right side portion 12a. As can be seen from FIG. 1, the lengths of the gate routing lines 133a and 133c are longer than those of the gate routing lines 133b. Further, the length of the gate routing wiring increases as the distance from the center of the right side portion 12a increases in the vertical direction in the drawing. At this time, if the width of the routing wiring is constant, the wiring resistance also increases.

  Therefore, the wiring resistance of the gate routing wirings 133a and 133c on the right side 12a is higher than the wiring resistance of the gate routing wiring 133b in the center of the driver IC 141. When a liquid crystal display panel using an array substrate having such a resistance difference is displayed, a display unevenness having a low resistance distribution of the gate routing wiring 133 in the vicinity of the connection portion between the gate routing wiring 133 and the gate wiring 131 is displayed. As described above, is easily visible.

  Patterns provided to improve such display unevenness are the first conductive pattern 160 and the second conductive pattern 161. Note that the first conductive pattern and the second conductive pattern may be simply referred to as a conductive pattern. The first conductive pattern 160 has a triangular shape in the plan view, and is further roughly an isosceles triangle, and is shown by hatching in the drawing. The base of the isosceles triangle is along the boundary between the gate wiring 131 and the gate routing wiring 133, and the apex angle is disposed near the gate routing wiring 133b.

  With such an arrangement, the length in which the first conductive pattern 160 and the gate routing wiring 133 overlap is the longest in the vicinity of the gate routing wiring 133b. And as it leaves | separates from the center part of the right side part 12a to the up-down direction in drawing, the overlap length becomes short. Thus, although the overlapping length is not the same for each gate routing wiring, it is arranged so that the area is different from the length when expressed more accurately. The point where the overlapping area is different will be described later including its effects.

  On the other hand, the shape of the second conductive pattern 161 is a triangle that encloses the first conductive pattern 160 and is roughly an isosceles triangle. Further, the size of the overlapping area between the second conductive pattern 161 and each gate routing wiring is almost the same as that of the first conductive pattern 160.

  Next, these conductive patterns will be further described with reference to FIG. 3 is a cross-sectional view in FIG. 1, and cross-sectional views of portions indicated by AA, BB, and CC in FIG. 1 are respectively shown in FIGS. 3 (a), 3 (b), and 3 ( corresponding to c). Specifically, FIG. 3A is a cross-sectional view in a region where the gate routing wiring 133b and the conductive pattern overlap. FIG. 3B is a cross-sectional view in a region where the region including the end portion of the first conductive pattern 160 overlaps with the gate routing wiring 133. Further, FIG. 3C is a cross-sectional view in a region where the region including the end portion of the second conductive pattern 161 and the gate routing wiring 133 overlap.

  Each drawing will be described below. In FIG. 3A, the gate routing wiring 133 formed on the insulating substrate 2 is covered with the gate insulating film 21 and the interlayer insulating film 25, and the first conductive pattern 160 is formed thereon. The capacitor insulating film 27 further covers the upper layer, and the second conductive pattern 161 is formed on the upper layer. That is, the gate routing wiring 133 overlaps the first conductive pattern and the second conductive pattern. This region will be referred to as region A as the first region.

  In the present embodiment, the first conductive pattern 160 and the pixel electrode 26 are formed in the same layer, and the second conductive pattern 161 and the common electrode 28 are formed in the same layer. There is no need to limit it to a layer. The conductive pattern may be formed of the same material as the pixel electrode 26 and the common electrode 28, or may be formed of a transparent conductive film. The transparent conductive film may have a higher resistance than the gate routing wiring. This is because, as will be described later, the conductive pattern mainly affects the capacitance and has little direct influence on the electrical resistance. Further, the conductive pattern may be formed in the same layer as the source electrode 23.

  In FIG. 3B, there is a part of the region where the first conductive pattern 160 is not formed. In this region, the second conductive pattern 161 is superimposed on the gate lead-out wiring 133 through a stack of the gate insulating film 21, the interlayer insulating film 25, and the capacitive insulating film 27. That is, the gate routing wiring 133 and the second conductive pattern 161 overlap. However, it does not overlap with the first conductive pattern 160. This region will be referred to as region B as the second region.

  In FIG. 3C, the first conductive pattern 160 is not formed, and there is a part of the region where the second conductive pattern 161 is not formed. In that region, only the gate insulating film 21, the interlayer insulating film 25, and the capacitive insulating film 27 are stacked on the upper layer of the gate routing wiring 133, and the gate routing wiring 133 and the conductive pattern do not overlap. This region will be referred to as region C as the third region.

  Here, the difference in capacitance between the gate routing wiring and the conductive pattern in the regions A to C will be described. In the region A, a capacitance is formed between the gate routing wiring 133 and the first conductive pattern 160. On the other hand, in the region B, a capacitance is formed between the gate lead-out wiring 133 and the second conductive pattern 161, but is different from the region A in that the capacitor insulating film 27 is also interposed. Therefore, the capacitance between the gate routing wiring and the conductive pattern is smaller in the region B than in the region A. Further, since there is no conductive pattern in the region C, the capacitance can be almost ignored. Therefore, the size relationship between the capacities per unit area in the overlapping region is region A> region B> region C.

  By the way, this capacity becomes a wiring load in synergy with the wiring resistance. That is, the wiring load is determined by the product of the wiring resistance and the wiring capacitance. Although the wiring resistance and capacitance include not only the frame region 12 but also the portion formed in the display region 11, the resistance and capacitance of the gate wiring in the display region 11 may be considered to be almost the same in each gate wiring. On the other hand, in the frame region 12, the lengths of the gate routing wirings 133 are different from each other. Therefore, a difference in wiring load occurs, causing display unevenness.

  As shown in FIGS. 1 and 3, the first conductive pattern 160 and the second conductive pattern 161 are formed in a region overlapping with a part of the gate routing wiring 133. Further, as shown in FIG. 1, the length overlapping with the gate routing wiring differs depending on the position. However, as will be described later, in the present invention, since the difference in the overlapping area is important, the expression focusing on the area is used hereinafter. Note that if the widths of the gate routing lines are the same, the overlapping length difference can be regarded as the same as the overlapping area difference.

  As shown in FIG. 1, the length of the gate routing wiring 133b led out from the central portion of the right side portion 12a of the gate driver IC 141 is shorter than that of the gate routing wirings 133a and 133c. For this reason, the wiring resistance of the gate routing wiring 133b is also lower than the wiring resistance of the gate routing wirings 133a and 133c. Moreover, as the distance from the central portion of the right side portion 12a increases in the vertical direction in the drawing, the gate routing wiring becomes longer and the wiring resistance also increases.

  On the other hand, as can be seen from FIGS. 1 and 3, since the conductive pattern is triangular, the area where the gate routing wiring 133b and the conductive pattern overlap is larger than the area where the gate routing wiring 133a and 133c overlaps the conductive pattern. growing. As the distance from the central portion of the right side portion 12a increases in the vertical direction in the drawing, the overlapping area between the gate routing wiring and the conductive pattern decreases.

  From the above, it can be seen that each area where the conductive pattern and each gate routing wiring overlap each other is arranged so as to decrease as the wiring resistance of the gate routing wiring increases. By arranging in this manner, display unevenness can be reduced because the effect of compensating the wiring load difference caused by the wiring resistance difference by the capacitance difference is achieved.

  Further, as described above, it is necessary to consider not only the difference in the overlapping area but also the difference in capacity per unit area between the region A and the region B. That is, the region A having a larger capacity per unit area than the region B is overlapped over a wide range, particularly with the gate lead-out wiring 133b. Therefore, the difference between the capacitance formed between the gate routing wiring 133b and the conductive pattern and the capacitance between the gate routing wiring 133a, 133c and the conductive pattern is further widened than the difference in area.

  That is, compensation for wiring load differences caused by wiring length and wiring resistance can be compensated with more precise adjustment in a wider range than in the case of the present invention having only one conductive pattern. Can do. When there is only one layer, for example, it is necessary to provide a small overlapping area for forming a capacitor in the vicinity of the longest wiring length among the gate routing wirings 133a and 133c, while in the vicinity of the gate routing wiring 133b. It was necessary to provide a large overlapping area. Therefore, depending on the balance between the two, the overlapping area of the gate routing wiring 133b is insufficient, or the area around the longest wiring length of the gate routing wirings 133a and 133c is so small that pattern processing control cannot be performed. Sometimes it became.

  In the embodiment according to the present invention, the conductive pattern overlapping the gate routing wiring is formed for each different layer, thereby reducing display unevenness by compensating with precise adjustment even when the wiring resistance difference is significant. Can do.

  Next, a method for determining the size of the area where the gate routing wiring 133 and the conductive pattern overlap is described.

  First, the pattern and number of gate routing lines 133 are determined. Then, the resistance value of each gate routing wiring 133 is calculated. Then, a difference in resistance value between the plurality of gate routing wires 133 is obtained. From the difference in resistance value and the wiring resistance of the gate wiring 131 in the display area 11, the capacitance required to compensate for the difference in wiring resistance is obtained. For the conductive pattern necessary to realize this capacity, the overlapping area with each gate lead-out wiring and which layer is formed is determined.

  Thereby, it is possible to reduce the difference in resistance value between the respective lead wirings by precise adjustment in a wider range than in the case where only one conductive film pattern is formed on the wiring via the insulating film. In the case of the FFS type liquid crystal display device, since the pixel electrode 26 and the common electrode 28 are formed on the array substrate via the capacitive insulating film, as described above, the first conductive pattern and the first conductive pattern The formation of the conductive pattern 2 is performed at the same time as the pixel electrode and the common electrode, so that there is no need to add a manufacturing process.

  In the present embodiment, as shown in FIG. 1, both the first conductive pattern 160 and the second conductive pattern 161 are approximately isosceles triangles, but the shape is not limited thereto. . The shape of the conductive pattern is line symmetric with respect to a line crossing the central portion of the gate driver IC 141, but may not be line symmetric. The conductive pattern may be separated into a plurality of patterns. What is important is to compensate for the difference in gate wiring resistance with capacitance.

  The conductive pattern is not limited to two layers, and may be three or more layers. In the present embodiment, for example, a conductive pattern made of a metal film in the same layer as the source electrode 23 may be additionally formed. A new conductive pattern may be added by increasing the number of steps.

  Further, the conductive pattern may be a pattern separated from other patterns. However, if the conductive pattern is a separated pattern, the potential formed on the conductive pattern also varies with the voltage applied to the gate routing wiring, so the capacitance formed between the gate routing wiring and the conductive pattern decreases. End up. In that case, the compensation effect described above is also reduced. Therefore, it is better to apply a potential different from that of the gate routing wiring to the conductive pattern.

  For example, a common potential may be applied to the conductive pattern. In this case, the conductive pattern may be formed so as to be electrically connected to a terminal (not shown) for applying a common potential from the outside and a wiring connected to the terminal. The second conductive pattern 162 may be integrally formed so as to extend from the common electrode 28 in the display region 11.

  Further, the pattern extending on the capacitor insulating film 27 from the common electrode 28 and the first conductive pattern 161 may be connected. In this case, a contact hole (not shown) may be opened in the capacitor insulating film 27 and both may be connected via the contact hole.

  Furthermore, in Embodiment 1, although the form which expanded the range which can compensate wiring resistance by providing the 1st conductive pattern 160 and the 2nd conductive pattern 161 was demonstrated, in addition to this form, as a conductive pattern, Similar effects can be obtained by mixing isolated patterns and patterns to which a common potential is applied.

Embodiment 2.
The configuration of the liquid crystal display panel according to the second embodiment will be described with reference to FIG. FIG. 4 is a plan view for explaining the frame region. Although the plurality of gate lines 131 extend in the horizontal direction on the drawing in the display area 11 and the gate routing lines 133 are formed in the frame area 12, they are the same as in the first embodiment, but there are also differences. .

  First, the difference is that the driver IC is formed only on one side. Specifically, in the second embodiment, the gate driver IC 141 and the source driver IC 142 described in the first embodiment are integrated into a common driver IC 150 and formed on one side. Therefore, the driver IC 150 is connected to both the source wiring and the gate routing wiring.

  Furthermore, the gate routing wiring is arranged at different positions according to the distance from the driver IC 150. Specifically, for the gate wiring that is close to the driver IC 150, the gate routing wiring 133d is disposed on the left side 12d of the frame area. On the other hand, for the gate wiring that is far from the driver IC 150, the gate routing wiring 133e is disposed on the right side 12a of the frame area.

  The arrangement shown in FIG. 4 is used to reduce the size of the display device or to narrow the frame by narrowing the right side portion 12a and the left side portion 12d, particularly in the frame region 12. A difference in wiring resistance of each gate wiring occurs. Therefore, similarly to the first embodiment, the first conductive pattern 160 and the second conductive pattern 161 are arranged as shown in FIG. 4, so that the difference in wiring resistance can be compensated and display unevenness is suppressed. Is possible. In FIG. 4, the gate lead-out wiring 133e is provided so as to overlap with the gate lead-out wiring 133e, but a conductive pattern may be provided separately from the gate lead-out wiring 133d.

  In the configuration as shown in FIG. 4, since the wiring load of the gate wiring on the upper side of the display area 11 is increased, the boundary between the upper side and the lower side of the display area 11, that is, the gate routing wiring 133d and the gate In some cases, display unevenness at the boundary with the lead-out wiring 133e is likely to occur. This will be described with reference to FIG. 5 as a modification of the second embodiment. FIG. 5 is also a plan view for explaining the frame region, similarly to FIG.

  A first conductive pattern 160 and a second conductive pattern 161 are formed so as to overlap with the gate routing wiring 133d. In FIG. 5, the first conductive pattern 160 is triangular. Furthermore, a rectangular second conductive pattern 161 is formed on the upper layer. In the configuration of FIG. 5, the second conductive pattern 161 compensates for the wiring resistance difference between the lead wiring 133e of the gate wiring far from the driver IC 150 and the lead wiring 133d of the gate wiring close to the driver IC 150, and further the first conductive pattern. By 160, it is possible to compensate for each wiring resistance difference between the gate routing wirings 133d. Of course, the shape of the conductive pattern is determined after determining which wiring resistance is effectively compensated in order to suppress display unevenness, and is in the form as shown in FIGS. It is not limited. In FIG. 5, the compensation targets of the first conductive pattern and the second conductive pattern may be interchanged, and the pattern shape may be changed as appropriate.

  As described in the first embodiment, the conductive pattern may be an isolated pattern. More preferably, a potential different from that of the gate routing wiring is applied to the conductive pattern.

  A display device can be manufactured by a known manufacturing method using the array substrates according to the first and second embodiments. For example, after attaching the liquid crystal to be sealed between the array substrate and the counter substrate and sealing the periphery of the substrate, connect an external circuit to the terminals of the array substrate and the counter substrate, and place the light source behind Thus, a liquid crystal display device can be manufactured.

  In addition, an electroluminescent display device can be manufactured by forming a light emitting layer that emits light by applying an electric field over the pixel electrodes of the array substrate, and then covering the insulating substrate with an insulating film and forming a common electrode. Furthermore, it is also possible to manufacture an electrophoretic display device that drives microcapsules containing white and black pigment particles by an electric field generated by an array substrate and an external circuit, and an electropowder fluid display device. . Although different from the display device, an image sensor for visible light, ultraviolet light, or radiation can be manufactured by providing a photoelectric conversion element instead of a pixel electrode in the array substrate according to the present invention.

1 array substrate, 11 display area, 12 frame area,
21 gate insulating film, 22 semiconductor film, 23 source electrode, 24 drain electrode,
25 interlayer insulating film, 26 pixel electrode, 27 capacitive insulating film, 28 common electrode,
131 Gate wiring, 132 Source wiring 133 Gate routing wiring, 134 Source routing wiring 141 Gate driver IC 142 Source driver IC
150 driver IC,
160 first conductive pattern, 161 second conductive pattern

Claims (6)

A display area on the insulating substrate and a frame area outside the display area;
In the display area, a gate wiring,
A source wiring crossing the gate wiring through a first insulating film;
A switching element formed in the vicinity of an intersection between the gate wiring and the source wiring;
A pixel electrode electrically connected to the switching element is formed,
A first conductive pattern having a region that overlaps with the gate routing wiring via at least the first insulating film, and a gate routing wiring connected to the gate wiring and extending to the external terminal in the frame region;
A capacitive insulating film on an upper layer of the first conductive pattern;
A second conductive pattern having a region overlapping with the gate routing wiring through at least the capacitive insulating film and the first insulating film;
An array substrate having
Each area where the first conductive pattern and each gate routing wiring overlap each other is arranged to be smaller as the wiring resistance of the gate routing wiring is higher,
An array substrate characterized in that each area where the second conductive pattern and each gate routing wiring overlap each other is arranged so as to decrease as the wiring resistance of the gate routing wiring increases. A first region where at least the first conductive pattern and the gate routing wiring overlap;
A second region in which the second conductive pattern and the gate routing wiring overlap, and the first conductive pattern and the gate routing wiring do not overlap,
The array substrate according to claim 1, wherein a wiring resistance of the gate routing wiring in the first region is higher than a wiring resistance of the gate routing wiring in the second region. The gate routing wiring has a third region that does not overlap the first conductive pattern and the second conductive pattern;
3. The array substrate according to claim 2, wherein the wiring resistance of the gate routing wiring in the first region is higher than the wiring resistance of the gate routing wiring in the third region. 4. The array substrate according to claim 1, wherein the pixel electrode and the first conductive pattern are the same layer. A common electrode facing the pixel electrode through the capacitive insulating film in the display region;
The array substrate according to claim 1, wherein the common electrode is in the same layer as the second conductive pattern. 6. A liquid crystal display device comprising the array substrate according to claim 1.

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