JP6506968B2 - Voltage detector - Google Patents

Description

  The present invention relates to a voltage detector.

Conventionally, a low power consumption voltage detector has been proposed by using a power supply terminal input type CMOS inverter with the power supply terminal as an input voltage and the gate terminal as a predetermined fixed voltage (see, for example, Non-Patent Document 1).
Non-Patent Document 1 KAWARI TAKAKUBO, HAJIME TAKAKUBO, "Wide Range CMOS Voltage Detector with Low Current Consumption and Low Temperature Variation", IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 2009/02/01, Vol. E92-A No. 2 pp. 443-450

  In the conventional voltage detector, when the fixed voltage Vref is increased to raise the detection voltage Vdet, the current consumption at the time of detection increases. In the conventional voltage detector, when the fixed voltage Vref is decreased to lower the detection voltage Vdet, the response speed at the time of detection becomes slower.

  In the first aspect of the present invention, a transistor of the first conductivity type to which an input voltage is input to the source terminal and a reference voltage to the gate terminal, and a constant connected to the drain terminal of the transistor of the first conductivity type A voltage detector comprising: a current circuit; and an output voltage based on an input voltage and a reference voltage from a connection node of a transistor of a first conductivity type and a constant current circuit.

  The above summary of the invention does not enumerate all of the features of the present invention. In addition, a subcombination of these feature groups can also be an invention.

1 shows an outline of a voltage detector 100 according to the present embodiment. An example of operation of voltage detector 100 is shown. An example of a structure of the comparator 50 is shown. 7 shows an example of a circuit configuration of a comparator 50. An example of composition of comparator 500 concerning a comparative example is shown. FIG. 7 is a diagram for describing an operation of the comparator 500. The relationship between the reference voltage Vref of the comparator 500 and the current consumption is shown. The relationship between the reference voltage Vrefb of the comparator 50 and the current consumption is shown. One example of the configuration of the comparator 500 is shown. FIG. 7 is a diagram for explaining the response speed of the comparator 500. FIG. 7 is a diagram for explaining the response speed of the comparator 50. It is a figure for demonstrating the range of detection voltage Vdet. An example of a structure of the comparator 50 is shown. An example of a structure of the voltage detector 100 is shown. An example of an input-output waveform of voltage detector 100 is shown. An example of an input output waveform of voltage detector 100 is shown. An example of a structure of the comparator 50 is shown. An example of a structure of the voltage detector 100 using the REFB circuit 23 is shown. An example of a concrete structure of REFB circuit 23 is shown. An example of a structure of the comparator 50 is shown. 1 shows an outline of a voltage detector 100 according to the present embodiment. An outline of a method of detecting a reference voltage (VrefH, VrefL) is shown. 2 shows a basic circuit of a reference voltage generation unit 20 according to the present embodiment. A non-volatile storage element 70 comprising a tunnel oxide is shown. 5 shows an example of a circuit configuration of a reference voltage generation unit 20. 1 shows an example of a circuit configuration of a reference voltage generation unit 20 according to the present embodiment. It is a flowchart which shows the setting method of the reference voltage Vref. It is a figure for demonstrating the setting method of the reference voltage Vref. 6 shows a method of setting the nonvolatile memory element 70 according to the present embodiment. An example of operation of voltage detector 100 in reference voltage setting mode is shown. The write operation to the enhancement type MOS transistor M2 is shown. An example of operation of voltage detector 100 in reference voltage setting mode is shown. The write operation to the depletion type MOS transistor M1w is shown. 1 shows an example of a circuit configuration of a reference voltage generation unit 20 according to the present embodiment. 5 shows an example of a circuit configuration of a reference voltage generation unit 20. 5 shows an example of a circuit configuration of a reference voltage generation unit 20. 5 shows an example of a circuit configuration of a reference voltage generation unit 20. The change amount of the threshold voltage Vth with respect to the write time is shown. 5 shows an example of a circuit configuration of a reference voltage generation unit 20. The change of the threshold voltage Vth with respect to writing time is shown. The transition state of the reference voltage Vref with respect to adjustment time is shown. 5 shows an example of a circuit configuration of a reference voltage generation unit 20. 5 shows an example of a circuit configuration of a reference voltage generation unit 20. The transition state of the reference voltage Vref with respect to adjustment time is shown. An example of a structure of the voltage detector 100 is shown. An example of a structure of the voltage detector 100 in a real operation mode is shown. 10 shows another connection example of the first MOS transistor M1 and the second MOS transistor M2 in the reference voltage generation unit 20.

  Hereinafter, the present invention will be described through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Moreover, not all combinations of features described in the embodiments are essential to the solution of the invention.

  FIG. 1 shows an outline of a voltage detector 100 according to the present embodiment. The voltage detector 100 includes a reference voltage generation unit 20, a voltage selection unit 40, and a comparator 50. The voltage detector 100 detects whether the input voltage Vin is equal to or higher than a predetermined detection voltage Vdet.

  The reference voltage generation unit 20 generates a reference voltage Vref corresponding to the detection voltage Vdet. The reference voltage generation unit 20 of the present example includes a first reference voltage generation unit 21 and a second reference voltage generation unit 22 having non-volatile storage elements. The reference voltage generation unit 20 adjusts the non-volatile storage element to adjust the reference voltage Vref generated by the first reference voltage generation unit 21 and the second reference voltage generation unit 22. The first reference voltage generation unit 21 and the second reference voltage generation unit 22 generate reference voltages Vref of different levels.

  The first reference voltage generation unit 21 generates a reference voltage VrefH for detecting a rise. The first reference voltage generation unit 21 outputs the generated reference voltage VrefH to the voltage selection unit 40.

  The second reference voltage generation unit 22 generates a reference voltage VrefL for falling detection. The second reference voltage generation unit 22 outputs the generated reference voltage VrefL to the voltage selection unit 40. The reference voltage VrefL in this example is smaller than the reference voltage VrefH.

  The voltage selection unit 40 selects one of the reference voltage VrefH and the reference voltage VrefL. The voltage selection unit 40 outputs the selected reference voltage Vref to the comparator 50.

  The comparator 50 outputs a signal corresponding to the comparison between the input voltage Vin and the detection voltage Vdet. The signal output from the comparator 50 changes depending on whether the input voltage Vin is equal to or higher than the detection voltage Vdet. In this example, when the input voltage Vin is smaller than the detection voltage Vdet, the output of the comparator 50 is the reference potential Vss. On the other hand, when the input voltage Vin is equal to or higher than the detection voltage Vdet, the output of the comparator 50 is substantially equal to the input voltage Vin. In the present specification, the change of the output of the comparator 50 from the reference potential Vss to the input voltage Vin and the change of the input voltage Vin from the input voltage Vin to the reference potential Vss are referred to as “inversion” of the output of the comparator 50.

  The voltage detector 100 of this example operates in hysteresis. When the hysteresis operation is performed, the voltage selection unit 40 selects one of the reference voltage VrefH and the reference voltage VrefL according to the output of the comparator 50. For example, when the comparator 50 outputs the reference potential Vss, the voltage selection unit 40 selects the reference voltage VrefH. On the other hand, when the comparator 50 outputs a voltage substantially equal to the input voltage Vin, the voltage selection unit 40 selects the reference voltage VrefL.

  FIG. 2 shows an example of the operation of the voltage detector 100. The horizontal axis represents the input voltage Vin [V] input to the voltage detector 100, and the vertical axis represents the output voltage Vout [V] of the comparator 50.

  The voltage detector 100 operates in hysteresis using a plurality of detection voltages Vdet. For example, in the voltage detector 100, the rising detection voltage when the comparator 50 outputs the reference potential Vss is VdetH, and the falling detection voltage when the comparator 50 outputs a voltage substantially equal to the input voltage Vin is VdetL. Set to In this case, the reference voltage VrefH corresponds to the rising detection voltage VdetH, and the reference voltage VrefL corresponds to the falling detection voltage VdetL.

  With the output voltage Vout of the comparator 50 at the reference potential Vss, when the input voltage Vin increases to the rise detection voltage VdetH, a voltage substantially equal to the input voltage Vin is output as the output voltage Vout of the comparator 50. When the output voltage Vout of the comparator 50 is substantially equal to the input voltage Vin and the input voltage Vin decreases to the falling detection voltage VdetL, the output voltage Vout of the comparator 50 becomes the reference potential Vss.

  The voltage detector 100 according to the present embodiment is particularly useful in the field of energy harvesting. When the voltage detector 100 is used in the field of energy harvesting, a small amount of energy is stored in a capacitor, and after it has accumulated up to a usable voltage, work is done with that energy. After the rise detection voltage VdetH is accumulated, work can be performed using the voltage difference from the rise detection voltage VdetH to the fall detection voltage VdetL. The voltage difference VdetH-VdetL between the rising detection voltage and the falling detection voltage differs depending on the system required. Therefore, by arbitrarily setting the potentials of the rising detection voltage VdetH and the falling detection voltage VdetL, it is possible to determine the performance of the system to be achieved, and a great merit is obtained.

  FIG. 3 shows an example of the configuration of the comparator 50. The comparator 50 includes a CMOS inverter 51 and an output circuit 52. The CMOS inverter 51 has a first transistor M1 and a constant current circuit 53.

  The CMOS inverter 51 compares the input voltage Vin with the detection voltage Vdet. The CMOS inverter 51 outputs an output voltage Vouti according to the result of comparing the input voltage Vin with the detection voltage Vdet. The CMOS inverter 51 is a power supply terminal input type CMOS inverter. Therefore, the input voltage Vin is input to the positive side power supply terminal of the CMOS inverter 51, and the reference potential Vss is input to the negative side power supply terminal. The positive power supply terminal of the CMOS inverter 51 is a terminal connected to the source terminal of the first transistor M1, and the negative power supply terminal is a terminal connected to one end of the constant current circuit 53. In the present specification, the electrical connection of the terminals is simply referred to as "connection".

  The first transistor M1 is an enhancement type PMOS transistor. An input voltage Vin is input to the source terminal of the first transistor M1. Further, a fixed reference voltage Vref corresponding to the reference voltage Vrefb is input to the gate terminal of the first transistor M1. The first transistor M1 raises the input voltage Vin in a state where the reference voltage Vref is input to the gate terminal, and turns on when the rise detection voltage VdetH is exceeded. In this case, the detection voltage Vdet is represented by Vref + Vgs_M1. Vgs_M1 is a voltage between the gate and the source of the first transistor M1, and is a fixed value unique to the first transistor M1. Therefore, the magnitude of the drain current flowing to the first transistor M1 is determined by the reference voltage Vref.

  The constant current circuit 53 is connected to the drain terminal of the first transistor M1. The constant current circuit 53 is grounded to the reference potential Vss. An output voltage Vouti is output from a connection point between the first transistor M1 and the constant current circuit 53. The constant current circuit 53 may be simply formed of a resistive element.

  The output circuit 52 outputs a voltage Vout corresponding to the output voltage Vouti output from the CMOS inverter 51. For example, the output circuit 52 includes a CMOS inverter connected in multiple stages with the CMOS inverter 51. The output circuit 52 may have a PMOS switch that switches whether to output the output voltage Vouti of the CMOS inverter 51. Further, the output circuit 52 may have an NMOS circuit in which the source operating according to the output voltage Vouti of the CMOS inverter 51 is connected to the ground potential. Further, the output circuit 52 may have a plurality of types of output circuits and output terminals corresponding to the respective output circuits.

  With the above configuration, the comparator 50 switches depending on whether the difference between the input voltage Vin and the reference voltage Vref is equal to or higher than the gate-source voltage Vgs_M1 of the first transistor M1. For example, the comparator 50 outputs a high (input voltage Vin) level voltage when the difference between the input voltage Vin and the reference voltage Vref is equal to or greater than Vgs_M1. The comparator 50 also outputs a low (reference potential Vss) level voltage when the difference between the input voltage Vin and the reference voltage Vref is smaller than Vgs_M1. The operating point (detection voltage Vdet) at which the output of the comparator 50 is inverted is adjusted by the reference voltage Vref. The comparator 50 of this example changes the detection voltage Vdet according to the output of the output circuit 52 by the voltage selection unit 40 selecting any one of the reference voltages VrefH and VrefL according to the output of the output circuit 52. Thus, the voltage detector 100 operates in hysteresis.

  The reference voltage Vref to be input to the comparator 50 with respect to the detection voltage Vdet at which the voltage detector 100 should operate depends on the characteristics of the CMOS inverter 51 included in the comparator 50. However, since the characteristics of the CMOS inverter 51 have variations, it is preferable to use the reference voltage Vref in consideration of variations in the characteristics of the CMOS inverter 51 in order to operate the voltage detector 100 with the detection voltage Vdet with high accuracy.

  FIG. 4 shows an example of the circuit configuration of the comparator 50. As shown in FIG. The constant current circuit 53 of this example includes a second transistor M2, a third transistor M3, and a constant current source 54. The second transistor M2 and the third transistor M3 constitute a current mirror circuit.

  The second transistor M2 is an enhancement type NMOS transistor. The drain terminal of the second transistor M2 is connected to the drain terminal of the first transistor M1. The source terminal of the second transistor M2 is grounded to the reference potential Vss. The gate terminal of the second transistor M2 is connected to the gate terminal of the third transistor M3. The second transistor M2 may be a depression type NMOS transistor.

  The third transistor M3 is an enhancement type NMOS transistor. The drain terminal of the third transistor M3 is connected to the constant current source 54. The source terminal of the third transistor M3 is grounded to the reference potential Vss. The gate terminal of the third transistor M3 is connected to the drain terminal of the third transistor M3. The third transistor M3 may be a depression type NMOS transistor.

  The constant current source 54 supplies a constant current Ic to the third transistor M3. Further, since the second transistor M2 and the third transistor M3 constitute a current mirror circuit, a constant current Ic flows in the second transistor M2 and the third transistor M3. Thus, the current flowing through the second transistor M2 is controlled to be constant regardless of the switching state of the comparator 50.

  The reference voltage Vref and the detection voltage Vdet of the comparator 50 are arbitrarily set according to the required characteristics. For example, in the comparator 50, the reference voltage VrefH for rising detection is 0.5V to 3.2V. In this case, the rising detection voltage VdetH is 1.8V to 4.4V. Further, the reference voltage VrefL for falling detection is 0.4V to 3.0V. In this case, the falling detection voltage VdetL is 1.7V to 4.0V. When the first transistor M1 is on and the operating temperature is normal temperature (25 ° C.), the drain current of the first transistor M1 and the drain current of the second transistor M2 are approximately 10 nA. However, although the drain currents of the first transistor M1 and the second transistor M2 increase and decrease depending on the temperature, they are constant regardless of the magnitudes of the detection voltage Vdet and the input voltage Vin. On the other hand, when the first transistor M1 is off, the consumption current of the comparator 50 is 0A.

  FIG. 5 shows an example of the configuration of the comparator 500 according to the comparative example. The comparator 500 includes a PMOS transistor Mp and an NMOS transistor Mn. The comparator 500 is a power supply terminal input type CMOS inverter type comparator. The PMOS transistor Mp and the NMOS transistor Mn of this example differ from the comparator 50 in that the reference voltage Vref according to the voltage Vrefa is input to any gate terminal.

  The PMOS transistor Mp is an enhancement type PMOS transistor. The input voltage Vin is input to the source terminal of the PMOS transistor Mp. The PMOS transistor Mp is turned on when the input voltage Vin exceeds the detection voltage Vdet, and the output is inverted. The detection voltage Vdet of the voltage detector 100 is represented by Vref + Vgs_Mp. Since Vgs_Mp is constant, the detection voltage Vdet changes according to the reference voltage Vref. Further, since the reference voltage Vref is input to the gate terminal of the PMOS transistor Mp, the magnitude of the current flowing through the PMOS transistor Mp is determined by the reference voltage Vref.

The NMOS transistor Mn is an enhancement type NMOS transistor. The drain terminal of the NMOS transistor Mn is connected to the drain terminal of the PMOS transistor Mp. The source terminal of the NMOS transistor Mn is grounded to the reference potential Vss. The reference voltage Vref is input to the gate terminal of the NMOS transistor Mn. That is, when the reference voltage Vref input to the gate terminal of the NMOS transistor Mn changes, the Mp-Mn drain current I _Mpnd flowing through the NMOS transistor Mn changes according to the reference voltage Vref.

  In the comparator 500, the reference voltage VrefH for detecting rising is 2.0V to 4.2V. In this case, the rising detection voltage VdetH is 1.8V to 4.4V. Further, the reference voltage VrefL for falling detection is 1.8V to 4.0V. In this case, the falling detection voltage VdetL is 1.7V to 4.0V. When the PMOS transistor Mp is on and the operating temperature is normal temperature (25 ° C.), the drain current of the PMOS transistor Mp and the drain current of the NMOS transistor Mn are 10 nA to 50 nA. However, the drain currents of the PMOS transistor Mp and the NMOS transistor Mn increase or decrease depending on the detection voltage Vdet, the input voltage Vin, the temperature, and the like. On the other hand, when the PMOS transistor Mp is off, the consumption current of the comparator 500 is 0A.

  FIG. 6 is a diagram for explaining the operation of the comparator 500. In this example, the input voltage Vin is raised from 0 V while the reference voltage Vref is a constant voltage Vrefa. When the input voltage Vin is smaller than the rising detection voltage VdetH, the PMOS transistor Mp is in the off state, and the NMOS transistor Mn is in the on state. When the input voltage Vin exceeds the rising detection voltage VdetH, the PMOS transistor Mp is turned on and the output of the comparator 500 is inverted.

  The rise detection voltage VdetH is Vrefa + Vgs_Mp. Vgs_Mp is a voltage between the gate and the source of the PMOS transistor Mp, which is a fixed value inherent to the PMOS transistor Mp. Therefore, Vrefa + Vgs_Mp changes according to the value of the reference voltage Vrefa. Further, the magnitude of the PMOS transistor Mp-Mn drain current is determined by the reference voltage Vrefa. Therefore, if the comparator 500 raises the reference voltage Vref and raises the setting level of the detection voltage Vdet, the consumption current at the time of detection increases.

  FIG. 7 shows the relationship between the reference voltage Vref of the comparator 500 and the current consumption. The reference voltage Vref of this example changes in three steps of the reference voltage Vrefa_0, the reference voltage Vrefa_1, and the Vrefa_2 according to the setting level of the detection voltage Vdet. In the case of the reference voltage Vrefa_0, the rise detection voltage VdetH = Vrefa_0 + Vgs_Mp. In the case of the reference voltage Vrefa_1, the rise detection voltage VdetH = Vrefa_1 + Vgs_Mp.

In the comparator 500, since the reference voltage Vref is input to the gate terminals of the PMOS transistor Mp and the NMOS transistor Mn, the Mp-Mn drain current changes in accordance with the magnitude of the reference voltage Vref. The Mp-Mn drain current _IMpnD increases as the reference voltage Vrefa input to the gate terminal increases. Therefore, the Mp-Mn drain current _IMpnD increases as the rising detection voltage VdetH increases. Thus, the consumption current at the time of detection of the comparator 500 changes with the magnitude of the reference voltage Vrefa.

  FIG. 8 shows the relationship between the reference voltage Vrefb of the comparator 50 and the current consumption. The reference voltage Vref of this example changes in three steps of the reference voltage Vrefb_0 and the reference voltages Vrefb_1 and Vrefb_2 according to the setting level of the detection voltage Vdet. In the case of the reference voltage Vrefb_0, the rise detection voltage VdetH = Vrefb_0 + Vgs_M1. In the case of the reference voltage Vrefb_1, the rise detection voltage VdetH = Vrefb_1 + Vgs_M1.

Since the reference voltage Vref is not input to the gate terminal of the second transistor M2, the drain current of the second transistor M2 is constant regardless of the magnitude of the reference voltage Vref in the comparator 50. Therefore, the M1-M2 drain current _IM12D is the current set by the constant current circuit 53. In other words, the drain current _{I M1D} of the first transistor M1 is constant regardless of the magnitude of the rise detection voltage VDETH. That is, the voltage detector 100 does not increase the current consumption even when the set level of the detection voltage Vdet is high. As described above, by appropriately setting the drain current of the second transistor M2, the consumption current of the voltage detector 100 becomes smaller than the consumption current of the comparator 500.

  FIG. 9 shows an example of the configuration of the comparator 500. In the circuit configuration of the comparator 500 of this example, the output end capacitance Cout connected to the output terminal is considered. The magnitude of the output end capacitance Cout is determined by the parasitic capacitance and the like of the next stage circuit element of the comparator 500. Therefore, the output end capacitance Cout is constant regardless of the magnitude of the reference voltage Vref.

  The output end capacitance Cout is related to the response speed of the comparator 500. For example, in the output terminal of the comparator 500, when the input voltage Vin falls and falls below Vref + Vgs_Mp which is the falling detection voltage VdetL, the PMOS transistor Mp is turned off and the output terminal becomes the reference potential Vss level. Here, in order for the PMOS transistor Mp to be turned off and the output terminal to have the reference potential Vss level, it is necessary to extract the charge of the output terminal capacitance Cout by the drain current of the NMOS transistor Mn. However, when the detection voltage Vdet is low (= the voltage of the reference voltage Vrefa is low), the current supply capability of the NMOS transistor Mn is reduced, and the response speed of the comparator 500 is reduced.

  FIG. 10 is a diagram for explaining the response speed of the comparator 500. As shown in FIG. FIG. 10 (a) shows the time change of the input voltage Vin, and FIG. 10 (b) shows the time change of the output voltage Vout.

The response speed of the comparator 500 is determined based on the output end capacitance Cout and the drain current I _MnD of the NMOS transistor Mn. More specifically, the response speed = Cout × Vout / I _MnD . In the comparator 500, the output end capacitance Cout is constant. On the other hand, drain currents I _MnD and V of the NMOS transistor Mn change in accordance with the reference voltage Vref. The solid line is for the high detection voltage V _H of the setting level, and the broken line is for the low detection voltage V _L of the setting level.

Time t1 is the time when the input voltage Vin becomes smaller than the falling detection voltage VdetL and the PMOS transistor Mp is turned off. In either case of the detection voltages V _H and V _L , the PMOS transistor Mp is turned off, thereby reducing the input voltage Vin.

Time tHL_V _H is a time in which all the charges accumulated in the output terminal capacitance Cout in the case of the detection voltage V _H are extracted. On the other hand, time tHL_V _L is a time in which all charges accumulated in the output end capacitance Cout in the case of the detection voltage V _L are withdrawn. In the comparator 500, since the detected voltage V _H is larger than the detected voltage V _L , the drain current I _MnD of the NMOS transistor Mn is larger, the time tHL_V _H is faster than the time tHL_V _L. That is, the detection voltage V _H has a faster response speed than the detection voltage V _L. As described above, in the comparator 500, when the setting level of the detection voltage Vdet is low, the current supply capability of the NMOS transistor Mn is reduced, and the response at the time of detection is delayed.

  FIG. 11 is a diagram for explaining the response speed of the comparator 50. As shown in FIG. FIG. 11 (a) shows the time change of the input voltage Vin, and FIG. 11 (b) shows the time change of the output voltage Vout.

The response speed of the comparator 50 is determined based on the output end capacitance Cout and the drain current _IM2D of the second transistor M2. More specifically, the response speed tHL = Cout × Vout / _IM2D . In this example, the output end capacitance Cout and the drain current _IM2D of the second transistor M2 are constant. On the other hand, the output voltage Vout changes in accordance with the reference voltage Vref. Therefore, the response time t decreases as the output voltage Vout decreases. The solid line is for the high detection voltage V _H of the setting level, and the broken line is for the low detection voltage V _L of the setting level.

Time t1 is a time during which the input voltage Vin becomes smaller than the falling detection voltage VdetL and the first transistor M1 is turned off. In either case of the detection voltages V _H and V _L , the input voltage Vin is lowered by turning off the first transistor M1.

In this example, the drain current _IM2D of the second transistor M2 is constant regardless of the magnitude of the detection voltage Vdet. Therefore, the comparator 50 can improve the response speed tHL at a low detection voltage as compared with the comparator 500. Further, since the comparator 50 draws the charge of the output terminal with a constant current regardless of the detection voltage Vdet, the response speed tHL of the comparator 50 depends on the output voltage Vout. Therefore, in the comparator 50, the response speed tHL at the time of low voltage detection becomes faster than the response speed tHL at the time of high voltage detection.

  FIG. 12 is a diagram for explaining the range of the detection voltage Vdet. FIG. 12A is a diagram for explaining the range of the detection voltage Vdet of the comparator 500, and FIG. 12B is a diagram for explaining the range of the detection voltage Vdet of the comparator 50.

  The lower limit of the detection voltage Vdet of the comparator 500 is the lowest voltage of the input voltage Vin necessary to flow drain current to the PMOS transistor Mp and the NMOS transistor Mn. Therefore, the lower limit of the detection voltage Vdet of the comparator 500 is the sum of the gate-source voltage of the PMOS transistor Mp and the NMOS transistor Mn. That is, the lower limit of the detection voltage Vdet of the comparator 500 is Vgs_Mp + Vgs_Mn.

  The lower limit of the detection voltage Vdet of the comparator 50 is the lowest voltage of the input voltage Vin required to flow drain current to the first transistor M1 and the second transistor M2. Accordingly, the lower limit of the detection voltage Vdet of the comparator 50 is the sum of the gate-source voltage of the first transistor M1 and the saturation voltage of the second transistor M2. That is, the lower limit of the detection voltage Vdet of the comparator 50 is Vgs_M1 + Vsat_M2.

  As described above, the lower limit of the detection voltage Vdet of the comparator 50 is Vgs_M1 + Vsat_M2, and the lower limit of the detection voltage Vdet of the comparator 500 is Vgs_Mp + Vgs_Mn. Here, the saturation voltage Vsat of the transistor is often smaller than the threshold voltage Vth of the transistor. Therefore, the comparator 50 has a detection voltage range wider than that of the comparator 500 by Vgs_M2-Vsat_Mn, which is a difference between Vgs_Mp + Vgs_Mn and Vgs_M1 + Vsat_M2.

  FIG. 13 shows an example of the configuration of the comparator 50. The constant current circuit 53 of this example includes a constant current source 54. The constant current circuit 53 of this example differs from the constant current circuit 53 shown in FIG. 4 in that the second transistor M2 and the third transistor M3 are not provided.

  The constant current source 54 is an example of a constant current circuit 53 that supplies a constant current Ic. The constant current source 54 is connected to the drain terminal of the first transistor M1. For example, the constant current source 54 functions as a constant current circuit by injecting charges into the floating gate like an EEP (Electrically Erasable Programmable) memory cell. Thereby, the comparator 50 of this example operates in the same manner as in the case where the constant current source 54 is formed of a current mirror circuit as shown in FIG.

  The constant current Ic flowing through the constant current circuit 53 is supplied to the second transistor M2 when the first transistor M1 is turned off under the condition that the reference voltage VrefL is input to the gate terminal of the second transistor M2. It may be the drain current IrefL that flows. The constant current Ic is a drain current IrefH that flows through the second transistor M2 when the first transistor M1 is turned off in a state where it is assumed that the reference voltage VrefH is input to the gate terminal of the second transistor M2. You may Furthermore, the constant current Ic may be set to greater than or equal to IrefL and less than or equal to IrefH. Basically, the magnitude of the constant current Ic is a trade-off between the current consumption and the response speed, and may be appropriately set according to the required characteristics.

  FIG. 14 shows an example of the configuration of the voltage detector 100. The voltage detector 100 outputs an output voltage Vo from the OUT terminal in accordance with the input voltage Vin input from the VIN terminal for voltage monitoring. The output voltage Vo may be a voltage equal to the input voltage Vin, or may be a power supply voltage Vdd for output connected to the VDD terminal.

  The voltage selection unit 40 includes a switch SWH and a switch SWL. The voltage selection unit 40 selects one of the reference voltage VrefH and the reference voltage VrefL by switching on and off of the switch SWH and the switch SWL. The voltage selection unit 40 outputs the selected reference voltage Vref to the positive input terminal of the comparator 50.

  The reference voltage VrefH output from the first reference voltage generation unit 21 is input to the switch SWH. The switch SWH outputs the input reference voltage VrefH to the positive side input terminal of the comparator 50. On the other hand, the reference voltage VrefL output from the second reference voltage generation unit 22 is input to the switch SWL. The switch SWL outputs the input reference voltage VrefL to the positive input terminal of the comparator 50.

  The switch SWH and the switch SWL are turned on / off according to the output of the comparator 50. Further, the switch SWH and the switch SWL are controlled so that the on / off states are reversed. More specifically, the signal output from the comparator 50 is input to the switch SWH of this example. On the other hand, a signal obtained by inverting the output of the comparator 50 by a NOT circuit is input to the switch SWL. For example, the switches SWH and SWL turn on when a high is input from the comparator 50 and turn off when a low is input.

  The control logic 55 controls the input of the output of the comparator 50 with any logic. The control logic 55 outputs the controlled output of the comparator 50 to the inverter circuit 56 in the subsequent stage. The control logic 55 of this example is connected to the VDD terminal. Thereby, the control logic 55 may output the power supply voltage Vdd for output connected to the VDD terminal to the OUT terminal according to the output of the comparator 50. The control logic 55 in this example is connected to a POL (Point of Load) terminal for polarity switching of the monitoring result and an enable (EN) terminal with a latch.

  The inverter circuit 56 is a CMOS inverter circuit provided with a PMOS transistor and an NMOS transistor. A reflux diode is provided in parallel to the PMOS transistor and the NMOS transistor of the inverter circuit 56. The source terminal of the PMOS transistor is connected to the VDD terminal, and the drain terminal is connected to the PMOSD terminal. The source terminal of the NMOS transistor is grounded to the reference potential Vss, and the drain terminal is connected to the NMOS D terminal.

  FIG. 15 shows an example of input and output waveforms of the voltage detector 100. The input output waveform of this example is a case where the input voltage Vin and the power supply voltage Vdd are set to the same voltage.

At time A, the input voltage Vin starts to rise from the reference potential Vss. In the period AB, the input voltage Vin is less than the minimum operating voltage _V.sub.MIN . The minimum operating voltage V _MIN refers to the minimum power supply voltage Vdd at which the logic of the control logic 55 is correctly output. Below the minimum operating voltage V _MIN , the output of the OUT terminal is not accurately output. Normally, although the period AB is a period in which the output of the low (reference potential Vss) level is expected, either the high or the low is in an undefined state. In this example, high is output in period AB.

  In the period B-C, since the input voltage Vin is smaller than the rising detection voltage VdetH, the output of the OUT terminal becomes low (reference potential Vss). Time C is the time when the input voltage Vin exceeds the rise detection voltage VdetH. The rising detection voltage VdetH in this example indicates the input voltage Vin that is inverted by the comparator 50 when the reference voltage VrefH is input to the positive side input terminal of the comparator 50. When time C elapses, the on / off of the comparator 50 is switched to output a high (power supply voltage Vdd). The comparator 50 does not output high at the same time as time C, but outputs high after a predetermined delay time (tPLH).

  Time D is a time when the input voltage Vin decreases and the input voltage Vin becomes the falling detection voltage VdetL. The falling detection voltage VdetL in this example indicates the input voltage Vin that is inverted by the comparator 50 when the reference voltage VrefL is input to the positive input terminal of the comparator 50. When the time D elapses, the on / off of the comparator 50 is switched to output a low (reference potential Vss). The comparator 50 does not output low at the same time as the time D, but outputs low after a predetermined delay time (tPHL).

In the period EF, as in the period AB, the voltage at the VIN terminal is less than the minimum operating voltage V _MIN . Normally, although the period AB is a period in which the output of the low (reference potential Vss) level is expected, either the high or the low is in an undefined state. In this example, high is output in the period EF.

  FIG. 16 shows an example of the input output waveform of the voltage detector 100. The input output waveform of this example is a case where the input voltage Vin and the power supply voltage Vdd are set to different voltages.

  At time G, the increase of the input voltage Vin starts. The time H is the time when the input voltage Vin is equal to or higher than the rising detection voltage VdetH. When the time H passes, the on / off of the comparator 50 is switched to output a high (power supply voltage Vdd). The voltage detector 100 of this example is different from the case where the input voltage Vin and the power supply voltage Vdd are equal in that the power supply voltage Vdd is output instead of the input voltage Vin when the high is output.

  The time I is a time when the input voltage Vin decreases and the input voltage Vin becomes the falling detection voltage VdetL. When time I passes, the on / off of the comparator 50 is switched to output a low (reference potential Vss). The voltage detector 100 of this example has a rectangular input / output waveform because the input voltage Vin and the power supply voltage Vdd are different.

  FIG. 17 shows an example of the configuration of the comparator 50. The constant current circuit 53 of this example includes a second transistor M2 and a third transistor M3.

  The second transistor M2 and the third transistor M3 are formed of HV (High Voltage) -NMOS. The gate terminal of the second transistor M2 and the gate terminal of the third transistor M3 are connected to each other. The second transistor M2 and the third transistor M3 are each formed of an EEPROM. Therefore, by controlling writing of the floating gates of the second transistor M2 and the third transistor M3, it is possible to control so that a predetermined drain current flows in the second transistor M2 and the third transistor M3. The second transistor M2 and the third transistor M3 of this example are set to flow 10 nA as a drain current.

  In the comparator 50, when the input voltage Vin rises and the first transistor M1 is turned on, the output of the output terminal CMPOUT is inverted. The comparator 50 in this example includes a predetermined logic circuit between the connection node of the first transistor M1 and the constant current circuit 53 and the output terminal CMPOUT. The comparator 50 can improve the response speed tHL because a predetermined current flows from the constant current circuit 53 when the set level of the detection voltage Vdet is low. In addition, when the setting level of the detection voltage Vdet is high, the comparator 50 does not increase the drain current flowing in the constant current circuit 53, so that the increase in current consumption can be suppressed.

  FIG. 18 shows an example of the configuration of a voltage detector 100 using the REFB circuit 23. The REFB circuit 23 is connected to the CMP terminal of the comparator 50. The CMP terminal is connected to the drain terminal of the first transistor M1 of the comparator 50. The REFB circuit 23 is set to flow a predetermined REF current to the CMP terminal. The REF current is adjusted by controlling the writing of the EEPROM.

  FIG. 19 shows an example of a specific configuration of the REFB circuit 23. The REFB circuit 23 includes a first write MOS transistor Mw-1, a first output MOS transistor Mr-1, a second write MOS transistor Mw-2, and a second output MOS transistor Mr-2.

  The first write MOS transistor Mw-1 and the first output MOS transistor Mr-1 each have a floating gate and a control gate. The floating gate and the control gate of the first write MOS transistor Mw-1 are connected to the floating gate and the control gate of the first output MOS transistor Mr-1, respectively. The first write MOS transistor Mw-1 has a tunnel oxide film. On the other hand, the first output MOS transistor Mr-1 does not have a tunnel oxide film.

  A predetermined input voltage Vin is applied to the drain terminal of the first output MOS transistor Mr-1. The source terminal of the first output MOS transistor Mr-1 is connected to the drain terminal of the second output MOS transistor Mr-2. The drain terminal of the second output MOS transistor Mr-2 is set to be a constant voltage Vr. The reference potential Vss is applied to the source terminal of the second output MOS transistor Mr-2.

  The second write MOS transistor Mw-2 has a floating gate and a control gate. The second output MOS transistor Mr-2 has a floating gate. The floating gate of the second write MOS transistor Mw-2 is connected to the floating gate of the second output MOS transistor Mr-2. The second write MOS transistor Mw-2 has a tunnel oxide film. On the other hand, the second output MOS transistor Mr-2 does not have a tunnel oxide film.

  The first write MOS transistor Mw-1 and the second write MOS transistor Mw-2 have a tunnel oxide film. Therefore, the threshold voltage Vth can be controlled by controlling the state of the charge of the floating gate of the first write MOS transistor Mw-1 and the second write MOS transistor Mw-2 through the tunnel oxide film. . Then, as described above, since the floating gates and the control gates of the two first MOS transistors Mw-1 and r are connected to each other, the first output MOS transistor Mr-1 is connected to the first write MOS transistor Mw-1. It has the same threshold voltage Vth. Similarly, the second output MOS transistor Mr-2 also has the same threshold voltage Vth as the second write MOS transistor Mw-2.

  The REFB circuit 23 of this example can flow a predetermined REF current to the CMP terminal by writing data in the EEPROM. Further, since the first output MOS transistor Mr-1 and the second output MOS transistor Mr-2 do not have a tunnel oxide film, there is no fluctuation of the threshold voltage Vth due to disturbance. Therefore, highly reliable REF current can be generated with high accuracy.

  The voltage Vr of the drain terminal of the second output MOS transistor Mr-2 may simply have a value less than the voltage at which the PMOS transistor in the logic circuit subsequent to the comparator 50 is turned on. However, when the drain current of the second transistor M2 is 0 A and the first transistor M1 is in the off state, the OUT terminal is in the floating state. Further, since the voltage at which the PMOS transistor in the logic circuit after the output terminal of the comparator 50 is turned on is lower than the voltage at which the first transistor M1 is turned on, the drain voltage of the second transistor M2 is 0 A and the input voltage Vin is When raised, a through current flows in the logic circuit after the output terminal of the comparator 50. Therefore, the voltage Vr in this example is set to a value lower than the voltage setting range (0.5 V to 3.2 V) of the reference voltage VrefH and the voltage setting range (0.4 V to 3.0 V) of the reference voltage VrefL. doing. Thereby, the second transistor M2 can supply the drain current even when the input voltage Vin is low. Therefore, the REFB circuit 23 can prevent the through current from flowing in the logic circuit after the output terminal of the comparator 50.

  FIG. 20 shows an example of the configuration of the comparator 50. The comparator 50 further includes a fourth transistor M4 and a fifth transistor M5. The comparator 50 of this example can switch the magnitude of the current flowing to the drain terminal of the first transistor M1 according to the on / off state of the first transistor M1.

  The fourth transistor M4 is an enhancement type NMOS transistor. The fourth transistor M4 forms a current mirror circuit with the third transistor M3 as in the second transistor M2. The gate terminal of the fourth transistor M4 is connected to the gate terminal of the second transistor M2 and the gate terminal of the third transistor M3. As a result, the fourth transistor M4 causes a constant current Ic according to the constant current source 54 to flow from the drain terminal of the first transistor M1.

  The fifth transistor M5 is an enhancement type NMOS transistor. The fifth transistor M5 switches whether to connect the drain terminal of the first transistor M1 and the drain terminal of the fourth transistor M4. The drain terminal of the fifth transistor M5 is connected to the drain terminal of the first transistor M1. A signal obtained by inverting the output of the first transistor M1 via the NOT circuit is input to the gate terminal of the fifth transistor M5. The source terminal of the fifth transistor M5 is connected to the drain terminal of the fourth transistor M4.

  In the comparator 50 of this example, the magnitude of the current flowing to the drain terminal of the first transistor M1 changes in accordance with the on / off state of the first transistor M1. For example, when the first transistor M1 is in the on state, the drain current of the first transistor M1 flows to the second transistor M2. On the other hand, when the first transistor M1 is in the OFF state, the drain current of the first transistor M1 flows to the second transistor M2 and the fourth transistor M4. That is, the comparator 50 of this example can improve the response speed tHL in the state in which the first transistor M1 is off while reducing the consumption current in the state in which the first transistor M1 is on.

  As described above, in the voltage detector using the power supply terminal input type CMOS inverter, the voltage detector 100 uses the NMOS transistor side as a constant current source. Thus, the voltage detector 100 can realize the improvement of the characteristic of the comparator circuit and the expansion of the function. Specifically, the voltage detector 100 can suppress an increase in current consumption when the setting level of the detection voltage Vdet is high, and can improve the response speed tHL when the setting level of the detection voltage Vdet is low. Also, the voltage detector 100 can extend the detection voltage range from Vgs_M1 + Vgs_M2 to Vgs_Mp + Vsat_Mn.

  The voltage detector 100 is highly effective when applied to recent portable electronic devices. For example, portable electronic devices use battery power rather than external power. In battery driving, the discharge voltage of the battery decreases with time, and the power supply voltage of the electronic device decreases. When the power supply voltage falls below the minimum operating voltage, the internal circuit of the electronic device operates unexpectedly and causes a failure. The voltage detector 100 of this example monitors the power supply voltage with the voltage detector, detects the power supply voltage drop, and can stop the supply of the power supply voltage to turn off the internal circuit before the minimum operating voltage is reached.

  FIG. 21 shows a detailed configuration example of the voltage detector 100 according to the present embodiment. The voltage detector 100 of this example is a reference voltage detection mode for detecting the reference voltage Vref for operating the comparator 50 with the set detection voltage Vdet, and a reference for causing the reference voltage generation unit 20 to output the detected reference voltage Vref. There are three operation modes of a reference voltage setting mode for setting the voltage generation unit 20 and an actual operation mode for comparing the input voltage Vin with the detected voltage Vdet using the set reference voltage Vref. The voltage detector 100 of this example further includes a mode selection unit 10 and a test circuit 60 in addition to the configuration shown in FIG. The voltage detector 100 also has terminals VPP, DATA, SCLK, PULSE, GND, VIN, VREF, IREF, VMON, and OUT which connect the inside and the outside of the voltage detector 100. The VREF terminal and the IREF terminal may be the same terminal.

  The mode selection unit 10 selects the operation mode of the voltage detector 100. The mode selection unit 10 may select the operation mode based on the voltage input from the VPP terminal. The mode selection unit 10 controls the voltage selection unit 40, the first reference voltage generation unit 21, and the second reference voltage generation unit 22 according to the selected operation mode.

  In the actual operation mode, the mode selection unit 10 causes the voltage selection unit 40 to select the reference voltage Vref based on a signal indicating the output state of the comparator 50. The test circuit 60 has a current mirror 61 and an amplifier circuit 62. The test circuit 60 does not operate in the actual operation mode, but operates in the reference voltage setting mode. In addition, the voltage selection unit 40 of this example is set to be externally input to the reference voltage VrefH output from the first reference voltage generation unit 21, the reference voltage VrefL output from the second reference voltage generation unit 22, and the VREF terminal. One of the voltages is selected according to the operation mode.

  First, the operation of the voltage detector 100 in the reference voltage detection mode will be described. A line through which a signal flows mainly in the reference voltage detection mode is indicated by a thick line. When the mode selection unit 10 selects the reference voltage detection mode, the mode selection unit 10 causes the voltage selection unit 40 to select the set voltage Vrefc output from the VREF terminal. In the reference voltage detection mode, the set voltage Vrefc whose level changes gradually is input to the VREF terminal. The voltage selection unit 40 inputs the selected set voltage Vrefc to the input terminal of the CMOS inverter 51.

  In the reference voltage detection mode, the same voltage as the detection voltage Vdet at which the voltage detector 100 operates is input to the comparator 50 from the VIN terminal. In this example, the voltage detector 100 operates with two detection voltages Vdet of the rising detection voltage VdetH and the falling detection voltage VdetL in order to perform the hysteresis operation. In this case, the rising detection voltage VdetH and the falling detection voltage VdetL are sequentially input to the VIN terminal. The VIN terminal is connected to the power supply terminal of the comparator 50.

  The comparator 50 operates in accordance with the input set voltage Vrefc and the detection voltage Vdet. Since the set voltage Vrefc gradually changes, the output state of the comparator 50 is inverted when the difference between the set voltage Vrefc and the detection voltage Vdet becomes equal to or greater than a predetermined value. The output terminal of the comparator 50 is connected to the OUT terminal. The level of the setting voltage Vrefc when the output state of the comparator 50 is inverted becomes the level of the reference voltage Vref corresponding to the detection voltage Vdet. The output state of the comparator 50 may be monitored by an external device connected to the OUT terminal, or may be monitored by the internal circuit of the voltage detector 100.

  FIG. 22 shows an outline of a method of detecting the reference voltage (VrefH, VrefL) in the reference voltage detection mode. The vertical axis represents the input voltage Vin input from the VIN terminal, the setting voltage Vrefc input to the input terminal of the CMOS inverter 51, and the voltage levels [V] of the reference voltages (VrefH and VrefL), and the horizontal axis represents time indicates t.

  The detection voltage Vdet input to the VIN terminal gradually increases with the passage of time, and is held constant when reaching a predetermined detection voltage Vdet. The set voltage Vrefc increases with the detected voltage to an initial value that is larger by a predetermined value than the predicted reference voltage VrefH. After the set voltage Vrefc becomes an initial value, the set voltage Vrefc is gradually changed (decreased in this example) to detect the set voltage Vrefc when the output of the CMOS inverter 51 is inverted. The detected set voltage Vrefc is the reference voltage Vref for the input detected voltage Vdet. Such a process is performed on both the rising detection voltage VdetH and the falling detection voltage VdetL, and the reference voltages VrefH and VrefL corresponding to each are detected. The mode selection unit 10 sets the reference voltage generation unit 20 based on the detected set voltage Vrefc. The setting voltage Vrefc may be changed so that the output state of the comparator 50 transitions after the input voltage Vin reaches the detection voltage Vdet, and the present invention is not limited to this example.

  FIG. 23 shows a basic circuit of the reference voltage generation unit 20 according to the present embodiment. The first reference voltage generation unit 21 and the second reference voltage generation unit 22 may each have the same circuit as the reference voltage generation unit 20. As shown in FIG. 23B, the reference voltage generation unit 20 according to the present embodiment generates a reference voltage Vref using an element that can be brought into two states, an enhancement state and a depletion state.

  FIG. 23A shows the reference voltage generation unit 20 configured of the depletion type MOS transistor M1 and the enhancement type MOS transistor M2. Each of the MOS transistors in FIG. 23A functions as a depletion type and an enhancement type, respectively, due to differences in manufacturing parameters such as the doping amount.

  FIG. 23B shows a reference voltage generation unit 20 having a first MOS transistor M1 functioning as a depletion type and a second MOS transistor M2 functioning as an enhancement type. The first MOS transistor M1 and the second MOS transistor M2 each have a floating gate and a control gate. In the first MOS transistor M1 and the second MOS transistor M2 of this example, the state of the charge stored in the floating gate is controlled according to the voltage applied to the control gate, and the non-volatile property shows characteristics according to the stored charge amount. It functions as a memory element. The state of charge stored by the floating gate refers to, for example, the positive / negative and charge amount of charge stored by the floating gate. In this example, the threshold voltages of the first MOS transistor M1 and the second MOS transistor M2 change according to the state of charge stored in the floating gate. Thus, each MOS transistor functions as a depletion type or an enhancement type.

  The gate terminal and the source terminal of the first MOS transistor M1 are connected to each other, and the drain terminal is connected to the power supply. The first MOS transistor M1 functions as a depletion type when positive charge is injected into the floating gate. The depletion type is an element in which the transistor is turned off when a voltage of 0 V is input to the gate terminal, and refers to a so-called normally-off element.

  The gate terminal and the drain terminal of the second MOS transistor M2 are connected to each other, and the source terminal is grounded. The drain terminal of the second MOS transistor M2 is connected to the source terminal of the first MOS transistor M1. The second MOS transistor M2 functions as an enhancement type when negative charge is injected into the floating gate. The enhancement type is an element in which a transistor is turned on when a voltage of 0 V is input to the gate terminal, and refers to a so-called normally on element. The reference voltage generation unit 20 outputs a reference voltage Vref from a connection point of the first MOS transistor M1 and the second MOS transistor M2.

  Since the reference voltage generation unit 20 shown in FIG. 23B can change the state of the nonvolatile memory element after manufacturing, it can compensate for variations in characteristics at design and after manufacturing. Therefore, the reference voltage generation unit 20 can adjust the reference voltage Vref output from the connection point of the first MOS transistor M1 and the second MOS transistor M2. The mode selection unit 10 adjusts the reference voltage Vref by controlling the state of charges stored by the floating gates of the first MOS transistor M1 and the second MOS transistor M2.

  FIG. 24 shows a non-volatile storage element 70 provided with a tunnel oxide film. The nonvolatile memory element 70 includes a substrate 71, a tunnel oxide film 74, a floating gate 75, an insulating film 76, and a control gate 77.

  The nonvolatile memory element 70 is an NMOS type element that can be brought into the enhancement state and the depletion state by having the floating gate 75. The substrate 71 in this example is a p-type substrate. The substrate 71 has a source region 72 and a drain region 73. Source region 72 and drain region 73 are formed using a general CMOS process such as ion implantation. The tunnel oxide film 74, the floating gate 75, the insulating film 76, and the control gate 77 are stacked in this order on the substrate 71.

  The control gate 77 controls a channel region formed between the source region 72 and the drain region 73 by a voltage applied to the gate terminal of the nonvolatile memory element 70. Thus, the nonvolatile memory element 70 turns on / off the current flowing between the source region 72 and the drain region 73.

  An insulating film 76 insulates between the floating gate 75 and the control gate 77. The insulating film 76 is formed of a general insulating film used in a CMOS process. The state of the charge stored in floating gate 75 changes in accordance with the voltage applied to control gate 77. For example, in response to the voltage applied to control gate 77, the amount of charge stored in floating gate 75 fluctuates in the positive or negative direction. As a result, the threshold voltage of the non-volatile storage element 70 is varied and controlled to the depletion state or the enhancement state.

  The tunnel oxide film 74 generally insulates between the substrate 71 and the floating gate 75. However, when a voltage equal to or greater than a predetermined value is applied to control gate 77, tunnel oxide film 74 is rendered conductive by FN tunneling (Fowler-Nordheim tunneling). FN tunneling refers to a moving state when electrons tunnel in the insulator. The floating gate 75 injects electrons from the source region 72 by FN tunneling or emits electrons. Thereby, the state of the charge stored in floating gate 75 is controlled.

FIG. 25 illustrates an example of a circuit configuration of the reference voltage generation unit 20. When the reference voltage generation unit 20 is outputting the reference voltage Vref, the switch (SW) is controlled as follows.
SWl: Vdd
SW2: Vss
SW3, SW4: OPEN
SW5, SW6, SW7, SW8: SHORT (connection)
SW9, SW10: Any

  The reference voltage generation unit 20 generates the reference voltage Vref when the first MOS transistor M1 is in the depletion state and the second MOS transistor M2 is in the enhancement state in a state where the switch is controlled as shown in FIG.

  The switches SW1 to SW10 need to be switches that operate at a high voltage, and have large on-resistance as compared to ordinary switches. In particular, since SWl, SW6, SW8, and SW2 enter the current path of the reference voltage generation unit 20, the on resistance of the switch affects the reference voltage Vref.

  More specifically, the reference voltage generation unit 20 includes a control gate and a floating gate, and includes a first MOS transistor Ml that functions as a depletion type. Further, the reference voltage generation unit 20 includes a control gate and a floating gate, and includes a second write MOS transistor M2 that functions as an enhancement type. The second write MOS transistor M2 is connected in series to the first MOS transistor Ml. The first MOS transistor M1 and the second write MOS transistor M2 are non-volatile memory elements having a tunnel oxide film through which charges injected to the floating gate tunnel. Thereby, the reference voltage generation unit 20 outputs the reference voltage Vref from the connection point of the first MOS transistor M1 and the second write MOS transistor M2.

  FIG. 26 shows an example of a circuit configuration of the reference voltage generation unit 20 according to the present embodiment. The first reference voltage generation unit 21 and the second reference voltage generation unit 22 may each have the same circuit as the reference voltage generation unit 20 shown in FIG. The reference voltage generation unit 20 includes a first write MOS transistor M1w having a tunnel oxide film, a first output MOS transistor M1r having no tunnel oxide film, and a second write MOS transistor M2w having a tunnel oxide film and a tunnel. It includes a second output MOS transistor M2r having no oxide film.

  The first write MOS transistor M1w and the first output MOS transistor M1r each have a floating gate and a control gate. The floating gate and the control gate of the first write MOS transistor M1w are electrically connected to the floating gate and the control gate of the first output MOS transistor M1r, respectively.

  The source terminal of the first write MOS transistor M1 w is connected to the drain terminal of the second write MOS transistor M2 w. Similar to the configuration shown in FIG. 25, a switch may be further provided to switch whether or not to connect the first write MOS transistor M1w and the second write MOS transistor M2w. The switch SW1 selects whether to apply the voltage Vpp or the reference potential Vss such as the ground potential to the drain terminal of the first write MOS transistor M1w. The switch SW2 selects whether to apply the voltage Vpp or the reference potential Vss such as the ground potential to the source terminal of the second write MOS transistor M2w.

  A predetermined power supply voltage Vdd is applied to the drain terminal of the first output MOS transistor M1r. The source terminal of the first output MOS transistor M1r is connected to the drain terminal of the second output MOS transistor M2r. The voltage at the connection point is output as the reference voltage Vref. The reference potential Vss is applied to the source terminal of the second output MOS transistor M2r.

  The second write MOS transistor M2w and the second output MOS transistor M2r respectively have a floating gate and a control gate. The floating gate and the control gate of the second write MOS transistor M2w are electrically connected to the floating gate and the control gate of the second output MOS transistor M2r, respectively.

  The first write MOS transistor M1 w and the second write MOS transistor M2 w have a tunnel oxide film. Therefore, it is possible to control the state of the charges of the floating gates of the first write MOS transistor M1 w and the second write MOS transistor M2 w via the tunnel oxide film, and control the respective threshold voltages Vth. Then, as described above, since the floating gate and the control gate of the two first MOS transistors M1 w and r are electrically connected to each other, the first output MOS transistor M1 r has the same threshold as the first write MOS transistor M1 w. It has a voltage Vth. Similarly, the second output MOS transistor M2r has the same threshold voltage Vth as the second write MOS transistor M2w.

  Since the first output MOS transistor M1r and the second output MOS transistor M2r do not have a tunnel oxide film, there is no fluctuation of the threshold voltage Vth due to disturbance. Therefore, the reference voltage Vref can be generated with high accuracy. The first output MOS transistor M1r and the second output MOS transistor M2r form a current path in the reference voltage generation unit 20, but do not have a switch in the current path. Therefore, the on-resistance of the switch does not affect the reference voltage Vref, and the reference voltage Vref can be generated with high accuracy.

  FIG. 27 is a flowchart showing an example of a method of setting the reference voltage Vref. In step S100, the detection voltage input to the power supply terminal of the CMOS inverter 51 is set to a predetermined value.

  In the reference voltage detection mode, the comparator 50 detects a voltage to be input to the input terminal of the CMOS inverter 51 in order to operate in accordance with the detection voltage Vdet. In step S200, as described in FIG. 22, the reference voltages (VrefH, VrefL) corresponding to the detection voltage Vdet set in step S100 are detected. The detected reference voltages (VrefH, VrefL) are stored in an external device of the voltage detector 100. The detected reference voltages (VrefH, VrefL) may be stored inside the voltage detector 100.

  In the reference voltage setting mode, the reference voltages (VrefH, VrefL) detected in step S200 are set in the reference voltage generation unit 20. Step S300 for executing the reference voltage setting mode includes steps S310 to S330. In addition, the process of step S300 is performed with respect to each detection voltage Vdet. The set detection voltage Vdet is input to the power supply terminal of the CMOS inverter 51.

  In step S310, the state of the charge stored in the floating gate of the first write MOS transistor M1w is set to a predetermined reference state. The reference state in step S310 may indicate a state in which the current does not flow from the first MOS transistor M1w, r to the second MOS transistor M2w, r while the threshold voltage of the first MOS transistor M1w, r is sufficiently high. The reference state may indicate a state in which the charge stored in the floating gate is erased (that is, the state in which the amount of charge in the floating gate is substantially zero). In step S310, the control pulse is applied to the control gate of the first write MOS transistor M1w to adjust the state of charge in the floating gate to the reference state, and the current from the first MOS transistors M1w, r to the second MOS transistors M2w, r Will not flow.

  In step S320, in a state where the adjustment current generated by the current mirror 61 is applied to the second output MOS transistor M2r, a control pulse is applied to the control gate of the second write MOS transistor M2w. By applying the control pulse, the threshold voltage of the second write MOS transistor M2w is changed in the positive direction. Thereby, the two second MOS transistors M2 are set to a predetermined enhancement state. The adjustment current may be provided with a current substantially equal to the current that should flow through the second output MOS transistor M2r in actual operation. In step S320, the control gate of second write MOS transistor M2w is maintained until reference voltage Vref output from reference voltage generation unit 20 becomes substantially equal to reference voltage Vref detected in step S200 with respect to detection voltage Vdet. Apply a control pulse.

  Next, in step S330, a control pulse is applied to the control gate of the first write MOS transistor M1w while the adjustment current generated by the current mirror 61 is not applied to the second output MOS transistor M2r. By applying the control pulse, the threshold voltage of the first write MOS transistor M1w is changed in the negative direction. Thus, the two first MOS transistors M1 are set to a predetermined depletion state. Also in step S330, until the reference voltage Vref output from the reference voltage generation unit 20 becomes substantially equal to the reference voltage Vref detected in step S200 with respect to the detection voltage Vdet, the control gate of the first write MOS transistor M1w Apply a control pulse. Such processing is performed on the first reference voltage generation unit 21 and the second reference voltage generation unit 22. Thus, a voltage equal to the reference voltage Vref detected in step S200 can be output to the first reference voltage generation unit 21 and the second reference voltage generation unit 22. In step S300, the reference voltage VrefH may be set earlier than the reference voltage VrefL, or the reference voltage VrefL may be set earlier.

  FIG. 28 is a diagram for describing a setting method of reference voltage Vref. FIG. 28A shows a method of setting the second MOS transistors M2w and r to function as the enhancement type. First, the charge stored in the floating gate of the first write MOS transistor Mlw is set to the reference state. For example, by applying a control pulse to the control gate to sufficiently increase the threshold voltage of the first write MOS transistor Mlw, the charge state is set to the reference state. The polarity of the voltage applied to the control gate can be controlled by switching the switches SW1 and SW9. As a result, when setting the second MOS transistors M2w and r to function as the enhancement type, current is prevented from flowing to the first MOS transistors Mlw and r.

  Next, in a state where the adjustment current Iref is applied to the second output MOS transistor M2r, a control pulse is applied to the control gate of the second write MOS transistor M2w to charge the floating gate. At this time, the floating gate of the second write MOS transistor M2w is charged so that the reference voltage Vref output by the reference voltage generation unit 20 becomes a predetermined voltage.

  FIG. 28B shows a method of setting the first MOS transistors M1w and r to function as a depletion type. When setting the first MOS transistors M1 w and r, the adjustment current Iref is stopped. Then, a control pulse is applied to the control gate of the second write MOS transistor M2 w to charge the floating gate so that the current flowing through the second output MOS transistor M2 r is substantially the same as the adjustment current Iref. . In this example, instead of detecting the current flowing through the second output MOS transistor M2r, the second write MOS transistor M2w is set such that the reference voltage Vref output by the reference voltage generation unit 20 becomes the above-described predetermined voltage. Charge the floating gate.

  FIG. 29 shows a method of setting the nonvolatile memory element 70. The nonvolatile memory element 70 corresponds to the first write MOS transistor M1 w and the second write MOS transistor M2 w described above. The non-volatile memory element 70 is an NMOS type element having a control gate and a floating gate. In the non-volatile storage element 70, charge is accumulated in the floating gate by FN tunneling to adjust the threshold voltage.

  FIG. 29A shows bias conditions in the case where the threshold voltage of the nonvolatile memory element 70 is changed in the positive direction. FIG. 29B shows bias conditions in the case where the threshold voltage of the nonvolatile memory element 70 is changed in the negative direction. Under these bias conditions, the threshold voltage of the nonvolatile memory element 70 is controlled by applying a control pulse to the control gate.

  When changing the threshold voltage in the positive direction, as shown in FIG. 29A, the voltage Vpp is applied to the control gate terminal, the source terminal is grounded, and the drain terminal is in a floating state. Thereby, electrons are injected into the floating gate of the nonvolatile memory element 70 by FN tunneling, and the threshold voltage Vth of the nonvolatile memory element 70 is increased. The voltage Vpp is a voltage necessary for performing FN tunneling in the tunnel oxide film of the nonvolatile memory element 70.

  When the threshold voltage is changed in the positive direction, as shown in FIG. 29B, the control gate terminal is grounded, the voltage Vpp is applied to the source terminal, and the drain terminal is in a floating state. Thus, in the nonvolatile memory element 70, electrons are emitted from the floating gate by FN tunneling, and the threshold voltage Vth of the nonvolatile memory element 70 decreases. By combining the operations described in FIGS. 29A and 29B, the threshold voltage of the nonvolatile memory element 70 can be adjusted to a predetermined voltage. As described above, if the threshold voltages of the first write MOS transistor M1w and the second write MOS transistor M2w are adjusted, the threshold voltages of the first output MOS transistor M1r and the second output MOS transistor M2r are similarly adjusted. .

  FIG. 30 shows an example of the operation of the voltage detector 100 in the reference voltage setting mode. The voltage detector 100 of this example shows a state in which the writing to the second write MOS transistor M2w of the first reference voltage generation unit 21 is performed. The configuration used in this example is mainly indicated by thick lines.

  The mode selection unit 10 applies a control pulse to the second write MOS transistor M2 w of the first reference voltage generation unit 21. The mode selection unit 10 causes the voltage selection unit 40 to select the VREF terminal. In this case, no voltage is externally input to the VREF terminal. The current mirror 61 generates an adjustment current Iref smaller than the external current IREF based on the external current IREF, and outputs the adjustment current Iref to the first reference voltage generation unit 21. For example, the current mirror 61 generates the adjustment current Iref that is 1 / n times (where n> 1) the external current IREF. Thereby, the minute adjustment current Iref can be generated with high accuracy. When the voltage detector 100 does not have the current mirror 61, a minute adjustment current Iref may be input from the outside of the voltage detector 100.

  The amplifier circuit 62 receives the output of the first reference voltage generation unit 21 via the voltage selection unit 40, and outputs a signal obtained by amplifying the output to the VMON terminal. The amplified signal output from the amplifier circuit 62 is input to the voltmeter 80. This improves the signal-to-noise ratio in the measuring device connected to the VMON terminal. The voltmeter 80 detects the voltage of the amplification signal output from the amplifier circuit 62. Also, a voltmeter 80 may be provided outside the voltage detector 100. The mode selection unit 10 applies a control pulse to the second write MOS transistor M2 w of the first reference voltage generation unit 21 such that the voltage output from the amplifier circuit 62 becomes a voltage corresponding to the reference voltage to be set. .

  In the first reference voltage generation unit 21 of this example, the reference voltage VrefH is set using adjustment sequences (1) to (5) described later. Also, when the reference voltage VrefL is set in the second reference voltage generation unit 22, the same configuration as that of the first reference voltage generation unit 21 of this example is set.

  FIG. 31 shows a write operation to the second write MOS transistor M2w. The vertical axis indicates the monitor voltage [V], and the horizontal axis indicates time t. A control pulse is input from the mode selection unit 10 to the second write MOS transistor M2w.

  First, a first control pulse is applied to the control gate of the second write MOS transistor M2w to set the state of the charge accumulated in the floating gate of the second write MOS transistor M2w to a predetermined initial state. . Thereby, the monitor voltage Vmon which monitored the voltage which the reference voltage generation part 20 outputs increases. The control pulse is applied to the control gate of the second write MOS transistor M2w until the monitor voltage Vmon of the reference voltage generation unit 20 becomes sufficiently larger than the end voltage to be set.

  Next, a second control pulse is applied to the control gate of the second write MOS transistor M2w to control the state of charge of the floating gate of the second write MOS transistor M2w. The second control pulse is a pulse whose positive / negative polarity is opposite to that of the first control pulse. In this example, the monitor voltage Vmon of the reference voltage generation unit 20 is lowered by applying the second control pulse. The second control pulse is applied such that the monitor voltage Vmon of the reference voltage generation unit 20 gradually approaches the end voltage.

  The control pulse stores charge corresponding to the intensity of the pulse in the floating gate. For example, when the pulse width is wide or when the pulse voltage is large, the amount of fluctuation of charge stored by the floating gate per pulse is large. If the amount of charge fluctuation is large, the monitor voltage is likely to greatly exceed the termination voltage. Therefore, as the monitor voltage Vmon approaches the end voltage, the mode selection unit 10 adjusts at least one of the pulse width or the voltage of the second control pulse to reduce the intensity of the second control pulse. The mode selection unit 10 may input the first control pulse to the control gate when the second control pulse is applied and the monitor voltage Vmon becomes smaller than the end voltage. Thus, the monitor voltage Vmon can be brought close to the end voltage. Such processing is continued until the difference between the monitor voltage Vmon and the end voltage is in the allowable range.

  The mode selection unit 10 is connected to the VPP terminal, the DATA terminal, the SCLK terminal, and the PULSE terminal. The mode selection unit 10 controls the voltage of the control pulse according to the voltage input from the VPP terminal. In addition, the mode selection unit 10 controls the pulse width of the control pulse by the periodic signal input from the PULSE terminal. The SCLK terminal outputs a clock signal serving as an operation clock of the mode selection unit 10 to the mode selection unit 10. The DATA terminal outputs a data signal related to the test mode to the mode selection unit 10.

  FIG. 32 shows an example of the operation of the voltage detector 100 in the reference voltage setting mode. The voltage detector 100 in the present example shows a state in which the first reference voltage generation unit 21 writes data to the first write MOS transistor M1 w. The configuration used in this example is indicated by a bold line.

  Writing to the first write MOS transistor M1w is performed when writing to the second write MOS transistor M2w shown in FIG. 30 and in that the output of the current mirror 61 is not input to the first reference voltage generation unit 21. It is different. The other configuration is basically the same as that of FIG.

  FIG. 33 shows a write operation to the first write MOS transistor M1w. The vertical axis indicates the monitor voltage [V], and the horizontal axis indicates time t. A control pulse is input from the mode selection unit 10 to the first write MOS transistor M1 w.

  First, a first control pulse is applied to the control gate of the first write MOS transistor M1w to set the state of the charge accumulated in the floating gate of the first write MOS transistor M1w to a predetermined initial state. . As a result, the monitor voltage Vmon of the reference voltage generation unit 20 decreases. The first control pulse is applied to the control gate of the first write MOS transistor M1w until the monitor voltage Vmon of the reference voltage generation unit 20 becomes sufficiently smaller than the end voltage.

  Next, a second control pulse is applied to the control gate of the first write MOS transistor M1w to control the state of the charge accumulated in the floating gate of the first write MOS transistor M1w. The second control pulse is a pulse whose positive / negative polarity is opposite to that of the first control pulse. In this example, the monitor voltage Vmon of the reference voltage generation unit 20 is increased by applying the second control pulse. The second control pulse is adjusted so that the monitor voltage Vmon of the reference voltage generation unit 20 gradually approaches the end voltage.

  Also in the case of the write operation to the first write MOS transistor M1w, the mode selection unit 10 adjusts at least one of the pulse width or the voltage of the second control pulse as the monitor voltage Vmon approaches the end voltage, Reduce the strength of the control pulse. The reference voltage setting mode ends when the monitor voltage Vmon substantially matches the end voltage. The fact that the monitor voltage Vmon substantially matches the end voltage does not necessarily have to completely match, but may be considered to substantially match depending on the use situation.

FIG. 34 shows an example of the circuit configuration of the reference voltage generation unit 20 according to the present embodiment. Each configuration is the same as the circuit configuration of reference voltage generation unit 20 shown in FIG. When the reference voltage generation unit 20 outputs the reference voltage Vref in the actual operation mode, the switches are controlled as follows as shown in FIG.
SWl: Vss
SW2: Vss
SW3, SW4: OPEN
SW5, SW7: SHORT (connection)
SW9, SW10: Any

  The reference voltage generation unit 20 uses the first MOS transistors M1 w and r set to the depletion state and the second MOS transistors M2 w and r set to the enhancement state in a state where the switches are controlled as in this example. A reference voltage Vref is generated.

The reference voltage Vref output from the reference voltage generation unit 20 is adjusted using adjustment sequences (1) to (5).
<Adjustment sequence (1)>
FIG. 35 shows an example of the circuit configuration of the reference voltage generation unit 20. The mode selection unit 10 applies a control pulse to the control gate of the first MOS transistor M1w to set the state of the charge stored by the floating gate of the first MOS transistor M1w, r to the reference state. In this example, the threshold voltage of the first MOS transistors M1 w and r is controlled to be sufficiently higher than the reference voltage Vref to be set in the reference voltage generation unit 20. In the adjustment sequence (1), the switches are controlled as follows. As a result, no current flows from the first MOS transistor M1 to the second MOS transistor M2.
SWl: Vss
SW2: Vss
SW3: SHORT
SW4: OPEN
SW5, SW7: OPEN
SW9: Vpp
SW10: Optional

<Adjustment sequence (2)>
FIG. 36 shows an example of the circuit configuration of the reference voltage generation unit 20. The mode selection unit 10 sets the second MOS transistors M2 w and r to the initial state described in FIG. 31 by applying a first control pulse to the control gate of the second write MOS transistor M2 w. In the adjustment sequence (2), the switches are controlled as follows.
SWl: Vss
SW2: Vss
SW3: OPEN
SW4: SHORT
SW5, SW7: OPEN
SW9: Optional SW10: Vpp

<Confirmation sequence>
The state of the second MOS transistors M2w and r in the adjustment sequence (2) and the adjustment sequence (3) described later can be determined by monitoring the reference voltage Vref output by the reference voltage generation unit 20.
FIG. 37 shows an example of the circuit configuration of the reference voltage generation unit 20. The voltage detector 100 of the present example checks the reference voltage Vref output by the reference voltage generation unit 20 by supplying the adjustment current Iref to the second output MOS transistor M2r. In the verification sequence, the switches are controlled as follows.
SWl, SW2: Vss
SW3, SW4, SW5: OPEN
SW7: SHORT
SW9, SW10: Any

  FIG. 38 shows the amount of change of the threshold voltage Vth with respect to the writing time of the first control pulse in the adjustment sequence (2). The vertical axis represents the threshold voltage Vth of the second MOS transistor M2w, r, and the horizontal axis represents the write time of the first control pulse for the second MOS transistor M2w, r.

  The threshold voltage Vth of the second MOS transistor M2 w, r changes with time as shown in FIG. 38 as the write time of the first control pulse increases. The mode selection unit 10 generates the first control pulse until the initial state described in FIG. 31 is reached.

<Adjustment sequence (3)>
FIG. 39 illustrates an example of the circuit configuration of the reference voltage generation unit 20. Mode selection unit 10 applies a second control pulse to the control gate of second write MOS transistor M2w, thereby terminating reference voltage Vref output from reference voltage generation unit 20 to a predetermined level, as described in FIG. Close to the voltage. In the adjustment sequence (3), the second control pulse is applied while supplying the adjustment current Iref to the second output MOS transistor M2r. In the adjustment sequence (3), the switches are controlled as follows. If the reference voltage Vref is lower than a predetermined voltage, the first control pulse may be applied to the control gate of the second write MOS transistor M2w to increase the reference voltage Vref.
SWl: Vss
SW2: Vpp
SW3: OPEN
SW4: SHORT
SW5, SW7: OPEN
SW9: Optional SW10: Vss

  FIG. 40 shows changes in threshold voltage Vth in adjustment sequences (2) and (3). The vertical axis represents the threshold voltage Vth of the second MOS transistors M2w and r, and the horizontal axis represents time.

  In the configuration according to FIG. 39, the threshold voltage Vth of the second MOS transistors M2w and r decreases in accordance with the write time of the second control pulse as shown in the adjustment sequence (3) in FIG. By adjusting the write time, the threshold voltage Vth of the second MOS transistors M2w and r is adjusted to the reference voltage Vref.

  FIG. 41 shows a change of the threshold voltage Vth when the adjustment sequence (3) and the confirmation sequence are alternately performed. In the confirmation sequence, the control voltage is not applied to the control gate of the second write MOS transistor M2w, so the reference voltage Vref does not change. The mode selection unit 10 may control the pulse width and voltage of the second control pulse generated in the adjustment sequence (3) according to the reference voltage Vref confirmed in the immediately preceding confirmation sequence.

  The adjustment sequence (3) ends when the reference voltage Vref output by the reference voltage generation unit 20 reaches a predetermined value. Thus, the adjustment of the second MOS transistor M2w, r is completed. Next, the first MOS transistor M1w, r is adjusted.

<Adjustment sequence (4)>
FIG. 42 shows an example of the circuit configuration of the reference voltage generation unit 20. The mode selection unit 10 applies the first control pulse to the control gate of the first write MOS transistor M1 w to set the first MOS transistors M1 w and r in the initial state described in FIG. In the adjustment sequence (4), the switches are controlled as follows.
SWl: Vpp
SW2: Vss
SW3: SHORT
SW4, SW5, SW7: OPEN
SW9: Vss
SW10: Optional

<Adjustment sequence (5)>
FIG. 43 illustrates an example of a circuit configuration of the reference voltage generation unit 20. The mode selection unit 10 applies the second control pulse to the control gate of the first write MOS transistor M1w, thereby terminating the reference voltage Vref output from the reference voltage generation unit 20 to a predetermined level, as described in FIG. Close to the voltage. In the adjustment sequences (4) and (5), the adjustment current Iref is not applied from the outside. However, the first MOS transistors M1w and r generate a current corresponding to the adjustment current Iref. In the adjustment sequence (5), the switches are controlled as follows.
SWl: Vss
SW2: Vss
SW3: SHORT
SW4: OPEN
SW5, SW7: OPEN
SW9: Vpp
SW10: Optional

  FIG. 44 shows changes in threshold voltage Vth in adjustment sequences (4) and (5). The vertical axis represents the threshold voltage Vth of the first MOS transistors M1 w and r, and the horizontal axis represents time. In the adjustment sequence (4), the threshold voltage Vth of the first MOS transistors M1 w and r decreases with time as shown in FIG. 44 as the write time of the first control pulse increases. The mode selection unit 10 generates the first control pulse until the initial state described in FIG. 33 is reached.

  In the adjustment sequence (5), the threshold voltage Vth of the first MOS transistors M1 w and r increases in accordance with the write time of the second control pulse. By adjusting the write time, the threshold voltage Vth of the first MOS transistors M1 w and r is adjusted to be the reference voltage Vref. In the confirmation sequence, the control voltage is not applied to the control gate of the first write MOS transistor M1w, so the reference voltage Vref does not change. The mode selection unit 10 may control the pulse width and voltage of the second control pulse generated in the adjustment sequence (5) in accordance with the reference voltage Vref confirmed in the immediately preceding confirmation sequence.

  The adjustment sequence (5) ends when the reference voltage Vref output by the reference voltage generation unit 20 reaches a predetermined value. Thus, the adjustment of the first MOS transistors M1 w and r is completed, and the adjustment of the reference voltage generation unit 20 is completed. When the reference voltage Vref in the adjustment sequences (4) and (5) is confirmed, each switch may be controlled in the same manner as in actual operation. For example, each switch is controlled similarly to the example shown in FIG.

  FIG. 45 shows an example of connection of the current mirror 61. As shown in FIG. The mode selection unit 10 of this example includes a write circuit 15 that operates as a gate control unit. The write circuit 15 controls the switches SW1 to SW10 described with reference to FIGS. 26 to 44 to control the control gates of the first write MOS transistor M1 w and the second write MOS transistor M2 w of the reference voltage generation unit 20. Input control pulse to.

  The current mirror 61 generates the adjustment current Iref smaller than the external current IREF based on the external current IREF input from the outside of the voltage detector 100 in the reference voltage setting mode. For example, based on the external current IREF input from the outside of the voltage detector 100, the current mirror 61 generates an adjustment current Iref of 1 / n. The current mirror 61 of this example is connected to an external terminal common to the first output MOS transistor M1r. The current mirror 61 generates a minute adjustment current Iref smaller than the external current IREF based on the external current IREF input from the external terminal.

  Further, a switch SW0 is provided between the current mirror 61 and the output terminal of the reference voltage generation unit 20. The mode selection unit 10 controls the switch SW0 according to each adjustment sequence. For example, in the adjustment sequence (3), the mode selection unit 10 turns on the switch SW0. Further, in the adjustment sequences (4) and (5), the mode selection unit 10 turns off the switch SW0 to cut off the adjustment current Iref flowing to the second output MOS transistor M2r.

  In the setting method of the reference voltage Vref of this example, the second output in the adjustment sequence (3) with the charge accumulated in the floating gate of the first MOS transistor M1 w, r in the adjustment sequence (1) set to the reference state The adjustment current Iref is input to the MOS transistor M2r. Therefore, when the adjustment current Iref flows in the second output MOS transistor M2r, no current flows from the first output MOS transistor M1r to the second output MOS transistor M2r. Therefore, the setting accuracy of the second MOS transistors M2 w and r is improved. Therefore, it is not necessary to provide a switch for blocking the influence of the charge stored in the depletion type MOS transistor M1r at the drain end of the first output MOS transistor M1r.

  FIG. 46 shows an example of the configuration of the voltage detector 100 in the actual operation mode. The voltage detector 100 uses the VIN terminal, the OUT terminal, and the GND terminal when the mode selection unit 10 selects the actual operation mode. The voltage detector 100 detects whether the voltage input from the VIN terminal is equal to or higher than a predetermined detection voltage, and outputs the voltage to the OUT terminal.

  The first reference voltage generation unit 21 outputs a reference voltage VrefH. Further, the second reference voltage generation unit 22 outputs the reference voltage VrefL. The reference voltage (VrefH, VrefL) and the input voltage Vin are input to the comparator 50. The comparator 50 outputs a signal corresponding to the reference voltage (VrefH, VrefL) and the input voltage Vin to the OUT terminal.

  The voltage selection unit 40 selects the reference voltage (VrefH, VrefL) according to the output of the comparator 50. The voltage selection unit 40 inputs the selected reference voltage (VrefH, VrefL) to the comparator 50. Thus, the detection voltage Vdet of the CMOS inverter 51 is changed in accordance with the output of the comparator 50 in order to perform hysteresis operation.

  FIG. 47 shows another connection example of the first MOS transistor M1 and the second MOS transistor M2 in the reference voltage generation unit 20. The first MOS transistor M1 and the second MOS transistor M2 of FIG. 47 (a) are elements similar to the first MOS transistor M1 and the second MOS transistor M2 of FIG. 23 (a). The first MOS transistor M1 and the second MOS transistor M2 in FIG. 47 (b) are non-volatile memory elements similar to the first MOS transistor M1 and the second MOS transistor M2 in FIG. 23 (b).

  In this example, the gate of the first MOS transistor M1 is connected to the source terminal of the second MOS transistor M2. The source of the first MOS transistor M1, the drain of the second MOS transistor M2, and the gate of the second MOS transistor M2 are connected to each other. The reference voltage generation unit 20 outputs the reference voltage Vref from the connection point.

  In the configuration shown in FIG. 26, the first MOS transistor M1 and the second MOS transistor M2 on the write side and the output side may have the same connection as the first MOS transistor M1 and the second MOS transistor M2 in FIG. Even in this case, it is possible to set the first MOS transistor M1 and the second MOS transistor M2 on the write side and the output side in the same manner as the method described in the specification of this application.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It is apparent to those skilled in the art that various changes or modifications can be added to the above embodiment. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the present invention.

  The execution order of each process such as operations, procedures, steps, and steps in the apparatuses, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly “before”, “preceding” It is to be noted that “it is not explicitly stated as“ etc. ”and can be realized in any order as long as the output of the previous process is not used in the later process. With regard to the flow of operations in the claims, the specification and the drawings, even if it is described using “first,” “next,” etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  DESCRIPTION OF SYMBOLS 10 ... Mode selection part, 15 ... Writing circuit, 20 ... Reference voltage generation part, 21 ... 1st reference voltage generation part, 22 ... 2nd reference voltage generation part, 23 ... REFB circuit 40: voltage selection unit 50: comparator 51: CMOS inverter 52: output circuit 53: constant current circuit 54: constant current source 55: Control logic 56 Inverter circuit 60 Test circuit 61 Current mirror 62 Amplifier circuit 70 Non-volatile memory element 71 Substrate 72 Source region 73: drain region 74: tunnel oxide film 75: floating gate 76: insulating film 77: control gate 80: voltmeter 100: 100・ Voltage detector, 500 ... Comparator

Claims (2)

A transistor of a first conductivity type in which an input voltage is input to a source terminal and a reference voltage is input to a gate terminal;
A constant current circuit electrically connected to the drain terminal of the first conductivity type transistor;
An output voltage based on the input voltage and the reference voltage is output from a connection node between the transistor of the first conductivity type and the constant current circuit,
The constant current circuit includes a transistor of a second conductivity type,
The drain terminal of the transistor of the second conductivity type is electrically connected to the drain terminal of the transistor of the first conductivity type,
The transistor of the second conductivity type has a floating gate,
The constant current circuit is
A first output MOS transistor having a gate terminal electrically connected to the gate terminal of the transistor of the second conductivity type, and a floating gate electrically connected to the floating gate of the transistor of the second conductivity type; ,
And a first write MOS transistor having a floating gate electrically connected to the floating gate of the first output MOS transistor and the second conductivity type transistor.
The gate terminal of the first output MOS transistor is electrically connected to the drain terminal of the first output MOS transistor.
The first write MOS transistor is a voltage detector having a tunnel oxide film through which charges injected to the floating gate tunnel. The voltage at the drain terminal of the first output MOS transistor, a voltage detector according to a low claim 1 than the reference voltage.

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