JPS63150959A - Eprom device - Google Patents

Abstract

PURPOSE:To improve writing/reading characteristics of an EPROM device by decoding by an address signal, and switching by a write control signal to transmit the output to the gate of a write only bit line switch transistor or the gate of a read only bit line switch transistor. CONSTITUTION:A write control signal PGM becomes a high level in a write mode, a P-channel transistor TP01, an N-channel transistor TN01 (TP11-TPn1, TN11-TNh1) become an ON state, and TP02, TN02 (TP12-TPn2, TN12-TNn2) become an OFF state. Accordingly, if X0 has a decoded output, the X0 does not drive a read bit switch transistor TR0, but drives only a write bit switch transistor TW0. A write control signal PGM becomes a low level in a read mode, TP01, TN01 (TP11-TPn1, TN11-TNn1) become an OFF state, and TP02, TN02 (TP23-TPn2, TN12-TNn2) become an ON state. Accordingly, if the X0 has, for example, a decoded output, the X0 does not drive the transistor TW0, but drives only the transistor TR0.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an EPROM device in a semiconductor device, and more particularly to an EPROM device comprising a memory cell having a write-only transistor and a read-only transistor.

[Conventional technology]

Conventionally, the decoder of this type of EPROM always drives both the word line of the write-only transistor and the word line of the read-only transistor regardless of the write mode or the read mode, and also drives the switch transistor of the write bit line and the read bit line. The configuration was such that both line switch transistors were driven. ° Figure 4 shows the conventional EPRO
It is a circuit diagram showing an example of M device. First, the operation in the data write mode will be explained. Memory cell M.

One of 0 to Mnl is specified by a row address and a column address. For example, assume that for the row address, the row decoder 1 outputs 1' to Yo of the word lines 101, and for the column address, the column decoder 2 outputs 1' to Xo at a specified bit line. As a result, Two of the switch transistors Two to Twn connected to the write bit line 102 is turned on. At this time, if data ``1'' is input to the data input terminal W, then the word line Y. Since the value is "1", the memory cell Moo is specified, and the floating gate type write transistor ROM in the memory cell Moo is set to ○.
N', and data '1' input from the data input terminal W is stored in the ROM1.

Next, in the case of reading, Y of word lines 101 is read. and Xo is the signal '1 to specify the bit line.
When this happens, the switch transistor Tao connected to the read bit line 103 is turned on, and the memory cell M is turned on. ROM2 of o is turned ON', and the data written in ROM+ is output to the data output terminal R through the switch transistor TRo via the floating gate of ROM and the floating gate of ROM2. In this way, the column decoder output always turns specified transistors of the write switch transistors Two to Twn and the read switch transistors TRo'TRQ into the ON' state, that is, both the write and read switch transistors are in the driven state. I have to.

[Problem that the invention seeks to solve]

The conventional EPROM address decoder described above is configured to drive the write bit line switch transistor and the read bit line switch transistor both in the write mode and in the read mode. There are drawbacks such as an increase in memory capacity, an increase in power consumption, an increase in write time and an access time, and an increase in chip size.

In contrast to the conventional EPROM decoder described above, the present invention is unique in that the same decoder drives only the write bit switch in the write mode and only drives the read bit switch in the read mode using the write signal or read signal. have content.

[Means for solving problems]

The decoder of the EPROM of the present invention includes a decoder section that performs decoding based on an address signal, and a write-in that determines whether the output of the decoder section is transmitted to the gate of the write-only bit line switch transistor or the read-only bit line switch transistor. It has an output switching circuit section that switches according to a control signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The memory cells MOO to Mno shown in the figure are arranged in a matrix, and each memory cell has an internal E P
It has ROM 1 and EPROM 2, each gate of which is connected to one of the word lines 101, which is the output of row decoder 1 for decoding row addresses.

Further, the respective 70-ting gates are connected to each other, and furthermore, the respective sources are grounded.

The drains of the EP ROM 1 are connected to write bit lines 107 on a column-by-column basis, and the drains of the EP ROM 2 are connected on a column-by-column basis to read bit lines 103. The write bit line of each column is connected to the source of one of the write pin I switch 1 to the transistor T Wfl whose drain is connected to the data input terminal W. The read bit line of each column includes read bit switch transistors TRo to T whose train is connected to the data output terminal R.
One source is connected to any one of FL, .

Also, write bit switch transistor T wo
The gate of (T ws ~ T Wn ) is connected to the drain of P channel transistor Tpo1 (Tp++ ~ Tpoin) and the drain of N channel transistor T Not (T
Nth to TNnl) sources. P channel I transistor Tpo+ (Tp++~TPNI
> source and N-channel transistor TNOI
The drains of (TNII-T01) are connected to the output Xo (Xl-X, .) of the column decoder 2 that decodes the column address. Similarly, the gate of the read bit line switch transistor T RO (T FLI to TRn) is connected to the P channel transistor T po2 (T p
12~TPa2) and the drain of N-channel transistor TNO2 (TN12~TNI, 2)
connected to the source. The source of the P-channel transistor TPO2 (TP12-TPn2) and the source of the N-channel transistor TNO2 (TN12-TPn2)
The drain of TNo.2) is X of column decoder 2. (X+～
X,). P channel transistor T
The gate of po1 (Tptt~TP-1> and the N-channel transistor TNO2 (T N12~T N112
> is connected to the output of inverter (INV) 3, and the gate of N-channel transistor TNOI (TNII~
TN-1) gate and P-channel transistor TPO
The gate of TPI2 (TPI2~'r, n2) is connected to the input side of INV3, that is, the write control signal input terminal PGM.

In the circuit described above, the operation in write mode will be explained. Since it is write mode, write control signal PG
M becomes Higb level and TPol.

TNOI (TPth~Tpal・TNN13~
TNIII is in ON state, TPO2+ TNO
2 (TPI2~T Pa 2 + T N I 2~T
No. 2) is in the OFF state. Therefore, for example, if Xo has a decode output, Xo will not drive the read bit switch transistor TRo, but will only drive the write bit switch transistor Two.

Next, the read mode will be explained. Since it is the read mode, the write control signal PGM becomes Low level, and Tpo2. TNOI (TPII ~'r,
I1. ．． 'r□1~TNIII) is OFF state, TPo
2°T NO2 (TP12 to TPI121TNI2ゝTNn2) is in the ON state. Therefore, for example, if Xo has a decode output, it is X. does not drive the write bit switch transistor Two, but drives only the read bit switch transistor TRo.

Figure 2 shows the circuit of the present invention under the condition that the sizes of the transistors constituting the decoder 2 are equal to each other, and the number of bits - Tp when the bit line is driven by the conventional circuit shown in Figure 4.
d (propagation delay time) characteristics. As shown in FIG. 2, the bit number-Tpd characteristic is improved by using the circuit of the present invention.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. Transistors Tpo1 to TPf11 in FIG. TPo2~TP
112+TNO1ゝT Nll 1, T N12~
TNo2 is the gate Gwo~Gw,,,GRo~
It is the same as in Figure 1 except that it has been replaced with GRfl. Gate Gw.

~G Wn I G Ro ~ G R11 are two-man power AND gate circuits, respectively. The operation of this embodiment is exactly the same as the embodiment shown in FIG.

That is, to explain the operation of the write mode using the above circuit, in the write mode, PGM is at the High level, so the output of GR, -'-G Rn becomes Low level regardless of the output state of the decoder 3, and TR8 ~T
Rn is in the OFF state, and G wo to G Wn transmit the output state of the decoder 3 to the gates of Two to Twti.

Next, the read mode will be explained. In read mode, PGM is low level and Gwo~Gw
The output of ll becomes Low level regardless of the output state of the decoder 3, TR8 to TRn become OFF state, and GWo
~Gwfl transmits the output state of the decoder 3 to the gates of TR8~TRn.

〔Effect of the invention〕

As explained above, in the present invention, the same decoder drives only the write bit switch transistor in the write mode by the write signal or the read signal,
By driving only the read bit switch transistor during read mode, the transistor size of the above decoder can be reduced, reducing power consumption and improving write characteristics.

This has the effect of improving read characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
Figure 3 is a circuit diagram of the second embodiment of the present invention, and Figure 4 is a conventional circuit diagram. be. 1 is row decoder, 2 is column decoder, 3 is INV, Moo
~Man is a memory cell, ROM+, 2 is EPROM
, T wo ~ T wn, T Ro ~ Th are N-channel transistors, TP, , ~ T Pa I +
TPO2'T Pa2 is a P channel transistor, T
,,,~T Nn l +TNo2~TN,,2 is N
Each channel transistor is shown. "￥'i" No. 10 10,000 3 times

Claims (1)

[Claims] In the memory cell, there is a write transistor whose source is grounded and whose drain is connected to a write bit line, and whose source is grounded and whose drain is connected to a read bit line, and whose floating gate and control gate are connected to the floating gate and control gate of the write transistor, respectively. In an EPROM having a connected read transistor and a write bit switch and a read bit switch, the EPROM has a circuit that drives only the write bit switch during writing, and drives only the read bit switch during read. An EPROM device characterized by: