JP6402461B2 - Multi-phase power supply - Google Patents

Description

  The present invention relates to a multiphase power supply apparatus having a plurality of DC / DC converters connected in parallel.

  As mobile terminal devices have higher performance and higher functionality, they are required to be smaller and more power is required. For this reason, a DC / DC converter mounted on a portable terminal device is required to be smaller, handle a large amount of power, and be highly efficient.

  As one solution to this problem, a multi-phase power supply device that operates a plurality of DC / DC converters in parallel has already been known. By connecting multiple converters in parallel and shifting the conversion (switching) timing of these multiple converters at equal intervals, and adding the outputs together, the ripple can be reduced, so the passive filter that forms the filter required for the output There is an advantage that it is easy to downsize the element.

  In addition, the parallel generation makes it possible to distribute heat generation due to loss to each DC / DC converter, which reduces the requirement for heat dissipation performance of each DC / DC converter and facilitates downsizing. is there. Furthermore, when driving a light load (various circuit units with low current consumption), it is possible to improve the power conversion efficiency as a whole by stopping some DC / DC converters. There is an advantage that high efficiency can be obtained with a wide range of loads.

  As a specific example of this multi-phase power supply device, for example, the one disclosed in Patent Document 1 is known.

  The multiphase power supply device described in Patent Document 1 includes a current detection circuit that detects a total current output from an output terminal, and the number of DC / DC converters that are operated according to the total current detected by the current detection circuit. And a control circuit for controlling.

  In such a multi-phase power supply device, the control circuit performs arithmetic processing to obtain an appropriate number of DC / DC converters to be driven based on the total current.

  For this reason, when all of the inactive DC / DC converters are activated when the load fluctuates greatly, all the inactive DCs are detected after the current detection circuit detects a large fluctuation for the arithmetic processing. / It takes a long time to drive the DC converter. For this reason, there is a problem that the output voltage is lowered and the original output voltage is not immediately restored.

  It is an object of the present invention to provide a multi-phase power supply apparatus that can start all of the DC / DC converters that are in rest in a short time when the output voltage fluctuates greatly.

The invention according to claim 1 is provided with a plurality of DC / DC converters connected in parallel, and the number of DC / DC converters operating according to the size of the load is changed to apply a constant output voltage to the load. A phase power supply,
Current detecting means for detecting an output current flowing through the load;
Based on the detected current detected by the current detection means, the number of DC / DC converters to be driven is determined, and a first start signal for starting a DC / DC converter that is inactive according to this determination is output. An output system;
When the output voltage falls below set voltage, a second start signal output line for outputting a second start signal for starting the DC / DC converter during pauses,
A logic circuit that operates asynchronously with a reference clock input between the DC / DC converters in the plurality of DC / DC converters;
In the logic circuit, when the output voltage is equal to or lower than a set voltage, the second start signal output system is shorter than the time from when the detected current becomes larger than a threshold until the first start signal is output. The second activation signal is output in time.

  According to the present invention, when the output voltage fluctuates greatly, all of the inactive DC / DC converters can be activated almost simultaneously with the detection of the fluctuation.

It is the block diagram which showed the structure of the Example of the multiphase power supply device which concerns on this invention. FIG. 2 is a block diagram showing a partial configuration of a DC / DC converter of the multiphase power supply device shown in FIG. 1. It is a flowchart which shows operation | movement of the control circuit of a DC / DC converter. FIG. 2 is a block diagram specifically showing a control circuit showing a configuration of another part of the DC / DC converter of the multiphase power supply device shown in FIG. 1. FIG. 4 is a circuit diagram showing a configuration of part of a control circuit of the DC / DC converter shown in FIG. 3. FIG. 4 is a flowchart showing the operation of the control circuit shown in FIG. 3. 5 is a time chart showing the relationship between fluctuations in output voltage, output signals of an error detection circuit, and operation signals. It is the time chart which showed the operation | movement of the DC / DC converter when load changes suddenly. It is the time chart which showed the operation | movement of the DC / DC converter when load changes gently. It is the block diagram which showed the structure of the multiphase power supply device of 2nd Example. It is the block diagram which showed the structure of the multiphase power supply device of 2nd Example.

  Hereinafter, an embodiment as an embodiment of a multi-phase power supply device according to the present invention will be described with reference to the drawings.

[First embodiment]
FIG. 1 shows a multiphase power supply apparatus 10 including a plurality of DC / DC converters 1 to 4 connected in parallel.

  The multi-phase power supply device 10 includes inductors L1 to L4 connected to the output terminals 1a to 4a of the DC / DC converters 1 to 4, and a capacitor C0 connected to the output terminal 10A. 6 is a load connected to the output terminal 10A.

  Each DC / DC converter 1 to 4 has terminals 1b to 1f, 2b to 2f, 3b to 3f, and 4b to 4f. The terminal 1b of the DC / DC converter (master DC / DC converter) 1 is connected to the voltage source Vc of the input voltage Vin, and the DC / DC converter 1 functions as a master converter that always operates. ing.

  The terminal 4f of the DC / DC converter 4 is grounded, and the terminals 1f to 3f of the DC / DC converters 1 to 3 are connected to terminals 2b to 4b of the DC / DC converters (slave DC / DC converters) 2 to 4, respectively. . The terminals 1c to 4c of the DC / DC converters 1 to 4 are connected to each other, and the terminals 1d to 4d are also connected to each other. Terminals 1e to 4e of the DC / DC converters 1 to 4 are connected to a voltage source Vc. The DC / DC converters 2 to 4 function as slave converters.

  The master DC / DC converter 1 has a function of generating a reference clock and transmitting it to the slave DC / DC converters 2 to 4 and a function of transmitting a voltage signal Vsense indicating the output current Iout (see FIG. 3). Have. The slave DC / DC converters 2 to 4 have a function of receiving a clock from the master DC / DC converter 1 and executing processing such as a switching operation based on the clock. The DC / DC converters 2 to 4 for the slave use the voltage signal Vsense1 (Vsense) indicating the output current Iout1 (Iout) from the DC / DC converter 1 for the master and the voltage signal Vsense2 indicating the output current Iout2 to 4 itself. 4 is compared. By this comparison, the output currents Iout2 to Iout4 are controlled so as to have the same output current Iout as that of the master DC / DC converter 1.

  The master DC / DC converter 1 transmits the voltage signal Vsense indicating the reference clock and the output current Iout to the other slave DC / DC converters 2 to 4 from the terminal 1d and the terminal 1c, respectively.

  The multi-phase power supply device 10 is used for a slave having a master DC / DC converter 1 that always generates an output current, an operation state that generates an output current, and a dormant state that does not generate an output current. DC / DC converters 2-4.

  The DC / DC converters 1 to 4 obtain the input voltage Vin from a common DC voltage source Vc, and send the output currents Iout1 to Iout4 (see FIG. 3) to the capacitor C0 via the inductors L1 to L4. The inductors L1 to L4 and the capacitor C0 constitute a filter, and the voltage smoothed by the filter is supplied to the load 6 as the output voltage Vout of the multiphase power supply device 10. Each of the DC / DC converters 1 to 4 internally monitors the magnitudes of the output currents Iout1 to Iout4 and the output voltage Vout.

  The DC / DC converter 1 sends a voltage signal Vsense1 (Vsense) indicating the magnitude of the output current of the DC / DC converter 1 to the other DC / DC converters 2-4. The DC / DC converters 2 to 4 operate so that their output currents Iout2 to Iout4 are equal to the output current Iout1 of the master DC / DC converter 1, whereby the outputs of all the DC / DC converters 1 to 4 are output. The currents Iout1 to Iout4 are equal.

  FIG. 2 shows a part of the DC / DC converters 1 to 4, and this part is a block diagram showing a circuit part for performing detection and transmission processing of the number of operating DC / DC converters. 2, each of the DC / DC converters 1 to 4 includes a control circuit 32, a current / voltage converter 33, an A / D converter 34, a variable current source 35, a master determination circuit 36, and a clock PWM modulation. A circuit 37 and a clock PWM demodulation circuit 38 are provided.

  The current / voltage converter 33 converts the current flowing from the terminal I sink into an analog voltage corresponding to the current, and the A / D converter 34 converts the converted analog voltage into a digital value and outputs it to the control circuit 32B. To do.

  When determining that the master determination circuit 36 is the master, the control circuit 32B detects the number of operation converters, PWM modulates the clock in accordance with the detected number of operation converters, and transmits it to the other control circuit 32B.

  The above detection and transmission process is performed according to the flowchart shown in FIG. 2A. Here, the description is omitted.

  Each control circuit 32 of the slave DC / DC converters 2 to 4 sets the current value set by the above processing in the variable current source 35 using the current value setting signal. The current having the set current value is supplied from the variable current source 35 to the other DC / DC converters 1 to 3 via the terminals 2b to 4b.

  The master determination circuit 36 determines that it is a master converter when the voltage source Vc of the input voltage Vin is connected to the terminals 1b to 4b, and determines that it is not a master converter when it is not connected. Here, since the voltage source Vc is connected to the terminal 1b of the DC / DC converter 1, it is determined that the master determination circuit 36 of the DC / DC converter 1 is the master.

  The clock PWM modulation circuit 37 of the DC / DC converter 1 determined as the master PWM-modulates the clock based on the information on the number of operations of the DC / DC converter detected by the control circuit 32 and outputs the result.

  The clock PWM demodulation circuit 38 of the slave DC / DC converters 2 to 4 obtains information on the number of operation converters by receiving the clock and performing PWM demodulation, and outputs the information to the control circuit 32. The clock PWM modulation circuit 37 operates as a master converter, and the clock PWM demodulation circuit 38 operates as a slave converter.

  FIG. 3 is a block diagram showing a configuration of another part of the DC / DC converters 1 to 4. In FIG. 3, DC / DC converters 1 to 4 include reference voltage sources E1 to E4, an error detection circuit 21, a triangular wave generation circuit 22, a comparator 23, a driver circuit 24, switch elements SW3 and SW4, and current sensors (current detection means). ) 15A-15D. The current sensors 15A to 15D are configured to output voltage signals Vsense1 to Vsense4 having voltages corresponding to the detected output current (detected current).

  The DC / DC converters 1 to 4 include an error detection circuit (fluctuation voltage detection means) 21, a target error voltage generation circuit 26, comparators 27 and 28, adders 29 and 31, an integrator 30, and comparators 11 to 13. , Switches 40 and 41 are provided.

The error detection circuit 21 outputs a first error voltage Verror1 corresponding to the difference between the reference voltage Vref2 and the output voltage Vout.
[Comparator 11]
The comparator (second comparison means) 11 compares the first error voltage Verror1 output from the error detection circuit 21 with a threshold voltage (set voltage) Vaim2 described later, and the first error voltage Verror1 is the threshold voltage Vaim2. Is exceeded, a comparison signal (second comparison signal) g3 is output. That is, the comparator 11 outputs the H level comparison signal g3 when the output voltage Vout becomes equal to or lower than the set voltage.
[Comparator 12]
The comparator 12 compares the voltage signal Vsense (Vsense1) with a threshold value Vthd, and outputs an H level comparison signal g1 when the voltage signal Vsense falls below the threshold value Vthd.
[Comparator 13]
The comparator (first comparison means) 13 compares the voltage signal Vsense and the threshold value Vthu (> Vthd), and outputs an H level comparison signal (first comparison signal) g2 when the voltage signal Vsense is equal to or higher than the threshold value Vthu. It is like that.

  In the master DC / DC converter 1, the switch 40 is turned on, the switch 41 is turned off, the voltage signal Vsense becomes equal to the voltage signal Vsense1, and the comparators 11 to 13, 28 do not operate.

In the DC / DC converters 2 to 4 for slaves, the switch 40 is turned off and the switch 41 is turned on. Therefore, the comparator 28 compares the voltage signal Vsense (the voltage signal Vsense1 of the DC / DC converter 1) with the voltage signals Vsense2 to Vsense4 inside the DC / DC converters 2 to 4, and outputs Verror3 obtained by amplifying the difference. To do.
[Target error voltage generator]
The target error voltage generation circuit 26 has a target error voltage Vaim that is a target value of the first error voltage Verror1 of the error detection circuit 21 (ideal value when the DC / DC converters 1 to 4 are in an operating state), and the target error voltage Vaim. A threshold voltage Vaim2 higher than the error voltage Vaim is generated. This threshold voltage Vaim2 corresponds to a set voltage described later.

The comparator 27 outputs a second error voltage Verror2 indicating an error between the first error voltage Verror1 and the target error voltage Vaim.
[Comparator 28]
The comparator 28 of the DC / DC converter 2 has a third error indicating an error between the voltage signal Vsense1 indicating the output current Iout1 of the DC / DC converter 1 and the voltage signal Vsense2 indicating the output current Iout2 of the DC / DC converter 2. A voltage Verror3 is generated. The same applies to the comparators 28 of the other DC / DC converters 3 and 4.
[Control circuit]
As shown in FIG. 4, the control circuit 32 includes a synchronous circuit (first activation signal output means: determination processing circuit) 50, an asynchronous circuit (second activation signal output means) 60, and an OR circuit 70. Yes.
[Synchronous circuit]
The synchronization circuit 50 is composed of a digital circuit that performs digital processing, and operates the DC / DC converters 2 to 4 based on the comparison signals g1 and g2 obtained by comparing the voltage signal Vsense1 with the threshold values Vthd and Vthu. Switch to. Note that the comparators 11 to 13 of the converter 1 are set not to operate.

  The synchronization circuit 50 of the DC / DC converter 2 determines that the power consumption of the load 6 has decreased when the voltage signal Vsense1 becomes less than a predetermined threshold Vthd when the DC / DC converter 2 is in an operating state. The DC / DC converter 2 is switched to a dormant state. That is, when the H level comparison signal g1 is output from the comparator 12, the synchronization circuit 50 switches the DC / DC converter 2 to a dormant state.

  The synchronization circuit 50 determines that the power consumption of the load 6 has increased when the voltage signal Vsense1 increases beyond a predetermined threshold value Vthu when the DC / DC converter 2 is in a dormant state. That is, when the voltage signal Vsense1 exceeds the threshold value Vthu and the comparator 13 outputs an H level comparison signal (up signal) g2, the synchronization circuit 50 outputs an H level activation signal (first activation signal) Ga. Then, the DC / DC converter 2 is switched to the operating state. Further, the synchronization circuit 50 outputs an H level hold signal g4 for a while after the activation signal Ga switches from the L level to the H level, and sets the hold signal g4 to the L level after a while.

  The synchronization circuit 50 controls on / off of each component in the DC / DC converter 2 depending on whether the DC / DC converter 2 is in an operating state or a dormant state.

  When the DC / DC converter 2 is in the operating state, only the comparator 27 and the target error voltage generation circuit 26 stop functioning, and the other components are operating. Therefore, at this time, the third error voltage Verror3 is integrated by the integrator 30 to become the voltage adjustment value Vadjust, and the sum of the reference voltage Vref1 and the voltage adjustment value Vadjust is input to the error detection circuit 21 as the reference voltage Vref2. . In other words, when the DC / DC converter 2 is in an operating state, the error detection circuit 21 uses the sum of the reference voltage Vref1 and the integrated third error voltage Verror3 as the reference voltage Vref2 of the error detection circuit 21. .

  On the other hand, when the DC / DC converter 2 is in an inactive state, only the error detection circuit 21, the comparator 27, the target error voltage generation circuit 26, the adders 29 and 31, the integrator 30, the reference voltage source E2, and the control circuit 32 only. Operates, and other components have stopped functioning. Accordingly, at this time, the second error voltage Verror2 is integrated by the integrator 30 to become the voltage adjustment value Vadjust, and the sum of the reference voltage Vref1 and the voltage adjustment value Vadjust is input to the error detection circuit 21 as the reference voltage Vref2. . In other words, when the DC / DC converter 2 is in an inactive state, the error detection circuit 21 uses the sum of the reference voltage Vref1 and the integrated second error voltage Verror2 as the reference voltage Vref2 of the error detection circuit 21. .

  The reference voltage Vref1 of the reference voltage source E2 of the DC / DC converter 2 should be originally identical with the reference voltage Vref1 of the reference voltage source E1 of the DC / DC converter 1, but may have an error due to manufacturing variations. There is sex. Therefore, when the converter 2 is in the operating state, the reference voltage Vref1 of the reference voltage source E1 is based on the third error voltage Verror3, and the output current Iout2 of the DC / DC converter 2 becomes the output current Iout1 of the DC / DC converter 1. Adjusted to be equal. When the DC / DC converters 1 and 2 operate for a long time and reach a steady state, the reference voltage Vref2 obtained by adjusting the reference voltage Vref1 of the reference voltage source E2 of the DC / DC converter 2 is the reference voltage of the DC / DC converter 1. It becomes equal to the reference voltage Vref1 of the voltage source E1. At this time, the magnitudes of the output currents Iout1 and Iout2 detected by the current sensors 15A and 15B of the DC / DC converters 1 and 2 are equal.

  However, the function of adjusting the error of the reference voltage Vref1 of the reference voltage source E2 in this way is based on the premise that the DC / DC converter 2 is in an operating state and generates an output current Iout2. Therefore, when the DC / DC converter 2 is in the resting state, the output current Iout2 becomes zero, so that it is impossible to correct the error of the reference voltage Vref1 of the reference voltage source E1 based on the third error voltage Verror3. For this reason, when the DC / DC converter 2 is in an inactive state, the reference voltage Vref1 of the reference voltage source E2 is adjusted based on the second error voltage Verror2 instead of the third error voltage Verror3.

  The DC / DC converters 2 to 4 are not only in the operating state but also in the resting state, the reference voltage Vref1 of the reference voltage source E2 of the converter 2 and the reference voltage Vref1 of the reference voltage source E1 of the converter 1 And adjust the error. By using the sum of the reference voltage Vref1 and the integrated second error voltage Verror2 as the reference voltage Vref2 of the error detection circuit 21 when the DC / DC converter 2 is in the resting state, the reference voltage Vref2 is It becomes equal to the reference voltage Vref1 of the source E1. The reason is described below.

  Even when the DC / DC converters 2 to 4 are in a resting state, the DC / DC converter 1 is always in an operating state so that the output voltage Vout of the multiphase power supply apparatus 10 becomes a reference voltage Vref1 that is a target value. The error detection circuit 21 is operating. Therefore, in a steady state, the error voltage Verror1 output from the error detection circuit 21 should be a value obtained by integrating the error (that is, substantially zero) between Vref1 and Vin. However, actually, the reference voltage Vref1 of the reference voltage sources E2 to E4 of the DC / DC converters 2 to 4 is different from the reference voltage Vref1 of the reference voltage source E1 of the converter 1. For this reason, the error voltage Verror1 gradually shifts from the ideal value when the DC / DC converters 2 to 4 are in the operating state.

  The error between the actual error voltage Verror1 and its ideal value increases with time due to the integration circuit included in the error detection circuit 21. Therefore, the target error voltage Vaim which is the target value of the error voltage Verror1 is generated by the target error voltage generation circuit 26, the target error voltage Vaim is compared with the actual error voltage Verror1 by the comparator 27, and the error becomes zero. So give feedback. Thereby, it can be expected that the reference voltage Vref2 is equal to the reference voltage Vref1 of the reference voltage source E1.

This is because the error voltage Verror1 is equal to the ideal value means that the DC / DC converter 1 and the DC / DC converters 2 to 4 perform the same operation and are input to the error detection circuit 21 of the DC / DC converters 1 to 4. This is because it means that the reference voltages Vref1 and Vref2 are equal to each other.
[Synchronous circuit processing]
The synchronization circuit 50 of the control circuit 32 performs a processing operation according to the flowchart shown in FIG. The flowchart shown in FIG. 5 will be briefly described.

  In step 1, the activation signal Ga (active) output from the control circuit 32, that is, the OR circuit 70 of the synchronization circuit 50, is set to H level.

  In step 2, it is determined whether or not the hold signal g4 is at the H level. If no, the process proceeds to step 6, and if yes, the process proceeds to step 3.

  In step 3, the numerical value set in an internal counter (not shown) is subtracted for each clock. The processing operations in steps 3 and 4 are repeated until the set numerical value becomes zero. That is, it waits until a predetermined time elapses.

  When the value of the internal counter becomes zero, the process proceeds to step 5, where the hold signal g4 is set to L level.

In step 6, the comparison signal g1 (is In step 7, it is determined whether or not the number of operating DC / DC converters 1 to 4 is equal to the number of orders obtained in the control control 32B. The Comparison signal g1 (is down) is at the H level, and when the number of drives of the DC / DC converters 1 to 4 is equal to the number of orders obtained by the control circuit 32, the activation signal Ga (active) is set to the L level (step 8). . In step 9, the hold signal g4 is set to H level.

  In step 9, the internal counter is set to a predetermined value. In step 10, the activation signal Ga (active) is set to L level.

  In step 11, it is determined whether or not the hold signal g4 is at the H level. If no, the process proceeds to step 15, and if yes, the process proceeds to step 12.

  In steps 12 and 13, while the hold signal g4 is at the H level, the value of the internal counter is decreased for each clock, and when the value becomes zero, that is, when a predetermined time elapses, the hold signal g4 is set to the L level. (Step 14).

In step 15, the comparison signal g2 (is up) is at the H level, and at step 16, it is determined whether or not the number of operating DC / DC converters 1 to 4 is one less than the order number obtained by the control circuit 32B. Comparison signal g2 (is up) is at the H level and the number of drives of the DC / DC converters 1 to 4 is one less than the order number obtained by the control circuit 32B, the activation signal Ga (active) is set to the H level (step 17). . In step 18, the hold signal g4 is set to H level, a predetermined value is set in the internal counter, and the process returns to step 1.

  This synchronization circuit 50 takes a long time (several tens of microseconds) to drive the number of DC / DC converters 2 to 4 corresponding to the size of the load 6 by performing the above processing operation. However, an appropriate number of DC / DC converters 2 to 4 corresponding to the size of the load 6 can be driven.

The comparator 13 and the synchronization circuit 50 constitute a first activation signal output system that outputs the first activation signal.
[Asynchronous circuit]
The asynchronous circuit 60 is composed of a digital logic circuit. The asynchronous circuit 60 includes an inverter 61 that inverts the hold signal g4 output from the synchronous circuit 50, and an AND circuit 62 that performs a logical product of the output signal g5 of the inverter 61 and the comparison signal g3 of the comparator 11. Has been.

  Since the output signal g5 of the inverter 61 becomes H level when the hold signal g4 output from the synchronization circuit 50 is L level, the asynchronous circuit 60 outputs the H level comparison signal g3 from the comparator 11. An H level activation signal Gb is output. The activation signal Gb is output via the OR circuit 70. In response to the start signal Gb output from the OR circuit 70, the inactive DC / DC converter 2 is started to start a switching operation.

  Since the asynchronous circuit 60 does not perform clock processing, when the H-level comparison signal g3 is output from the comparator 11, the asynchronous circuit 60 outputs the H-level start signal Gb in a short time (within several n seconds). . That is, the asynchronous circuit 60 outputs the H level start signal Gb almost simultaneously with the output of the H level comparison signal g3 from the comparator 11.

  The error detection circuit 21, the comparator 11, and the asynchronous circuit 60 constitute a second activation signal output system.

  Since the converters 3 and 4 are configured in the same manner as the converter 2, the description thereof is omitted.

[Operation]
Next, the operation of the multi-phase power supply device 10 configured as described above will be described with reference to the time charts shown in FIGS.

  It is assumed that the master DC / DC converter 1 is operating and the slave DC / DC converters 2 to 4 are inactive. Since the error detection circuit 21 of the DC / DC converter 2 in operation is operating, the sum of the reference voltage Vref1 of the reference voltage source E2 and the integrated second error voltage Verror2 is the reference voltage of the error detection circuit 21. Vref2.

  Now, the output voltage Vout of the multiphase power supply apparatus 10 fluctuates (decreases) because the load 6 slightly fluctuates from the light load to the heavy load at time t1. Due to this variation, the output voltage Vout immediately returns to the original voltage due to the action of the voltage control system of the DC / DC converter 1 (the error detection circuit 21, the comparator 23, the switching elements SW3 and SW4, the inductor L1, and the capacitor C0). .

  That is, the output voltage Vout only decreases for a moment. In this case, the error voltage Verror1 of the error detection circuit 21 is compared with the target error voltage Vaim by the comparator 27 as described above, and becomes equal to Vaim. Although the output voltage Vout varies little, it deviates slightly from the target error voltage Vaim but does not exceed the threshold voltage Vaim2.

  Similarly, when the load 6 greatly fluctuates at time t2, the output voltage Vout immediately returns to the original voltage due to the action of the voltage control system. In other words, the output voltage Vout only decreases for a moment. In this case, the error voltage Verror1 of the error detection circuit 21 has a large fluctuation in the output voltage Vout. The voltage Vaim2 will be exceeded.

In either case, the error voltage Verror1 of the error detection circuit 21 changes according to the output voltage Vout. However, when viewed in a long time, the correction of the voltage adjustment value Vadjust of the integrator 30 is effective and converges to the target error voltage Vaim. .
[When load suddenly fluctuates to heavy load]
Next, the case where the load 6 suddenly increases will be described with reference to the time chart of FIG.

  It is assumed that the master DC / DC converter 1 is operating and the slave DC / DC converters 2 to 4 are inactive.

  Assuming that the load 6 suddenly increases at time t3, the voltage control system of the operating DC / DC converter 1 cannot fully follow, and the output voltage Vout is greatly reduced to the set voltage or lower. As the output voltage Vout decreases, the error voltage Verror1 of the error detection circuit 21 (see FIG. 3) of each DC / DC converter 2 to 4 increases. The error voltage Verror1 exceeds the threshold voltage Vaim2 of the target error voltage generation circuit 26 due to a drop below the set voltage of the output voltage Vout.

  For this reason, the comparison signal g3 of the comparator 11 of each of the DC / DC converters 2 to 4 becomes H level, and this H level comparison signal g3 is input to the AND circuit 62 of the asynchronous circuit 60 of the control circuit 32 shown in FIG. . Since each of the DC / DC converters 2 to 4 is at rest, an L level hold signal g4 is output from each of the synchronous circuits 50 of the DC / DC converters 2 to 4, and the output signal g5 of the inverter 61 of each asynchronous circuit 60 is output. Becomes H level and is input to the AND circuit 62. Therefore, when the H level comparison signal g 3 is input to the AND circuit 62 of the asynchronous circuit 60, the H level start signal Gb is output from each AND circuit 62, and this start signal Gb passes through each OR circuit 70. Is output.

Incidentally, since the asynchronous circuit 60 is composed of a logic circuit asynchronous to the clock, the OR circuit 70 of each DC / DC converter 2 to 4 is almost simultaneously with the input of the H level comparison signal g3 output from the comparator 11. Start signals Gb are respectively output from. For this reason, the DC / DC converters 2 to 4 that have been suspended can be started all at once in a short time after the detection of a large variation in the output voltage Vout, and the greatly varied output voltage Vout immediately returns to the original output voltage. become.
[When the load after change is light]
Here, although the change of the load 6 itself was abrupt, the power consumption of the load 6 after the change is not so much, and a case where all the DC / DC converters 1 to 4 are operated too much will be described below. To do.

  When the DC / DC converters 2 to 4 start operating, the output current per DC / DC converter 1 to 4 becomes 1/4. The voltage corresponding to the output current detected by the current sensor 15A corresponding to this, that is, the voltage signal Vsense (= Vsense1) gradually decreases. This is because the stability problem occurs when the control band is too wide, and therefore the change of the voltage signal Vsense1 is adjusted to be slow.

  When the voltage signal Vsense1 decreases and falls below the threshold value Vthd of the comparator 12, the comparator 12 of the DC / DC converters 2 to 4 outputs the H level comparison signal g1 (time t4).

  The DC / DC converters 2 to 4 recognize the operation order obtained by the control circuit 32B. First, the DC / DC converter 4 first shifts to the sleep state (according to the flow of FIG. 5). A plurality of DC / DC converters do not simultaneously shift from an operating state to a dormant state).

  By the way, immediately after the DC / DC converters 2 to 4 are shifted from the hibernation state to the operation state, the control system is not in the stable state, and an unstable state in which the control system shifts to the hibernation state continues again. There is a risk of transition and repeated state transitions. For this reason, when there is a transition between the operation state and the sleep state, a prohibition time is provided so that the state does not transition again for a certain period of time.

That is, the comparison signal g1 (is The start signal Ga (active) output from the synchronization circuit 50 of the converter 4 is not changed to L level immediately after down) becomes H level, and the converter 4 is not shifted to the sleep state. After sufficient time has elapsed since the converter 4 has shifted to the operating state and has become stable, the converter 4 is again shifted to the resting state. That is, the activation signal Gb of the DC / DC converter 4 is set to L level (time t5) after a predetermined time has elapsed since the time t4 when the comparison signal g1 became H level, and the DC / DC converter 4 is shifted to a resting state.

Since the number of operations of the DC / DC converters 1 to 4 is changed from 4 to 3 due to the suspension of the DC / DC converter 4, the output current per DC / DC converter increases 4/3 times. Correspondingly, the voltage signal Vsense detected by the current sensor 15A rises, but is still below the threshold value Vthd of the comparator 12, and the comparison signal g1 (is down) remains at the H level.

  The DC / DC converters 2 and 3 recognize the operation order obtained by the control circuit 32B, and it is known that the DC / DC converter 3 next shifts to the sleep state. As before, as the DC / DC converter 4 shifts to the resting state, the entire control system including the DC / DC converters 1 to 4 is in an unstable state. In this state, when the DC / DC converter 3 shifts to a dormant state, a transiently unstable state continues.

Each DC / DC converter 1 to 4 shares information that the DC / DC converter 4 shifts to a sleep state and the number of parallel operations has changed by means (clock PWM modulation circuit 37, clock PWM demodulation circuit 38). Immediately after the number of parallel operations changes, a prohibition time is provided so that the state transition of each converter is not performed. Thereby, the comparison signal g1 (is Even if down) is at the H level, the DC / DC converter 3 does not shift to the sleep state immediately after the DC / DC converter 4 shifts to the sleep state. After the DC / DC converter 4 shifts to the resting state and sufficiently time elapses and becomes stable, the DC / DC converter 3 transitions to the resting state.

  That is, the activation signal Gb of the DC / DC converter 3 is set to L level (time t6) after a lapse of a predetermined time from the time t5 when the DC / DC converter 4 shifts to the hibernation state, and the DC / DC converter 3 shifts to the hibernation state. The

  Since the number of operations of the DC / DC converters 1 to 4 has changed from 3 to 2, the output current of one converter increases 3/2 times. For this reason, the voltage signal Vsense1 detected by the current sensor 15A rises and exceeds the threshold value Vthd of the comparator 12 of the DC / DC converter 2 (time point t7). The converter 2 continues to operate as it is.

During the above period, the change in the current consumption of the load 6 is abrupt, so the change in the output voltage Vout is large. As a result, the start signals Gb (f active) is output and the converters 2 to 4 are activated simultaneously. The output current Iout1 of the DC / DC converter 1 increases rapidly when the load 6 suddenly becomes heavier, and then decreases rapidly to ¼ upon activation of the DC / DC converters 2-4. The voltage signal Vsense1 output from the DC / DC converter 1 has a voltage value proportional to the output voltage of the DC / DC converter 1, but the band is limited for the stabilization of the control system, and the abrupt change described above. Cannot follow.

As a result, the voltage of the voltage signal Vsense1 detected by the current sensor 15A does not rise and exceed the threshold value Vthu of the comparator 12. Therefore, the comparator 13 of the DC / DC converters 2 to 4 outputs an H level comparison signal g2 ( is up) is never output. This is because the comparator 11 outputs the comparison signal g3 (f) before the voltage of the voltage signal Vsense1 rises. This is because the output current of the DC / DC converter 1 decreases.
[When the load changes slowly]
Next, the case where the load 6 gradually increases will be described with reference to the time chart of FIG.

  It is assumed that the master DC / DC converter 1 is operating and the slave DC / DC converters 2 to 4 are inactive.

Now, the load 6 gradually increases (time t10), and the output current Iout of the DC / DC converter 1 increases. As the output current Iout increases, the voltage of the voltage signal Vsense1 output from the current sensor 15A increases. When the voltage of the voltage signal Vsense1 exceeds the threshold value Vthu of the comparator 13 of the DC / DC converters 2 to 4 (time t11), the comparison signal g2 (is) respectively output from the comparator 13 of the DC / DC converters 2 to 4 up) becomes H level.

  Since the DC / DC converters 2 to 4 recognize the operation order obtained by the control circuit 32B and know that it is the DC / DC converter 2 that starts up, the DC / DC converter 2 synchronization circuit The H level activation signal Ga (active) is output from only 50. In response to the activation signal Ga, the DC / DC converter 2 returns from an inactive state to an operating state.

  When the DC / DC converter 2 shifts to the operating state, control is performed so as to output a current equal to the output current Iout of the DC / DC converter 1, so that the output current per one of the DC / DC converter 1 falls by half. . Along with this, the voltage of the voltage signal Vsense1 output from the current sensor 15A also decreases (time t11).

  Further, when the current consumption of the load 6 gradually increases, the voltage of the voltage signal Vsense output from the current sensor 15A again exceeds the threshold value Vthu of the comparator 13 of the DC / DC converters 2 to 4 (time t12). Since the DC / DC converter 2 has already shifted to the operating state, the comparator 13 of the DC / DC converter 2 does not output the H-level comparison signal g2, and the comparator 13 of the DC / DC converters 3 and 4 does not output it. An H level comparison signal g2 is output.

  Each DC / DC converter 3 and 4 recognizes the order of operation, and since it is known that the next DC / DC converter 3 is started up, only the synchronizing circuit 50 of the DC / DC converter 3 is set to the H level. The activation signal Ga (active) is output. In response to the activation signal Ga, the DC / DC converter 3 returns from the resting state to the operating state.

  When the DC / DC converter 3 shifts to the operating state, control is performed so as to output a current equal to the output current Iout of the DC / DC converter 1, so that the output current per converter falls to 2/3. That is, the state where the two DC / DC converters 1 and 2 operate is shifted to the state where the three DC / DC converters 1 to 3 operate. Accordingly, the voltage signal Vsense output from the current sensor 15A also decreases (time 12).

  Further, the current consumption of the load 6 gradually increases, and the DC / DC converter 4 also shifts from the resting state to the operating state in the same manner as described above (time t13).

During the above period, since the change in the current consumption of the load 6 is gradual, there is almost no change in the output voltage Vout of the multiphase power supply device 10. Immediately after the DC / DC converters 2 to 4 return from the resting state to the operating state, the voltage may rise and fall transiently until the control system is stabilized. However, in the DC / DC converters 2 to 4 in the dormant state, the error voltage Verror1 of the error detection circuit 21 of each DC / DC converter 2 to 4 does not exceed the threshold voltage Vaim2 of the target error voltage generation circuit 26. For this reason, the comparison signal g3 (f active) is never output.

Since the voltage of the voltage signal Vsense output from the current sensor 15A does not fall below the threshold value Vthd of the comparator 12, the comparison signal g1 (is down) is not output.
[Second Embodiment]
FIG. 9 is a block diagram showing the configuration of the multiphase power supply apparatus 100 of the second embodiment.

  The multiphase power supply apparatus 100 of the second embodiment includes four DC / DC converters 101 to 104 connected in parallel and a comparator (second activation signal output system: second activation signal output means) 111. .

  The DC / DC converters 101 to 104 are obtained by omitting the comparator 11 of the DC / DC converters 1 to 4 shown in FIG. 3, the asynchronous circuit 60 and the OR circuit 70 shown in FIG. 4, and others are DC / DC converters. It has the same configuration as 1-4.

The comparator 111 compares the output voltage Vout with the set voltage Ve, and outputs an H level start signal Gb when the output voltage Vout drops below the set voltage Ve. This activation signal Gb is used to activate all the DC / DC converters 102 to 104 that are inactive. As a result, as in the first embodiment, the greatly varied output voltage Vout immediately returns to the original output voltage.
[Third embodiment]
FIG. 10 is a block diagram showing the configuration of the multiphase power supply apparatus 200 of the third embodiment.

  The multiphase power supply apparatus 200 of the third embodiment includes four DC / DC converters 201 to 204 connected in parallel, a comparator 111, a current detection sensor 215 that detects an output current, and a control device 210. Yes.

  The DC / DC converters 201 to 204 are obtained by omitting the comparators 11, 12, and 13 of the DC / DC converters 1 to 4 and the control circuit 32 shown in FIG. It is the same composition as.

  Based on the current value detected by current detection sensor 215, control device 210 determines the number of converter operations and DC / DC converters 201 to 204 to be operated, and operates predetermined DC / DC converters 201 to 204. It is going.

  In the third embodiment, the controller 210 does not determine whether or not each of the DC / DC converters 201 to 204 is activated, but a comparator 111 is provided. As a result, the same effects as in the first embodiment can be obtained.

  The present invention is not limited to the above-described embodiments, and design changes and additions are permitted without departing from the scope of the claimed invention.

1 DC / DC converter (master DC / DC converter 2-4 DC / DC converter (slave DC / DC converter)
6 Load 10 Multiphase power supply device 11 Comparator (second comparison means)
12 comparator 13 comparator (first comparing means)
15A to 15D Current sensor (current detection means)
21 Error detection circuit (fluctuation voltage detection means)
32 control circuit 50 synchronization circuit (first activation signal output means: determination processing circuit)
60 Asynchronous circuit (second activation signal output means)
C0 capacitor

JP-A-11-127573

Claims (6)

A multi-phase power supply apparatus comprising a plurality of DC / DC converters connected in parallel, and applying a constant output voltage to the load by changing the number of DC / DC converters operating according to the size of the load,
Current detecting means for detecting an output current flowing through the load;
Based on the detected current detected by the current detection means, the number of DC / DC converters to be driven is determined, and a first start signal for starting a DC / DC converter that is inactive according to this determination is output. An output system;
When the output voltage falls below set voltage, a second start signal output line for outputting a second start signal for starting the DC / DC converter during pauses,
A logic circuit that operates asynchronously with a reference clock input between the DC / DC converters in the plurality of DC / DC converters;
In the logic circuit, when the output voltage is equal to or lower than a set voltage, the second start signal output system is shorter than the time from when the detected current becomes larger than a threshold until the first start signal is output. A multi-phase power supply apparatus that outputs a second activation signal in time. The first activation signal output system compares the detected current detected by the current detecting unit with a preset threshold value, and outputs a first comparison signal when the detected current is larger than the threshold value. When a first comparison signal is output from one comparison means, it is determined whether to start based on the number of operating DC / DC converters, and the first start signal is output when it is determined to start. Starting signal output means,
The second activation signal output system includes a second activation signal output unit that compares the output voltage with a set voltage and outputs a second activation signal when the output voltage becomes equal to or lower than the set voltage. The multi-phase power supply device according to claim 1. A master DC / DC converter that operates at all times, a plurality of slave DC / DC converters that are connected in parallel to the master DC / DC converter and that operate or pause according to the magnitude of the load, and the master DC / DC A multi-phase power supply device that includes a current detection means for detecting an output current of the converter, and applies a constant output voltage to the load by changing the number of DC / DC converters operating according to the size of the load,
Each of the slave DC / DC converters determines whether or not to start based on the number of slave DC / DC converters that are operating when the detected current detected by the current detection means exceeds a preset threshold value. to a first start signal output line for outputting a first activation signal which activates the slave DC / DC converter dormant when it is determined to start, when the output voltage falls below the set voltage, dormant A second start signal output system for outputting a second start signal for starting the slave DC / DC converter of
A logic circuit that operates asynchronously with a reference clock input from the master DC / DC converter to each of the slave DC / DC converters, wherein the logic circuit has a second activation signal output system and the output voltage is set; A multi-phase power supply apparatus that outputs a second activation signal in a time shorter than a time from when the detected current becomes larger than a threshold to when the first activation signal is output when the voltage becomes lower than a voltage. The first activation signal output system compares the detected current detected by the current detecting unit with a preset threshold value, and outputs a first comparison signal when the detected current is larger than the threshold value. When a first comparison signal is output from one comparison means, it is determined whether or not to start based on the number of slave DC / DC converters that are operating, and the first start signal is output when it is determined to start. 1 start signal output means,
The second activation signal output system compares the fluctuation voltage detected by the fluctuation voltage detection means for detecting the fluctuation of the output voltage with the preset voltage set in advance by the fluctuation voltage detected by the fluctuation voltage detection means. Second comparison means for outputting a second comparison signal at the time, and a second activation signal for outputting a second activation signal for activating the slave DC / DC converter that has been stopped when the second comparison means outputs the second comparison signal. The multi-phase power supply device according to claim 3, further comprising an output unit. The first activation signal output means includes a determination processing circuit that determines whether or not to output the first activation signal based on the number of operations of other slave DC / DC converters.
5. The multi-phase power supply apparatus according to claim 4, wherein the second activation signal output means is composed of an asynchronous logic circuit. The master DC / DC converter, multi-phase power supply according to claim 4 or claim 5, characterized that you configured the same as the slave DC / DC converter.