JP6445387B2 - Semiconductor device and memory inspection method - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a memory inspection technique.

  With the high performance of information processing devices, communication devices, video devices, etc., the amount of processing of signals and data has increased and the demand for processing speed has also increased. In order to perform signal and data processing at high speed in each device, a configuration in which a plurality of semiconductor devices that perform each processing are provided and processed in parallel may be used. In the case of a configuration including a plurality of CPUs (Central Processing Units), a multi-core configuration in which a CPU is cored and a plurality of CPUs are housed in one package may be used.

  In order to process a large amount of data in parallel in a multi-core semiconductor device, a large capacity storage device is required. When trying to process a large amount of data in an information processing apparatus or the like, the number of CPUs or memory modules to be used increases and the apparatus can be increased in size. However, since the size of the housing of the device and the installation area of the device are limited, it is desirable that the size of the electronic substrate constituting the device is suppressed as much as possible.

  In the case of a semiconductor device composed of multi-core CPUs, each CPU accesses a large-capacity memory module used in common via a common memory bus. In a memory module provided in an information processing apparatus or the like, an inspection is performed to check whether there is an abnormality in a storage element at the time of starting the apparatus or at other necessary timing for stable operation of the apparatus. However, if an inspection is performed for all storage areas of a large-capacity memory module, there is a possibility that the inspection takes an enormous amount of time, and it may take a long time to start necessary processing.

  On the other hand, it is desirable that each apparatus such as an information processing apparatus can be started at a high speed when restarting. In order for an information processing apparatus or the like to start up at high speed, it is necessary to check whether there is an abnormality in a large-capacity memory as quickly as possible. For this reason, a technique for performing a test of a large-capacity memory module or the like in a short time has been developed. As a technique for performing such an inspection of a large-capacity memory module or the like in a short time, for example, a technique such as Patent Document 1 is disclosed.

  Patent Document 1 relates to a multiprocessor system in which a memory is inspected by a plurality of processors. The multiprocessor system of Patent Document 1 includes a main processor, a plurality of sub processors, and a memory.

  In Patent Document 1, a main processor allocates a memory area to be inspected for each sub processor. When each sub processor receives a memory inspection request from the main processor, each sub processor stores an inspection program in a storage area in the sub processor. Each sub-processor writes data to the entire memory area allocated using the stored inspection program. When the data writing is completed, each sub processor reads the data from the memory, and determines whether there is an abnormality or not by comparing with the written data. In the multiprocessor system of Patent Document 1, a plurality of sub processors provided are inspected in parallel for memory areas assigned to them. In Patent Document 1, it is said that a plurality of processors perform processing in parallel to reduce the time required for memory inspection.

  Japanese Patent Application Laid-Open No. 2003-228561 discloses a computer that performs an inspection for the presence or absence of an abnormality in parallel using a CPU and a tester. The computer of Patent Document 2 includes a CPU, a first peripheral function, a second peripheral function, and a bus that connects each unit. The computer of Patent Document 2 includes a switch that disconnects the bus between the first peripheral function and the second peripheral function. The computer of Patent Document 2 further includes a connection bus that connects to an external tester, and is connected to the tester via the connection bus. In the computer disclosed in Patent Document 2, when the switch is disconnected, the CPU is connected to the first peripheral function and disconnected from the second peripheral function.

  In the computer disclosed in Patent Document 2, when the first peripheral function and the second peripheral function are tested, the switch is disconnected, and the CPU tests the first peripheral device. In parallel with the test by the CPU, the second peripheral function tester connected to the connection bus is tested. In Patent Document 2, the time required for the peripheral function test can be shortened by performing the test in parallel between the CPU and the tester.

JP 2009-169897 A Japanese Patent Laid-Open No. 5-108395

  However, the technique of Patent Document 1 is not sufficient in the following points. In Patent Document 1, tests of memory areas to which sub processors are assigned are performed in parallel. However, since the memory bus is shared, each sub-processor performs a memory area test in accordance with the use timing of the memory bus allocated to each sub-processor in a time division manner. Therefore, the time other than the time required for data transfer can be shortened, but the time required for data transfer to and from the memory is equivalent to the time required for testing with one processor. For this reason, the technique disclosed in Patent Document 1 is not sufficient as a technique for testing a large-capacity memory in a short time.

  In the technique disclosed in Patent Document 2, the second peripheral function is tested using an external tester connected via a connection bus. In other words, in Patent Document 2, a tester is required as a dedicated test device in addition to the configuration required during normal operation of the information processing apparatus and the like. Therefore, in the technique of Patent Document 2, the apparatus can be increased in size. Therefore, the technique of Patent Document 2 is not sufficient as a technique for inspecting a large-capacity memory in a short time while suppressing an increase in size of the apparatus.

  An object of the present invention is to obtain a semiconductor device capable of performing a test of a large-capacity memory in a short time while suppressing an increase in size of the device.

  In order to solve the above problems, a semiconductor device of the present invention includes a first memory control unit, a second memory control unit, a first arithmetic processing unit, a second arithmetic processing unit, A bus, a second bus, a third bus, and bus dividing means are provided. The first memory control means controls access to the first memory. The second memory control means controls access to the second memory. The first arithmetic processing means inspects the first memory and the second memory via the first memory control means and the second memory control means and the presence or absence of an abnormality in the first memory. Means. The second arithmetic processing means operates in parallel with the first arithmetic processing means, and accesses the first memory and the second memory via the first memory control means and the second memory control means. And means for inspecting whether there is an abnormality in the second memory. The first bus connects the first arithmetic processing means and the first memory control means. The second bus connects the second arithmetic processing means and the second memory control means. The third bus connects the first bus and the second bus. The bus dividing means divides or combines the third buses based on a predetermined control signal so as to switch the presence / absence of connection between the first bus and the second bus on the third bus. The bus dividing means divides the third bus when the first arithmetic processing means and the second arithmetic processing means inspect whether there is an abnormality in the first memory and the second memory.

  In the memory inspection method of the present invention, the first arithmetic processing means and the second arithmetic processing means are connected to the first memory and the second memory control means connected to the first memory control means. The third bus is divided when the presence or absence of abnormality in the second memory is inspected. The first arithmetic processing means is connected to the first memory control means via the first bus. The second arithmetic processing means is connected to the second memory control means via the second bus. The third bus connects the first connection bus and the second connection bus. According to the memory inspection method of the present invention, the first arithmetic processing unit is disconnected from the second memory control unit, and the second arithmetic processing unit is disconnected from the first memory control unit. 3 buses are divided based on a predetermined control signal. In the memory inspection method according to the present invention, the first arithmetic processing means inspects whether there is an abnormality in the first memory, and the second arithmetic processing means inspects whether there is an abnormality in the second memory.

  According to the present invention, a large-capacity memory can be inspected in a short time while suppressing an increase in the size of the apparatus.

It is a figure which shows the outline | summary of a structure of the 1st Embodiment of this invention. It is a figure which shows the outline | summary of a structure of the 2nd Embodiment of this invention. It is a figure which shows the example of a structure of the information processing apparatus of the 2nd Embodiment of this invention. It is the figure which showed the outline | summary of the operation | movement flow in the 2nd Embodiment of this invention. It is the figure which showed the example of the structure of the information processing apparatus contrasted with this invention. It is the figure which showed the example of the operation state of the information processing apparatus contrasted with this invention. It is the figure which showed the example of the operation state of the information processing apparatus contrasted with this invention. It is the figure which showed the example of the operation state in the 2nd Embodiment of this invention. It is the figure which showed the example of the other structure of the information processing apparatus of this invention. It is the figure which showed the example of the other structure of the information processing apparatus of this invention.

(First embodiment)
A first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an outline of the configuration of the semiconductor device of this embodiment. The semiconductor device according to this embodiment includes a first memory control unit 1, a second memory control unit 2, a first arithmetic processing unit 3, a second arithmetic processing unit 4, and a first bus 5. The second bus 6, the third bus 7, and the bus dividing means 8 are provided.

  The first memory control unit 1 controls access to the first memory. The second memory control unit 2 controls access to the second memory. The first arithmetic processing means 3 includes means for accessing the first memory and the second memory via the first memory control means 1 and the second memory control means 2, and whether there is an abnormality in the first memory. And means for inspecting. The second arithmetic processing means 4 operates in parallel with the first arithmetic processing means 3, and passes through the first memory control means 1 and the second memory control means 2 to the first memory and the second memory. Means for accessing, and means for inspecting whether there is an abnormality in the second memory. The first bus 5 connects the first arithmetic processing means 3 and the first memory control means 1. The second bus 6 connects the second arithmetic processing means 4 and the second memory control means 2. The third bus 7 connects the first bus 5 and the second bus 6. The bus dividing means 6 divides or combines the third bus 7 on the third bus 7 based on a predetermined control signal so as to switch the connection between the first bus 5 and the second bus 6. To do. Further, the bus dividing means 6 divides the third bus 7 when the first arithmetic processing means 3 and the second arithmetic processing means 4 inspect whether there is an abnormality in the first memory and the second memory. To do.

  In the semiconductor device of this embodiment, the first arithmetic processing means 3 and the second arithmetic processing means 4 are connected to the first memory and the second memory control means 2 via the first memory control means 1 and the second memory control means 2, respectively. The second memory is accessed and operated. The first arithmetic processing means 3 and the second arithmetic processing means 4 operate in parallel. In the semiconductor device of the present embodiment, the third bus 7 is divided by the bus dividing means 6 when the first memory and the second memory are inspected for abnormality. By dividing the third bus 7 connecting the first bus 5 and the second bus 6, the first arithmetic processing means 3 is connected to the first memory control means 1 and the second bus The arithmetic processing means 4 can be accessed simultaneously with the second memory control means 2. Therefore, the first arithmetic processing unit 3 can check whether the first memory is abnormal, and the second arithmetic processing unit 4 can check the second memory for abnormality. . Therefore, in the semiconductor device of this embodiment, the time required for the inspection for the presence or absence of memory abnormality can be shortened. In the semiconductor device of the present embodiment, the first arithmetic processing means 3 and the second arithmetic processing means 4 inspect in parallel when inspecting whether there is an abnormality in the memory. Since an inspection circuit or the like is not required, an increase in size of the apparatus can be suppressed. As a result, in the semiconductor device of this embodiment, it is possible to inspect a large capacity memory in a short time while suppressing an increase in the size of the device.

(Second Embodiment)
A second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 shows an outline of the configuration of the information processing apparatus according to this embodiment.

  The information processing apparatus according to the present embodiment includes a first CPU 11, a second CPU 12, a bus dividing unit 13, a first memory controller 14, a second memory controller 15, and a first memory module 16. The second memory module 17 is provided.

  In the information processing apparatus according to this embodiment, a plurality of first memory modules 16 and a plurality of second memory modules 17 are provided. The number of the first memory module 16 and the second memory module 17 may be one.

  The first bus 11 is connected between the first CPU 11 and the first memory controller 14. The second bus 12 is connected between the second CPU 12 and the second memory controller 15. The first bus 51 and the second bus 52 are connected by a third bus 53. Further, the bus dividing unit 13 is provided on the third bus 53. The first memory controller 14 and the first memory module 16 are connected by a bus 54. The second memory controller 15 and the second memory module 17 are connected by a bus 55. In addition, each part of the information processing apparatus according to the present embodiment may be mounted on an electronic substrate or the like as an independent semiconductor device or the like, and several parts are integrated and formed in one package. It may be.

  FIG. 3 schematically illustrates an example in which the first CPU 11, the second CPU 12, the bus division unit 13, the first memory controller 14, and the second memory controller 15 are formed in a package of one semiconductor device 10. It is shown in. The semiconductor device 10 of FIG. 3 is a multi-core processor including two CPUs, a first CPU 11 and a second CPU 12. In the example of FIG. 3, the information processing apparatus includes the semiconductor device 10 and a plurality of first memory modules 16 and second memory modules 17 as independent components.

  Next, each part of the information processing apparatus of this embodiment will be described. The first CPU 11 and the second CPU 12 have a function as a central processing unit that performs arithmetic processing and control necessary for program execution, data processing, and the like. Further, the first CPU 11 and the second CPU 12 have a function of inspecting whether or not the first memory module 16 and the second memory module 17 are abnormal.

  The first CPU 11 accesses the first memory module 16 and the second memory module 17 via the first memory controller 14 and the second memory controller 15 to perform data writing and data reading. The first CPU 11 accesses the first memory controller 14 via the first bus 51. In addition, during the normal operation, that is, when the memory is not inspected, the first CPU 11 also sends to the second memory controller 15 via the first bus 51, the third bus 53, and the second bus 52. to access.

  The first CPU 11 inspects whether there is an abnormality in the first memory module 16 via the first memory controller 14. When the first CPU 11 inspects the first memory module 16, the first CPU 11 sends a predetermined control signal for requesting the division of the third bus 53 to the bus dividing unit 13 as the bus setting signal S11. In addition, when the first CPU 11 completes the inspection of the first memory module 16, the first CPU 11 sends a predetermined control signal for requesting the connection of the third bus 53 to the bus dividing unit 13 as the bus setting signal S11. When inspecting whether there is an abnormality, the third bus 53 is divided, so the first CPU 11 can access only the first memory controller 14 via the first bus 51. That is, the first CPU 11 cannot access the second memory controller 15.

  The division of the bus means that a signal cannot be transmitted between the first bus 51 and the second bus 52 via the third bus 53. That is, the division of the bus means that the first bus 51 and the second bus 52 are disconnected. In addition, the bus coupling means that a signal can be transmitted between the first bus 51 and the second bus 52 via the third bus 53. That is, the bus coupling means that the first bus 51 and the second bus 52 are connected.

  The second CPU 12 accesses the first memory module 16 and the second memory module 17 via the first memory controller 14 and the second memory controller 15 to perform data writing and data reading. The second CPU 12 accesses the second memory controller 15 via the second bus 52. In addition, during normal operation, that is, when the memory is not inspected, the second CPU 12 also sends the first memory controller 14 to the first memory controller 14 via the second bus 52, the third bus 53, and the first bus 51. to access.

  The second CPU 12 inspects whether there is an abnormality in the second memory module 17 via the second memory controller 15. When the second CPU 12 inspects the second memory module 17, the second CPU 12 sends a predetermined control signal for requesting the division of the third bus 53 to the bus dividing unit 13 as the bus setting signal S12. When the second CPU 12 finishes the inspection of the second memory module 17, the second CPU 12 sends a predetermined control signal for requesting the connection of the third bus 53 to the bus dividing unit 13 as the bus setting signal S12. When inspecting whether there is an abnormality, the third bus 53 is divided, so that the second CPU 12 can access only the second memory controller 15 via the second bus 52. That is, the second CPU 12 cannot access the first memory controller 14.

  The first CPU 11 and the second CPU 12 of this embodiment correspond to the first arithmetic processing unit 3 and the second arithmetic processing unit 4 of the first embodiment, respectively.

  The bus dividing unit 13 has a function of dividing the third bus 53 that connects the first bus 51 and the second bus 52. The bus division unit 13 according to the present embodiment includes a switch element, and divides the third bus 53 passing through the bus division unit 13 so that no signal passes when the memory test is started. Further, when the memory test is completed, the bus dividing unit 13 couples the third bus 53 passing through the bus dividing unit 13 to put the signal through.

  The bus dividing unit 13 operates based on the bus setting signal S11 and the bus setting signal S12 sent as predetermined control signals from the first CPU 11 and the second CPU 12. The bus dividing unit 13 of the present embodiment divides the third bus 53 upon receiving a request to divide the bus from either the first CPU 11 or the second CPU 12. In addition, when the bus dividing unit 13 of this embodiment receives a request to divide the bus from both the first CPU 11 and the second CPU 12, the bus dividing unit 13 couples the third bus 53.

  When the bus dividing unit 13 divides the third bus 53, the first CPU 11 can access only the first memory module 16 via the first memory controller 14. That is, in a state where the third bus 53 is divided, the first CPU 11 cannot access the second memory controller 15 and the second memory module 17.

  Further, when the bus dividing unit 13 divides the third bus 53, the second CPU 12 can access only the second memory module 17 via the second memory controller 15. That is, in a state where the third bus 53 is divided, the second CPU 12 cannot access the first memory controller 14 and the first memory module 16.

  When the memory test is completed, the bus division unit 13 couples the third bus 53 that has been divided. When the third bus 53 is coupled, the first CPU 11 and the second CPU 12 can access each memory module via the first memory controller 14 and the second memory controller 15. The bus dividing unit 13 of the present embodiment corresponds to the bus dividing unit 8 of the first embodiment.

  The first memory controller 14 has a function of controlling data writing to the first memory module 16 and data reading from the first memory module 16. The first memory controller 14 controls writing and reading of data in the first memory module 16 based on requests from the first CPU 11 and the second CPU 12.

  The second memory controller 15 has a function of controlling data writing to the second memory module 17 and data reading from the second memory module 17. The second memory controller 15 controls writing and reading of data in the second memory module 17 based on requests from the first CPU 11 and the second CPU 12.

  The first memory controller 14 and the second memory controller 15 of the present embodiment correspond to the first memory control unit 1 and the second memory control unit 2 of the first embodiment, respectively.

  The first memory module 16 and the second memory module 17 are composed of semiconductor elements and have a function of storing and outputting data. The first memory module 16 and the second memory module 17 of the present embodiment are configured as a RAM (Random Access Memory). The first memory module 16 and the second memory module 17 may be other types of storage devices.

  The first memory module 16 and the second memory module 17 store data by writing to the storage element and data by reading from the storage element based on the control of the first memory controller 14 and the second memory controller 15. Is output. The first memory module 16 and the second memory module 17 of the present embodiment correspond to the first memory and the second memory of the first embodiment, respectively.

  The first bus 51, the second bus 52, the third bus 53, the bus 54, and the bus 55 have a function of transmitting signals between the respective parts. The first bus 51, the second bus 52, the third bus 53, the bus 54, and the bus 55 include an address bus and a data bus. The third bus 53 has a function as a connection bus that connects between the first bus 51 and the second bus 52. In addition, the first bus 51, the second bus 52, and the third bus 53 of the present embodiment control bus division and coupling between the first CPU 11, the second CPU 12, and the bus division unit 13. The bus setting signal S11 and the bus setting signal S12 to be transmitted are transmitted.

  In the present embodiment, the first bus 51 and the third bus 53 are shown as separate separate parts. However, the first bus 51 and the third bus 53 are provided as continuously formed buses. It may be done. Similarly, the second bus 52 and the third bus 53 may be provided as a continuously formed bus.

  The first bus 51 and the second bus 52 of the present embodiment correspond to the first bus 5 and the second bus 6 of the first embodiment, respectively. Further, the third bus 53 of the present embodiment corresponds to the third bus 7 of the first embodiment.

  The operation of the information processing apparatus of this embodiment will be described. During normal operation, the first CPU 11 and the second CPU 12 of the information processing apparatus according to the present embodiment write data to each memory module via the first memory controller 14 and the second memory controller 15. . Further, the first CPU 11 and the second CPU 12 read data from each memory module via the first memory controller 14 and the second memory controller 15. That is, during normal operation, the first CPU 11 and the second CPU 12 can access both the first memory module 16 and the second memory module 17.

  Next, the operation when each CPU inspects whether there is an abnormality in each memory module will be described. FIG. 4 shows an outline of a flow when the information processing apparatus according to the present embodiment is inspected for the presence or absence of abnormality of the memory module.

  The memory inspection operation is started by starting or resetting the information processing apparatus or inputting a signal requesting inspection from an operator or a control unit.

  The first CPU 11 sends a control signal for requesting division of the third bus 53 to the bus dividing unit 13 as a bus setting signal S11. When the bus dividing unit 13 receives the bus setting signal S11 for requesting the division of the third bus 53, the bus dividing unit 13 sets the third bus 53 in the divided state (step 101). Since the third bus 53 is divided, no signal is transmitted between the first bus 51 and the second bus 52. Therefore, the first CPU 11 can transmit signals in parallel with the first memory controller 14, and the second CPU 12 can transmit signals in parallel with the second memory controller 15.

  When the third bus 53 is divided, the first CPU 11 and the second CPU 12 start an initial setting operation for memory inspection (step 102). In the initial setting, an initial value of an address to be inspected of a memory, that is, an address of a memory at which an inspection for abnormality is started, and inspection data used for the inspection are set. The first CPU 11 sets the start address of the memory test of the first memory module 16. Further, the second CPU 12 sets the start address of the memory test of the second memory module 17.

  When the initial value of the address is set, the first CPU 11 writes a test pattern to the inspection target address on the first memory module 16 via the first memory controller 14 (step 103).

  When the test pattern is written to the first memory module 14, the first CPU 11 reads data from the address where the writing is performed via the first memory controller 14 (step 104).

  When the first CPU 11 reads the data, the first CPU 11 compares the read data with the test pattern data (step 105). When the read data matches the test pattern data, the first CPU 11 determines that there is no abnormality in the storage element at the address to be inspected. Further, when the read data matches the test pattern data, the first CPU 11 determines that an abnormality has occurred in the memory element of the address to be inspected. When the first CPU 11 determines the presence / absence of abnormality of the storage element of the address to be inspected, the first CPU 11 stores the value of the address subjected to the inspection and information on the presence / absence of abnormality.

  When the inspection result indicating whether there is an abnormality is stored, the first CPU 11 increments the address value to be inspected by a predetermined value (step 106). The predetermined value is set, for example, such that the value of the next address to be inspected is continuous with the last part of the address that has been inspected. In this case, the predetermined amount corresponds to an address value corresponding to an area where data written at a time as a test pattern can be stored. The predetermined value may be set so that the inspected area and a part of the area to be newly inspected overlap each other.

  When the value of the address to be inspected is set, the first CPU 11 confirms whether all the storage areas of the first memory module 16 have been inspected. When all the storage areas have not been inspected and the address set as the inspection target is an incomplete inspection area (No in step 107), the first CPU 11 performs the operation from step 103, Check for memory errors.

  When the set address is an address outside the storage area of the first memory module 14 and all areas have been inspected (Yes in step 107), the first CPU 11 determines that the first memory module 14 It is determined that the inspection has been completed (step 108). When determining that the inspection is completed, the first CPU 11 sends a signal requesting the connection of the third bus 53 to the bus dividing unit 13 as the bus setting signal S11.

  The second CPU 12 performs the same operation as the first CPU 11 from step 102 to step 108. If it is determined in step 107 that the check of the second memory module 15 has been completed, the second CPU 12 sends a signal requesting connection of the third bus 53 to the bus dividing unit 13 as the bus setting signal S12.

  When the bus division unit 13 receives the bus setting signal S11 and the bus setting signal S12 requesting the coupling of the third bus 53 from the first CPU 11 and the second CPU 12, the bus dividing unit 13 couples the third bus 53. When the third bus 53 is coupled, the first CPU 11 and the second CPU 12 can access the first memory module 16 and the second memory module 17 via the respective memory controllers.

  A comparison between the information processing apparatus of the present embodiment and an information processing apparatus that does not include a bus division unit will be described. FIG. 5 shows an example of the configuration of an information processing apparatus that does not include a bus division unit. The information processing apparatus illustrated in FIG. 5 includes a first CPU 21, a second CPU 22, a first memory controller 24, a second memory controller 25, a first memory module 26, and a second memory. A module 27 is provided.

  In the information processing apparatus shown in FIG. 5, the first CPU 21 and the first memory controller 24 are connected by a first bus 61. Further, the second CPU 22 and the second memory controller 25 are connected by a second bus 62. The first bus 61 and the second bus 62 are connected by a third bus 63. Therefore, a signal can be transmitted between the first bus 61 and the second bus 62 via the third bus 63 at all times. The first memory controller 24 and the first memory module 26 are connected by a bus 64. Similarly, the second memory controller 25 and the second memory module 27 are connected by a bus 65. Each part of the information processing apparatus shown in FIG. 5 has a function equivalent to that of each part of the information processing apparatus of the present embodiment, except that it does not have a control function of the bus dividing unit.

  FIG. 6 shows an example of the operating state of the multi-core processor in which the first CPU 21, the second CPU 22, the first memory controller 24, and the second memory controller 25 are one package in the information processing apparatus having the configuration shown in FIG. Is shown. In FIG. 6, a portion corresponding to the first CPU 21 and the second CPU 22 is shown as a CPU core, and a portion corresponding to the first memory controller 24 and the second memory controller 25 is shown as a memory controller. The parts corresponding to the first memory module 26 and the second memory module 27 are shown as memories.

  In the example of FIG. 6, the left CPU core inspects whether there is an abnormality in the memory module via the left memory controller. At this time, when the left CPU core is inspecting the memory module, the right CPU core is in an unused state because it cannot perform the memory inspection.

  FIG. 7 schematically shows a state when two CPU cores simultaneously inspect the memory module in the state of FIG. FIG. 7 shows a situation where two CPUs simultaneously perform a memory check operation and a collision occurs on the bus. If two CPUs access at the same time, a collision occurs on the bus, so the two CPUs cannot access the memory at the same time.

  FIG. 8 shows an example of the operation state at the time of memory inspection of the information processing apparatus of this embodiment. In the example of FIG. 8, since the bus is divided, the two CPUs can test the memory modules in parallel via different memory controllers. Assume that the time required to complete the inspection of the memory module is X hours when only one CPU performs the inspection of the memory module as in the example of FIG. At this time, since the semiconductor device of this embodiment performs the inspection of the memory modules in parallel as shown in FIG. 8, it may be possible to complete the inspection of the memory modules in (X / 2) time.

  In the information processing apparatus according to the present embodiment, the first CPU 11 and the second CPU 12 are normally connected to the first memory module 16 and the second memory module via the first memory controller 14 and the second memory controller 15, respectively. 17 is accessed and operated. In the information processing apparatus of the present embodiment, the third bus 53 is divided by the bus dividing unit 13 when the first memory module 16 and the second memory module are inspected for abnormality. When the third bus 53 is divided, the first CPU 11 can access the first memory module 16 and the second CPU 12 can access the second memory module 17 simultaneously. Therefore, the first CPU 11 and the second CPU 12 can inspect the first memory module 16 and the second memory module 17 in parallel processing.

  By checking whether there is a memory abnormality in the parallel processing by the first CPU 11 and the second CPU 12, it is possible to shorten the time required for the memory inspection compared to the case where one CPU inspects all memory areas. be able to. The effect of shortening the memory inspection performed in parallel by a plurality of CPUs becomes more prominent as the capacity of the memory increases. In the information processing apparatus according to the present embodiment, since only the bus dividing unit 13 needs to be provided for the memory inspection by parallel processing, an increase in the size of the apparatus can be suppressed. As described above, the information processing apparatus according to the present embodiment can inspect a large-capacity memory module in a short time while suppressing an increase in the size of the apparatus.

  In the second embodiment, an example in which two CPUs and two memory controllers are provided has been described. However, three or more CPUs and memory controllers may be provided. FIG. 9 schematically illustrates an example of an information processing apparatus including N CPUs and a memory controller. The information processing apparatus of FIG. 9 includes a CPU 31, a bus dividing unit 32, a memory controller 33, and a memory module 34.

  In the information processing apparatus of FIG. 9, the CPU 31 and the memory controller 33 are connected via a bus 35. The buses 35 are connected by a bus 36. Each bus 36 is provided with a bus division unit 32. The memory controller 33 and the memory 34 are connected by a bus 37.

  The information processing apparatus shown in FIG. 9 includes N CPUs 31 and N memory controllers 33. Each memory controller 33 is connected to one or more memory modules 34 via a bus 37. The information processing apparatus in FIG. 9 includes (N−1) bus division units 32. The function of each part of the information processing apparatus in FIG. 9 is the same as that of the part having the same name in the second embodiment.

  The information processing apparatus of FIG. 9 has (N−1) bus dividing units 33, so that N CPUs 31 can inspect the memory module 34 in parallel. Therefore, it can be possible to complete the inspection in (1 / N) time compared to the time required for completion when one CPU 31 inspects all the memory modules.

  FIG. 10 shows an example of a configuration in which a memory bus is formed in a ring shape in an information processing apparatus similar to the information processing apparatus of the second embodiment. The information processing apparatus in FIG. 10 includes a CPU 41, a bus division unit 42, a memory controller 43, and a memory module 44.

  In the information processing apparatus of FIG. 10, the CPU 41 and the memory controller 43 are connected via a bus 45. The buses 45 are connected by a bus 46. Each bus 46 is provided with a bus dividing unit 42. The memory controller 43 and the memory 44 are connected by a bus 47.

  The information processing apparatus of FIG. 10 includes N CPUs 41 and N memory controllers 43. In the information processing apparatus of FIG. 10, the bus division unit 42 -N and the bus division unit 42-1 are connected by a bus 46 -N. That is, the memory buses of the information processing apparatus in FIG. 10 are connected in a ring shape. Each memory controller 43 is connected to one or more memory modules 44 via a bus 47. The semiconductor device of FIG. 10 includes N bus division units 42. The function of each part of the semiconductor device in FIG. 10 is the same as that of the part having the same name in the second embodiment.

  Even in an information processing apparatus having an annular memory bus as shown in FIG. 10, the N CPUs 41 can test the memory modules 44 in parallel by providing the N bus dividing units 43. . Therefore, when one CPU 41 inspects all the memory modules, it may be possible to complete the inspection in (1 / N) time compared to the time required for completion.

  9 and 10 may also be configured to include a multi-core processor and a memory module in which a plurality of CPUs and the like are formed in one package, as in the second embodiment.

  In the second embodiment, an information processing apparatus using a CPU has been described, but another semiconductor device such as a DSP (Digital Signal Processor) or an FPGA (Field-Programmable Gate Array) may be used instead of the CPU.

DESCRIPTION OF SYMBOLS 1 1st memory control means 2 2nd memory control means 3 1st arithmetic processing means 4 2nd arithmetic processing means 5 1st bus 6 2nd bus 7 3rd bus 8 Bus division means 11 1st CPU
12 Second CPU
13 Bus Divider 14 First Memory Controller 15 Second Memory Controller 16 First Memory Module 17 Second Memory Module 21 First CPU
22 Second CPU
24 1st memory controller 25 2nd memory controller 26 1st memory module 27 2nd memory module 31 CPU
32 bus division unit 33 memory controller 34 memory module 35 bus 36 bus 37 bus 41 CPU
42 Bus Dividing Unit 43 Memory Controller 44 Memory Module 45 Bus 46 Bus 47 Bus 51 First Bus 52 Second Bus 53 Third Bus 54 Bus 55 Bus 61 First Bus 62 Second Bus 63 Third Bus 64 bus 65 bus S11 bus setting signal S12 bus setting signal

Claims (10)

First memory control means for controlling access to the first memory;
Second memory control means for controlling access to the second memory;
Means for accessing the first memory and the second memory via the first memory control means and the second memory control means; and means for inspecting whether or not the first memory is abnormal. First arithmetic processing means comprising:
Means for operating in parallel with the first arithmetic processing means and accessing the first memory and the second memory via the first memory control means and the second memory control means; Second arithmetic processing means having means for inspecting whether there is an abnormality in the memory of 2,
A first bus connecting the first arithmetic processing means and the first memory control means;
A second bus connecting the second arithmetic processing means and the second memory control means;
A third bus connecting the first bus and the second bus;
A bus dividing means for dividing or coupling the third bus based on a predetermined control signal so as to switch the presence or absence of connection between the first bus and the second bus on the third bus;
With
When inspecting whether there is an abnormality in the first memory and the second memory, at least one of the first arithmetic processing means and the second arithmetic processing means requests division of the third bus Sending the predetermined control signal to the bus dividing means,
The bus dividing means is configured such that, based on the predetermined control signal requesting division of the third bus, the first arithmetic processing means is disconnected from the second memory control means, and the second arithmetic operation is performed. A semiconductor device , wherein the third bus is divided so that a processing means is disconnected from the first memory control means . When the first arithmetic processing means and the second arithmetic processing means have finished checking whether there is an abnormality in the first memory and the second memory, the bus dividing means is provided with the third bus. Sending the predetermined control signal requesting the combination of
The bus dividing means is configured such that the first arithmetic processing means is connected to the second memory control means based on the predetermined control signal requesting coupling of the third bus, and the second arithmetic processing is performed. 2. The semiconductor device according to claim 1, wherein said third bus is coupled so that a means is connected to said first memory control means. Three or more processors including the first arithmetic processing means and the second arithmetic processing means;
The same number of memory control means as the processor, including the first memory control means and the second memory control means;
Connecting the processor and the memory control means, respectively, including the first bus and the second bus, and the same number of buses as the processor;
A connection bus connecting the two buses;
With
3. The semiconductor device according to claim 1, wherein the bus dividing unit is provided for each connection bus. 4. The semiconductor device according to claim 3, wherein the connection bus is formed in a ring shape and includes the same number of bus dividing means as the number of the processors. First memory control means for controlling access to the first memory;
Second memory control means for controlling access to the second memory;
Means for accessing the first memory and the second memory via the first memory control means and the second memory control means; and means for inspecting whether or not the first memory is abnormal. First arithmetic processing means comprising:
Means for operating in parallel with the first arithmetic processing means and accessing the first memory and the second memory via the first memory control means and the second memory control means; Second arithmetic processing means having means for inspecting whether there is an abnormality in the memory of 2,
A first bus connecting the first arithmetic processing means and the first memory control means;
A second bus connecting the second arithmetic processing means and the second memory control means;
A third bus connecting the first bus and the second bus;
A bus dividing means for dividing or coupling the third bus based on a predetermined control signal so as to switch the presence or absence of connection between the first bus and the second bus on the third bus;
With
When the first arithmetic processing means and the second arithmetic processing means have finished checking whether there is an abnormality in the first memory and the second memory, the bus dividing means is provided with the third bus. Sending the predetermined control signal requesting the combination of
The bus dividing means is configured such that the first arithmetic processing means is connected to the second memory control means based on the predetermined control signal requesting coupling of the third bus, and the second arithmetic processing is performed. A semiconductor device characterized in that said third bus is coupled so that means is connected to said first memory control means. A first memory;
A second memory;
A semiconductor device according to any one of claims 1 to 5;
With
The first arithmetic processing means of the semiconductor device inspects whether there is an abnormality in the first memory, and the second arithmetic processing means inspects whether there is an abnormality in the second memory. Information processing device. A first memory;
A second memory;
First arithmetic processing means having means for accessing the first memory and the second memory, and means for inspecting whether there is an abnormality in the first memory;
A second operation having means for accessing the first memory and the second memory, and means for inspecting whether or not the second memory is abnormal, operating in parallel with the first operation processing means; Processing means;
A first bus connecting between the first memory and the first arithmetic processing means;
A second bus connecting between the second memory and the second arithmetic processing means;
A third bus connecting the first bus and the second bus;
A bus dividing means for dividing or coupling the third bus based on a predetermined control signal so as to switch the presence or absence of connection between the first bus and the second bus on the third bus;
With
When inspecting whether there is an abnormality in the first memory and the second memory, at least one of the first arithmetic processing means and the second arithmetic processing means requests division of the third bus Sending the predetermined control signal to the bus dividing means,
The bus dividing means is configured such that, based on the predetermined control signal requesting division of the third bus, the first arithmetic processing means is not connected to the second memory, and the second arithmetic processing means The information processing apparatus divides the third bus so as to be disconnected from the first memory . A first arithmetic processing means connected to the first memory control means via the first bus and a second arithmetic processing means connected to the second memory control means via the second bus; When inspecting whether there is an abnormality in the first memory connected to the first memory control means and the second memory connected to the second memory control means,
When inspecting whether there is an abnormality in the first memory and the second memory, at least one of the first arithmetic processing means and the second arithmetic processing means has the first bus and the second memory A predetermined control signal requesting division of the third bus connected to the other bus,
Said first processing means said second memory control means and the non-connection state, such that the second processing means is disconnected and the first memory control means, said third bus divided based on the predetermined control signal,
The first arithmetic processing means checks whether the first memory is abnormal;
A method for inspecting a memory, wherein the second arithmetic processing means inspects whether there is an abnormality in the second memory. The first arithmetic processing means and the second arithmetic processing means request the connection of the third bus when the first memory and the second memory have been inspected for abnormality. Sending the predetermined control signal,
Based on the predetermined control signal requesting connection of the third bus, the first arithmetic processing means is connected to the second memory control means, and the second arithmetic processing means is the first 9. The memory inspection method according to claim 8, wherein the third bus is coupled so as to be connected to the memory control means. A first arithmetic processing means connected to the first memory control means via the first bus and a second arithmetic processing means connected to the second memory control means via the second bus; When inspecting whether there is an abnormality in the first memory connected to the first memory control means and the second memory connected to the second memory control means,
The first bus so that the first arithmetic processing means is disconnected from the second memory control means, and the second arithmetic processing means is disconnected from the first memory control means. Dividing a third bus connecting to the second bus based on a predetermined control signal;
The first arithmetic processing means checks whether the first memory is abnormal;
The second arithmetic processing means inspects whether there is an abnormality in the second memory;
The first arithmetic processing means and the second arithmetic processing means request the connection of the third bus when the first memory and the second memory have been inspected for abnormality. Sending the predetermined control signal,
Based on the predetermined control signal requesting connection of the third bus, the first arithmetic processing means is connected to the second memory control means, and the second arithmetic processing means is the first A method for inspecting a memory, wherein the third bus is coupled so as to be connected to a memory control means.

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