JP6237336B2 - Wide band gap semiconductor device - Google Patents

Description

  The present invention relates to a wide band gap semiconductor device. In particular, the present invention relates to a Schottky barrier diode.

  A Schottky barrier diode is a diode that applies a Schottky barrier generated by a junction between a metal and a semiconductor. The Schottky barrier diode has an advantage that a forward voltage drop is small and a high-speed response is possible.

  On the other hand, with respect to the Schottky barrier diode, a problem that the reverse leakage current is large and a problem that the reverse withstand voltage is low are conventionally known. In order to solve these problems, a Schottky barrier diode having a structure in which a plurality of junction barriers are provided at a Schottky junction interface has been proposed. Such a Schottky barrier diode is called a junction barrier Schottky diode (JBS).

  For example, Japanese Patent Laid-Open No. 52-24465 (Patent Document 1) discloses a JBS including a first semiconductor region, a plurality of second semiconductor regions, and a Schottky barrier electrode layer. The conductivity type of the second semiconductor region is opposite to the conductivity type of the first semiconductor region. The plurality of second semiconductor regions are arranged in the first semiconductor region at a predetermined interval. The electrode layer is disposed on the plurality of second semiconductor regions and the first semiconductor region sandwiched between the plurality of second semiconductor regions.

JP 52-24465 A

  Wide band gap semiconductors are being adopted as materials constituting semiconductor devices. A wide band gap semiconductor is a semiconductor having a larger band gap than silicon (Si).

  A wide band gap semiconductor can contribute to a high breakdown voltage of a semiconductor device and a reduction in resistance (for example, on-resistance). However, in order to improve the performance of the semiconductor device, it is possible not only to replace the material of the semiconductor device from silicon to a wide band gap semiconductor, but also to improve the structure of the semiconductor device.

  An object of the present invention is to provide a wide band gap semiconductor device capable of achieving a high breakdown voltage and a low resistance.

  In one aspect, a wide band gap semiconductor device of the present invention includes a wide band gap semiconductor layer, a first impurity region, a second impurity region, and a Schottky electrode. The wide band gap semiconductor layer includes a first main surface and a second main surface located on the opposite side of the first main surface, and has the first conductivity type. The first impurity region is disposed inside the wide band gap semiconductor layer so as to be in contact with the first main surface of the wide band gap semiconductor layer, and has the second conductivity type. The second impurity region is disposed inside the wide band gap semiconductor layer so as to be separated from the first main surface of the wide band gap semiconductor layer and the first impurity region, and has the second conductivity type. The Schottky electrode is disposed on the first main surface of the wide band gap semiconductor layer so as to be in contact with the first impurity region and the wide band gap semiconductor layer.

  According to the present invention, it is possible to provide a wide band gap semiconductor device capable of achieving a high breakdown voltage and a low resistance.

1 is a schematic plan view of a Schottky barrier diode 101 according to Embodiment 1 of the present invention. It is sectional drawing which showed the cross section of the Schottky barrier diode 101 along II-II of FIG. 2 is a cross-sectional view schematically showing a state of the Schottky barrier diode 101 when a reverse bias voltage is applied to the Schottky barrier diode 101 according to Embodiment 1 of the present invention. FIG. FIG. 4 is an energy band diagram of the Schottky barrier diode 101 corresponding to the state of the Schottky barrier diode 101 shown in FIG. 3. 2 is a cross-sectional view schematically showing a state of the Schottky barrier diode 101 when a larger reverse bias voltage is applied to the Schottky barrier diode 101 according to Embodiment 1 of the present invention. FIG. FIG. 6 is an energy band diagram of the Schottky barrier diode 101 corresponding to the state of the Schottky barrier diode 101 shown in FIG. 5. It is sectional drawing which showed typically the state from which the reverse bias voltage was removed from the Schottky barrier diode 101 which concerns on Embodiment 1 of this invention. FIG. 8 is an energy band diagram of the Schottky barrier diode 101 corresponding to the state of the Schottky barrier diode 101 shown in FIG. 7. 2 is a cross-sectional view of Schottky barrier diode 101 showing a state of Schottky barrier diode 101 when a forward bias voltage is applied to Schottky barrier diode 101 according to Embodiment 1 of the present invention after application of a reverse bias voltage. FIG. 2 is a cross-sectional view schematically showing a state of the Schottky barrier diode 101 when a forward current flows through the Schottky barrier diode 101 according to Embodiment 1 of the present invention. FIG. It is a schematic plan view of the Schottky barrier diode 102 according to the second embodiment of the present invention. It is sectional drawing which showed the cross section of the Schottky barrier diode 102 along XII-XII of FIG. It is sectional drawing which showed typically the state of the Schottky barrier diode 102 when a reverse bias voltage is applied to the Schottky barrier diode 102 which concerns on Embodiment 2 of this invention. It is a schematic plan view of the Schottky barrier diode 103 according to Embodiment 3 of the present invention. It is sectional drawing which showed the cross section of the Schottky barrier diode 103 along XV-XV of FIG. It is a schematic plan view of the Schottky barrier diode 104 according to the fourth embodiment of the present invention. It is sectional drawing which showed the cross section of the Schottky barrier diode 104 along XVII-XVII of FIG. It is sectional drawing which showed the cross section of the Schottky barrier diode 104 along XVIII-XVIII of FIG. It is a schematic plan view of the Schottky barrier diode 105 according to the fifth embodiment of the present invention. FIG. 20 is a cross-sectional view showing a cross section of the Schottky barrier diode 105 along XX-XX in FIG. 19. It is a schematic plan view of the Schottky barrier diode 106 according to the sixth embodiment of the present invention. It is a schematic plan view of the Schottky barrier diode 107 according to the seventh embodiment of the present invention. FIG. 23 is a cross-sectional view showing a cross section of a Schottky barrier diode 107 along XXIII-XXIII in FIG. 22. It is the elements on larger scale which expanded some cross sections of the Schottky barrier diode 107 shown in FIG. FIG. 10 is a partially enlarged view schematically illustrating a depletion layer 15 extending from a p-type buried region 4 when a forward bias voltage is applied to a Schottky barrier diode 107 according to a seventh embodiment of the present invention. FIG. 10 is a partial enlarged view schematically illustrating a depletion layer 15 extending from a p-type buried region 4 when a reverse bias voltage is applied to a Schottky barrier diode 107 according to a seventh embodiment of the present invention. It is a schematic plan view of the Schottky barrier diode 108 according to the eighth embodiment of the present invention. It is sectional drawing which showed the cross section of the Schottky barrier diode 108 along XXVIII-XXVIII of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  As used herein, “electrically connected” is not limited to the case where the direct connection of two elements causes electrical conduction between the two elements, but electrical conduction between the two elements. Includes the case of intervening another element disposed between the two elements.

[Description of Embodiment of Present Invention]
First, embodiments of the present invention will be listed and described.

  (1) The wide band gap semiconductor device according to the embodiment of the present invention includes a wide band gap semiconductor layer 1, a first impurity region 2, a second impurity region 4, and a Schottky electrode 6. Wide band gap semiconductor layer 1 includes a first main surface 1A and a second main surface 10B located on the opposite side of first main surface 1A, and has a first conductivity type. The first impurity region 2 is disposed inside the wide band gap semiconductor layer 1 so as to be in contact with the first main surface 1A of the wide band gap semiconductor layer 1 and has the second conductivity type. The second impurity region 4 is disposed inside the wide band gap semiconductor layer 1 so as to be separated from the first main surface 1A of the wide band gap semiconductor layer 1 and the first impurity region 2, and the second impurity region 4 Has conductivity type. Schottky electrode 6 is arranged on first main surface 1A of wide band gap semiconductor layer 1 so as to be in contact with first impurity region 2 and wide band gap semiconductor layer 1.

  According to the above configuration, it is possible to provide a wide band gap semiconductor device that can achieve high breakdown voltage and low resistance. First impurity region 2 and second impurity region 4 have a conductivity type opposite to that of wide band gap semiconductor layer 1. When a reverse bias voltage is applied to the wide band gap semiconductor device, the depletion layer spreads from the junction surface between the wide band gap semiconductor layer 1 and the first impurity region 2, and the second impurity region 4 and the wide band gap semiconductor layer The depletion layer spreads from the joint surface with 1. These depletion layers can protect the interface (Schottky junction interface) between the wide band gap semiconductor layer 1 and the Schottky electrode 6.

  By protecting the Schottky junction interface, leakage current can be reduced. Therefore, it is possible to provide a wide band gap semiconductor device that can achieve a high breakdown voltage.

  (2) Preferably, the second impurity region 4 is arranged at a position not overlapping the first impurity region 2 in plan view.

  According to the above configuration, it is possible to make it difficult to disturb the current when the forward bias voltage is applied to the wide band gap semiconductor device. Therefore, an increase in resistance of the wide band gap semiconductor device can be suppressed.

  The “plan view” means a visual field viewed along a direction perpendicular to the main surface 1 </ b> A of the wide band gap semiconductor layer 1.

  (3) Preferably, at least a part of the second impurity region 4 is disposed at a position overlapping the first impurity region 2 in plan view.

  According to the above configuration, when the reverse bias voltage is applied to the wide band gap semiconductor device, the second band of the wide band gap semiconductor layer 1 is formed from the junction surface between the wide band gap semiconductor layer 1 and the first impurity region 2. A depletion layer extends toward main surface 10B. This depletion layer is easily connected to the depletion layer extending from the junction surface between the second impurity region 4 and the wide band gap semiconductor layer 1 to the wide band gap semiconductor layer 1 side. Thereby, the Schottky junction interface can be more reliably protected. Therefore, the breakdown voltage of the wide band gap semiconductor can be maintained.

  (4) Preferably, the first impurity region 2 has a first stripe shape in plan view. In plan view, the second impurity region 4 has a second stripe shape. The first stripe shape includes a major axis along a first direction Y parallel to the first main surface 1A, and a second axis that is parallel to the first main surface 1A and perpendicular to the first direction Y. A minor axis extending along the direction X. The second stripe shape includes a major axis along one of the first direction Y and the second direction X, and a minor axis along the other of the first direction Y and the second direction X. Have In plan view, a part of the second impurity region 4 overlaps the first impurity region 2.

  According to the above configuration, a part of the second impurity region 4 overlaps the first impurity region 2 in plan view. Thereby, the depletion layer extending from the junction surface between the wide band gap semiconductor layer 1 and the first impurity region 2 toward the second main surface 10B of the wide band gap semiconductor layer 1, and the second impurity region 4 The depletion layer extending from the joint surface with the wide band gap semiconductor layer 1 to the wide band gap semiconductor layer 1 side is easily connected. Thereby, the Schottky junction interface can be more reliably protected. Therefore, the breakdown voltage of the wide band gap semiconductor can be maintained.

  The “stripe shape” is not particularly limited as long as it is a two-dimensional shape having a major axis and a minor axis. Stripe shapes can include, but are not limited to, rectangles, ellipses, rectangles with rounded corners, and the like.

  (5) Preferably, the long axis of the second stripe shape extends along the first direction Y. The minor axis of the second stripe shape extends along the second direction X. In plan view, the end portion of the second impurity region 4 in the second direction X overlaps the end portion of the first impurity region 2 in the second direction X.

  According to the above configuration, the breakdown voltage of the wide band gap semiconductor can be maintained. Furthermore, the distance between the first impurity region 2 and the second impurity region 4 can be shortened. Therefore, carriers (for example, holes) can be effectively injected from the first impurity region 2 to the second impurity region 4 when a forward bias voltage is applied to the wide band gap semiconductor device. Thereby, the electrical neutrality of the second impurity region 4 can be recovered more quickly. Therefore, the response speed of the wide band gap semiconductor device can be increased.

  (6) Preferably, the second stripe shape includes a first portion 41 and a second portion 42. The first portion 41 has a major axis along the first direction Y and a minor axis along the second direction X. The second portion 42 protrudes from the first portion along the second direction X. In plan view, at least part of the second portion 42 in the second impurity region 4 overlaps the first impurity region 2.

  According to the above configuration, the breakdown voltage of the wide band gap semiconductor can be maintained. Furthermore, it is possible not to overlap the first stripe shape with the first stripe shape (shift from the first stripe shape). Therefore, an increase in resistance of the wide band gap semiconductor device can be suppressed.

  (7) Preferably, in a plan view, the second impurity region 4 and the first impurity region 2 are arranged so that the long axis of the first stripe shape and the long axis of the second stripe shape intersect each other. overlapping.

  According to the above configuration, a part of the second stripe shape can be overlapped with the first stripe shape. Therefore, the breakdown voltage of the wide band gap semiconductor can be maintained.

  (8) Preferably, in the wide band gap semiconductor device according to any one of (3) to (5) above, one of the first impurity region 2 and the second impurity region 4 is not It overlaps with the other of the first impurity region 2 and the second impurity region 4.

  According to the above configuration, the depletion layer extending from the junction surface between the wide band gap semiconductor layer 1 and the first impurity region 2 toward the second main surface 10B of the wide band gap semiconductor layer 1, and the second impurity The depletion layer extending from the junction surface between the region 4 and the wide band gap semiconductor layer 1 toward the wide band gap semiconductor layer 1 is easily connected. Thereby, the Schottky junction interface can be more reliably protected. Therefore, the breakdown voltage of the wide band gap semiconductor can be maintained.

  (9) Preferably, the wide band gap semiconductor device further includes a third impurity region 7. The third impurity region 7 is arranged inside the wide band gap semiconductor layer 1 so as to be aligned with the second impurity region 4 along the direction X parallel to the first main surface 1A, and the first conductive region 7 Has a mold. The third impurity region 7 is located around the third impurity region 7 in the wide band gap semiconductor layer 1 and has an impurity concentration higher than that of the portion having the first conductivity type.

  According to the above configuration, the third impurity region 7 can suppress the spread of the depletion layer from the second impurity region 4 in the lateral direction (direction parallel to the first main surface 1A). Furthermore, the resistance in the wide band gap semiconductor layer 1 can be lowered. Therefore, the resistance of the wide band gap semiconductor device can be lowered. “Aligned with the second impurity region 4 along the direction X parallel to the first main surface 1A” means in the direction (depth direction) from the first main surface 1A to the second main surface 10B. This means that the position of the end portion of the third impurity region 7 on the first main surface 1A side coincides with the position of the junction surface of the second impurity region 4 (depth of the second impurity region 4). It is not limited to be. The position of the end of the third impurity region 7 on the first main surface 1A side may be shifted from the position of the bonding surface of the second impurity region 4 in the depth direction.

  (10) Preferably, the third impurity region 7 includes a first end portion 7A located on the first main surface 1A side and a second end portion 7B located on the second main surface 10B side. Have. The first impurity region 7 in the depth direction in which the bonding surface of the second impurity region 4 facing the first main surface 1A is directed from the first main surface 1A to the second main surface 10B. Of the third impurity region 7 to the position of the second end 7B of the third impurity region 7.

  According to the above configuration, when a forward bias voltage is applied to the wide band gap semiconductor device, the depletion layer can be more effectively spread from the second impurity region 4 in the lateral direction (direction parallel to the main surface 1A). Can be suppressed. Therefore, the resistance of the wide band gap semiconductor device can be lowered.

(11) Preferably, the second impurity region 4 is electrically floating.
According to the above configuration, the potential of the second impurity region 4 becomes high when a reverse bias voltage is applied to the wide band gap semiconductor device. As a result, the depletion layer easily extends from the first impurity region 2. Therefore, the breakdown voltage can be maintained.

  (12) Preferably, second impurity region 4 is electrically connected to Schottky electrode 6.

  According to the above configuration, since the potential of the second impurity region 4 is fixed, the operation of the wide band gap semiconductor device can be stabilized. Furthermore, as a result of the second impurity region 4 being electrically connected to the Schottky electrode 6, carriers (for example, holes) can be more effectively injected into the second impurity region 4. Therefore, a high-speed response can be realized.

  (13) Preferably, the distance between the first impurity region 2 and the second impurity region 4 is 5 μm or less.

  According to the above configuration, depletion of the second impurity region 4 can be eliminated by injecting carriers (for example, holes) from the first impurity region 2 to the second impurity region 4, and the second impurity region 4 Can be restored.

  (14) Preferably, the distance between the first impurity region 2 and the second impurity region 4 is 2 μm or less.

  According to the above configuration, depletion of the second impurity region 4 can be eliminated at a higher speed, and the potential of the second impurity region 4 can be recovered at a higher speed.

(15) Preferably, wide band gap semiconductor layer 1 includes silicon carbide.
According to the above configuration, a silicon carbide semiconductor device having a high breakdown voltage and a low resistance can be realized.

[Details of the embodiment of the present invention]
The wide band gap semiconductor device according to each embodiment described below is a Schottky barrier diode, more specifically, a junction barrier Schottky diode (JBS).

<Embodiment 1>
FIG. 1 is a schematic plan view of a Schottky barrier diode 101 according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view showing a cross section of the Schottky barrier diode 101 along II-II in FIG.

  Referring to FIGS. 1 and 2, Schottky barrier diode 101 according to the first embodiment of the present invention includes a wide band gap semiconductor layer 1, a plurality of p-type regions 2, p-type regions 21 and 22, A plurality of p-type buried regions 4, an insulating film 5, a Schottky electrode 6, an anode electrode 8, and a cathode electrode 9 are provided.

  The wide band gap semiconductor layer 1 is a semiconductor layer including a wide band gap semiconductor. In this embodiment, the wide band gap semiconductor layer 1 is a semiconductor layer containing silicon carbide (SiC).

  The wide band gap semiconductor layer 1 includes two layers. The first layer is the drift layer 12. The second layer is silicon carbide substrate 10.

  Silicon carbide substrate 10 is, for example, a hexagonal silicon carbide single crystal having polytype 4H. Silicon carbide substrate 10 has a first main surface 10A and a second main surface 10B. Second main surface 10B is located on the opposite side to first main surface 10A. Silicon carbide substrate 10 has n type (first conductivity type) as a conductivity type.

  Drift layer 12 is a layer of silicon carbide provided on first main surface 10 </ b> A of silicon carbide substrate 10. Drift layer 12 is formed on first main surface 10A of silicon carbide substrate 10 by, for example, epitaxial growth. Drift layer 12 has n-type conductivity. The impurity concentration of drift layer 12 may be lower than the impurity concentration of silicon carbide substrate 10.

  Wide band gap semiconductor layer 1 has a first main surface and a second main surface. The second main surface is located on the opposite side to the main surface of the first main surface. In this embodiment, the main surface 1 </ b> A corresponds to the first main surface of the wide band gap semiconductor layer 1. On the other hand, second main surface 10 </ b> B of silicon carbide substrate 10 corresponds to the second main surface of wide band gap semiconductor layer 1. In other words, the drift layer 12 is in contact with the first main surface (main surface 1A) of the wide band gap semiconductor layer 1. Silicon carbide substrate 10 is in contact with second main surface (10B) of wide band gap semiconductor layer 1 and in contact with drift layer 12.

  As shown in FIG. 2, a part of the main surface 1 </ b> A is covered with an insulating film 5. However, in FIG. 1, the insulating film 5 is not shown in order to clearly show the main surface 1A. The same applies to the plan view of the Schottky barrier diode according to each embodiment described below.

  Each of the plurality of p-type regions 2 and p-type regions 21 and 22 is arranged inside wide band gap semiconductor layer 1 so as to be in contact with main surface 1A of wide band gap semiconductor layer 1. More specifically, each of the plurality of p-type regions 2 and p-type regions 21 and 22 is arranged inside drift layer 12.

  One end of each of the plurality of p-type regions 2 is connected to p-type region 21. The other end of each of the plurality of p-type regions 2 is connected to p-type region 22. The plurality of p-type regions 2 and p-type regions 21 and 22 form one p-type region 2A. The p-type regions 21 and 22 can be arranged inside the drift layer 12 by the same manufacturing process as the plurality of p-type regions 2. Note that the p-type regions 21 and 22 are not essential.

  Each of the plurality of p-type buried regions 4 is arranged inside the wide band gap semiconductor layer 1 so as to be separated from the main surface 1A of the wide band gap semiconductor layer 1 and the plurality of p type regions 2. Further, each of the plurality of p type buried regions 4 is also separated from first main surface 10 </ b> A of silicon carbide substrate 10. Therefore, the plurality of p-type buried regions 4 are arranged inside the drift layer 12.

  The p-type region 2A (each of the plurality of p-type regions 2 and p-type regions 21 and 22) has a conductivity type different from the n-type, that is, p-type (second conductivity type). Similarly, each of the plurality of p-type buried regions 4 has p-type conductivity. In one embodiment, the impurity (acceptor) concentration of the p-type region 2 </ b> A is higher than the impurity concentration of each p-type buried region 4. Furthermore, the impurity concentration of the p-type region 2A and the impurity concentration of each p-type buried region 4 are higher than the impurity (donor) concentration of the drift layer 12. However, the relationship among the impurity concentration of p-type region 2A, the impurity concentration of each p-type buried region 4 and the impurity concentration of drift layer 12 is not limited in this way. Further, the impurity concentration of the p-type region 2 and the impurity concentration of the p-type region 21 or the p-type region 22 are not limited to be the same.

  As shown in FIG. 1, each of the plurality of p-type regions 2 has a stripe shape in plan view. Similarly, in plan view, each of the plurality of p-type buried regions 4 has a stripe shape. “Plan view” means a visual field viewed along a direction perpendicular to the main surface 1A of the wide band gap semiconductor layer 1. The “striped shape” means a two-dimensional shape having a major axis and a minor axis.

  In the embodiment of the present invention, the stripe shape is a rectangle. The direction of the long axis of the rectangle is equal to the direction of the long side of the rectangle. Similarly, the direction of the short axis of the rectangle is equal to the direction of the short side of the rectangle. Therefore, in the following, the term “long side” is used instead of the long axis, and the term “short side” is used instead of the short axis. Note that the rectangle is one embodiment of a stripe shape. The stripe shape can include, but is not limited to, for example, an ellipse, a rectangle with rounded corners, and the like.

  The Y direction and the X direction shown in FIG. 1 are directions parallel to the main surface 1A of the wide band gap semiconductor layer 1. Furthermore, the X direction is orthogonal to the Y direction.

  In plan view, the long side of each p-type region 2 (first stripe shape) and the long side of each p-type buried region 4 (second stripe shape) extend along the same direction (Y direction). To do. Accordingly, in plan view, the short side of each p-type region 2 (first stripe shape) and the short side of each p-type buried region 4 (second stripe shape) extend along the same direction (X direction). Exists.

  Further, the plurality of p-type regions 2 and the plurality of p-type buried regions 4 are alternately arranged in the direction along the short side of the rectangle, that is, in the X direction. In the first embodiment, the p-type region 2 and the p-type buried region are arranged so that the p-type buried region 4 (second stripe shape) does not overlap the p-type region 2 (first stripe shape) in plan view. Region 4 is arranged.

  The distance d1 shown in FIG. 2 is a distance in the X direction between the p-type region 2 and the p-type buried region 4 closest to the p-type region 2. The distance d2 is a distance (preferably the shortest distance) between one p-type region 2 and the p-type buried region 4 closest to the p-type region 2. For example, the magnitude of the component in the X direction of the distance d2 is equal to the distance d1. The distance d2 is 5 μm or less, more preferably 2 μm or less.

  Schottky electrode 6 is arranged on main surface 1 </ b> A of wide band gap semiconductor layer 1. Schottky electrode 6 is in contact with p-type region 2 </ b> A (each of a plurality of p-type regions 2 and p-type regions 21 and 22) and wide band gap semiconductor layer 1. The Schottky electrode 6 is made of a metal that forms a Schottky junction with the drift layer 12. The material of Schottky electrode 6 is not particularly limited as long as it is a metal that can achieve a Schottky junction with drift layer 12, that is, the n-type silicon carbide semiconductor layer. The Schottky electrode 6 can include, for example, titanium (Ti), nickel (Ni), titanium nitride (TiN), gold (Au), molybdenum (Mo), tungsten (W), and the like.

  The insulating film 5 is disposed on the main surface 1A of the wide band gap semiconductor layer. As shown in FIG. 2, for example, the insulating film 5 is arranged so as to cover a part of the surface of the p-type region 2 arranged on the outermost side among the plurality of p-type regions 2 arranged along the X direction. The Further, a part of the Schottky electrode 6 is disposed on the insulating film 5.

  Furthermore, the insulating film 5 may be disposed so as to cover at least a part of the surface of the p-type regions 21 and 22. That is, contact holes for bringing Schottky electrode 6 into contact with the surface of drift layer 12 and the surface of p-type region 2 may be formed in insulating film 5.

  The anode electrode 8 is superimposed on the Schottky electrode 6. Thereby, the anode electrode 8 is electrically connected to the Schottky electrode 6. The anode electrode 8 may be made of aluminum, for example.

  Cathode electrode 9 is arranged in contact with second main surface 10B of silicon carbide substrate 10 (second main surface of wide band gap semiconductor layer 1). As a result, the cathode electrode 9 is electrically connected to the wide band gap semiconductor layer 1. Cathode electrode 9 may be made of a material that can be in ohmic contact with n-type silicon carbide substrate 10, such as nickel.

  FIG. 3 is a cross-sectional view schematically showing the state of the Schottky barrier diode 101 when a reverse bias voltage is applied to the Schottky barrier diode 101 according to Embodiment 1 of the present invention. FIG. 4 is an energy band diagram of the Schottky barrier diode 101 corresponding to the state of the Schottky barrier diode 101 shown in FIG. FIG. 4 shows an energy band diagram in a direction along the line IX-IX in FIG.

  Referring to FIGS. 3 and 4, a reverse bias voltage is applied between anode electrode 8 and cathode electrode 9, and the potential of cathode electrode 9 becomes higher than the potential of anode electrode 8. A depletion layer 15 extends from the junction surface between p-type region 2 and drift layer 12 and from the junction surface between p-type buried region 4 and drift layer 12. The impurity concentration of drift layer 12 is lower than the impurity concentration of p-type region 2 and the impurity concentration of p-type buried region 4. For this reason, the depletion layer 15 is further expanded toward the drift layer 12 side.

  Referring to FIG. 4, “Ev” and “Ec” indicate the upper end of the valence band and the lower end of the conduction band, respectively. “Ef” indicates the Fermi level. In the p-type region 2, the p-type buried region 4, and the region that is not depleted in the drift layer 12, the electrical neutral condition is satisfied by carriers and space charges. The carriers in p-type region 2 and p-type buried region 4 are holes. On the other hand, carriers in the drift layer 12 are electrons. Since carriers do not exist in the depletion layer 15, an electric field due to space charge is generated in the depletion layer 15.

  FIG. 5 is a cross-sectional view schematically showing the state of Schottky barrier diode 101 when a larger reverse bias voltage is applied to Schottky barrier diode 101 according to Embodiment 1 of the present invention. FIG. 6 is an energy band diagram of the Schottky barrier diode 101 corresponding to the state of the Schottky barrier diode 101 shown in FIG. FIG. 6 shows an energy band diagram in the direction along the line VI-VI in FIG.

  Referring to FIGS. 5 and 6, the reverse bias voltage applied to Schottky barrier diode 101 is increased, so that the wide band gap semiconductor layer 1 is The depletion layer extends toward the main surface side of 2. This depletion layer reaches the depletion layer 15 extending from the junction surface between the p-type buried region 4 and the drift layer 12 toward the drift layer 12. In the following description, “downward” or “depth direction” refers to a direction from the first main surface of the wide band gap semiconductor layer 1 toward the second main surface of the wide band gap semiconductor layer 1. Point to. On the other hand, “upward” refers to a direction from the second main surface of the wide band gap semiconductor layer 1 toward the first main surface of the wide band gap semiconductor layer 1.

  In the p-type buried region 4, some or all of the carriers are lost. When some carriers are lost, a part of the p-type buried region 4 is depleted. On the other hand, when all carriers are lost, the entire p-type buried region 4 is depleted. In both cases, the p-type buried region 4 is charged to a negative voltage by the space charge remaining in the p-type buried region 4.

  FIG. 7 is a cross-sectional view schematically showing a state where the reverse bias voltage is removed from the Schottky barrier diode 101 according to the first embodiment of the present invention. FIG. 8 is an energy band diagram of the Schottky barrier diode 101 corresponding to the state of the Schottky barrier diode 101 shown in FIG. FIG. 8 shows an energy band diagram in the direction along the line VII-VII in FIG.

  Referring to FIGS. 7 and 8, the reverse bias voltage is removed from Schottky barrier diode 101, and the voltage between cathode electrode 9 and anode electrode 8 becomes 0V. The space between the cathode electrode 9 and the anode electrode 8 may be open. The conductivity type of the drift layer 12 is n-type. Electrons quickly flow into the drift layer 12 to restore the electrical neutrality of the drift layer 12.

  However, holes are not positively injected into the p-type buried region 4. Therefore, when the p-type buried region 4 is completely depleted, or when the conductive region remains in a part of the p-type buried region 4, the potential of the p-type buried region 4 is negative. There is a possibility of being maintained at a potential.

  Since the p-type buried region 4 has a negative potential, the depletion layer 15 remains around the p-type buried region 4. When the voltage between the cathode electrode 9 and the anode electrode 8 is 0 V, the depletion layer 15 extending from the junction surface between the p-type buried region 4 and the drift layer 12 is gradually reduced. Since the depletion layer 15 remains, a path through which electrons pass (in other words, a path through which current flows) is narrowed. Therefore, the resistance of the Schottky barrier diode 101 is increased.

  FIG. 9 is a cross section of the Schottky barrier diode 101 showing the state of the Schottky barrier diode 101 when a forward bias voltage is applied to the Schottky barrier diode 101 according to Embodiment 1 of the present invention after application of the reverse bias voltage. FIG. Referring to FIG. 9, a forward bias voltage is applied between anode electrode 8 and cathode electrode 9, and the potential of anode electrode 8 becomes higher than the potential of cathode electrode 9. Holes (represented by “h” in FIG. 9) are injected from p-type region 2 into p-type buried region 4.

  By injecting holes into the p-type buried region 4, the depletion layer 15 extending from the junction surface between the p-type buried region 4 and the drift layer 12 is reduced to widen the current path. Therefore, the resistance of the Schottky barrier diode 101 can be reduced. Since the energy band diagram representing the state of Schottky barrier diode 101 shown in FIG. 9 is similar to the energy band diagram shown in FIG. 4, detailed description thereof will not be repeated.

  You may apply the Schottky barrier diode which concerns on embodiment of this invention to the freewheel diode connected to the semiconductor switching element which comprises an inverter in antiparallel. In such a case, the forward bias voltage and the reverse bias voltage are alternately applied to the Schottky barrier diode 101 as described above.

  FIG. 10 is a cross-sectional view schematically showing the state of the Schottky barrier diode 101 when a forward current flows through the Schottky barrier diode 101 according to Embodiment 1 of the present invention. Referring to FIG. 10, arrows represent current. By applying a forward bias voltage to the Schottky barrier diode 101, a current flows from the anode electrode 8 through the wide band gap semiconductor layer 1 to the cathode electrode 9.

  According to the first embodiment, the p-type buried region 4 is provided in the wide band gap semiconductor layer 1 so as to be separated from the p-type region 2. As shown in FIG. 5, when a reverse bias voltage is applied to Schottky barrier diode 101, depletion layer 15 extends downward from the junction surface between p-type region 2 and drift layer 12. Further, the depletion layer 15 extends from the junction surface between the p-type buried region 4 and the drift layer 12 to the drift layer 12 side. By connecting these depletion layers 15, it is possible to protect the Schottky junction interface (the interface between the Schottky electrode 6 and the wide band gap semiconductor layer 1). In FIG. 5, a depletion layer formed by connecting these depletion layers is represented as a depletion layer 15.

  By protecting the Schottky junction interface, leakage current can be reduced when a reverse bias voltage is applied to the Schottky barrier diode 101. Therefore, according to the first embodiment, the breakdown voltage of the Schottky barrier diode 101 can be improved as compared with the prior art.

  For example, the rated reverse bias voltage of the Schottky barrier diode 101 can be set to 1000V to 3000V. This rated reverse bias voltage is sufficiently higher than the rated reverse bias voltage of a Schottky barrier diode made of silicon.

  Furthermore, according to the first embodiment, the potential of p type buried region 4 is set to a floating state. As a result, when a reverse bias is applied to the Schottky barrier diode 101, the potential of the p-type buried region 4 tends to increase. Therefore, since the depletion layer 15 tends to extend downward from the p-type region 2, a Schottky barrier diode that achieves a high breakdown voltage can be realized.

  When the rated reverse bias is applied to the Schottky barrier diode 101, the p-type buried region 4 may be completely depleted. In this case, the parasitic capacitance of the Schottky barrier diode 101 can be reduced. In order to completely deplete the p-type buried region 4, it is preferable that the impurity concentration of the p-type buried region 4 is low and the distance of the p-type buried region 4 from the Schottky junction interface is small.

  On the other hand, part of the p-type buried region 4 may be depleted when a rated reverse bias is applied to the Schottky barrier diode 101. In this case, the depletion layer can be further expanded from the junction surface between the p-type buried region 4 and the drift layer 12 to the drift layer 12 side. Therefore, the breakdown voltage of the Schottky barrier diode 101 can be ensured. In order to deplete part of the p-type buried region 4, the impurity concentration of the p-type buried region 4 may be increased, and the distance of the p-type buried region 4 from the Schottky junction interface is increased. Also good.

  The width of the depletion layer in the p-type buried region 4 is obtained by substituting the impurity concentration of the drift layer 12, the impurity concentration of the p-type buried region 4 and the rated reverse bias voltage of the Schottky barrier diode 101 into Poisson's equation. And can be obtained in advance. Therefore, when the rated reverse bias is applied to Schottky barrier diode 101, it is designed in advance whether all of p type buried region 4 is depleted or part of p type buried region 4 is depleted. It is possible.

The distance d2 between the p-type region 2 and the p-type buried region 4 is preferably 5 μm or less. For example, according to PA Ivanov et al., “High Hole lifetime (3.8μs) in 4H-SiC diodes with 5.5kV blocking voltage”, Electronic letters, 1999, Vol. 35, No. 16, pages 1382 to 1383 The lifetime of holes in a 4H-SiC diode with a withstand voltage of 5.5 kV is 0.6 to 3.8 μs (300 to 550 K), and the diffusion length of holes is 16 to 22 μm (impurity concentration: 6 × 10 ¹⁴ cm ⁻³ ). It is. By setting the distance d2 between the p-type region 2 and the p-type buried region 4 to 5 μm or less, holes can be injected from the p-type region 2 into the p-type buried region 4. Thereby, elimination of depletion of p-type buried region 4 and potential recovery can be achieved when switching from reverse bias to forward bias.

  More preferably, the distance d2 between the p-type region 2 and the p-type buried region 4 is 2 μm or less. From the above document, it can be expected that depletion of the p-type buried region 4 and potential recovery can be achieved in a time of several tens ns (nanoseconds) or less by setting the distance d2 to 2 μm or less. Therefore, the Schottky barrier diode 101 can respond at high speed.

  Furthermore, it is preferable that the Schottky electrode 6 is ohmic-bonded to the p-type region 2. As a result, when the bias voltage of the Schottky barrier diode 101 is switched from the reverse bias voltage to the forward bias voltage, more holes can be injected from the p-type region 2 into the p-type buried region 4. Therefore, the Schottky barrier diode 101 can respond at high speed.

  Furthermore, according to the first embodiment, p type buried region 4 is arranged at a position that does not overlap p type region 2 in plan view. More specifically, there is a gap between the p-type region 2 and the p-type buried region 4 in plan view (see FIG. 1). Since the portion corresponding to the gap is a part of the drift layer 12, a forward current can flow. This makes it difficult to prevent forward current when a forward bias voltage is applied to the Schottky barrier diode 101. Therefore, an increase in resistance of the Schottky barrier diode 101 can be suppressed.

  As described above, according to the first embodiment, a Schottky barrier diode capable of obtaining a high breakdown voltage while suppressing an increase in resistance can be realized by a wide band gap semiconductor. Therefore, according to the first embodiment, a wide band gap semiconductor device having a high breakdown voltage and a low resistance can be realized.

<Embodiment 2>
FIG. 11 is a schematic plan view of the Schottky barrier diode 102 according to the second embodiment of the present invention. 12 is a cross-sectional view showing a cross section of the Schottky barrier diode 102 along XII-XII of FIG.

  Referring to FIGS. 11 and 12, in the second embodiment, p-type buried region 4 (second stripe shape) partially overlaps p-type region 2 (first stripe shape) in plan view. In addition, p-type region 2 and p-type buried region 4 are arranged.

  As in the first embodiment, the long side of each p-type region 2 (first stripe shape) and the long side of each p-type buried region 4 (second stripe shape) are in the same direction (Y direction). Along. Accordingly, in plan view, the short side of each p-type region 2 (first stripe shape) and the short side of each p-type buried region 4 (second stripe shape) are along the same direction (X direction). . In plan view, the end of the p-type buried region 4 in the X direction overlaps the end of the p-type region 2 in the X direction. That is, the ends of the p-type region 2 and the p-type buried region 4 in the X direction overlap each other in plan view.

  Referring to FIG. 12, distance d <b> 3 corresponds to the length of the overlapping portion in the X direction between p-type region 2 and p-type buried region 4 closest to p-type region 2. The distance d4 corresponds to the distance between the p-type region 2 and the p-type buried region 4 closest to the p-type region 2. From the viewpoint of withstand voltage or resistance, the distance d3 is set to an appropriate value of 0 or more. As in the first embodiment, from the viewpoint of hole injection from the p-type region 2 to the p-type buried region 4, the distance d4 is preferably 5 μm or less. More preferably, the distance d4 is 2 μm or less.

  FIG. 13 is a cross-sectional view schematically showing the state of the Schottky barrier diode 102 when a reverse bias voltage is applied to the Schottky barrier diode 102 according to Embodiment 2 of the present invention. Referring to FIG. 13, when a reverse bias voltage is applied to Schottky barrier diode 102, depletion layer 15 extending downward from the junction surface between p type region 2 and drift layer 12, p type buried region 4 and drift The depletion layer 15 extending to the drift layer 12 from the junction surface with the layer 12 can be easily connected. Thereby, the Schottky junction interface can be more reliably protected when a reverse bias voltage is applied to the Schottky barrier diode 102. Therefore, the breakdown voltage of the Schottky barrier diode 102 can be maintained. In FIG. 13, the entire depletion layer formed by connecting these depletion layers is represented as a depletion layer 15.

  Further, since part of p-type region 2 and p-type buried region 4 overlaps in plan view, the distance between p-type region 2 and p-type buried region 4 can be shortened. Therefore, when a forward bias voltage is applied to the Schottky barrier diode 102, holes can be effectively injected from the p-type region 2 into the p-type buried region 4. Thereby, the electrical neutrality of the p-type buried region 4 can be recovered more quickly. Therefore, the response speed of the Schottky barrier diode can be increased.

  As described above, according to the second embodiment, as in the first embodiment, a Schottky barrier diode capable of obtaining a high breakdown voltage while suppressing an increase in resistance can be realized by a wide band gap semiconductor. .

<Embodiment 3>
FIG. 14 is a schematic plan view of the Schottky barrier diode 103 according to Embodiment 3 of the present invention. FIG. 15 is a cross-sectional view showing a cross section of the Schottky barrier diode 103 along XV-XV in FIG.

  Referring to FIGS. 14 and 15, p type buried region 4 (second stripe shape) includes a first portion 41 and a second portion 42. The first portion 41 corresponds to the p-type buried region 4 included in the Schottky barrier diode 101 according to the first embodiment. Therefore, in a plan view, the first portion 41 has a major axis along the Y direction and a minor axis along the X direction. The second portion 42 protrudes from the first portion 41 along the X direction in plan view.

  In plan view, part of the second portion 42 of the p-type buried region 4 is overlapped with the p-type region 2. The whole second portion 42 may be overlaid on the p-type region 2 in plan view.

  The arrangement of the second portion 42 in the p-type buried region 4 is not limited as shown in FIG. For example, the plurality of second portions 42 may be arranged so that the plurality of second portions 42 are connected to each other.

  The number of the second portions 42 included in one p-type buried region 4 is not particularly limited as long as it is 1 or more. One p-type buried region 4 may have a plurality of second portions 42.

  The distance d5 corresponds to the length of the overlapping portion in the X direction between the p-type region 2 and the p-type buried region 4 closest to the p-type region 2. The distance d6 corresponds to the distance in the X direction between the p-type region 2 and the nearest p-type buried region 4 that is separated from the p-type region 2 in the X direction. The distance d7 corresponds to the distance between the p-type region 2 and the p-type buried region 4 closest to the p-type region 2.

  The distance d5 may be the same as the distance d3 shown in FIG. The distance d6 may be the same as the distance d1 shown in FIG. The distance d7 may be the same as the distance d4 shown in FIG. Similar to the first embodiment, from the viewpoint of hole injection from the p-type region 2 to the p-type buried region 4, the distance d7 is preferably 5 μm or less. More preferably, the distance d7 is 2 μm or less.

  According to the third embodiment, the effects of both the first and second embodiments can be obtained. As in the first embodiment, Schottky barrier diode 103 has a portion in which a gap is provided between p-type region 2 and first portion 41 of p-type buried region 4 in plan view. Since the portion corresponding to the gap is a part of the drift layer 12, a forward current can flow. Therefore, according to the third embodiment, an increase in resistance of Schottky barrier diode 103 can be suppressed.

  In addition, when a reverse bias voltage is applied to the Schottky barrier diode 103, the depletion layer 15 extending downward from the junction surface between the p-type region 2 and the drift layer 12 and the p-type buried region 4 (second It is possible to easily connect the depletion layer 15 extending from the joint surface between the portion 42) and the drift layer 12 to the drift layer 12 side. Thereby, the Schottky junction interface can be more reliably protected when a reverse bias voltage is applied to the Schottky barrier diode 103. Therefore, the breakdown voltage of the Schottky barrier diode 103 can be maintained.

  Furthermore, holes can be effectively injected from the p-type region 2 into the p-type buried region 4 when a forward bias voltage is applied to the Schottky barrier diode 103. As a result, the response speed of the Schottky barrier diode 103 can be increased.

<Embodiment 4>
FIG. 16 is a schematic plan view of the Schottky barrier diode 104 according to the fourth embodiment of the present invention. 17 is a cross-sectional view showing a cross section of the Schottky barrier diode 104 along XVII-XVII in FIG. 18 is a cross-sectional view showing a cross section of the Schottky barrier diode 104 along XVIII-XVIII in FIG.

  Referring to FIGS. 16 to 18, the long side of p type buried region 4 (second stripe shape) is in the X direction (second direction) in plan view. Therefore, the direction of the long side (Y direction) of the p-type region 2 (first stripe shape) and the direction of the long side of the p-type buried region 4 (second stripe shape) intersect. In this respect, the Schottky barrier diode 104 is different from the Schottky barrier diode 101.

  17 and 18 show the distance d8. The distance d8 is a distance between the p-type region 2 and the p-type buried region 4 closest to the p-type region 2. The distance d8 may be the same as the distance d4 shown in FIG. From the viewpoint of effectively injecting holes from the p-type region 2 to the p-type buried region 4, the distance d8 is preferably 5 μm or less as in the first to third embodiments. More preferably, the distance d8 is 2 μm or less.

  According to the fourth embodiment, the same effect as in the third embodiment can be obtained. Schottky barrier diode 104 has a portion in which a gap is provided between p type region 2 and p type buried region 4 in plan view. Therefore, according to the fourth embodiment, the resistance of Schottky barrier diode 104 can be reduced.

  Furthermore, Schottky barrier diode 104 has a portion where p-type region 2 and p-type buried region 4 overlap in plan view. Therefore, the breakdown voltage of the Schottky barrier diode 104 can be maintained. Furthermore, the response speed of the Schottky barrier diode 104 can be increased.

<Embodiment 5>
FIG. 19 is a schematic plan view of a Schottky barrier diode 105 according to the fifth embodiment of the present invention. 20 is a cross-sectional view showing a cross section of the Schottky barrier diode 105 taken along the line XX-XX in FIG.

  Referring to FIGS. 19 and 20, the entire p type buried region 4 (second stripe shape) is arranged so as to overlap the p type region 2 (first stripe shape) in plan view. In this respect, the Schottky barrier diode 105 is different from the Schottky barrier diode 101.

  19 and 20, the length of the p-type region 2 in the X direction (length of the short side) and the length of the p-type buried region 4 in the X direction (length of the short side). ) Are substantially equal. Similarly, the length in the Y direction (long side length) of the p-type region 2 and the length in the Y direction (long side length) of the p-type buried region 4 are also substantially equal. However, the present invention is not limited to this. In the fifth embodiment, it is only necessary that one of p-type region 2 and p-type buried region 4 overlaps the other of p-type region 2 and p-type buried region 4 in plan view. . Therefore, the length in the X direction and the length in the Y direction of the p-type region 2 may be larger than the length in the X direction and the length in the Y direction of the p-type buried region 4, respectively. Conversely, the length in the X direction and the length in the Y direction of the p-type buried region 4 may be larger than the length in the X direction and the length in the Y direction of the p-type region 2, respectively.

  The distance d9 is a distance between the p-type region 2 and the p-type buried region 4 closest to the p-type region 2. From the viewpoint of effectively injecting holes from the p-type region 2 to the p-type buried region 4, the distance d9 is preferably 5 μm or less, as in the first to fourth embodiments. More preferably, the distance d9 is 2 μm or less.

  The distance d10 is a distance between two adjacent p-type buried regions 4. The distance d10 can be appropriately determined from the viewpoint of performance such as withstand voltage and resistance required for the Schottky barrier diode 105.

  According to the fifth embodiment, as in the first to fourth embodiments, a Schottky barrier diode capable of obtaining a high breakdown voltage while suppressing an increase in resistance can be realized by a wide band gap semiconductor. Furthermore, the response speed of the Schottky barrier diode can be increased.

<Embodiment 6>
FIG. 21 is a schematic plan view of the Schottky barrier diode 106 according to the sixth embodiment of the present invention. Referring to FIG. 21, a plurality of p type buried regions 4 are formed in an island shape. A plurality of p-type buried regions 4 are two-dimensionally arranged between the plurality of p-type regions 2. In plan view, the plurality of p-type buried regions 4 are separated from each other.

  For example, as in the first embodiment, p type region 2 and p type buried region 4 are arranged such that there is a gap between p type region 2 and p type buried region 4 in plan view. . However, like the other embodiments, part or all of the p-type buried region 4 may overlap the p-type region 2 in plan view.

  The planar shape of the p-type buried region 4 is, for example, a square. However, the planar shape of the p-type embedded region 4 is not particularly limited, and may be, for example, a rectangle, another polygon (for example, a regular hexagon), a circle, an ellipse, or the like.

  In plan view, both the p-type region 2 and the p-type buried region 4 may have an island shape.

  According to the sixth embodiment, the area of the gap between p-type region 2 and p-type buried region 4 in plan view can be increased. As described above, since the portion corresponding to the gap is a part of the drift layer 12, a forward current can flow. Therefore, according to the sixth embodiment, the resistance of the Schottky barrier diode can be further reduced as compared with the first embodiment.

<Embodiment 7>
FIG. 22 is a schematic plan view of the Schottky barrier diode 107 according to the seventh embodiment of the present invention. 23 is a cross-sectional view showing a cross section of the Schottky barrier diode 107 along XXIII-XXIII in FIG.

  Referring to FIGS. 22 and 23, Schottky barrier diode 107 according to the seventh embodiment of the present invention has a Schottky barrier according to the first embodiment in that a plurality of n-type buried regions 7 are further added. Different from the barrier diode 101. N type buried region 7 is arranged inside drift layer 12 so as to be aligned with p type buried region 4 along a direction parallel to first main surface 1A. Therefore, two n-type buried regions 7 are arranged so as to sandwich one p-type buried region 4 in the X direction. Furthermore, n type buried region 7 is arranged to overlap p type region 2 in plan view.

  In plan view, the n-type buried region 7 has a stripe shape (third stripe shape) similarly to the p-type region 2 and the p-type buried region 4. Specifically, the third stripe shape is a rectangle having a long side along the Y direction and a short side along the X direction.

  The conductivity type of n type buried region 7 is the same as that of drift layer 12. The impurity concentration of n-type buried region 7 is higher than the impurity concentration of the portion located around n-type buried region 7 and having the conductivity type of n-type (that is, the portion of drift layer 12). Therefore, the n-type buried region 7 in the drift layer 12 can be specified based on the impurity concentration. For example, the n-type buried region 7 is specified by analyzing the impurity (donor) concentration from the main surface 1A of the wide band gap semiconductor layer 1 downward using a scanning capacitance microscope (SCM). May be. Further, the “portion located around the n-type buried region 7 and having n-type conductivity” is, for example, a drift above the n-type buried region 7 in the depth direction of the wide band gap semiconductor layer 1. A portion of the layer 12 (for example, a portion of the drift layer 12 sandwiched between the n-type buried region 7 and the p-type region 2), directly below the n-type buried region 7 in the depth direction of the wide band gap semiconductor layer 1. The drift layer 12 may be a portion of the drift layer 12 or the drift layer 12 sandwiched between the n-type buried region 7 and the p-type buried region 4.

  FIG. 24 is a partially enlarged view in which a part of the cross section of the Schottky barrier diode 107 shown in FIG. 23 is enlarged. Referring to FIG. 24, the top line of n-type buried region 7 is larger than the top line 4 </ b> L of p-type buried region 4. Good).

  The top line 4L of the p-type buried region 4 is a virtual line indicating the position of the upper joint surface of the p-type buried region 4. The upper junction surface of p type buried region 4 is formed so as to face main surface 1A of wide band gap semiconductor layer 1 among the plurality of junction surfaces of p type buried region 4 and drift layer 12. The bonded surface is a bonded surface located closer to the main surface 1A than the first main surface 10A of the silicon carbide substrate 10.

  N-type buried region 7 has an end 7A and an end 7B. The end portions 7A and 7B correspond to the boundary between the n-type buried region 7 and the drift layer 12. The end 7 </ b> A is located on the first main surface (main surface 1 </ b> A) side of the wide band gap semiconductor layer 1. The top line of the n-type buried region 7 is a virtual line indicating the position of the end portion 7A. End portion 7B is located on the second main surface (second main surface 10B of silicon carbide substrate 10) side of wide band gap semiconductor layer 1.

  N type buried region 7 is arranged in drift layer 12 to include this top line 4L. In other words, the bonding surface of the p-type buried region 4 facing the first main surface (main surface 1A) of the wide band gap semiconductor layer 1 is directed from the first main surface 1A to the second main surface 10B. It is located within the range from the position of the end 7A of the n-type buried region to the position of the end 7B of the n-type buried region in the direction (depth direction).

  FIG. 25 is a partially enlarged view schematically illustrating the depletion layer 15 extending from the p-type buried region 4 when a forward bias voltage is applied to the Schottky barrier diode 107 according to the seventh embodiment of the present invention. 23 and 25, when a forward bias voltage is applied to Schottky barrier diode 107, depletion layer 15 extends upward, that is, in a direction toward main surface 1A of wide band gap semiconductor layer 1.

  The depletion layer 15 can also extend in the lateral direction (for example, the X direction) inside the drift layer 12. However, the spread of the depletion layer 15 in the X direction is suppressed by the n-type buried region 7 adjacent to the p-type buried region 4. Since the two n-type buried regions 7 are located on both sides of the p-type buried region 4, the effect of suppressing the depletion layer 15 from spreading in the X direction is enhanced.

  As described above, the current path is narrowed as the depletion layer 15 is expanded. In the seventh embodiment, the n-type buried region 7 suppresses the spread of the depletion layer 15, so that it is possible to suppress the narrowing of the current path. Further, n type buried region 7 has the same conductivity type as drift layer 12 and has a higher impurity concentration than drift layer 12. Thereby, the resistance of the Schottky barrier diode 107 can be reduced as compared with the first embodiment.

  FIG. 26 is a partially enlarged view schematically illustrating the depletion layer 15 extending from the p-type buried region 4 when a reverse bias voltage is applied to the Schottky barrier diode 107 according to the seventh embodiment of the present invention. Referring to FIGS. 23 and 26, when a reverse bias voltage is applied to Schottky barrier diode 107, depletion layer 15 tends to extend downward, that is, toward first main surface 10A of silicon carbide substrate 10. However, as in the first to sixth embodiments, depletion layer 15 (not shown in FIG. 26) extending downward from the junction surface between p-type region 2 and drift layer 12, p-type buried region 4 and drift layer 12 is connected to the depletion layer 15 extending from the junction surface with the Schottky junction interface.

  As described above, according to the seventh embodiment, the resistance of the Schottky barrier diode can be reduced as compared with the first embodiment. Note that the number of n-type buried regions 7 arranged (sandwiched) between two p-type buried regions 4 is not limited to one. A plurality of n-type buried regions 7 may be arranged between the two p-type buried regions 4.

<Eighth embodiment>
In the first to seventh embodiments, each of the plurality of p type buried regions 4 is electrically floating. That is, the potential of the p-type buried region 4 is not fixed. However, the p-type buried region 4 is not limited to be electrically floating.

  FIG. 27 is a schematic plan view of the Schottky barrier diode 108 according to the eighth embodiment of the present invention. 28 is a cross-sectional view showing a cross section of the Schottky barrier diode 108 taken along the line XXVIII-XXVIII in FIG.

  27 and 28, Schottky barrier diode 108 differs from Schottky barrier diode 101 according to the first embodiment in that it further includes a plurality of contact regions 16.

  Contact region 16 is a p-type region disposed inside drift layer 12. Contact region 16 is electrically connected to p-type buried region 4 and electrically connected to Schottky electrode 6. Therefore, p type buried region 4 is electrically connected to Schottky electrode 6 and anode electrode 8 through contact region 16. In plan view, contact region 16 is arranged to overlap p-type buried region 4, Schottky electrode 6, and anode electrode 8 and to be located outside p-type region 2, for example.

  According to the eighth embodiment, the same potential is applied to p type region 2 and p type buried region 4. Since the potential of the p-type buried region 4 is fixed, the operation of the Schottky barrier diode 108 can be stabilized. Furthermore, holes can be more effectively injected from the anode electrode 8 into the p-type buried region 4 via the Schottky electrode 6. Therefore, a high-speed response of the Schottky barrier diode can be realized.

  In the diodes according to the respective embodiments other than the seventh embodiment, at least one n-type buried region 7 may be disposed between the two p-type buried regions 4. In that case, the number of n-type buried regions 7 arranged between the two p-type buried regions 4 is not particularly limited.

  In each of the above embodiments, the first conductivity type is n-type, and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the donor and acceptor in the above description are also replaced.

  In each of the above embodiments, the wide band gap semiconductor layer 1 is made of silicon carbide. However, the wide band gap includes gallium nitride (GaN), diamond and the like in addition to silicon carbide. Therefore, the wide band gap semiconductor layer 1 may be formed of gallium nitride or diamond.

  Each of the p-type region 2 and the p-type buried region 4 may be at least one. The number of both the p-type region 2 and the p-type buried region 4 is not limited to a plurality.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Wide Band Gap Semiconductor Layer 1A Main Surface (Wide Band Gap Semiconductor Layer)
2, 2A, 21, 22 p-type region 4 p-type buried region 4L top line 5 insulating film 6 Schottky electrode 7 n-type buried regions 7A and 7B end (n-type buried region)
8 Anode electrode 9 Cathode electrode 10 Silicon carbide substrate 10A First main surface (silicon carbide substrate)
10B Second main surface (silicon carbide substrate)
12 drift layer 15 depletion layer 16 contact region 41 first part (p-type buried region)
42 Second part (p-type buried region)
101-108 Schottky barrier diode X, Y direction d1-d10 distance.

Claims (9)

A wide band gap semiconductor layer including a first main surface and a second main surface located opposite to the first main surface and having the first conductivity type;
A first impurity region disposed inside the wide band gap semiconductor layer so as to be in contact with the first main surface of the wide band gap semiconductor layer and having a second conductivity type;
A second conductivity type disposed within the wide band gap semiconductor layer so as to be separated from the first main surface of the wide band gap semiconductor layer and the first impurity region; Impurity regions of
Wherein on said first major surface of the wide band gap semiconductor layer, Bei example a Schottky electrode disposed so as to be in contact with the first impurity region and said wide bandgap semiconductor layer,
In plan view, the first impurity region has a first stripe shape,
In the plan view, the second impurity region has a second stripe shape,
The first stripe shape includes a long axis along a first direction parallel to the first main surface, and a second axis parallel to the first main surface and perpendicular to the first direction. A minor axis extending along the direction,
The second stripe shape is:
A first portion having a major axis along the first direction and a minor axis along the second direction;
A second portion projecting from the first portion along the second direction,
The wide band gap semiconductor device , wherein at least a part of the second portion in the second impurity region overlaps the first impurity region in the plan view . A wide band gap semiconductor layer including a first main surface and a second main surface located opposite to the first main surface and having the first conductivity type;
A first impurity region disposed inside the wide band gap semiconductor layer so as to be in contact with the first main surface of the wide band gap semiconductor layer and having a second conductivity type;
A second conductivity type disposed within the wide band gap semiconductor layer so as to be separated from the first main surface of the wide band gap semiconductor layer and the first impurity region; Impurity regions of
A Schottky electrode disposed on the first main surface of the wide band gap semiconductor layer so as to be in contact with the first impurity region and the wide band gap semiconductor layer;
A third impurity having the first conductivity type and disposed inside the wide band gap semiconductor layer so as to be aligned with the second impurity region along a direction parallel to the first main surface; and a region,
The third impurity region in the wide band gap semiconductor layer, located around the third impurity region, and having a higher impurity concentration than the impurity concentration of the portion having the first conductivity type, Wa Id band gap semiconductor device. The third impurity region is
A first end located on the first main surface side;
A second end located on the second main surface side,
The junction surface of the second impurity region opposed to the first main surface has a first surface of the third impurity region in a depth direction from the first main surface to the second main surface. The wide band gap semiconductor device according to claim 2 , wherein the wide band gap semiconductor device is located within a range from a position of one end portion to a position of the second end portion of the third impurity region. A wide band gap semiconductor layer including a first main surface and a second main surface located opposite to the first main surface and having the first conductivity type;
A first impurity region disposed inside the wide band gap semiconductor layer so as to be in contact with the first main surface of the wide band gap semiconductor layer and having a second conductivity type;
A second conductivity type disposed within the wide band gap semiconductor layer so as to be separated from the first main surface of the wide band gap semiconductor layer and the first impurity region; Impurity regions of
A Schottky electrode disposed on the first main surface of the wide band gap semiconductor layer so as to be in contact with the first impurity region and the wide band gap semiconductor layer;
The wide-bandgap semiconductor device, wherein the second impurity region is formed in an island shape that is disposed at a position that does not overlap the first impurity region and is separated from each other in plan view. The second impurity region, and is electrically floating, the wide band gap semiconductor device according to any one of claims 1 to 4. The second impurity region, said Schottky electrodes are electrically connected, the wide band gap semiconductor device according to any one of claims 1 to 4. Wherein a first impurity region, the distance between the second impurity region is 5μm or less, the wide band gap semiconductor device according to any one of claims 1 to 6. The wide band gap semiconductor device according to claim 7 , wherein the distance between the first impurity region and the second impurity region is 2 μm or less. The wide band gap semiconductor device according to any one of claims 1 to 8 , wherein the wide band gap semiconductor layer includes silicon carbide.

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