JP6119118B2 - Image sensor - Google Patents

Description

  The present invention relates to an image sensor.

There is known an imaging unit in which a back-illuminated imaging chip and a signal processing chip are connected via a micro bump for each cell unit in which a plurality of pixels are combined.
[Prior art documents]
[Patent Literature]
[Patent Document 1] Japanese Patent Application Laid-Open No. 2006-49361

  However, the imaging unit has a problem that the microbumps are uniformly arranged in the region where the pixels are provided, and the degree of freedom in design is very low.

  In the first aspect of the present invention, the imaging device is a unit group including a plurality of pixels that convert incident light into a pixel signal, and each of the plurality of pixels of the unit group is provided corresponding to the unit group. An imaging chip having a plurality of sets of output lines from which pixel signals read out from the output are output, and a plurality of A / D converters that digitize and output pixel signals input from the plurality of output lines. A plurality of signal processing chips, a plurality of output lines, and corresponding A / D converters are electrically connected to each other, and a plurality of signals are arranged at a non-uniform density in the stacked surface of the imaging chip and the signal processing chip. Connection bumps.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a cross-sectional view of a backside illuminating type MOS imaging device according to the present embodiment. It is a figure explaining the unit group of an imaging chip. A unit group is shown typically. The circuit diagram of the pixel unit in a unit group is shown. It is a block diagram which shows the structure of the imaging device which concerns on this embodiment. An example of a layout of a unit group and a processing circuit unit is shown. The other example of the layout of a unit group and a processing circuit part is shown. The other example of the layout of a unit group and a processing circuit part is shown. The other example of the layout of a unit group and a processing circuit part is shown. The other example of the layout of a unit group and a processing circuit part is shown. The other example of the layout of a unit group and a processing circuit part is shown. An arrangement example of a plurality of unit groups is shown. The other example of arrangement | positioning of a several unit group is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment. The imaging element 100 includes an imaging chip 113 that outputs a pixel signal corresponding to incident light, a signal processing chip 111 that processes the pixel signal, and a memory chip 112 that stores the pixel signal. The imaging chip 113, the signal processing chip 111, and the memory chip 112 are stacked, and are electrically connected to each other by connection bumps 200 having conductivity such as Cu.

  As shown in the figure, incident light is incident mainly in the positive direction of the Z-axis indicated by a white arrow. In the present embodiment, in the imaging chip 113, the surface on the side where incident light is incident is referred to as a back surface. Further, as indicated by the coordinate axes, the right direction on the plane orthogonal to the Z axis is defined as the X axis plus direction, and the front side of the sheet orthogonal to the Z axis and the X axis is defined as the Y axis plus direction. In the following several figures, the coordinate axes are displayed so that the orientation of each figure can be understood with reference to the coordinate axes of FIG.

  An example of the imaging chip 113 is a back-illuminated MOS image sensor. The PD layer 106 is disposed on the back side of the wiring layer 108. The PD layer 106 includes a plurality of PDs (photodiodes) 104 arranged two-dimensionally and a transistor 105 provided corresponding to the PD 104.

  A color filter 102 is provided on the incident side of incident light in the PD layer 106 via a passivation film 103. The color filter 102 has a plurality of types that transmit different wavelength regions, and has a specific arrangement corresponding to each of the PDs 104. A set of the color filter 102, the PD 104, and the transistor 105 forms one pixel.

  On the incident light incident side of the color filter 102, a microlens 101 is provided corresponding to each pixel. The microlens 101 condenses incident light toward the corresponding PD 104.

  The wiring layer 108 includes a wiring 107 that transmits the pixel signal from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multilayer, and a passive element and an active element may be provided.

  A plurality of connection bumps 200 are disposed on the surface of the wiring layer 108. The plurality of connection bumps 200 are aligned with the plurality of connection bumps 200 provided on the opposing surfaces of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed and the like, thereby aligning. The connected connection bumps 200 are joined and electrically connected.

  Similarly, a plurality of bumps 109 are disposed on the mutually facing surfaces of the signal processing chip 111 and the memory chip 112. The bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressurized, so that the aligned bumps 109 are joined and electrically connected. Note that the bonding between the connection bumps 200 and the bumps 109 is not limited to Cu bump bonding by solid phase diffusion, and microbump bonding by solder melting may be employed.

  The signal processing chip 111 has a TSV (silicon through electrode) 110 that connects circuits provided on the front and back surfaces to each other. The TSV 110 is preferably provided in the peripheral area. The TSV 110 may also be provided in the peripheral area of the imaging chip 113 and the memory chip 112.

  FIG. 2 is a diagram illustrating the unit group 130 of the imaging chip 113. In particular, a state where the imaging chip 113 is observed from the back side is shown. In the pixel area, 14 million or more pixels 141 are arranged in a matrix.

  In this embodiment, a total of 2048 pixels of 32 pixels in the adjacent X-axis direction and 64 pixels in the Y-axis direction form one unit group 131. In the entire imaging chip 113, 144 unit groups 131 are arranged in the X-axis direction and 48 in the Y-axis direction. The number of pixels included in the unit group 131 is not limited to this. The number of unit groups 131 is not limited to this.

  FIG. 3 schematically shows the unit group 130. FIG. 4 shows a circuit diagram of the pixel unit 140 in the unit group 130. Note that XYZ in FIG. 3 indicates the direction with respect to the unit group 130, and does not indicate the spatial direction of the processing circuit unit 144.

  In the unit group 130, the pixels 141 are two-dimensionally arranged in a so-called Bayer arrangement. One unit in the Bayer array forms a pixel unit 140. That is, the pixel unit 140 has four pixels Gb, Gr, B, and R.

  The green pixels Gb and Gr have a green filter as the color filter 102 and receive light in the green wavelength band of incident light. Similarly, the blue pixel B has a blue filter as the color filter 102 and receives light in the blue wavelength band, and the red pixel R has a red filter as the color filter 102 and receives light in the red wavelength band. .

  In the unit group 130, one row selection line is provided for every two rows of pixels, and two rows of pixels are commonly connected to each row selection line. In the example of FIG. 3, 32 row selection lines are provided corresponding to the 64 pixels in the Y-axis direction.

  One output wiring 142 is provided for each pixel in two columns, and two columns of pixels are commonly connected to each output wiring 142. In the example of FIG. 3, 16 output wirings 142 are provided corresponding to 32 pixels in the X-axis direction.

  These output wirings 142 are electrically connected to the processing circuit unit 144 provided in the signal processing chip 111 via the connection bumps 200. The unit group 130 and the processing circuit unit 144 electrically connected to the unit group 130 are provided in an overlapping region when viewed from the direction in which the imaging chip 113 and the signal processing chip 111 are stacked.

  The power supply wiring Vdd and the reset wiring in FIG. 4 are commonly connected to the entire pixel 141 included in the unit group 130. Further, the Gb transfer wiring is commonly connected to the pixels Gb in the unit group 130. Similarly, the Gr transfer wiring is commonly connected to the pixel Gr in the unit group 130, the B transfer wiring is commonly connected to the pixel B in the unit group 130, and the R transfer wiring is common to the pixel R in the unit group 131. It is connected to the. Further, the reset wiring and each transfer wiring are separately provided between the plurality of unit groups 130.

  The pixels Gb, Gr, B, and R of the pixel unit 140 share the reset transistor 150, the amplification transistor 152, and the selection transistor 154. The pixel Gb1 includes transfer transistors 156 and 158. Similarly, the pixel Gr includes transfer transistors 160 and 162, the pixel B includes transfer transistors 164 and 166, and the pixel R includes transfer transistors 168 and 170. At least some of these transistors correspond to the transistor 105 in FIG.

  Hereinafter, the connection relationship of each transistor will be described using the pixel Gb as an example. An example of each transistor is an n-channel FET, but the type of transistor is not limited to this.

  The gate, drain, and source of the transfer transistor 156 of the pixel Gb are connected to the Gb transfer wiring, the row selection line 1, and the gate of the transfer transistor 158, respectively. The source and drain of the transfer transistor 158 are connected to one end of the PD of the pixel Gb and the gate of the amplification transistor 152, respectively. In addition, the drain of the reset transistor 150 is connected to the power supply wiring Vdd, and the source is connected to the gate of the amplification transistor 152. The drain of the amplification transistor 152 is connected to the power supply wiring Vdd, and the source is connected to the drain of the selection transistor 154. The selection transistor 154 has a gate connected to the row selection wiring 1 and a source connected to the output wiring 142. Since the connection relationship between the pixels Gr, B, and R is the same, the description thereof is omitted.

  Each of the output wirings 142 is connected to the CDS circuit 146 on a one-to-one basis via connection bumps 200 that electrically connect the imaging chip 113 and the signal processing chip 111. The outputs of these CDS circuits 146 are input to a multiplexer 148. Further, the output from the multiplexer 148 is input to the A / D conversion circuit 149, and the output of the A / D conversion circuit 149 is connected to the pixel memory 180 provided in the memory chip 112. In the example shown in FIG. 3, one A / D conversion circuit 149 is provided for one unit group 130, but a plurality of A / D conversion circuits 149 may be provided.

  3 and FIG. 4, the image signal of each pixel 141 is read as follows. Note that the description of the reset operation is omitted for the sake of simplicity.

  One of the row selection lines, for example, the row selection line 1 is turned on. In this state, one of the transfer wirings, for example, the Gb transfer wiring is turned on. As a result, both transfer transistors 156 and 158 of the pixel Gb are turned on, and the charge of the pixel Gb is transferred to the gate of the amplification transistor 152. Here, since the row selection line 1 is on, the selection transistor 154 is also on, and a pixel signal amplified in accordance with the charge transferred to the gate of the amplification transistor 152 is output from the output wiring 142.

  Since the row selection line 1 is common to the pixels in two rows in the unit group 130 and the Gb transfer wiring is common to the pixels Gb in the unit group 130, the pixels of the pixels Gb for one row in the unit group 130 A signal is simultaneously output to the corresponding output wiring 142. Here, since the CDS circuits 146 are arranged one-to-one on the output wiring 142, each pixel signal is temporarily held in each CDS circuit 146 in a state where noise is removed.

  The multiplexer 148 sequentially reads out the pixel signals temporarily held in the plurality of CDS circuits 146 and delivers them to the A / D conversion circuit 149. The A / D conversion circuit 149 sequentially digitizes the pixel signals and writes them in the pixel memory 180. Thereby, each pixel signal of the pixels Gb for one row of the unit group 130 is stored in the pixel memory 180 without being influenced by other pixel signals.

  Next, when the Gr transfer wiring is turned on while the row selection line 1 is turned on, each of the pixel signals of the pixels Gr for one row of the unit group 130 is affected by other pixel signals. Read sequentially. Similarly, when the B transfer wiring is turned on while the row selection line 1 is turned on, each pixel signal of the pixel B for one row of the unit group 130 is read and stored in the pixel memory 180. When the R transfer wiring is turned on while the row selection line 1 is turned on, each pixel signal of the pixel R for one row of the unit group 130 is read and stored in the pixel memory 180. As described above, the pixel signals of the two rows of pixels of the unit group 130 are read out.

  Next, the row selection line 2 is turned on and the above procedure is repeated to read out pixel signals of pixels for the next two rows of the unit group 130. By repeating the above procedure for all row selection lines, the pixel signals of all the pixels in the unit group 130 are read out.

  According to the embodiment shown in FIG. 3 and FIG. 4, it is only necessary to provide one row selection line for two rows of pixels for each unit group 130, so that wiring can be easily routed. In addition, since it is only necessary to provide one output wiring for two columns of pixels for each unit group 130, wiring is facilitated.

  FIG. 5 is a block diagram illustrating a configuration of the imaging apparatus according to the present embodiment. The imaging apparatus 500 includes a photographic lens 520 as a photographic optical system, and the photographic lens 520 guides a subject luminous flux incident along the optical axis OA to the imaging element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging apparatus 500. The imaging apparatus 500 mainly includes an imaging device 100, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, and a display unit 506.

  The photographing lens 520 is composed of a plurality of optical lens groups, and forms an image of a subject light flux from the scene in the vicinity of its focal plane. In FIG. 5, the photographic lens 520 is representatively represented by a single virtual lens disposed in the vicinity of the pupil. The drive unit 502 is a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 100 in accordance with instructions from the system control unit 501. In this sense, it can be said that the drive unit 502 functions as an image sensor control unit that causes the image sensor 100 to perform charge accumulation and output a pixel signal.

  The image sensor 100 delivers the pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 performs various image processing using the work memory 504 as a work space, and generates image data. For example, when generating image data in JPEG file format, a compression process is executed after generating a color video signal from a signal obtained by the Bayer array. The generated image data is recorded in the recording unit 505, converted into a display signal, and displayed on the display unit 506 for a preset time.

  The photometric unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor having about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance for each area of the scene. The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The light metering unit 503 may be shared by the image sensor 100. Note that the arithmetic unit 512 also executes various arithmetic operations for operating the imaging device 500.

  A part or all of the drive unit 502 may be mounted on the imaging chip 113, or part or all of the drive unit 502 may be mounted on the signal processing chip 111. A part of the system control unit 501 may be mounted on the imaging chip 113 or the signal processing chip 111.

  FIG. 6 shows an example of the layout of the unit group 130 and the processing circuit unit 144 corresponding to the unit group 130. In FIG. 6, the unit group 130 and the processing circuit unit 144 are overlapped in the Z-axis direction, but they are shown shifted in the X-axis direction for explanation. Further, in order to show the arrangement of the pixels 141 in the unit group 130, four boundary lines between the pixels are representatively shown by XY.

When the repeating unit of the pixel 141 included in the unit group 130 is a square, the unit group 130 is a 1: 2 rectangle that is long in the Y-axis direction, reflecting the number of XY pixels. Here, when one pixel is, for example, 3 μm square, one unit group 130 has a length in the X-axis direction of 96 μm, a length in the Y-axis direction of 192 μm, and an area of about 18000 μm ² .

  One processing circuit unit 144 provided corresponding to one unit group 130 has the same shape as that of the unit group 130. Note that the unit group 130 and the processing circuit unit 144 need not have the same shape.

  In the processing circuit unit 144, a CDS circuit 146, a multiplexer 148, an A / D conversion circuit 149, and a part of the driving unit 502 as logic are arranged in order from the + Y side in the example of FIG. Since the multiplexer 148 and the A / D conversion circuit 149 have a larger number of elements than the CDS circuit 146 and the like, the processing circuit unit 144 is preferably arranged near the center, and the layout is preferably determined preferentially.

  The CDS circuits 146 are arranged in a line in the X-axis direction, and 16 CDS circuits 146 are provided corresponding to the example of FIG. Thereby, two columns of pixels corresponding to one output wiring 142 and the corresponding CDS circuit 146 overlap in the Z-axis direction.

  The connection bumps 200 that connect the output wiring 142 of the pixel 141 and the CDS circuit 146 are disposed below the corresponding two columns of pixels and above the CDS circuit 146. That is, one connection bump 202 is disposed on each CDS circuit 146. In this case, the connection bumps 200 are arranged so as to overlap with the area where the pixels are provided when viewed from the Z-axis direction. Since the connection bumps 202 are arranged so as to overlap with the corresponding pixel columns and the CDS circuit 146, it is possible to simplify wiring in the planes of the unit group 130 and the processing circuit unit 144.

  In the example shown in FIG. 6, every eight connection bumps 200 are arranged in the X-axis direction, and are arranged in two rows offset by one in the Y-axis direction. Thereby, when the diameter of the connection bump 200 is set to be approximately the same as the width of the CDS circuit 146, it is possible to prevent a short circuit or noise from being generated due to the connection bumps 200 approaching each other.

  Further, connection bumps 202 and 204 that connect the drive unit 502 and the unit group 130 side are disposed so as to overlap the region where the drive unit 502 of the processing circuit unit 144 is disposed. In the example of FIG. 6, corresponding to FIG. 4, six connection bumps 202 respectively connected to the reset, row selection line, Gb transfer line, Gr transfer line, B transfer line and R transfer line are arranged at equal intervals. The Furthermore, one connection bump 204 for grounding is arranged at equal intervals with them.

  Here, the connection bumps 200, 202, and 204 are arranged with a non-uniform density when viewed in the entire region of the unit group 130. In particular, the connection bumps 200 are biased toward the + Y side in the unit group 130, and the connection bumps 200 are biased toward the -Y side.

  As described above, according to the example shown in FIG. 6, since the connection bumps 200 are arranged with a non-uniform density, the degree of freedom in arrangement increases. Furthermore, it is possible to simplify the routing of the wiring in the respective surfaces of the unit group 130 and the processing circuit unit 144 while preventing a short circuit between the connection bumps 200. The connection bump 200 and the connection bumps 202 and 204 are preferably provided with the same diameter and the same interval, but may be provided with different diameters or different intervals.

  FIG. 7 shows another example of the layout of the unit group 130 and the processing circuit unit 144 corresponding to the unit group 130. 7, the same components as those in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 7, the CDS circuit 146 is two-dimensionally arranged in the X-axis direction and the Y-axis direction. Specifically, eight columns are arranged in the X direction and two rows are arranged in the Y axis direction. Thereby, the aspect ratio of the area of each CDS circuit 146 can be made close to 1, and the degree of freedom of design in the CDS circuit 146 can be increased.

  The connection bumps 210 that connect the CDS circuit 146 and the output wiring 142 from the pixel 141 are disposed on the corresponding CDS circuit 146. That is, one connection bump 202 is disposed on each CDS circuit 146. In this case, corresponding to the CDS circuit 146 being arranged in 8 columns × 2 rows, the connection bumps 202 are also arranged in 8 columns × 2 rows.

  Further, these connection bumps 210 are equally spaced within one row and are aligned between columns. In addition, it does not need to be equally spaced within one row, and may be offset between columns.

  Also in FIG. 7, as in the case of FIG. 6, the connection bumps 210 are arranged with a nonuniform density biased toward the + Y side when viewed in the entire region of the unit group 130. In addition, since the position of the connection bump 210 and the position of the pixel column corresponding to this do not coincide with each other, an in-plane wiring for connecting them is provided on the unit group 130 side.

  As described above, according to the example shown in FIG. 7, as in the case of FIG. 6, since the connection bumps 210 are arranged at a non-uniform density, the degree of freedom in arrangement increases. Furthermore, it is possible to simplify the routing of wiring in the planes of the unit group 130 and the processing circuit unit 144 while the aspect ratio of the CDS circuit 146 is close to 1.

  FIG. 8 shows still another example of the layout of the unit group 130 and the processing circuit unit 144 corresponding to the unit group 130. 8, the same components as those in FIG. 6 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 8, CDS circuits 146 and 147 are arranged on both sides of the multiplexer 148 and the A / D conversion circuit 149 corresponding to the unit group 130 across the Y-axis direction. Eight rows of CDS circuits 146 are arranged on the + Y side, and eight rows of CDS circuits 147 are arranged on the −Y side. Thereby, the aspect ratio of the area of each CDS circuit 146, 147 can be made close to 1, and the degree of freedom of design in the CDS circuit 146, 147 can be increased.

  The connection bumps 220 that connect the CDS circuit 146 and the output wiring 142 from the pixel 141 are disposed below the corresponding two columns of pixels and above one CDS circuit 146. Similarly, connection bumps 226 that connect the CDS circuit 147 and the output wiring 142 from the pixel 141 are disposed below the corresponding two columns of pixels and above one CDS circuit 147. Therefore, the group of connection bumps 220 and the group of connection bumps 226 are arranged at offset positions. Note that, by providing in-plane wirings that connect the positions of the pixel columns and the connection bumps 220 and 226, these may be arranged without offset.

  Also in FIG. 8, as in the case of FIG. 6, the connection bumps 220 and 226 are arranged at a non-uniform density, so that the degree of freedom in arrangement becomes high. Furthermore, the connection bumps 210 are arranged with a nonuniform density and biased toward the + Y side when viewed in the entire region of the unit group 130. As described above, according to the example shown in FIG. 8, the connection bumps 220 and 226 are arranged so as to overlap with the corresponding pixel columns and the CDS circuits 146 and 147, and thus the respective surfaces of the unit group 130 and the processing circuit unit 144. It is possible to simplify the routing of the wiring inside. Furthermore, the aspect ratio of the CDS circuits 146 and 147 can be made close to 1, and the degree of design freedom can be increased.

  FIG. 9 shows still another example of the layout of the unit group 130 and the processing circuit unit 144 corresponding to the unit group 130. 9, the same components as those in FIG. 7 are denoted by the same reference numerals, and description thereof is omitted. 9, the CDS circuit 146 is two-dimensionally arranged in the X-axis direction and the Y-axis direction as in FIG.

  The connection bumps 230 that connect the CDS circuit 146 and the output wiring 142 from the pixel 141 are disposed so as to overlap the region where the multiplexer 148 and the A / D conversion circuit 149 are disposed. Further, each of the connection bumps 230 is connected to the corresponding CDS circuit 146 by the in-plane wiring 236. These in-plane wirings 236 are preferably the same wiring distance, but may be wiring distances different from each other.

  In the example shown in FIG. 9, four connection bumps 230 are arranged in the X-axis direction every other one, and are arranged in four rows offset by one in the Y-axis direction. Accordingly, it is possible to prevent the occurrence of a short circuit or noise due to the connection bumps 230 approaching each other while the connection bumps 230 are enlarged to about the width of the CDS circuit 146.

  The connection bumps 232 and 234 of the drive unit 502 are also arranged with the same diameter and the same interval as the connection bump 230. In the example of FIG. 9, a row of four connection bumps 232 and three connection bumps 232 and 234 are arranged offset.

  Also in FIG. 9, as in the case of FIG. 6, the connection bumps 230 are arranged with a nonuniform density and biased toward the + Y side when viewed in the entire region of the unit group 130. In addition, since the position of the connection bump 230 and the position of the pixel column corresponding to this do not coincide with each other, an in-plane wiring for connecting them is provided on the unit group 130 side.

  As described above, according to the example shown in FIG. 9, as in the case of FIG. 6, since the connection bumps 230 are arranged with a non-uniform density, the degree of freedom in arrangement increases. Furthermore, the reliability of the electrical connection can be improved by increasing the diameter of the connection bump 230 to about the width of the CDS circuit 146.

  FIG. 10 shows still another example of the layout of the unit group 130 and the processing circuit unit 144 corresponding to the unit group 130. 10, the same components as those in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 10, the CDS circuits 146 and 147 are arranged in a staggered manner across the A / D conversion circuit 149 and the like in the X-axis direction, with two in the Y-axis direction as a set. The connection bumps 230 and 237 that connect the CDS circuits 146 and 147 and the output wiring 142 from the pixel 141 are arranged so as to overlap the area where the multiplexer 148 and the A / D conversion circuit 149 are arranged.

  Each of the connection bumps 230 is connected to the corresponding CDS circuit 146 by the in-plane wiring 236. Similarly, each of the connection bumps 237 is connected to the corresponding CDS circuit 147 by the in-plane wiring 238. The in-plane wirings 236 and 238 are preferably the same wiring distance, but may be wiring distances different from each other.

  As described above, according to the example shown in FIG. 10, as in the case of FIG. 9, since the connection bumps 230 and 237 are arranged with a non-uniform density, the degree of freedom in arrangement increases. Further, the wiring distances to the corresponding CDS circuits 146 and 147 can be made substantially the same while making the diameters of the connection bumps 230 and 237 larger than the width of the CDS circuits 146 and 147.

  FIG. 11 shows still another example of the layout of the unit group 130 and the processing circuit unit 144 corresponding to the unit group 130. 11, the same components as those in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted.

  In the example of FIG. 11, a plurality of dummy bumps 206 are arranged separately from the connection bumps 200, 202, and 204 of FIG. The dummy bump 206 is arranged in a region where the connection bumps 200, 202, and 204 are sparse. In the case of FIG. 11, the dummy bump 206 is arranged so as to overlap with a region where the multiplexer 148 and the A / D conversion circuit 149 are arranged, which is a region where the connection bumps 200, 202, and 204 are sparse.

  In this case, the dummy bumps 206 are preferably arranged with the same diameter and the same density as the connection bumps 200 and the like, but may be arranged with different diameters or different densities. In the example of FIG. 11, the dummy bumps 206 are not disposed in the region of the CDS circuit 146 and the region of the drive unit 502, but the dummy bumps 206 may be disposed in these regions. In this case, the connection bumps 200, 202, 204 and the dummy bump 206 may be arranged at the same interval.

  As described above, in the example of FIG. 11, by providing the dummy bump 206, the mechanical connection strength between the unit group 130 and the processing circuit unit 144 can be improved, and the flatness in CMP or the like can be improved. Note that dummy bumps may also be provided for the examples of FIGS.

  FIG. 12 shows an arrangement example of a plurality of unit groups 130. In the example shown in FIG. 12, the plurality of unit groups 130 have the same layout of the connection bumps 200 and the like. Thereby, the imaging chip 113 including the plurality of unit groups 130 can be easily made by the same design and process for each unit group 130.

  FIG. 13 shows another arrangement example of the plurality of unit groups 130. In the example shown in FIG. 13, the unit group 130 and the unit group 131 adjacent to each other have different layouts of the connection bumps 200 and the like. In the example of FIG. 13, the unit group 130 and the unit group 131 have layouts that are reversed with respect to the X axis. Thereby, the bias of the connection bumps 200 and the like can be reduced in the entire imaging chip 113.

  Note that the unit groups 130 and the unit groups 131 need not be alternately arranged. If at least one of the plurality of unit groups included in the imaging chip 113 is different from at least one of the other unit groups in the position where the plurality of connection bumps are biased, the entire imaging chip 113 may have a connection bump. The bias can be reduced.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  100 imaging device, 101 microlens, 102 color filter, 103 passivation film, 104 PD, 105 transistor, 106 PD layer, 107 wiring, 108 wiring layer, 109 bump, 110 TSV, 111 signal processing chip, 112 memory chip, 113 imaging Chip, 130 unit group, 131 unit group, 140 pixel unit, 141 pixel, 142 output wiring, 144 processing circuit unit, 146 CDS circuit, 147 CDS circuit, 148 multiplexer, 149 A / D conversion circuit, 150 reset transistor, 152 amplification Transistor, 154 Select transistor, 156 Transfer transistor, 158 Transfer transistor, 160 Transfer transistor, 162 Transfer transistor, 164 Transfer transistor 166 transfer transistor, 168 transfer transistor, 170 transfer transistor, 180 pixel memory, 200 connection bump, 202 connection bump, 204 connection bump, 206 dummy bump, 210 connection bump, 220 connection bump, 226 connection bump, 230 connection bump, 232 Connection bump, 234 Connection bump, 236 In-plane wiring, 237 Connection bump, 238 In-plane wiring, 500 Imaging device, 520 Shooting lens, 501 System control unit, 502 Drive unit, 503 Photometry unit, 504 Work memory, 505 Recording unit, 506 Display unit, 511 Image processing unit, 512 arithmetic unit

Claims (7)

An imaging chip provided with a plurality of pixel groups each having at least one pixel that outputs a pixel signal corresponding to incident light;
A plurality of processing circuits provided corresponding to each of the plurality of pixel groups, the plurality of processing circuits processing the pixel signals output from the plurality of pixel groups, and stacked on the imaging chip Signal processing chip,
A plurality of connection portions that electrically connect each of the plurality of pixel groups and each of the plurality of processing circuits corresponding to each of the plurality of pixel groups;
The plurality of pixel groups are arranged along a first direction on the imaging chip,
Each of the plurality of connection portions corresponding to each of the plurality of pixel groups adjacent to each other in the first direction is disposed at a position shifted from each other in a second direction intersecting with the first direction. And
The plurality of connecting portions are arranged in a region different from the plurality of processing circuits in the signal processing chip, and are connected to corresponding processing circuits among the plurality of processing circuits by wiring ,
The plurality of connection portions are image sensors arranged under the plurality of pixel groups .   The imaging device according to claim 1, wherein a wiring distance between each of the plurality of processing circuits and each of the plurality of connection portions corresponding to each of the plurality of processing circuits is equal. The imaging chip is provided corresponding to each of the plurality of pixel groups, wired along the second direction, and outputs the pixel signal read from each pixel of the plurality of pixel groups. Has an output line,
3. The imaging according to claim 1, wherein each of the plurality of connection portions is provided corresponding to each of the plurality of output lines, and electrically connects the plurality of output lines and the plurality of processing circuits. element. The plurality of processing circuits include a plurality of correlated double sampling units that remove noise from the pixel signals input from the plurality of output lines,
The imaging device according to claim 3, wherein each of the plurality of connection units is provided corresponding to each of the plurality of correlated double sampling units. The imaging chip has a plurality of unit groups each including the plurality of pixel groups,
Wherein the plurality of connecting portions, the imaging device according to any one of claims 1 to 4, wherein the plurality of pixels are arranged unevenly on one in a region provided in each of the plurality of unit groups. The image pickup device according to claim 5 , wherein positions of the plurality of connection portions in at least one of the plurality of unit groups are different from positions in at least one other group. Superimposed on the plurality of pixel groups when viewed from the laminating direction is provided region, according to any one of claims 1 to 6 wherein the plurality of connecting portions having a plurality of dummy bumps which separately arranged Image sensor.

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