JP6181500B2 - Chip resistor and manufacturing method thereof - Google Patents
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- JP6181500B2 JP6181500B2 JP2013204379A JP2013204379A JP6181500B2 JP 6181500 B2 JP6181500 B2 JP 6181500B2 JP 2013204379 A JP2013204379 A JP 2013204379A JP 2013204379 A JP2013204379 A JP 2013204379A JP 6181500 B2 JP6181500 B2 JP 6181500B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 84
- 238000001035 drying Methods 0.000 claims description 13
- 238000010304 firing Methods 0.000 claims description 13
- 238000007639 printing Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 49
- 238000009966 trimming Methods 0.000 description 14
- 238000007650 screen-printing Methods 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000011241 protective layer Substances 0.000 description 9
- 238000007747 plating Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
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- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Description
本発明は、絶縁基板の表裏両面に抵抗体が設けられたチップ抵抗器と、そのようなチップ抵抗器の製造方法に関するものである。 The present invention relates to a chip resistor in which resistors are provided on both front and back surfaces of an insulating substrate, and a method for manufacturing such a chip resistor.
チップ抵抗器の小型化が促進されていくと、それに伴って抵抗体や電極を形成できるスペースが制限されるため、絶縁基板の表裏両面に抵抗体を形成して並列回路とすることにより、抵抗値精度や負荷特性の悪化を解消するようにした両面型のチップ抵抗器が知られている（例えば、特許文献１参照）。 As miniaturization of chip resistors is promoted, the space in which resistors and electrodes can be formed is limited accordingly. Therefore, by forming resistors on both the front and back sides of the insulating substrate to form parallel circuits, resistance 2. Description of the Related Art A double-sided chip resistor that eliminates deterioration in value accuracy and load characteristics is known (see, for example, Patent Document 1).
図４は従来より知られている両面型チップ抵抗器の断面図であり、同図に示すように、このチップ抵抗器２０は、直方体形状の絶縁基板２１と、絶縁基板２１の表面の長手方向両端部に設けられた一対の表面電極２２と、これら一対の表面電極２２に接続するように絶縁基板２１の表面に設けられた第１抵抗体２３と、この第１抵抗体２３を覆うように設けられた第１保護膜２４と、絶縁基板２１の裏面の長手方向両端部に設けられた一対の裏面電極２５と、これら一対の裏面電極２５に接続するように絶縁基板２１の裏面に設けられた第２抵抗体２６と、この第２抵抗体２６を覆うように設けられた第２保護膜２７と、表面電極２２と裏面電極２５を橋絡している一対の端面電極２８と、表面電極２２と端面電極２８および裏面電極２５を覆う断面コ字状の外部電極２９とによって主に構成されている。 FIG. 4 is a cross-sectional view of a double-sided chip resistor conventionally known. As shown in FIG. 4, the chip resistor 20 includes a rectangular parallelepiped insulating substrate 21 and a longitudinal direction of the surface of the insulating substrate 21. A pair of surface electrodes 22 provided at both ends, a first resistor 23 provided on the surface of the insulating substrate 21 so as to be connected to the pair of surface electrodes 22, and so as to cover the first resistor 23 The first protective film 24 provided, the pair of back electrodes 25 provided at both ends in the longitudinal direction of the back surface of the insulating substrate 21, and the back surface of the insulating substrate 21 to be connected to the pair of back electrodes 25. The second resistor 26, the second protective film 27 provided so as to cover the second resistor 26, a pair of end face electrodes 28 bridging the surface electrode 22 and the back electrode 25, and the surface electrode 22, end face electrode 28 and back face electrode 25. It is mainly constituted by a power sale U-shaped cross-section of the external electrodes 29.
絶縁基板２１はセラミック等からなり、この絶縁基板２１は大判基板を縦横に延びる分割線に沿って分割して多数個取りされたものである。表面電極２２は導電性ペーストをスクリーン印刷して乾燥・焼成させたものであり、同じく裏面電極２５も導電性ペーストをスクリーン印刷して乾燥・焼成させたものである。第１抵抗体２３は抵抗体ペーストをスクリーン印刷して乾燥・焼成させたものであり、第１抵抗体２３の両端部は表面電極２２の端部を覆うように重ね合わされている。第２抵抗体２６も抵抗体ペーストをスクリーン印刷して乾燥・焼成させたものであり、第２抵抗体２６の両端部は裏面電極２５の端部を覆うように重ね合わされている。図示省略されているが、これら第１抵抗体２３と第２抵抗体２６には抵抗値を調整するためにトリミング溝が形成されている。第１保護膜２４はアンダーコート層とオーバーコート層の２層構造からなり、同じく第２保護膜２７もアンダーコート層とオーバーコート層の２層構造からなるものである。アンダーコート層はガラスペーストを印刷して焼成させたものであり、このアンダーコート層はトリミング溝を形成する前の第１抵抗体２３や第２抵抗体２６に形成されている。オーバーコート層はエポキシ系樹脂ペーストを印刷して加熱硬化させたものであり、このオーバーコート層は第１抵抗体２３や第２抵抗体２６にトリミング溝を形成した後に形成されている。また、端面電極２８は絶縁基板２１の端面に導電性ペーストの塗布やスパッタにより形成されたものであり、外部電極２９はニッケルとはんだ等からなる２層構造のめっき層である。 The insulating substrate 21 is made of ceramic or the like, and the insulating substrate 21 is obtained by dividing a large-sized substrate along a dividing line extending vertically and horizontally and taking a large number. The front electrode 22 is obtained by screen-printing a conductive paste, dried and fired, and the back electrode 25 is also obtained by screen-printing a conductive paste, dried and fired. The first resistor 23 is a resistor paste screen-printed, dried and fired, and both end portions of the first resistor 23 are overlapped so as to cover the end portions of the surface electrode 22. The second resistor 26 is also formed by screen-printing a resistor paste, dried and fired, and both ends of the second resistor 26 are overlapped so as to cover the end of the back electrode 25. Although not shown, trimming grooves are formed in the first resistor 23 and the second resistor 26 in order to adjust the resistance value. The first protective film 24 has a two-layer structure of an undercoat layer and an overcoat layer. Similarly, the second protective film 27 also has a two-layer structure of an undercoat layer and an overcoat layer. The undercoat layer is obtained by printing and baking glass paste, and this undercoat layer is formed on the first resistor 23 and the second resistor 26 before the trimming groove is formed. The overcoat layer is obtained by printing an epoxy resin paste and heat-curing, and this overcoat layer is formed after trimming grooves are formed in the first resistor 23 and the second resistor 26. The end face electrode 28 is formed on the end face of the insulating substrate 21 by applying a conductive paste or sputtering, and the external electrode 29 is a two-layered plating layer made of nickel and solder.
このように構成されたチップ抵抗器２０を製造する場合、表面電極２２と裏面電極２５や両抵抗体２３，２６等を乾燥・焼成させる熱処理が必要であり、通常、かかる熱処理には量産性を考慮して連続炉が使用されている。この連続炉は、無端状のコンベアベルトの上に被処理物を搭載し、それが炉の中を通過しながら加熱されるというものであり、バッチ炉に比べて炉内温度の制御が簡単で多量生産に適している。 When manufacturing the chip resistor 20 configured as described above, a heat treatment for drying and baking the front surface electrode 22 and the back surface electrode 25, both the resistors 23 and 26, and the like is necessary. A continuous furnace is used in consideration. In this continuous furnace, an object to be processed is mounted on an endless conveyor belt and heated while passing through the furnace, and control of the furnace temperature is easier than in a batch furnace. Suitable for mass production.
この種の連続炉には被処理物の形態などに応じて様々な工夫がなされており、その一例として、コンベアベルトに所定間隔を存して対向する一対の凸部を設け、これら凸部に被処理物を載置した状態で焼成するようにした連続炉が従来より提案されている（例えば、特許文献２参照）。このような連続炉を用いて被処理物の熱処理を行うと、凸部によって被処理物をコンベアベルトの表面から浮かせた姿勢に保持できるため、被処理物のコンベアベルトに対向する面の損傷を回避することができる。 Various contrivances have been made in this type of continuous furnace depending on the form of the object to be processed. As an example, a pair of convex portions facing the conveyor belt with a predetermined interval are provided, and these convex portions are provided with these convex portions. Conventionally, a continuous furnace in which the object to be processed is fired in a state where it is placed has been proposed (see, for example, Patent Document 2). When heat treatment is performed on the workpiece using such a continuous furnace, the convex portion can hold the workpiece in a posture where it floats from the surface of the conveyor belt. It can be avoided.
しかしながら、特許文献１に記載された従来のチップ抵抗器では、絶縁基板２１の表面側に形成された表面電極２２と第１抵抗体２３の接続構造と、絶縁基板２１の裏面側に形成された裏面電極２５と第２抵抗体２６の接続構造が同様な構成になっているため、焼成時に第１抵抗体２３と第２抵抗体２６のいずれか一方がコンベアベルトに接触して損傷を受けやすいという問題がある。例えば、先に第１抵抗体２３を形成してから第２抵抗体２６を焼成する場合は、第１抵抗体２３を下に向けてコンベアベルトに載置した状態で上を向いた第２抵抗体２６を焼成するため、第１抵抗体２３がコンベアベルトの表面に接触して損傷する虞がある。その反対に先に第２抵抗体２６を形成してから第１抵抗体２３を焼成する場合は、第２抵抗体２６を下に向けてコンベアベルトに載置した状態で上を向いた第１抵抗体２３を焼成するため、第２抵抗体２６がコンベアベルトの表面に接触して損傷する虞があり、いずれの場合も先に形成した抵抗体がコンベアベルトに接触してしまう虞がある。 However, in the conventional chip resistor described in Patent Document 1, the connection structure between the surface electrode 22 and the first resistor 23 formed on the front surface side of the insulating substrate 21 and the back surface side of the insulating substrate 21 is formed. Since the connection structure of the back electrode 25 and the second resistor 26 has the same structure, either the first resistor 23 or the second resistor 26 is in contact with the conveyor belt and easily damaged during firing. There is a problem. For example, when the first resistor 23 is formed first and then the second resistor 26 is fired, the second resistor facing upward with the first resistor 23 placed on the conveyor belt facing down. Since the body 26 is baked, the first resistor 23 may come into contact with the surface of the conveyor belt and be damaged. On the other hand, when the first resistor 23 is fired after the second resistor 26 is formed first, the first resistor 26 is placed on the conveyor belt with the second resistor 26 facing down. Since the resistor 23 is baked, the second resistor 26 may come into contact with the surface of the conveyor belt and may be damaged. In any case, the resistor formed earlier may come into contact with the conveyor belt.
そこで、特許文献２に記載されたような凸部を有するコンベアベルトを使用し、この凸部に被処理物（絶縁基板）を搭載して下向きの抵抗体をコンベアベルトの表面から浮かせることにより、先に形成した抵抗体の損傷を回避することが考えられる。しかしながら、凸部に対する絶縁基板の位置精度は非常にシビアであり、僅かな位置ずれによって下向きの抵抗体を傷付けてしまうため、抵抗体の損傷を確実に回避することは困難であった。また、このような凸部をコンベアベルトに設けた場合、絶縁基板を搭載可能なスペースが狭くなって生産効率が低下したり、コンベアベルトのメンテナンス性を悪化させる等の問題が発生する。 Therefore, by using a conveyor belt having a convex portion as described in Patent Document 2, a workpiece (insulating substrate) is mounted on the convex portion, and a downward resistor is floated from the surface of the conveyor belt, It is conceivable to avoid damage to the previously formed resistor. However, the positional accuracy of the insulating substrate with respect to the convex portion is very severe, and a slight positional shift damages the downward resistor, so that it is difficult to reliably prevent the resistor from being damaged. Moreover, when such a convex part is provided in a conveyor belt, the space which can mount an insulation board | substrate becomes narrow, production efficiency falls, problems, such as degrading the maintainability of a conveyor belt, generate | occur | produce.
本発明は、このような従来技術の実情に鑑みてなされたものであり、その第１の目的は、両面の抵抗体の損傷を簡単かつ確実に回避することができるチップ抵抗器を提供することにある。また、本発明の第２の目的は、そのようなチップ抵抗器の製造方法を提供することにある。 The present invention has been made in view of such a state of the art, and a first object of the present invention is to provide a chip resistor capable of easily and reliably avoiding damage to resistors on both sides. It is in. A second object of the present invention is to provide a method for manufacturing such a chip resistor.
上記第１の目的を達成するために、本発明のチップ抵抗器は、絶縁基板の一面の長手方向両端部に設けられた一対の第１電極と、これら一対の第１電極に接続するように前記絶縁基板の一面の長手方向中央部に設けられた第１抵抗体と、前記絶縁基板の他面の長手方向両端部に設けられた一対の第２電極と、これら一対の第２電極に接続するように前記絶縁基板の他面の長手方向中央部に設けられた第２抵抗体と、前記絶縁基板の両端面に設けられて前記第１電極と前記第２電極とを橋絡している一対の外部電極とを備え、前記第１電極がその端部を内側にした状態で前記第１抵抗体に接続されていると共に、前記第２電極がその端部を外側にした状態で前記第２抵抗体に接続されているという構成にした。 In order to achieve the first object, a chip resistor of the present invention is connected to a pair of first electrodes provided at both ends in the longitudinal direction of one surface of an insulating substrate, and to the pair of first electrodes. A first resistor provided at a central portion in the longitudinal direction of one surface of the insulating substrate, a pair of second electrodes provided at both longitudinal ends of the other surface of the insulating substrate, and a connection to the pair of second electrodes As described above, the second resistor provided in the center in the longitudinal direction of the other surface of the insulating substrate and the first electrode and the second electrode provided on both end surfaces of the insulating substrate are bridged. A pair of external electrodes, wherein the first electrode is connected to the first resistor with its end facing inward, and the second electrode has its end facing outward. It was configured to be connected to two resistors.
このように構成されたチップ抵抗器では、抵抗体と電極の接続構造が絶縁基板の表裏両面側で相違しており、いずれか一面側では第１電極の端部を覆うように第１抵抗体が接続されているが、他面側では第２抵抗体の端部を覆うように第２電極が接続されているため、第１抵抗体を形成する前に第２抵抗体を上向きにして乾燥・焼成した後に、絶縁基板を反転して第２抵抗体を下向きにしてコンベアベルトに載置すれば、第２抵抗体の端部に重なる第２電極の厚みによって第２抵抗体とコンベアベルトとの接触を回避することができる。したがって、コンベアベルトにわざわざ凸部等を設けなくても、第１抵抗体や第２抵抗体がコンベアベルトに接触することを回避でき、第１および第２抵抗体の損傷を確実に回避することができる。また、絶縁基板の一面側において、第１電極の端部を覆うように第１抵抗体が接続されているため、第１抵抗体の膜厚を厚く形成して負荷特性を向上させることができる。 In the chip resistor configured as described above, the connection structure of the resistor and the electrode is different on both the front and back sides of the insulating substrate, and the first resistor is provided so as to cover the end of the first electrode on either side. Is connected, but since the second electrode is connected so as to cover the end of the second resistor on the other surface side, the second resistor is dried upward before forming the first resistor. -After firing, if the insulating substrate is inverted and placed on the conveyor belt with the second resistor facing downward, the second resistor and the conveyor belt will depend on the thickness of the second electrode that overlaps the end of the second resistor. Can be avoided. Therefore, it is possible to avoid the first resistor and the second resistor from coming into contact with the conveyor belt without providing a convex portion or the like on the conveyor belt, and to reliably avoid damage to the first and second resistors. Can do. Further, since the first resistor is connected so as to cover the end portion of the first electrode on the one surface side of the insulating substrate, the load characteristic can be improved by forming the first resistor thicker. .
また、上記第２の目的を達成するために、本発明によるチップ抵抗器の製造方法は、絶縁基板の一面の長手方向両端部に一対の第１電極を印刷により形成し、これら第１電極を上向きにしたまま乾燥する第１電極形成工程と、前記第１電極形成工程後に前記絶縁基板の他面の長手方向中央部に第２抵抗体を印刷により形成し、この第２抵抗体を上向きにしたまま乾燥・焼成する第２抵抗体形成工程と、前記第２抵抗体の両端部を覆うように前記絶縁基板の他面の長手方向両端部に一対の第２電極を印刷により形成し、これら第２電極を上向きにしたまま乾燥する第２電極形成工程と、前記第２電極形成工程後に一対の前記第１電極の端部を覆うように前記絶縁基板の一面の長手方向中央部に第１抵抗体を印刷により形成し、この第１抵抗体を上向きにしたまま乾燥・焼成する第１抵抗体形成工程と、を含むことを特徴としている。 In order to achieve the second object, a chip resistor manufacturing method according to the present invention includes a pair of first electrodes formed by printing on both ends in the longitudinal direction of one surface of an insulating substrate. A first electrode forming step that dries while facing upward, and a second resistor is formed by printing in the longitudinal center of the other surface of the insulating substrate after the first electrode forming step, and the second resistor is directed upward A second resistor forming step of drying and firing as it is, and a pair of second electrodes formed by printing on both ends in the longitudinal direction of the other surface of the insulating substrate so as to cover both ends of the second resistor. A second electrode forming step of drying with the second electrode facing upward; and a first central portion in the longitudinal direction of one surface of the insulating substrate so as to cover the ends of the pair of first electrodes after the second electrode forming step. A resistor is formed by printing, and the first resistor is Is characterized in that it comprises a first resistor forming step of drying and firing while the direction, the.
このような工程を経て製造されたチップ抵抗器では、絶縁基板の一面に第１抵抗体を形成しないで第１電極だけを形成した後、絶縁基板の他面に第２抵抗体とその端部を覆うように第２電極とを形成し、しかる後に絶縁基板の一面に第１電極の端部を覆うように第１抵抗体を形成するようにしたので、第１抵抗体の乾燥・焼成工程で第２抵抗体を下向きにしてコンベアベルトに載置した際に、第２抵抗体の端部に重なる第２電極の厚みによって第２抵抗体とコンベアベルトとの接触を回避することが可能となり、コンベアベルトにわざわざ凸部等を設けなくても第１抵抗体と第２抵抗体の損傷を確実に回避することができる。 In the chip resistor manufactured through such processes, after forming only the first electrode without forming the first resistor on one surface of the insulating substrate, the second resistor and its end on the other surface of the insulating substrate. Since the first resistor is formed so as to cover the end portion of the first electrode on one surface of the insulating substrate after that, the first resistor is dried and fired. When the second resistor is placed on the conveyor belt with the second resistor facing downward, the contact between the second resistor and the conveyor belt can be avoided by the thickness of the second electrode overlapping the end of the second resistor. The damage of the first resistor and the second resistor can be reliably avoided without providing a convex portion or the like on the conveyor belt.
本発明のチップ抵抗器は、抵抗体と電極の接続構造が絶縁基板の表裏両面側で相違しており、いずれか一面側では第１電極の端部を覆うように第１抵抗体が接続されているが、他面側では第２抵抗体の端部を覆うように第２電極が接続されているため、第１抵抗体を形成する前に第２抵抗体を上向きにして乾燥・焼成した後に、絶縁基板を反転して第２抵抗体を下向きにしてコンベアベルトに載置すれば、第２抵抗体の端部に重なる第２電極の厚みによって第２抵抗体とコンベアベルトとの接触を回避することが可能となり、コンベアベルトにわざわざ凸部等を設けなくても第１抵抗体と第２抵抗体の損傷を確実に回避することができる。また、絶縁基板の一面側において、第１電極の端部を覆うように第１抵抗体が接続されているため、第１抵抗体の膜厚を厚く形成して負荷特性を向上させることができる。 In the chip resistor of the present invention, the connection structure of the resistor and the electrode is different on both the front and back sides of the insulating substrate, and the first resistor is connected so as to cover the end of the first electrode on either side. However, since the second electrode is connected so as to cover the end of the second resistor on the other side, the second resistor is dried and fired with the second resistor facing upward before forming the first resistor. Later, if the insulating substrate is inverted and placed on the conveyor belt with the second resistor facing downward, the contact between the second resistor and the conveyor belt is made depending on the thickness of the second electrode that overlaps the end of the second resistor. This makes it possible to avoid the damage to the first resistor and the second resistor without providing a convex portion or the like on the conveyor belt. Further, since the first resistor is connected so as to cover the end portion of the first electrode on the one surface side of the insulating substrate, the load characteristic can be improved by forming the first resistor thicker. .
また、本発明によるチップ抵抗器の製造方法は、絶縁基板の一面に第１抵抗体を形成しないで第１電極だけを形成した後、絶縁基板の他面に第２抵抗体とその端部を覆うように第２電極とを形成し、しかる後に絶縁基板の一面に第１電極の端部を覆うように第１抵抗体を形成するようにしたので、第１抵抗体の乾燥・焼成工程で第２抵抗体を下向きにしてコンベアベルトに載置した際に、第２抵抗体の端部に重なる第２電極の厚みによって第２抵抗体とコンベアベルトとの接触を回避することが可能となり、コンベアベルトにわざわざ凸部等を設けなくても第１抵抗体と第２抵抗体の損傷を確実に回避することができる。 Also, in the method of manufacturing a chip resistor according to the present invention, after forming only the first electrode without forming the first resistor on one surface of the insulating substrate, the second resistor and its end are formed on the other surface of the insulating substrate. Since the second electrode is formed so as to cover, and then the first resistor is formed so as to cover the end portion of the first electrode on one surface of the insulating substrate, the first resistor is dried and fired. When placed on the conveyor belt with the second resistor facing downward, it becomes possible to avoid contact between the second resistor and the conveyor belt due to the thickness of the second electrode overlapping the end of the second resistor, Even without providing a convex part or the like on the conveyor belt, damage to the first resistor and the second resistor can be reliably avoided.
以下、発明の実施の形態について図面を参照しながら説明する。図１に示すように、本発明の第１実施形態例に係るチップ抵抗器１は、直方体形状の絶縁基板２と、絶縁基板２の表面（図１では上面）の長手方向両端部に設けられた一対の表面電極３と、絶縁基板２の裏面（図１では下面）の長手方向両端部に設けられた一対の裏面電極４と、一対の表面電極３に両端部を重ね合わせて絶縁基板２の表面に設けられた表面抵抗体５と、一対の裏面電極４に両端部を重ね合わせて絶縁基板２の裏面に設けられた裏面抵抗体６と、表面抵抗体５を被覆する２層構造の表面保護層７と、裏面抵抗体６を被覆する２層構造の裏面保護層８と、表面電極３と裏面電極４を橋絡している一対の端面電極９と、表面電極３と端面電極９および裏面電極４を覆う断面コ字状の外部電極１０とによって主に構成されている。 Hereinafter, embodiments of the invention will be described with reference to the drawings. As shown in FIG. 1, a chip resistor 1 according to a first embodiment of the present invention is provided at a rectangular parallelepiped insulating substrate 2 and at both longitudinal ends of the surface of the insulating substrate 2 (upper surface in FIG. 1). The pair of front surface electrodes 3, the pair of back surface electrodes 4 provided at both ends in the longitudinal direction of the back surface (the lower surface in FIG. 1) of the insulating substrate 2, and the both surfaces of the pair of surface electrodes 3 are overlapped with each other. A two-layer structure that covers the surface resistor 5, the surface resistor 5 provided on the surface of the insulating substrate 2, the back surface resistor 6 provided on the back surface of the insulating substrate 2 with both ends overlapped with each other. A surface protective layer 7, a back surface protective layer 8 having a two-layer structure covering the back surface resistor 6, a pair of end surface electrodes 9 bridging the front surface electrode 3 and the back surface electrode 4, and the front surface electrode 3 and the end surface electrode 9 And the external electrode 10 having a U-shaped cross-section covering the back electrode 4.
絶縁基板２はセラミック等からなり、この絶縁基板２は後述する大判基板を縦横の分割溝に沿って分割して多数個取りされたものである。第１電極である表面電極３はＡｇ−Ｐｄ等のＡｇを主成分とするＡｇ系ペーストをスクリーン印刷して乾燥・焼成させたものであり、第２電極である裏面電極４もＡｇ−Ｐｄ等のＡｇを主成分とするＡｇ系ペーストをスクリーン印刷して乾燥・焼成させたものである。第１抵抗体である表面抵抗体５は酸化ルテニウム等の抵抗体ペーストをスクリーン印刷して乾燥・焼成させたものであり、この表面抵抗体５には抵抗値を調整するためにトリミング溝１１が形成されている。第２抵抗体である裏面抵抗体６も酸化ルテニウム等の抵抗体ペーストをスクリーン印刷して乾燥・焼成させたものであり、この裏面抵抗体６にも抵抗値を調整するためにトリミング溝１２が形成されている。ただし、抵抗体と電極の接続構造が絶縁基板２の表裏両面側で相違しており、表面電極３は表面抵抗体５の端部に潜り込むように接続されているが、裏面電極４は裏面抵抗体６の端部に覆い被さるように接続されている。 The insulating substrate 2 is made of ceramic or the like, and the insulating substrate 2 is obtained by dividing a large-size substrate, which will be described later, along a vertical and horizontal dividing groove and by taking a large number. The surface electrode 3 as the first electrode is obtained by screen-printing and drying and firing an Ag-based paste containing Ag as a main component such as Ag-Pd, and the back electrode 4 as the second electrode is also Ag-Pd or the like. An Ag-based paste mainly composed of Ag is screen-printed, dried and fired. The surface resistor 5 as the first resistor is obtained by screen-printing a resistor paste such as ruthenium oxide, drying and firing, and the surface resistor 5 has trimming grooves 11 for adjusting the resistance value. Is formed. The back resistor 6 as the second resistor is also obtained by screen-printing a resistor paste such as ruthenium oxide, drying and firing, and the back resistor 6 also has a trimming groove 12 for adjusting the resistance value. Is formed. However, the connecting structure of the resistor and the electrode is different on both the front and back sides of the insulating substrate 2, and the surface electrode 3 is connected so as to enter the end of the surface resistor 5, but the back electrode 4 It is connected so as to cover the end of the body 6.
表面保護層７はアンダーコート層１３とオーバーコート層１４の２層構造からなり、裏面保護層８もアンダーコート層１５とオーバーコート層１６の２層構造からなる。アンダーコート層１３，１５はガラスペーストをスクリーン印刷して焼成させたものであり、これらアンダーコート層１３，１５はトリミング溝１１，１２を形成する前に対応する表面抵抗体５や裏面抵抗体６を覆うように形成されている。オーバーコート層１４，１６はエポキシ系の樹脂ペーストをスクリーン印刷して加熱硬化させたものであり、これらオーバーコート層１４，１６は表面抵抗体５や裏面抵抗体６にトリミング溝１１，１２を形成した後に形成されている。 The surface protective layer 7 has a two-layer structure of an undercoat layer 13 and an overcoat layer 14, and the back surface protective layer 8 also has a two-layer structure of an undercoat layer 15 and an overcoat layer 16. The undercoat layers 13 and 15 are obtained by screen-printing and baking glass paste, and these undercoat layers 13 and 15 correspond to the front surface resistor 5 and the back surface resistor 6 before the trimming grooves 11 and 12 are formed. It is formed so as to cover. The overcoat layers 14 and 16 are obtained by screen-printing and curing an epoxy resin paste, and these overcoat layers 14 and 16 form the trimming grooves 11 and 12 in the surface resistor 5 and the back resistor 6. After being formed.
端面電極９は絶縁基板２の端面にスパッタリングにより形成されたものであり、この端面電極９は絶縁基板２に対する密着性が良いニクロム（Ｎｉ／Ｃｒ）からなる。外部電極１０はバリア層１７と半田メッキ層１８の２層構造からなり、内層のバリア層１７はニッケル（Ｎｉ）メッキによって形成され、外層の半田層１８は錫（Ｓｎ）−鉛（Ｐｂ）や鉛フリーのＳｎ等からなる。 The end face electrode 9 is formed on the end face of the insulating substrate 2 by sputtering, and the end face electrode 9 is made of nichrome (Ni / Cr) having good adhesion to the insulating substrate 2. The external electrode 10 has a two-layer structure of a barrier layer 17 and a solder plating layer 18, the inner barrier layer 17 is formed by nickel (Ni) plating, and the outer solder layer 18 is tin (Sn) -lead (Pb) or the like. It consists of lead-free Sn.
次に、このように構成されたチップ抵抗器１の製造工程について、図２を参照しながら説明する。 Next, the manufacturing process of the chip resistor 1 configured as described above will be described with reference to FIG.
まず、絶縁基板２が多数個取りされる大判基板２Ａを準備する。この大判基板２Ａには予め１次分割溝と２次分割溝（いずれも図示省略）が格子状に設けられており、両分割溝によって区切られたマス目の１つ１つが１個分のチップ領域となる。図２には１個分のチップ領域に相当する大判基板２Ａが代表して示されているが、実際は多数個分のチップ領域に相当する大判基板２Ａに対して以下に説明する各工程が一括して行われる。 First, a large substrate 2A from which a large number of insulating substrates 2 are taken is prepared. The large substrate 2A is preliminarily provided with a primary dividing groove and a secondary dividing groove (both not shown) in a lattice shape, and each of the squares divided by both the dividing grooves is one chip. It becomes an area. FIG. 2 representatively shows a large substrate 2A corresponding to one chip area. Actually, however, the following steps are collectively performed for a large substrate 2A corresponding to a large number of chip areas. Done.
すなわち、図２（ａ）に示すように、この大判基板２Ａの一面にＡｇ−Ｐｄペーストをスクリーン印刷した後、図２（ｂ）に示すように、大判基板２Ａをコンベアベルト１９上に搭載したまま図示せぬ炉の中を通過させることにより、印刷形成した未焼成の表面電極３を２００℃程度の温度で乾燥する（第１電極形成工程）。 That is, as shown in FIG. 2A, after screen printing the Ag-Pd paste on one surface of the large substrate 2A, the large substrate 2A is mounted on the conveyor belt 19 as shown in FIG. 2B. By passing it through a furnace (not shown) as it is, the unfired surface electrode 3 formed by printing is dried at a temperature of about 200 ° C. (first electrode forming step).
次に、大判基板２Ａの他面に抵抗体ペーストをスクリーン印刷した後、図２（ｃ）に示すように、表面電極３が下を向くように大判基板２Ａをコンベアベルト１９上に搭載した状態で炉中を通過させることにより、印刷した未焼成の裏面抵抗体６を８５０℃程度の焼成温度で乾燥・焼成し（第２抵抗体形成工程）、その際に乾燥後の表面電極３も同時に焼成する。 Next, after the resistor paste is screen-printed on the other surface of the large substrate 2A, the large substrate 2A is mounted on the conveyor belt 19 so that the surface electrode 3 faces downward as shown in FIG. The printed unfired backside resistor 6 is dried and fired at a firing temperature of about 850 ° C. (second resistor forming step), and the dried surface electrode 3 is simultaneously dried. Bake.
次に、裏面抵抗体６の両端部を覆うように大判基板２Ａの他面にＡｇ−Ｐｄペーストをスクリーン印刷した後、図２（ｄ）に示すように、大判基板２Ａをコンベアベルト１９上に搭載して印刷した未焼成の裏面電極４を２００℃程度の温度で乾燥する（第２電極形成工程）。その際、裏面抵抗体６を上に向けたまま裏面電極４の乾燥が行われるため、焼成後の裏面抵抗体６がコンベアベルト１９の表面に接触することはない。 Next, after the Ag-Pd paste is screen-printed on the other surface of the large substrate 2A so as to cover both ends of the back surface resistor 6, the large substrate 2A is placed on the conveyor belt 19 as shown in FIG. The unfired back electrode 4 mounted and printed is dried at a temperature of about 200 ° C. (second electrode forming step). At that time, since the back electrode 4 is dried with the back resistor 6 facing upward, the back resistor 6 after firing does not come into contact with the surface of the conveyor belt 19.
次に、反転した大判基板２Ａの一面に表面電極３の端部を覆うように抵抗体ペーストをスクリーン印刷した後、図２（ｅ）に示すように、裏面電極４が下を向くように大判基板２Ａをコンベアベルト１９上に搭載した状態で炉中を通過させることにより、印刷した未焼成の表面抵抗体５を８５０℃程度の焼成温度で乾燥・焼成し（第１抵抗体形成工程）、その際に乾燥後の裏面電極４も同時に焼成する。この場合、裏面抵抗体６の端部に重なる裏面電極４の厚みによって、下向きにした裏面抵抗体６とコンベアベルト１９との間に所定の間隙が確保されるため、焼成後の裏面抵抗体６がコンベアベルト１９の表面に接触して損傷する虞はなく、上を向いたまま焼成される表面抵抗体５についてもコンベアベルト１９の表面に接触することはない。 Next, after a resistor paste is screen-printed on one surface of the inverted large substrate 2A so as to cover the end of the front electrode 3, the large electrode is placed so that the back electrode 4 faces downward as shown in FIG. By passing the substrate 2A through the furnace while being mounted on the conveyor belt 19, the printed unfired surface resistor 5 is dried and fired at a firing temperature of about 850 ° C. (first resistor forming step), At that time, the dried back electrode 4 is simultaneously fired. In this case, a predetermined gap is ensured between the back-side resistor 6 and the conveyor belt 19 that are directed downward depending on the thickness of the back-side electrode 4 that overlaps the end portion of the back-side resistor 6. However, the surface resistor 5 that is fired while facing upward does not come into contact with the surface of the conveyor belt 19.
しかる後、表面抵抗体５と裏面抵抗体６を覆う領域にそれぞれガラスペーストをスクリーン印刷した後、これらガラスペーストを６００℃程度の高温で乾燥・焼成することにより、表面抵抗体５を覆うアンダーコート層１３と裏面抵抗体６を覆うアンダーコート層１５をそれぞれ形成する。次に、これらアンダーコート層１３，１５の上からレーザを照射してトリミング溝１１，１２を形成することにより、表面抵抗体５と裏面抵抗体６を所望の抵抗値に調整する。 Thereafter, after the glass paste is screen-printed in the areas covering the surface resistor 5 and the back resistor 6, these glass pastes are dried and fired at a high temperature of about 600 ° C., thereby covering the surface resistor 5. Undercoat layers 15 covering the layer 13 and the backside resistor 6 are formed. Next, laser irradiation is performed on the undercoat layers 13 and 15 to form the trimming grooves 11 and 12, thereby adjusting the surface resistor 5 and the back resistor 6 to desired resistance values.
次に、アンダーコート層１３，１５を覆うようにエポキシ系の樹脂ペーストをスクリーン印刷した後、これら樹脂ペーストを２３０℃程度で加熱硬化して焼付けることによってオーバーコート層１４，１６を形成する。これらオーバーコート層１４，１６は表面抵抗体５と裏面抵抗体６を外部環境から保護するためのものであり、このようにしてアンダーコート層１３，１５とオーバーコート層１４，１６を形成することによって、表面抵抗体５を被覆する２層構造の表面保護層７と裏面抵抗体６を被覆する２層構造の裏面保護層８とが得られる。 Next, after the epoxy resin paste is screen-printed so as to cover the undercoat layers 13 and 15, the overcoat layers 14 and 16 are formed by baking and curing these resin pastes at about 230 ° C. These overcoat layers 14 and 16 are for protecting the front surface resistor 5 and the back surface resistor 6 from the external environment. Thus, the undercoat layers 13 and 15 and the overcoat layers 14 and 16 are formed. Thus, a two-layered surface protective layer 7 covering the surface resistor 5 and a two-layered rear surface protective layer 8 covering the backside resistor 6 are obtained.
ここまでの各工程は多数個取り用の大判基板２Ａに対する一括処理であるが、次なる工程では、大判基板２Ａを１次分割溝に沿って短冊状に分割するという１次ブレーク加工を行うことより、複数個分のチップ領域が設けられた図示せぬ短冊状基板を得る。 Each process so far is a batch process for a large-sized substrate 2A for taking a large number of pieces, but in the next step, a primary break process is performed in which the large-sized substrate 2A is divided into strips along the primary dividing groove. Thus, a strip-shaped substrate (not shown) provided with a plurality of chip regions is obtained.
そして、次なる工程で、短冊状基板の分割面にＣｒ／Ｎｉをスパッタリングすることにより、裏面電極４と表面電極３とを橋絡する端面電極９を形成した後、短冊状基板を２次分割溝に沿って分割するという２次ブレーク加工を行うことにより、チップ抵抗器１と同等の大きさの個片（チップ単体）を得る。 Then, in the next step, the end face electrode 9 that bridges the back electrode 4 and the front electrode 3 is formed by sputtering Cr / Ni on the split surface of the strip-shaped substrate, and then the strip-shaped substrate is secondarily split. By performing a secondary break process of dividing along the groove, a piece (chip alone) having the same size as the chip resistor 1 is obtained.
次に、こうして個片化された各チップ単体の絶縁基板２に電解メッキを施すことにより、絶縁基板２の長手方向両端部にニッケルメッキからなるバリア層１７を形成した後、このバリヤー層１７を被覆するように半田メッキ層１８を電解メッキで形成することにより、図１に示すように、２層構造の端面電極９（バリヤー層１７と半田メッキ層１８）を有するチップ抵抗器１が完成する。 Next, electrolytic plating is performed on the insulating substrate 2 of each chip thus separated to form a barrier layer 17 made of nickel plating at both longitudinal ends of the insulating substrate 2. By forming the solder plating layer 18 by electrolytic plating so as to cover, the chip resistor 1 having the end face electrode 9 (barrier layer 17 and solder plating layer 18) having a two-layer structure is completed as shown in FIG. .
以上説明したように、本実施形態例に係るチップ抵抗器１は、抵抗体と電極の接続構造が絶縁基板２の表裏両面で相違しており、いずれか一面側では表面電極３（第１電極）の端部を覆うように表面抵抗体５（第１抵抗体）が接続されているが、他面側では裏面抵抗体６（第２抵抗体）の端部を覆うように裏面電極４（第２電極）が接続されているため、絶縁基板２の一面に表面抵抗体５を形成しないで表面電極３だけを形成した後、絶縁基板２の他面に裏面抵抗体６とその端部を覆うように裏面電極４を形成し、しかる後に絶縁基板２の一面に表面電極３の端部を覆うように表面抵抗体５を形成するようにすれば、裏面抵抗体６の端部に重なる裏面電極４の厚みによって、下向きにした裏面抵抗体６とコンベアベルト１９との間に所定の間隙を確保することができる。したがって、表面抵抗体５の乾燥・焼成工程で裏面抵抗体６を下向きにしてコンベアベルト１９に載置した際に、裏面抵抗体６がコンベアベルト１９の表面に接触して損傷することを防止できると共に、上を向いたまま焼成される表面抵抗体５についてもコンベアベルト１９の表面に接触することがなくなり、コンベアベルト１９にわざわざ凸部等を設けなくても表面抵抗体５と裏面抵抗体６の損傷を確実に回避することができる。 As described above, in the chip resistor 1 according to this embodiment, the connection structure between the resistor and the electrode is different between the front and back surfaces of the insulating substrate 2, and the surface electrode 3 (first electrode) is provided on either side. The surface resistor 5 (first resistor) is connected so as to cover the end of the back electrode 4 (on the other side) so as to cover the end of the back resistor 6 (second resistor). Since the second electrode) is connected, only the surface electrode 3 is formed on the one surface of the insulating substrate 2 without forming the surface resistor 5, and then the back surface resistor 6 and its end are connected to the other surface of the insulating substrate 2. If the back electrode 4 is formed so as to cover, and then the surface resistor 5 is formed so as to cover the end of the surface electrode 3 on one surface of the insulating substrate 2, the back surface overlaps with the end of the back resistor 6. Depending on the thickness of the electrode 4, there is a predetermined interval between the back-side resistor 6 and the conveyor belt 19 that face downward. It can be ensured. Therefore, it is possible to prevent the backside resistor 6 from coming into contact with the surface of the conveyor belt 19 and being damaged when the backside resistor 6 is placed on the conveyor belt 19 with the backside resistor 6 facing downward in the drying / firing process of the surface resistor 5. At the same time, the surface resistor 5 that is baked while facing upward also does not come into contact with the surface of the conveyor belt 19, and the surface resistor 5 and the back surface resistor 6 do not have to be provided with a convex portion or the like. Can be reliably avoided.
なお、上記した第１実施形態例では、表面抵抗体５と裏面電極４を同時に焼成するようにしたが、表面抵抗体５の形成前（抵抗体ペーストをスクリーン印刷する前）に乾燥後の裏面電極４を焼成するようにしても良く、その場合、一対の裏面電極４間に跨がる裏面抵抗体６の抵抗値を測定しておくことにより、この抵抗値を参考にして表面抵抗体５用の抵抗体ペーストを選定することができるため、後から形成される表面抵抗体５の抵抗値の調整を効率良く行うことができる。 In the first embodiment described above, the surface resistor 5 and the back electrode 4 are fired at the same time, but the back surface after drying before the surface resistor 5 is formed (before screen printing of the resistor paste). The electrode 4 may be fired. In this case, the resistance value of the back surface resistor 6 straddling between the pair of back surface electrodes 4 is measured, and the surface resistor 5 is referred to with reference to the resistance value. Therefore, the resistance value of the surface resistor 5 to be formed later can be adjusted efficiently.
また、上記した第１実施形態例では、表面抵抗体５と裏面抵抗体６の両方にトリミング溝１１，１２を形成してチップ抵抗器１の抵抗値を調整するようにしているが、図３に示す第２実施形態例のように、表面抵抗体５だけにトリミング溝１１を形成して裏面抵抗体６のトリミング溝を省略することも可能である。 In the first embodiment described above, the trimming grooves 11 and 12 are formed in both the front surface resistor 5 and the back surface resistor 6 to adjust the resistance value of the chip resistor 1, but FIG. It is also possible to form the trimming groove 11 only in the surface resistor 5 and omit the trimming groove of the back surface resistor 6 as in the second embodiment shown in FIG.
この第２実施形態例に係るチップ抵抗器１を製造する場合、図２（ｅ）に示す第１抵抗体形成工程までは第１実施形態例と同じであるが、次なる工程では、表面抵抗体５を覆うアンダーコート層１３だけを形成した後、このアンダーコート層１３と表面抵抗体５にレーザを照射してトリミング溝１１を形成する。その際、前もって裏面抵抗体６の抵抗値を測定しておき、その測定結果に応じて表面抵抗体５にトリミング溝１１を形成することにより、チップ抵抗器１全体に要求される抵抗値を所望値に調整する。しかる後、アンダーコート層１３を覆うようにオーバーコート層１４を形成すると共に、裏面抵抗体６を外部環境から保護するために裏面保護層８（オーバーコート層１６）を形成する。なお、それ以降の工程は第１実施形態例と同じであり、最終的に図３に示すようなチップ抵抗器１が得られる。 When the chip resistor 1 according to the second embodiment is manufactured, the process up to the first resistor forming step shown in FIG. 2E is the same as that of the first embodiment. After only the undercoat layer 13 covering the body 5 is formed, the undercoat layer 13 and the surface resistor 5 are irradiated with laser to form the trimming grooves 11. At that time, the resistance value of the back resistor 6 is measured in advance, and the trimming groove 11 is formed in the surface resistor 5 according to the measurement result, so that the resistance value required for the entire chip resistor 1 is desired. Adjust to the value. Thereafter, an overcoat layer 14 is formed so as to cover the undercoat layer 13, and a back surface protective layer 8 (overcoat layer 16) is formed to protect the back surface resistor 6 from the external environment. The subsequent steps are the same as those in the first embodiment, and a chip resistor 1 as shown in FIG. 3 is finally obtained.
また、上記の各実施形態例では、絶縁基板２の一面側で表面電極３（第１電極）がその端部を内側にした状態で表面抵抗体５（第１抵抗体）に接続され、絶縁基板２の他面側で裏面電極４（第２電極）がその端部を外側にした状態で裏面抵抗体６（第２抵抗体）に接続されている場合について説明したが、抵抗体と電極の接続構造の関係は絶縁基板２の表裏両面で逆になっていても良い。すなわち、表面電極の端部を外側にした状態で表面抵抗体に接続すると共に、裏面電極の端部を内側にした状態で裏面抵抗体に接続することも可能であり、この場合は、第２抵抗体となる表面抵抗体を第１抵抗体となる裏面抵抗体よりも先に形成し、裏面抵抗体の焼成時に表面抵抗体を下向きにしてコンベアベルトに載置すれば、表面抵抗体の端部に重なる表面電極（第２電極）の厚みによって表面抵抗体とコンベアベルトとの接触を回避することができる。 Further, in each of the above-described embodiments, the surface electrode 3 (first electrode) is connected to the surface resistor 5 (first resistor) with the end portion inside on the one surface side of the insulating substrate 2 and insulated. Although the case where the back surface electrode 4 (second electrode) is connected to the back surface resistor 6 (second resistor) with the end facing outside on the other surface side of the substrate 2 has been described, the resistor and electrode The relationship of the connection structure may be reversed on both the front and back surfaces of the insulating substrate 2. In other words, it is possible to connect to the surface resistor with the end portion of the front surface electrode facing outward, and to connect to the back surface resistor with the end portion of the back surface electrode facing inward. If the surface resistor serving as the resistor is formed before the back resistor serving as the first resistor and placed on the conveyor belt with the surface resistor facing downward when firing the back resistor, the end of the surface resistor The contact between the surface resistor and the conveyor belt can be avoided by the thickness of the surface electrode (second electrode) overlapping the portion.
１ チップ抵抗器
２ 絶縁基板
２Ａ 大判基板
３ 表面電極（第１電極）
４ 裏面電極（第２電極）
５ 表面抵抗体（第１抵抗体）
６ 裏面抵抗体（第２抵抗体）
７ 表面保護層
８ 裏面保護層
９ 端面電極
１０ 外部電極
１１，１２ トリミング溝
１３，１５ アンダーコート層
１４，１６ オーバーコート層
１７ バリア層
１８ 半田メッキ
１９ コンベアベルト
DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Insulating board 2A Large format board 3 Surface electrode (1st electrode)
4 Back electrode (second electrode)
5 Surface resistor (first resistor)
6 Back resistor (second resistor)
DESCRIPTION OF SYMBOLS 7 Surface protective layer 8 Back surface protective layer 9 End surface electrode 10 External electrode 11, 12 Trimming groove 13, 15 Undercoat layer 14, 16 Overcoat layer 17 Barrier layer 18 Solder plating 19 Conveyor belt
Claims (2)
前記第１電極がその端部を内側にした状態で前記第１抵抗体に接続されていると共に、前記第２電極がその端部を外側にした状態で前記第２抵抗体に接続されていることを特徴とするチップ抵抗器。 A pair of first electrodes provided at both longitudinal ends of one surface of the insulating substrate, and a first resistor provided at a longitudinal central portion of the one surface of the insulating substrate so as to be connected to the pair of first electrodes; A pair of second electrodes provided at both ends in the longitudinal direction of the other surface of the insulating substrate, and a second portion provided at the longitudinal center of the other surface of the insulating substrate so as to be connected to the pair of second electrodes. A two-resistor and a pair of external electrodes provided on both end faces of the insulating substrate and bridging the first electrode and the second electrode;
The first electrode is connected to the first resistor with its end facing inward, and the second electrode is connected to the second resistor with its end facing outward. A chip resistor characterized by that.
前記第１電極形成工程後に前記絶縁基板の他面の長手方向中央部に第２抵抗体を印刷により形成し、この第２抵抗体を上向きにしたまま乾燥・焼成する第２抵抗体形成工程と、
前記第２抵抗体の両端部を覆うように前記絶縁基板の他面の長手方向両端部に一対の第２電極を印刷により形成し、これら第２電極を上向きにしたまま乾燥する第２電極形成工程と、
前記第２電極形成工程後に一対の前記第１電極の端部を覆うように前記絶縁基板の一面の長手方向中央部に第１抵抗体を印刷により形成し、この第１抵抗体を上向きにしたまま乾燥・焼成する第１抵抗体形成工程と、
を含むことを特徴とするチップ抵抗器の製造方法。 A first electrode forming step of forming a pair of first electrodes by printing on both longitudinal ends of one surface of the insulating substrate, and drying the first electrodes facing upward;
A second resistor forming step in which, after the first electrode forming step, a second resistor is formed by printing in a central portion in the longitudinal direction of the other surface of the insulating substrate, and drying and firing are performed with the second resistor facing upward; ,
A second electrode is formed by printing a pair of second electrodes at both longitudinal ends of the other surface of the insulating substrate so as to cover both ends of the second resistor, and drying with the second electrodes facing upward. Process,
After the second electrode forming step, a first resistor is formed by printing at the longitudinal center of one surface of the insulating substrate so as to cover the ends of the pair of first electrodes, and the first resistor is directed upward. A first resistor forming step of drying and baking as it is;
A method for manufacturing a chip resistor, comprising:
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