JP6032911B2 - Photoelectric conversion element and manufacturing method thereof - Google Patents

Description

  The present invention relates to a photoelectric conversion element and a manufacturing method thereof.

  In recent years, a solar cell that directly converts solar energy into electric energy has been rapidly expected as a next-generation energy source particularly from the viewpoint of global environmental problems. There are various types of solar cells, such as those using compound semiconductors or organic materials, but the mainstream is currently using silicon crystals.

  Currently, the most manufactured and sold solar cells have a structure in which electrodes are formed on a light receiving surface that is a surface on which sunlight is incident and a back surface that is the opposite side of the light receiving surface.

  However, when an electrode is formed on the light receiving surface, since there is reflection and absorption of light at the electrode, sunlight incident on the area of the formed electrode is reduced, so a solar cell having an electrode formed only on the back surface Has been developed.

  FIG. 11 is a plan view showing a conventional solar cell in which electrodes are formed only on the back surface disclosed in Patent Document 1. In FIG. FIG. 12 is a cross section of the solar cell taken along line XII-XII shown in FIG.

  On the back surface of the solar cell 300, an n-side electrode 140n and a p-side electrode 140p are formed. Further, an in-junction 120 and an ip junction 130 are formed on the back surface of the semiconductor substrate 111. The in-junction 120 includes an i-type amorphous silicon layer 120i and an n-type amorphous silicon layer 120n. The ip junction 130 includes an i-type amorphous silicon layer 130i and a p-type amorphous silicon layer 130p. The n-type amorphous silicon layer 120n and the p-type amorphous silicon layer 130p are electrically separated by the i-type amorphous silicon layer 130i. 120f is a slope.

  FIG. 13 is a process diagram showing an example of a method for manufacturing a solar cell disclosed in Patent Document 1. As shown in FIG. 13, a method for manufacturing the solar cell 300 will be described with reference to a schematic cross-sectional view.

  First, as shown in FIG. 13A, an i-type amorphous silicon layer 120i and an n-type amorphous silicon layer 120n are sequentially formed on the back surface of a semiconductor substrate 111, which is an n-type single crystal silicon substrate, using a CVD method. To do. Thereby, the in-junction 120 is formed.

  Next, as shown in FIG. 13B, a coating layer 150 is formed on the n-type amorphous silicon layer 120n by CVD. As the coating layer 150, for example, silicon nitride, silicon oxide, or the like can be used.

  Next, as shown in FIG. 13C, a part of the coating layer 150 is removed along the first direction at a predetermined interval by photolithography. Thereby, a plurality of first grooves 150g extending along the first direction are formed.

  Next, as shown in FIG. 13D, a part of the i-type amorphous silicon layer 120i and the n-type amorphous silicon layer 120n are formed by an isotropic etching method using an alkaline aqueous solution using the coating layer 150 as a mask. Removal along the first direction at predetermined intervals. Thereby, a plurality of second grooves 120g extending along the first direction are formed. The second groove 120g is formed so as to extend from the first groove 150g to the semiconductor substrate 111 side and reach the semiconductor substrate 111.

  Here, in the step of forming the second groove 120g, the n-type amorphous silicon layer 120n is provided between one end portion in the second direction substantially orthogonal to the first direction of the coating layer 150 and the semiconductor substrate 111. Also remove the part. That is, the n-type amorphous silicon layer 120n provided under the covering layer 150 is removed so as to cover it. By performing isotropic etching under the covering layer 150, a slope 120f is formed in the in-junction 120.

  Next, as shown in FIG. 13E, an i-type amorphous silicon layer 130i and a p-type amorphous silicon layer 130p are sequentially formed on the bottom and side surfaces of the second groove 120g by using the CVD method. As a result, the ip junction 130 is formed. By forming the i-type amorphous silicon layer 130 i and the p-type amorphous silicon layer 130 p so as to go around the lower part of the covering layer 150, the inclined surface 120 f of the in-junction 120 is covered with the i-type amorphous silicon layer 130 i of the ip junction 130. . The n-type amorphous silicon layer 120n and the p-type amorphous silicon layer 130p are electrically separated by the i-type amorphous silicon layer 130i.

  Next, as shown in FIG. 13F, the entire coating layer 150 is removed by an etching method. As a result, the ip junction 130 and the n-type amorphous silicon layer 120n are exposed. At this time, the end portion of the p-type amorphous silicon layer 130p is covered with the i-type amorphous silicon layer 130i, and the central portion of the p-type amorphous silicon layer 130p is exposed. In this step, the i-type amorphous silicon layer 130 i and the p-type amorphous silicon layer 130 p formed on the surface of the coating layer 150 are removed together with the coating layer 150.

  Next, a transparent electrode layer, which is an indium tin oxide (ITO) layer, is formed along the first direction on the n-type amorphous silicon layer 120n and the p-type amorphous silicon layer 130p by using a sputtering method. Subsequently, a conductive layer that is a silver paste is formed on the transparent electrode layer using a printing method, a coating method, or the like. In this way, solar cell 300 is manufactured.

JP 2010-80887 A

  However, in Patent Document 1, in order to form a pn junction on the back surface, it is necessary to form a film at least twice at the time of forming the pn junction, and at the time of the second film formation, the plasma damage layer due to the first film formation. The film will be formed on top. As a result, there is a problem in that the interface passivation at the second film forming portion is not sufficiently performed and the solar cell characteristics are deteriorated.

  Therefore, according to the embodiment of the present invention, a photoelectric conversion element that does not deteriorate the interface passivation property of the second film forming portion is provided.

  Moreover, according to this Embodiment, the manufacturing method of the photoelectric conversion element which does not reduce the interface passivation property of the 2nd film forming location is provided.

  According to the embodiment of the present invention, the photoelectric conversion element includes a semiconductor substrate and first and second amorphous films. The semiconductor substrate is made of single crystal silicon having the first conductivity type. The first amorphous film is provided in contact with one surface of the semiconductor substrate and includes at least a first impurity layer having a second conductivity type opposite to the first conductivity type. The second amorphous film is provided in contact with one surface of the semiconductor substrate adjacent to the first amorphous film in the in-plane direction of the semiconductor substrate, and the second impurity having the first conductivity type Including at least a layer. The interface between one of the first and second amorphous films and the semiconductor substrate is different from the interface between the other of the first and second amorphous films and the semiconductor substrate in the thickness direction of the semiconductor substrate. Exists.

  According to the embodiment of the present invention, the method for manufacturing a photoelectric conversion element is in contact with one surface of a semiconductor substrate made of single crystal silicon having the first conductivity type and is opposite to the first conductivity type. A first amorphous film including at least a first impurity layer having a second conductivity type, and a second amorphous film including at least a second impurity layer having the first conductivity type. A first step of forming one of the amorphous films; a second step of removing a portion of the one amorphous film in the in-plane direction of the semiconductor substrate and a portion of the semiconductor substrate in contact with the portion; A third step of forming a coating layer on the remaining portion of the one amorphous film, and the other amorphous film of the first and second amorphous films on one surface of the semiconductor substrate and the coating layer And a fourth step of removing the coating layer.

  In the photoelectric conversion element according to the embodiment of the present invention, the interface between one of the first and second amorphous films and the semiconductor substrate is the first and second amorphous films in the thickness direction of the semiconductor substrate. It exists in a position different from the interface between the other of the semiconductor substrate and the semiconductor substrate. As a result, both the first and second amorphous films are formed in contact with the semiconductor substrate free from plasma damage, and the conduction characteristics of carriers (electrons and holes) are improved.

  Therefore, the conversion efficiency of the photoelectric conversion element can be improved.

  In the method of manufacturing a photoelectric conversion element according to the embodiment of the present invention, one of the first and second amorphous films is formed on a semiconductor substrate, and the one amorphous film The other amorphous film of the first and second amorphous films is formed at a position where a part of the semiconductor substrate and a part of the semiconductor substrate in contact with the part are removed. As a result, both the first and second amorphous films are formed in contact with the semiconductor substrate free from plasma damage, and the conduction characteristics of carriers (electrons and holes) are improved.

  Therefore, the conversion efficiency of the photoelectric conversion element can be improved.

It is a top view of the photoelectric conversion element by Embodiment 1 of this invention. It is sectional drawing of the photoelectric conversion element between the lines II-II shown in FIG. FIG. 3 is an enlarged view of the amorphous film shown in FIG. 2. It is a top view of the back surface side of the photoelectric conversion element shown in FIG. It is a 1st process drawing which shows the manufacturing method of the photoelectric conversion element shown to FIG. It is a 2nd process figure which shows the manufacturing method of the photoelectric conversion element shown to FIG. It is sectional drawing which shows a part of photoelectric conversion element back surface side shown in FIG. 6 is a cross-sectional view illustrating a configuration of a photoelectric conversion element according to Embodiment 2. FIG. FIG. 9 is a first process diagram illustrating part of a manufacturing process for the photoelectric conversion element illustrated in FIG. 8. FIG. 9 is a second process diagram illustrating a part of the manufacturing process of the photoelectric conversion element illustrated in FIG. 8. It is a top view showing the conventional solar cell which formed the electrode only in the back surface currently disclosed by patent document 1. FIG. It is a cross section of the solar cell between line XII-XII shown in FIG. It is process drawing which shows an example of the manufacturing method of the solar cell currently disclosed by patent document 1. FIG.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  In this specification, the “amorphous phase” refers to a state in which silicon (Si) atoms and the like are randomly arranged. Moreover, although amorphous silicon is described as “a-Si”, this notation actually means that hydrogen (H) atoms are included. Amorphous silicon carbide (a-SiC), amorphous silicon oxide (a-SiO), amorphous silicon nitride (a-SiN), amorphous silicon carbon nitride (a-SiCN), amorphous silicon germanium (a-SiGe) and amorphous germanium Similarly, (a-Ge) means that an H atom is contained.

[Embodiment 1]
FIG. 1 is a plan view of a photoelectric conversion element according to Embodiment 1 of the present invention. 2 is a cross-sectional view of the photoelectric conversion element taken along the line II-II shown in FIG. FIG. 1 is a plan view of the back side of the photoelectric conversion element. 1 and 2, a photoelectric conversion element 100 according to Embodiment 1 of the present invention includes an n-type single crystal silicon substrate 1, an antireflection film 2, and amorphous films 11 to 1m (m is 2 or more). ), Amorphous films 21 to 2m-1, and electrodes 3 and 4.

  The n-type single crystal silicon substrate 1 has, for example, a (100) plane orientation and a specific resistance of 0.1 to 1.0 Ω · cm. The n-type single crystal silicon substrate 1 has a thickness of 100 to 300 μm, for example, and preferably has a thickness of 100 to 200 μm. Further, the n-type single crystal silicon substrate 1 has a texture structure on the light incident side surface (the surface on which the antireflection film 2 is formed). Further, n-type single crystal silicon substrate 1 has rectangular convex portions 1A and concave portions 1B on the back surface (the surface opposite to the surface on which antireflection film 2 is formed). The height of the convex portion 1A (= depth of the concave portion 1B) is 20 nm to 5 μm.

  The antireflection film 2 is made of, for example, a silicon nitride film, and is provided in contact with the light incident side surface of the n-type single crystal silicon substrate 1. The antireflection film 2 has a thickness of 100 nm, for example.

  Each of the amorphous films 11 to 1m is made of an amorphous phase, and is provided in contact with the surface of the n-type single crystal silicon substrate 1 opposite to the light incident side. More specifically, each of the amorphous films 11 to 1m is provided in contact with the convex portion 1A of the n-type single crystal silicon substrate 1. The amorphous films 11 to 1m are arranged at a desired interval in the in-plane direction of the n-type single crystal silicon substrate 1.

  Amorphous films 21-2m-1 are made of an amorphous phase, and are provided in contact with the surface of n-type single crystal silicon substrate 1 opposite to the light incident side. More specifically, each of amorphous films 21 to 2m−1 is provided in contact with recess 1B of n-type single crystal silicon substrate 1. The amorphous films 21 to 2m−1 are arranged at a desired interval in the in-plane direction of the n-type single crystal silicon substrate 1.

  The electrode 3 is provided in contact with the amorphous films 11 to 1m. The electrode 4 is provided in contact with the amorphous films 21 to 2m−1. And the electrodes 3 and 4 have a comb-shaped planar shape, and are arrange | positioned so that it may mesh | engage alternately. Each of the electrodes 3 and 4 is made of, for example, silver (Ag). As a result, the electrodes 3 and 4 form ohmic contacts with the amorphous films 11 to 1m and the amorphous films 21 to 2m−1, respectively.

  FIG. 3 is an enlarged view of the amorphous films 11 and 21 shown in FIG. Referring to FIG. 3, amorphous film 11 is made of either amorphous film 11A or 11B, and amorphous film 21 is made of any of amorphous films 21A and 21B. Then, there are four combinations of the amorphous films 11A and 11B and the amorphous films 21A and 21B as shown in FIGS.

  The amorphous film 11 </ b> A includes a non-doped layer 101 and a p-type impurity layer 102. Non-doped layer 101 is arranged in contact with convex portion 1 </ b> A of n-type single crystal silicon substrate 1. The p-type impurity layer 102 is disposed in contact with the non-doped layer 101.

The non-doped layer 101 has an i-type conductivity, is made of, for example, i-type a-Si, and has a film thickness of, for example, 5 to 10 nm. The p-type impurity layer 102 has a p-type conductivity, is made of, for example, p-type a-Si, and includes, for example, boron (B) of 5 × 10 ¹⁹ cm ⁻³ . The p-type impurity layer 102 has a thickness of 5 to 10 nm. Therefore, the amorphous film 11A has a total thickness of 10 to 20 nm.

  The amorphous film 21 </ b> A includes a non-doped layer 201 and an n-type impurity layer 202. Non-doped layer 201 is arranged in contact with recess 1 </ b> B of n-type single crystal silicon substrate 1. N-type impurity layer 202 is disposed in contact with non-doped layer 201.

The non-doped layer 201 has i-type conductivity, and is made of, for example, i-type a-Si, and has a film thickness of, for example, 5 nm to 10 nm. The n-type impurity layer 202 has an n-type conductivity type, and is made of, for example, n-type a-Si and includes, for example, phosphorus (P) of 5 × 10 ¹⁹ cm ⁻³ . The n-type impurity layer 202 has a thickness of 5 nm to 10 nm. Therefore, the amorphous film 21A has a total thickness of 10 nm to 20 nm.

The amorphous film 11B is made of a p-type impurity layer 103. P-type impurity layer 103 is disposed in contact with convex portion 1 </ b> A of n-type single crystal silicon substrate 1. In addition, the p-type impurity layer 103 is made of, for example, p-type a-Si, and includes, for example, B of 5 × 10 ¹⁹ cm ⁻³ . Furthermore, the p-type impurity layer 103 has a thickness of 10 to 20 nm.

The amorphous film 21B is made of an n-type impurity layer 203. N-type impurity layer 203 is disposed in contact with recess 1 </ b> B of n-type single crystal silicon substrate 1. The n-type impurity layer 203 is made of, for example, n-type a-Si, and includes, for example, P of 5 × 10 ¹⁹ cm ⁻³ . Further, the n-type impurity layer 203 has a thickness of 10 to 20 nm.

  Thus, the amorphous film 11A is made of i-type a-Si / p-type a-Si, and the amorphous film 11B is made of p-type a-Si. The amorphous film 21A is made of i-type a-Si / n-type a-Si, and the amorphous film 21B is made of n-type a-Si.

  Each of the amorphous films 12 to 1m shown in FIG. 2 is also composed of any of the amorphous films 11A and 11B shown in FIG. 3, and each of the amorphous films 22 to 2m-1 shown in FIG. These are made of either of the amorphous films 21A and 21B shown in FIG.

  Each of the amorphous films 11 to 1m is made of any of the amorphous films 11A and 11B shown in FIG. 3, and each of the amorphous films 21 to 2m-1 is an amorphous film 21A and 21B shown in FIG. The electrode 3 is provided in contact with one of the p-type impurity layers 102 and 103, and the electrode 4 is provided in contact with one of the n-type impurity layers 202 and 203.

  As described above, each of the amorphous films 11 to 1m includes the amorphous film 11A (= non-doped layer 101 / p-type impurity layer 102) or the amorphous film 11B (= p-type impurity layer 103). . Each of the amorphous films 21 to 2m−1 includes the amorphous film 21A (= non-doped layer 201 / n-type impurity layer 202) or the amorphous film 21B (= n-type impurity layer 203). Accordingly, each of the amorphous films 11 to 1m is an amorphous film including at least a p-type impurity layer, and each of the amorphous films 21 to 2m−1 is an amorphous film including at least an n-type impurity layer. It is a membrane.

  Referring to FIGS. 1 and 2 again, the amorphous films 11 to 1m and the amorphous films 21 to 2m-1 have the same length in the direction perpendicular to the paper surface of FIG. The area occupancy ratio, which is the ratio of the total area of the amorphous films 11 to 1 m including at least the p-type impurity layer to the area of the n-type single crystal silicon substrate 1, is 60 to 93%, and is at least n-type. The area occupation ratio, which is the ratio of the total area of the amorphous films 21 to 2m−1 including the impurity layer to the area of the n-type single crystal silicon substrate 1, is 5 to 20%.

  As described above, the area occupation ratio of the amorphous films 11 to 1m including at least the p-type impurity layer is larger than the area occupation ratio of the amorphous films 21 to 2m−1 including at least the n-type impurity layer. Electrons and holes photoexcited in the n-type single crystal silicon substrate 1 are easily separated by a pn junction (amorphous films 11 to 1 m / n type single crystal silicon substrate 1 including at least a p-type impurity layer) and photoexcited. This is to increase the contribution rate of generated electrons and holes to power generation.

  Further, a part of the amorphous film 21 overlaps a part of the amorphous films 11 and 12, and a part of the amorphous film 22 overlaps a part of the amorphous films 12 and 13. Similarly, a part of the amorphous film 2m-1 overlaps a part of the amorphous films 1m-1 and 1m.

  As a result, the photoelectric conversion element 100 has a structure in which the regions 5 to 7 are arranged in the in-plane direction of the n-type single crystal silicon substrate 1. The region 5 is a region where the amorphous films 11 to 1m overlap the amorphous films 21 to 2m−1, the region 6 is a region including the amorphous films 11 to 1m, and the region 7 is a non- This is a region composed of the crystalline films 21-2m-1.

  When the amorphous films 11 to 1m are made of the amorphous film 11A and the amorphous films 21 to 2m-1 are made of the amorphous film 21A, the region 5 is non-doped from the n-type single crystal silicon substrate 1 side. The layer 101 has a structure in which a p-type impurity layer 102, a non-doped layer 201, and an n-type impurity layer 202 are sequentially stacked. The region 7 has a structure in which the non-doped layer 201 and the n-type impurity layer 202 are sequentially stacked from the n-type single crystal silicon substrate 1 side.

  When the amorphous films 11 to 1m are made of the amorphous film 11B and the amorphous films 21 to 2m-1 are made of the amorphous film 21A, the region 5 is formed from the n-type single crystal silicon substrate 1 side. The p-type impurity layer 103, the non-doped layer 201, and the n-type impurity layer 202 are sequentially stacked, and the region 6 has a structure in which the p-type impurity layer 103 is deposited on the n-type single crystal silicon substrate 1. The region 7 has a structure in which a non-doped layer 201 and an n-type impurity layer 202 are sequentially stacked from the n-type single crystal silicon substrate 1 side.

  Further, when the amorphous films 11 to 1m are made of the amorphous film 11A and the amorphous films 21 to 2m-1 are made of the amorphous film 21B, the region 5 is formed from the n-type single crystal silicon substrate 1 side. The non-doped layer 101, the p-type impurity layer 102, and the n-type impurity layer 203 are sequentially stacked. In the region 6, the non-doped layer 101 and the p-type impurity layer 102 are sequentially formed from the n-type single crystal silicon substrate 1 side. The region 7 has a structure in which an n-type impurity layer 203 is deposited on the n-type single crystal silicon substrate 1.

  Further, when the amorphous films 11 to 1m are made of the amorphous film 11B and the amorphous films 21 to 2m-1 are made of the amorphous film 21B, the region 5 is formed from the n-type single crystal silicon substrate 1 side. The p-type impurity layer 103 and the n-type impurity layer 203 are sequentially stacked. The region 6 has a structure in which the p-type impurity layer 103 is deposited on the n-type single crystal silicon substrate 1. The n-type impurity layer 203 is deposited on the n-type single crystal silicon substrate 1.

  4 is a plan view of the back side of the photoelectric conversion element 100 shown in FIG. In FIG. 4, the electrodes 3 and 4 are omitted. Referring to FIG. 4, region 5 has a width of 1 mm or less. This is because when the width of the region 5 is larger than 1 mm, the photoexcited minority carriers cannot reach the electrode, and the power generation efficiency of the photoelectric conversion element 100 decreases.

  In the following, an example will be described in which each of the amorphous films 11 to 1m is made of an amorphous film 11A and each of the amorphous films 21 to 2m-1 is made of an amorphous film 21A.

  FIGS. 5 and 6 are first and second process diagrams showing a method for manufacturing the photoelectric conversion element 100 shown in FIGS.

  A method for manufacturing the photoelectric conversion element 100 will be described. The photoelectric conversion element 100 is manufactured by a plasma CVD method mainly using a plasma apparatus.

  The plasma apparatus includes a preparation chamber, reaction chambers CB1 to CB3, an extraction chamber, a matching unit, and an RF power source. The charging chamber, the reaction chambers CB1 to CB3, and the take-out chamber are arranged in series. A partition valve is used to partition between the charging chamber and the reaction chamber CB1, between the reaction chamber CB1 and the reaction chamber CB2, between the reaction chamber CB2 and the reaction chamber CB3, and between the reaction chamber CB3 and the take-out chamber. It has been. Further, the plasma apparatus is provided with a transport mechanism for sequentially transporting the single crystal silicon substrate from the preparation chamber to the reaction chamber CB1, the reaction chamber CB2, the reaction chamber CB3, and the take-out chamber.

The charging chamber includes a heating mechanism and an exhaust mechanism. The heating mechanism raises the temperature of the single crystal silicon substrate to a predetermined temperature. The exhaust mechanism exhausts the gas in the preparation chamber, and sets the ultimate pressure in the preparation chamber to, for example, 1 × 10 ⁻⁵ Pa or less.

Each of the reaction chambers CB1 to CB3 includes a parallel plate electrode, a heating mechanism, and an exhaust mechanism. The heating mechanism raises the temperature of the single crystal silicon substrate to a predetermined temperature. The exhaust mechanism exhausts the gases in the reaction chambers CB1 to CB3, and sets the ultimate pressure in the reaction chambers CB1 to CB3 to, for example, 1 × 10 ⁻⁵ Pa or less. The parallel plate electrodes are connected to an RF power source through a matching unit. The reaction chamber CB1 is a reaction chamber for depositing i-type a-Si, the reaction chamber CB2 is a reaction chamber for depositing p-type a-Si, and the reaction chamber CB3 is an n-type a-a. A reaction chamber for depositing Si.

The take-out chamber includes an exhaust mechanism. The exhaust mechanism exhausts the gas in the extraction chamber and sets the ultimate pressure in the extraction chamber to, for example, 1 × 10 ⁻⁵ Pa or less.

  Each exhaust mechanism of the charging chamber, the reaction chambers CB1 to CB3, and the take-out chamber includes a turbo molecular pump, a mechanical booster pump, and a rotary pump. The turbo molecular pump, the mechanical booster pump and the rotary pump are serially connected to the charging chamber, the reaction chambers CB1 to CB3 and the extraction chamber, respectively, so that the turbo molecular pump is closest to the charging chamber, the reaction chambers CB1 to CB3 and the extraction chamber. It is connected to. Each exhaust mechanism exhausts the gas in the charging chamber, reaction chambers CB1 to CB3, and the extraction chamber with a turbo molecular pump, a mechanical booster pump, and a rotary pump, respectively, or is charged with a mechanical booster pump and a rotary pump, respectively. The gases in the chamber, reaction chambers CB1 to CB3 and the extraction chamber are exhausted.

  The RF power source applies, for example, RF power of 13.56 MHz to the parallel plate electrodes of the reaction chambers CB1 to CB3 via the matching unit.

  When the manufacture of the photoelectric conversion element 100 is started, the n-type single crystal silicon substrate 1 is ultrasonically cleaned with ethanol or the like and degreased, and the surface of the n-type single crystal silicon substrate 1 is chemically anisotropic using an alkali. Etching is performed to texture the surface of the n-type single crystal silicon substrate 1. Thereafter, the n-type single crystal silicon substrate 1 is immersed in hydrofluoric acid to remove the natural oxide film formed on the surface of the n-type single crystal silicon substrate 1, and the surface of the n-type single crystal silicon substrate 1 is hydrogenated. Terminate (see step (a) in FIG. 5).

  When the cleaning of the n-type single crystal silicon substrate 1 is completed, the n-type single crystal silicon substrate 1 is put into a sputtering apparatus, and an antireflection film 2 made of a silicon nitride film is sputtered on the light incident side of the n-type single crystal silicon substrate 1. Form on the surface (see step (b) in FIG. 5).

  Then, the n-type single crystal silicon substrate 1 / antireflection film 2 is disposed on the substrate holder in the preparation chamber of the plasma apparatus.

After that, the evacuation mechanism in the preparation chamber exhausts the gas in the preparation chamber to 1 × 10 ⁻⁵ Pa or less, and the heating mechanism in the preparation chamber sets the temperature of the n-type single crystal silicon substrate 1 / antireflection film 2 to 200 ° C. Heat the substrate holder to set.

  When the temperature of the n-type single crystal silicon substrate 1 / antireflection film 2 reaches 200 ° C., the partition valve between the preparation chamber and the reaction chamber CB1 is opened, and the n-type single crystal silicon substrate 1 / antireflection film 2 is Then, it is transferred from the preparation chamber to the reaction chamber CB1.

  Table 1 shows the flow rates of the material gases when forming the non-doped layers 101 and 201, the p-type impurity layers 102 and 103, and the n-type impurity layers 202 and 203.

When the n-type single crystal silicon substrate 1 / antireflection film 2 is transported to the reaction chamber CB1, 10 sccm of silane (SiH ₄ ) gas and 100 sccm of hydrogen (H ₂ ) gas are allowed to flow into the reaction chamber CB1. The pressure of CB1 is set in the range of 13.3 Pa to 665 Pa. The RF power source applies RF power in the range of 16 to 80 mW / cm ² to the parallel plate electrodes through the matching unit. As a result, plasma is generated in the reaction chamber CB1, and the non-doped layer 18 made of i-type a-Si is on the surface of the n-type single crystal silicon substrate 1 (= the surface opposite to the surface on which the antireflection film 2 is formed). It is deposited on.

When the film thickness of the non-doped layer 18 is 5 to 10 nm, the application of RF power to the parallel plate electrodes in the reaction chamber CB1 is stopped, and the supply of SiH ₄ gas and H ₂ gas to the reaction chamber CB1 is stopped, and the exhaust gas is exhausted. The reaction chamber CB1 is evacuated to 1 × 10 ⁻⁵ Pa or less by the mechanism. Then, the gate valve is opened, and the non-doped layer 18 / n-type single crystal silicon substrate 1 / antireflection film 2 is transferred from the reaction chamber CB1 to the reaction chamber CB2.

Thereafter, 2 sccm of SiH ₄ gas, 42 sccm of H ₂ gas, and 12 sccm of diborane (B ₂ H ₆ ) gas diluted with hydrogen are flowed into the reaction chamber CB2, and the pressure in the reaction chamber CB2 is set to 13.3 Pa to 665 Pa. Set to range. The RF power source applies RF power in the range of 16 to 80 mW / cm ² to the parallel plate electrodes through the matching unit. The concentration of B ₂ H ₆ gas diluted with hydrogen is 0.1%.

  As a result, plasma is generated in the reaction chamber CB2, and the p-type impurity layer 19 made of p-type a-Si is deposited on the non-doped layer 18. As a result, the amorphous film 20 for the amorphous films 11 to 1 m is formed on the back surface of the n-type single crystal silicon substrate 1 (the surface opposite to the surface on which the antireflection film 2 is formed) (FIG. 5). Step (c)).

When the thickness of the p-type impurity layer 19 is 5 to 10 nm, the application of RF power to the parallel plate electrodes in the reaction chamber CB2 is stopped, and the reaction chamber CB2 for SiH ₄ gas, H ₂ gas, and B ₂ H ₆ gas is used. The reaction chamber CB2 is evacuated to 1 × 10 ⁻⁵ Pa or less by an exhaust mechanism. Then, the gate valve is opened, and the amorphous film 20 / n-type single crystal silicon substrate 1 / antireflection film 2 is transferred from the reaction chamber CB2 to the take-out chamber. The antireflection film 2 is cooled to room temperature and then taken out.

  Then, a resist is applied to the entire surface of the amorphous film 20 of the extracted amorphous film 20 / n-type single crystal silicon substrate 1 / antireflection film 2, and the applied resist is patterned by photolithography to form a resist pattern. 30 is formed (see step (d) in FIG. 5).

  Thereafter, the amorphous film 20 and a part of the n-type single crystal silicon substrate 1 are etched by dry etching or wet etching using the resist pattern 30 as a mask to form amorphous films 11 to 1m (step of FIG. e)). In this case, n-type single crystal silicon substrate 1 is etched in the thickness direction by 20 nm to 5 μm to form convex portions 1A and concave portions 1B. Thereby, the plasma damage layer when the amorphous film 20 is formed by the plasma CVD method is removed.

  Subsequently, a coating layer is formed on the entire back surface of the n-type single crystal silicon substrate 1 of the amorphous film 11 to 1 m / n type single crystal silicon substrate 1 / antireflection film 2, and then photolithography and etching are performed. The coating layer 40 is formed on the amorphous films 11 to 1m while leaving the coating layer on the amorphous films 11 to 1m (see step (f) in FIG. 6). In this case, the coating layer 40 is formed such that the dimension of the coating layer 40 in the in-plane direction DR1 of the n-type single crystal silicon substrate 1 is smaller than the dimension of the amorphous films 11 to 1m in the in-plane direction DR1. The covering layer 40 is made of a silicon nitride film or a silicon oxide film and has a thickness of about 100 nm.

  Then, the recess 1B of the n-type single crystal silicon substrate 1 of the coating layer 40 / amorphous film 11 to 1 m / n type single crystal silicon substrate 1 / antireflection film 2 is washed with hydrofluoric acid, and the coating layer 40 / non-crystalline The material films 11 to 1 m / n type single crystal silicon substrate 1 / antireflection film 2 are arranged on the substrate holder in the preparation chamber of the plasma apparatus.

And the exhaust mechanism of the preparation chamber exhausts the gas in the preparation chamber to 1 × 10 ⁻⁵ Pa or less, and the heating mechanism of the preparation chamber is the coating layer 40 / amorphous film 11 to 1 m / n type single crystal silicon substrate. 1 / The substrate holder is heated so that the temperature of the antireflection film 2 is set to 200 ° C.

  When the temperature of the coating layer 40 / amorphous film 11 to 1 m / n type single crystal silicon substrate 1 / antireflection film 2 reaches 200 ° C., the coating layer 40 / amorphous film 11 to 1 m / n type single crystal silicon The substrate 1 / antireflection film 2 is transferred from the preparation chamber to the reaction chamber CB1.

When coating layer 40 / amorphous film 11-1 m / n type single crystal silicon substrate 1 / antireflection film 2 is transferred to reaction chamber CB1, 10 sccm of SiH ₄ gas and 100 sccm of H ₂ gas are reacted into reaction chamber. Flow through CB1 (see Table 1), and set the pressure in the reaction chamber CB1 to a range of 13.3 Pa to 665 Pa. The RF power source applies RF power in the range of 16 to 80 mW / cm ² to the parallel plate electrodes through the matching unit. As a result, plasma is generated in the reaction chamber CB1, and the non-doped layer 48 made of i-type a-Si is formed on the amorphous films 11 to 1m, on the coating layer 40, and on the recess 1B of the n-type single crystal silicon substrate 1. Is deposited.

When the film thickness of the non-doped layer 48 becomes 5 to 10 nm, the application of RF power to the parallel plate electrodes in the reaction chamber CB1 is stopped, the supply of SiH ₄ gas and H ₂ gas to the reaction chamber CB1 is stopped, and the exhaust gas is exhausted. The reaction chamber CB1 is evacuated to 1 × 10 ⁻⁵ Pa or less by the mechanism. Then, the gate valve is opened, and the non-doped layer 48 / coating layer 40 / amorphous film 11-1 m / n type single crystal silicon substrate 1 / antireflection film 2 is transferred from the reaction chamber CB1 to the reaction chamber CB3.

When the non-doped layer 48 / coating layer 40 / amorphous film 11 to 1 m / n type single crystal silicon substrate 1 / antireflection film 2 is transferred to the reaction chamber CB3, 20 sccm of SiH ₄ gas and 150 sccm of H ₂ gas are used. Then, 50 sccm of phosphine (PH ₃ ) gas diluted with hydrogen is allowed to flow into the reaction chamber CB3 (see Table 1), and the pressure in the reaction chamber CB3 is set in the range of 13.3 Pa to 665 Pa. The RF power source applies RF power in the range of 16 to 80 mW / cm ² to the parallel plate electrodes through the matching unit. The concentration of PH ₃ gas diluted with hydrogen is 0.2%.

  As a result, plasma is generated in the reaction chamber CB3, and an n-type impurity layer 49 made of n-type a-Si is deposited on the non-doped layer 48. As a result, an amorphous film 50 for the amorphous films 21-2m-1 is formed on the entire back surface of the n-type single crystal silicon substrate 1 (see step (g) in FIG. 6).

When the film thickness of the n-type impurity layer 49 is 5 to 10 nm, the application of RF power to the parallel plate electrodes in the reaction chamber CB3 is stopped, and the SiH ₄ gas, H ₂ gas, and PH ₃ gas are supplied to the reaction chamber CB3. The supply is stopped, and the reaction chamber CB3 is evacuated to 1 × 10 ⁻⁵ Pa or less by an exhaust mechanism. Then, the gate valve is opened, and the amorphous film 50 / coating layer 40 / amorphous film 11 to 1 m / n type single crystal silicon substrate 1 / antireflection film 2 is transferred from the reaction chamber CB3 to the take-out chamber. Then, the amorphous film 50 / coating layer 40 / amorphous film 11 to 1 m / n type single crystal silicon substrate 1 / antireflection film 2 is cooled to room temperature and taken out from the take-out chamber.

  Thereafter, the coating layer 40 of the amorphous film 50 / coating layer 40 / amorphous film 11 to 1 m / n type single crystal silicon substrate 1 / antireflection film 2 is removed using an acidic etching solution. As a result, the amorphous film 50 on the covering layer 40 is removed by lift-off, and the amorphous films 11 to 1m are formed on the convex portions 1A of the n-type single crystal silicon substrate 1, and the amorphous films 21 to 2m are formed. -1 is formed on the recess 1B of the n-type single crystal silicon substrate 1 (see step (h) in FIG. 6).

  Then, Ag 3 is deposited on the amorphous films 11 to 1 m and 21 to 2 m−1 to form the electrodes 3 and 4. Thereby, the photoelectric conversion element 100 is completed (see step (i) in FIG. 6).

  As described above, by making the dimension in the in-plane direction DR1 of the coating layer 40 smaller than the dimension in the in-plane direction DR1 of the amorphous films 11 to 1m, in the step (g), the non-doped layer 48 (= i type) The coverage when depositing (a-Si) can be improved, and the n-type a-Si deposited thereafter and the p-type a-Si already deposited are more reliably electrically separated. be able to.

  In the photoelectric conversion element 100, when sunlight is irradiated onto the photoelectric conversion element 100 from the antireflection film 2 side, electrons and holes are photoexcited in the n-type single crystal silicon substrate 1.

  Even if the photoexcited electrons and holes diffuse to the antireflection film 2 side, they are difficult to recombine due to the passivation effect of the n-type single crystal silicon substrate 1 by the antireflection film 2, and the amorphous films 11 to 1m, 21 Diffuses to ~ 2m-1 side.

  The electrons and holes diffused toward the amorphous films 11 to 1m and 21 to 2m-1 are (amorphous films 11 to 1m including the non-doped layer 101 and the p-type impurity layer 102) / n-type single crystal. The holes are separated by an internal electric field by the silicon substrate 1 (= pin junction), and holes reach the electrode 3 through the amorphous films 11 to 1m (= non-doped layer 101 / p-type impurity layer 102), and the electrons are It reaches the electrode 4 through the amorphous films 21 to 2m−1 (= non-doped layer 201 / n-type impurity layer 202).

  The electrons that have reached the electrode 4 reach the electrode 3 via a load connected between the electrodes 3 and 4 and recombine with the holes.

  In this way, the photoelectric conversion element 100 converts the electrons and holes photoexcited in the n-type single crystal silicon substrate 1 into the back surface of the n-type single crystal silicon substrate 1 (= n-type single crystal on which the antireflection film 2 is formed). This is a back contact type photoelectric conversion element taken out from the surface opposite to the surface of the silicon substrate 1.

  In the photoelectric conversion element 100, the amorphous films 21 to 2m-1 including the n-type impurity layer 202 are removed after the back surface side of the n-type single crystal silicon substrate 1 has a depth of 20 nm to 5 μm. The n-type single crystal silicon substrate 1 is formed in contact with the back surface (= recessed portion 1B) (see steps (f), (g), and (h)).

  As a result, the amorphous films 21 to 2m−1 including the n-type impurity layer 202 are formed on the back surface (= recessed portion) of the n-type single crystal silicon substrate 1 from which the plasma damage layer when the amorphous film 20 is formed is removed. 1B), the amorphous films 11 to 1m including the p-type impurity layer 102 are formed in contact with the back surface (= projection 1A) of the n-type single crystal silicon substrate 1 without plasma damage. , Electrons reach the electrode 4 through the amorphous films 21 to 2m-1 from the back surface of the n-type single crystal silicon substrate 1 from which the plasma damage layer has been removed, and the holes are n-type single crystals having no plasma damage. It reaches the electrode 3 from the back surface of the crystalline silicon substrate 1 through the amorphous films 11 to 1 m. That is, holes and electrons reach the electrodes from the back surface of the n-type single crystal silicon substrate 1 without plasma damage through the amorphous films 11 to 1m and 21 to 2m−1, respectively.

  Therefore, in the photoelectric conversion element 100, the conduction characteristics with respect to carriers (electrons and holes) can be improved, and the conversion efficiency of the photoelectric conversion element 100 can be improved.

  In the above description, the case where the amorphous films 11 to 1m are made of the amorphous film 11A and the amorphous films 21 to 2m-1 are made of the amorphous film 21A (see FIG. 3A) has been described. However, the amorphous films 11 to 1m may be made of the amorphous film 11B, and the amorphous films 21 to 2m-1 may be made of the amorphous film 21A (see FIG. 3B). In this case, in step (c) of FIG. 5, the p-type a-Si for the p-type impurity layer 103 uses the gas flow rate shown in Table 1 to form the back surface of the n-type single crystal silicon substrate 1 (the antireflection film 2 is formed). On the opposite side of the surface).

  As a result, even when the amorphous films 11 to 1m are made of the amorphous film 11B, the amorphous films 21 to 2m-1 including the n-type impurity layer 202 are 20 nm on the back side of the n-type single crystal silicon substrate 1. It is formed in contact with the back surface (= recessed portion 1B) of n-type single crystal silicon substrate 1 after being removed over a depth of ˜5 μm (see steps (f), (g), (h)). Therefore, also when the amorphous films 11 to 1m are made of the amorphous film 11B and the amorphous films 21 to 2m-1 are made of the amorphous film 21A, as described above, carriers (electrons and holes) are formed. Therefore, the conversion characteristic of the photoelectric conversion element 100 can be improved.

  Further, the amorphous films 11 to 1m may be made of the amorphous film 11A, and the amorphous films 21 to 2m-1 may be made of the amorphous film 21B (see FIG. 3C). In this case, in the step (g) of FIG. 6, n-type a-Si for the n-type impurity layer 203 is deposited on the entire back surface side of the n-type single crystal silicon substrate 1 using the gas flow rate shown in Table 1. .

  As a result, even when the amorphous films 21 to 2m-1 are made of the amorphous film 21B, the amorphous films 21 to 2m-1 made of the n-type impurity layer 203 are formed on the back surface of the n-type single crystal silicon substrate 1. The side is formed in contact with the back surface (= recessed portion 1B) of the n-type single crystal silicon substrate 1 after being removed over a depth of 20 nm to 5 μm (see steps (f), (g), (h)) . Therefore, when the amorphous films 11 to 1m are made of the amorphous film 11A and the amorphous films 21 to 2m-1 are made of the amorphous film 21B, as described above, carriers (electrons and holes) are also formed. Therefore, the conversion characteristic of the photoelectric conversion element 100 can be improved.

  Further, the amorphous films 11 to 1m may be made of an amorphous film 11B, and the amorphous films 21 to 2m-1 may be made of an amorphous film 21B (see FIG. 3D). In this case, in step (c) of FIG. 5, the p-type a-Si for the p-type impurity layer 103 uses the gas flow rate shown in Table 1 to form the back surface of the n-type single crystal silicon substrate 1 (the antireflection film 2 is formed). On the opposite side of the surface). 6, n-type a-Si for the n-type impurity layer 203 is deposited on the entire back surface of the n-type single crystal silicon substrate 1 using the gas flow rate shown in Table 1.

  As a result, even when the amorphous films 11 to 1m are made of the amorphous film 11B and the amorphous films 21 to 2m-1 are made of the amorphous film 21B, the amorphous film made of the n-type impurity layer 203 is used. 21 to 2m−1 are formed in contact with the back surface (= recessed portion 1B) of the n-type single crystal silicon substrate 1 after the back surface side of the n-type single crystal silicon substrate 1 is removed over a depth of 20 nm to 5 μm. (See steps (f), (g), (h)). Therefore, when the amorphous films 11 to 1m are made of the amorphous film 11B and the amorphous films 21 to 2m-1 are made of the amorphous film 21B, as described above, carriers (electrons and holes) are also formed. Therefore, the conversion characteristic of the photoelectric conversion element 100 can be improved.

  In the above description, it has been described that the non-doped layer 101 constituting the amorphous films 11 to 1m is made of i-type a-Si. However, in Embodiment 1, the non-doped layer 101 is not limited to this. It may consist of any one of type a-SiC, i-type a-SiO, i-type a-SiN, i-type a-SiCN, and i-type a-SiGe.

  Further, it has been described that each of the p-type impurity layers 102 and 103 constituting the amorphous films 11 to 1m is made of p-type a-Si. However, in the first embodiment, the p-type impurity layer is not limited thereto. Each of 102 and 103 may be composed of any one of p-type a-SiC, p-type a-SiO, p-type a-SiN, p-type a-SiCN, p-type a-SiGe, and p-type a-Ge. Good.

  Furthermore, although it has been described that the non-doped layer 201 constituting the amorphous films 21 to 2m-1 is made of i-type a-Si, in Embodiment 1, the present invention is not limited to this, and the non-doped layer 201 is made of i-type a-a. -SiC, i-type a-SiO, i-type a-SiN, i-type a-SiCN, and i-type a-SiGe may be included.

  Further, it has been described that each of the n-type impurity layers 202 and 203 constituting the amorphous films 21 to 2m-1 is made of n-type a-Si. However, the first embodiment is not limited thereto, and the n-type impurity layers 202 and 203 are not limited to this. Each of the impurity layers 202 and 203 is made of any of n-type a-SiC, n-type a-SiO, n-type a-SiN, n-type a-SiCN, n-type a-SiGe, and n-type a-Ge. May be.

  That is, in the photoelectric conversion element 100, the p-type impurity layers 102 and 103, the n-type impurity layers 202 and 203, and the non-doped layers 101 and 201 may each be made of any of the materials shown in Table 2.

In this case, the p-type a-SiC is formed by the above-described plasma CVD method using SiH ₄ gas, methane (CH ₄ ) gas, B ₂ H ₆ gas, and H ₂ gas as material gases. The p-type a-SiO is formed by the above-described plasma CVD method using SiH ₄ gas, oxygen (O ₂ ) gas, B ₂ H ₆ gas and H ₂ gas as material gases. The p-type a-SiN is formed by the above-described plasma CVD method using SiH ₄ gas, ammonia (NH ₃ ) gas, B ₂ H ₆ gas and H ₂ gas as material gases. The p-type a-SiCN is formed by the above-described plasma CVD method using SiH ₄ gas, CH ₄ gas, NH ₃ gas, B ₂ H ₆ gas and H ₂ gas as material gases. The p-type a-SiGe is formed by the above-described plasma CVD method using SiH ₄ gas, germane (GeH ₄ ) gas, B ₂ H ₆ gas and H ₂ gas as material gases. The p-type a-Ge is formed by the above-described plasma CVD method using GeH ₄ gas, B ₂ H ₆ gas, and H ₂ gas as material gases.

The n-type a-SiC is formed by the above-described plasma CVD method using SiH ₄ gas, CH ₄ gas, PH ₃ gas, and H ₂ gas as material gases. The n-type a-SiO is formed by the above-described plasma CVD method using SiH ₄ gas, O ₂ gas, PH ₃ gas, and H ₂ gas as material gases. The n-type a-SiN is formed by the above-described plasma CVD method using SiH ₄ gas, NH ₃ gas, PH ₃ gas, and H ₂ gas as material gases. The n-type a-SiCN is formed by the above-described plasma CVD method using SiH ₄ gas, CH ₄ gas, NH ₃ gas, PH ₃ gas, and H ₂ gas as material gases. The n-type a-SiGe is formed by the above-described plasma CVD method using SiH ₄ gas, GeH ₄ gas, PH ₃ gas, and H ₂ gas as material gases. The n-type a-Ge is formed by the above-described plasma CVD method using GeH ₄ gas, PH ₃ gas, and H ₂ gas as material gases.

Furthermore, i-type a-SiC is formed by the above-described plasma CVD method using SiH ₄ gas, CH ₄ gas, and H ₂ gas as material gases. i-type a-SiO is formed by the above-described plasma CVD method using SiH ₄ gas, O ₂ gas, and H ₂ gas as material gases. i-type a-SiN is formed by the above-described plasma CVD method using SiH ₄ gas, NH ₃ gas, and H ₂ gas as material gases. The i-type a-SiCN is formed by the above-described plasma CVD method using SiH ₄ gas, CH ₄ gas, NH ₃ gas, and H ₂ gas as material gases. i-type a-SiGe is formed by the above-described plasma CVD method using SiH ₄ gas, GeH ₄ gas, and H ₂ gas as material gases.

  Note that i-type a-Ge is also assumed as the non-doped layers 101 and 201. However, since i-type a-Ge has a smaller optical band gap than the n-type single crystal silicon substrate 1, i-type a-Ge is used. When used as the non-doped layers 101 and 201, it is difficult to improve the open circuit voltage Voc. This is because, in the photoelectric conversion element 100, the optical band gaps of the non-doped layers 101 and 201 in the amorphous films 11 to 1m and 21 to 2m−1 dominately determine the open circuit voltage Voc.

  Therefore, in the first embodiment, i-type a-SiC, i-type a-SiO, i-type a-SiN, and i-type a- having an optical band gap larger than the optical band gap of the n-type single crystal silicon substrate 1. SiCN, i-type a-Si, and i-type a-SiGe are used as the non-doped layers 101 and 201.

  FIG. 7 is a cross-sectional view showing a part of the back side of the photoelectric conversion element 100 shown in FIGS. Referring to FIG. 7, coating layer 40 has a tapered shape 41 at the end in in-plane direction DR1. The tapered shape 41 is formed so that the film thickness of the coating layer 40 gradually increases in the direction from the recess 1B of the n-type single crystal silicon substrate 1 toward the amorphous films 11 and 12 side. The tapered shape 41 is formed by dry etching or wet etching.

  By making the dimension of the coating layer 40 in the in-plane direction DR1 smaller than the dimension of the amorphous films 11 and 12 in the in-plane direction DR1, and providing the tapered shape 41 at the end in the in-plane direction DR1 of the coating layer 40, The coverage of the non-doped layer 48 (= i-type a-Si) is further improved.

  When the non-doped layer 48 (= i-type a-Si) and the n-type impurity layer 49 (= n-type a-Si film) on the covering layer 40 are removed by lift-off, the vicinity of the dotted line shown in FIG. The outer non-doped layer 48 (= i-type a-Si) and n-type impurity layer 49 (= n-type a-Si film) are removed.

  Accordingly, by providing the cover layer 40 with the tapered shape 41, the amorphous films 21 to 2m-1 can be formed with good coverage.

[Embodiment 2]
FIG. 8 is a cross-sectional view showing the configuration of the photoelectric conversion element according to the second embodiment. Referring to FIG. 8, in photoelectric conversion element 200 according to the second embodiment, amorphous film 11 replaces n-type single crystal silicon substrate 1 of photoelectric conversion element 100 shown in FIG. ˜1 m and the amorphous films 21 to 2 m−1 are respectively replaced with the amorphous films 61 to 6 m and the amorphous films 71 to 7 m−1, and the others are the same as the photoelectric conversion element 100.

  The n-type single crystal silicon substrate 301 has, for example, a (100) plane orientation and a specific resistance of 0.1 to 1.0 Ω · cm. The n-type single crystal silicon substrate 301 has a thickness of, for example, 100 to 300 μm, and preferably has a thickness of 100 to 200 μm. Further, the n-type single crystal silicon substrate 301 has a textured surface on the light incident side. Furthermore, n-type single crystal silicon substrate 301 has rectangular convex portions 301A and concave portions 301B on the back surface (the surface opposite to the surface on which antireflection film 2 is formed). The height of the convex portion 301A (= depth of the concave portion 301B) is 20 nm to 5 μm.

  Each of the amorphous films 61 to 6m includes the above-described amorphous film 11A or amorphous film 11B (see FIG. 3), and is disposed in the recess 301B. The amorphous films 61 to 6m have the same film thickness as the amorphous films 11 to 1m.

  Each of the amorphous films 71 to 7m-1 includes the above-described amorphous film 21A or amorphous film 21B (see FIG. 3), and is disposed on the convex portion 301A. The amorphous films 71 to 7m-1 have the same film thickness as the amorphous films 21 to 2m-1.

  A part of the amorphous films 61 to 6m overlaps a part of the amorphous films 71 to 7m-1.

  As a result, the photoelectric conversion element 200 has a structure in which the regions 31 to 33 are arranged in the in-plane direction DR1 of the n-type single crystal silicon substrate 301. The region 31 is a region where the amorphous films 61 to 6m overlap the amorphous films 71 to 7m−1, the region 32 is a region composed of the amorphous films 71 to 7m−1, and the region 33 is This is a region composed of amorphous films 61 to 6m.

  When the amorphous films 61 to 6m are made of the amorphous film 11A and the amorphous films 71 to 7m-1 are made of the amorphous film 21A, the region 31 is non-doped from the n-type single crystal silicon substrate 301 side. A layer 201, an n-type impurity layer 202, a non-doped layer 101, and a p-type impurity layer 102 are sequentially stacked. The region 33 has a structure in which the non-doped layer 101 and the p-type impurity layer 102 are sequentially stacked from the n-type single crystal silicon substrate 301 side.

  When the amorphous films 61 to 6m are made of the amorphous film 11B and the amorphous films 71 to 7m-1 are made of the amorphous film 21A, the region 31 is formed from the n-type single crystal silicon substrate 301 side. The non-doped layer 201, the n-type impurity layer 202, and the p-type impurity layer 103 are sequentially stacked. In the region 32, the non-doped layer 201 and the n-type impurity layer 202 are sequentially formed from the n-type single crystal silicon substrate 301 side. The region 33 has a structure in which a p-type impurity layer 103 is deposited on an n-type single crystal silicon substrate 301.

  Further, when the amorphous films 61 to 6m are made of the amorphous film 11A and the amorphous films 71 to 7m-1 are made of the amorphous film 21B, the region 31 is formed from the n-type single crystal silicon substrate 301 side. The n-type impurity layer 203, the non-doped layer 101, and the p-type impurity layer 102 are sequentially stacked, and the region 32 has a structure in which the n-type impurity layer 203 is deposited on the n-type single crystal silicon substrate 301. The region 33 has a structure in which the non-doped layer 101 and the p-type impurity layer 102 are sequentially stacked from the n-type single crystal silicon substrate 301 side.

  Further, when the amorphous films 61 to 6m are made of the amorphous film 11B and the amorphous films 71 to 7m-1 are made of the amorphous film 21B, the region 31 is formed from the n-type single crystal silicon substrate 301 side. The n-type impurity layer 203 and the p-type impurity layer 103 are sequentially stacked, the region 32 has a structure in which the n-type impurity layer 203 is deposited on the n-type single crystal silicon substrate 301, and the region 33 has The p-type impurity layer 103 is deposited on the n-type single crystal silicon substrate 301.

  In the photoelectric conversion element 200, the electrode 3 is disposed on the amorphous films 61 to 6m, and the electrode 4 is disposed on the amorphous films 71 to 7m-1.

  In the following description, an example in which each of the amorphous films 61 to 6m is made of an amorphous film 11A and each of the amorphous films 71 to 7m-1 is made of an amorphous film 21A will be described. .

  9 and 10 are first and second process diagrams respectively showing a part of the manufacturing process of the photoelectric conversion element 200 shown in FIG. The photoelectric conversion element 200 includes steps (c) to (i ′) shown in FIGS. 9 and 10 in steps (c) to (i) of steps (a) to (i) shown in FIGS. Manufactured according to the process instead of

  When the manufacture of the photoelectric conversion element 200 is started, the steps (a) and (b) described above are sequentially performed. After the step (b), the n-type single crystal silicon substrate 301 / antireflection film 2 is placed on the substrate holder in the preparation chamber of the plasma apparatus.

Thereafter, the evacuation mechanism in the brewing chamber evacuates the gas in the brewing chamber to 1 × 10 ⁻⁵ Pa or less, and the heating mechanism in the brewing chamber sets the temperature of the n-type single crystal silicon substrate 301 / antireflection film 2 to 200 ° C. Heat the substrate holder to set.

  When the temperature of the n-type single crystal silicon substrate 301 / antireflection film 2 reaches 200 ° C., the partition valve between the preparation chamber and the reaction chamber CB1 is opened, and the n-type single crystal silicon substrate 301 / antireflection film 2 Then, it is transferred from the preparation chamber to the reaction chamber CB1.

When the n-type single crystal silicon substrate 301 / antireflection film 2 is transferred to the reaction chamber CB1, 10 sccm of SiH ₄ gas and 100 sccm of H ₂ gas are allowed to flow into the reaction chamber CB1 (see Table 1), and the reaction chamber CB1. Is set to a range of 13.3 Pa to 665 Pa. The RF power source applies RF power in the range of 16 to 80 mW / cm ² to the parallel plate electrodes through the matching unit. As a result, plasma is generated in the reaction chamber CB1, and the non-doped layer 58 made of i-type a-Si is formed on the surface of the n-type single crystal silicon substrate 301 (= the surface opposite to the surface on which the antireflection film 2 is formed). It is deposited on.

When the film thickness of the non-doped layer 58 reaches 5 to 10 nm, the application of RF power to the parallel plate electrodes in the reaction chamber CB1 is stopped, the supply of SiH ₄ gas and H ₂ gas to the reaction chamber CB1 is stopped, and the exhaust gas is exhausted. The reaction chamber CB1 is evacuated to 1 × 10 ⁻⁵ Pa or less by the mechanism. Then, the partition valve is opened, and the non-doped layer 58 / n-type single crystal silicon substrate 301 / antireflection film 2 is transferred from the reaction chamber CB1 to the reaction chamber CB3.

Thereafter, 20 sccm of SiH ₄ gas, 150 sccm of H ₂ gas, and 50 sccm of PH ₃ gas diluted with hydrogen are flowed into the reaction chamber CB3 (see Table 1), and the pressure in the reaction chamber CB3 is set to 13.3 Pa to 665 Pa. Set to range. The RF power source applies RF power in the range of 16 to 80 mW / cm ² to the parallel plate electrodes through the matching unit.

  As a result, plasma is generated in the reaction chamber CB3, and an n-type impurity layer 59 made of n-type a-Si is deposited on the non-doped layer 58. As a result, an amorphous film 60 for the amorphous films 71 to 7m-1 is formed on the back surface of the n-type single crystal silicon substrate 1 (surface opposite to the surface on which the antireflection film 2 is formed) ( Step (c ′) in FIG. 9).

When the film thickness of the n-type impurity layer 59 is 5 to 10 nm, the application of RF power to the parallel plate electrode in the reaction chamber CB3 is stopped and the reaction chamber CB3 of SiH ₄ gas, H ₂ gas, and PH ₃ gas enters the reaction chamber CB3. The supply is stopped, and the reaction chamber CB3 is evacuated to 1 × 10 ⁻⁵ Pa or less by an exhaust mechanism. Then, the partition valve is opened, and the amorphous film 60 / n-type single crystal silicon substrate 301 / antireflection film 2 is transferred from the reaction chamber CB3 to the take-out chamber. Then, the amorphous film 60 / n-type single crystal silicon substrate 1 / antireflection film 2 is cooled to room temperature and taken out from the take-out chamber.

  Thereafter, a resist is applied on the amorphous film 60 / n-type single crystal silicon substrate 1 / the amorphous film 60 of the antireflection film 2, and the applied resist is patterned by photolithography to form a resist pattern 70. (See step (d ′) in FIG. 9).

  Then, using the resist pattern 70 as a mask, the amorphous film 60 and the n-type single crystal silicon substrate 301 are etched by dry etching or wet etching, and the resist pattern 70 is removed. As a result, amorphous films 71 to 7m−1 are formed, and convex portions 301A and concave portions 301B are formed on the back surface of n-type single crystal silicon substrate 301.

  Subsequently, a coating layer is formed on the entire back surface of the amorphous film 71 to 7m-1 / n-type single crystal silicon substrate 301 / antireflection film 2 on the n-type single crystal silicon substrate 1; Etching is used to leave the coating layer on the amorphous films 71 to 7m−1 and form the coating layer 80 on the amorphous films 71 to 7m−1 (see step (f ′) in FIG. 9). In this case, the coating layer 80 is formed so that the dimension of the coating layer 80 in the in-plane direction DR1 of the n-type single crystal silicon substrate 301 is smaller than the dimension in the in-plane direction DR1 of the amorphous films 71 to 7m-1. . The covering layer 80 is made of a silicon nitride film or a silicon oxide film and has a thickness of about 100 nm.

  Then, the covering layer 80 / amorphous films 71 to 7m-1 / n type single crystal silicon substrate 301 / antireflection film 2 are arranged on the substrate holder in the preparation chamber of the plasma apparatus.

After that, the evacuation mechanism of the brewing chamber evacuates the gas in the stuffing chamber to 1 × 10 ⁻⁵ Pa or less, and the heating mechanism of the brewing chamber is the coating layer 80 / amorphous films 71-7m−1 / n type single crystal. The substrate holder is heated so that the temperature of the silicon substrate 301 / antireflection film 2 is set to 200 ° C.

  When the temperature of coating layer 80 / amorphous film 71-7m-1 / n type single crystal silicon substrate 301 / antireflection film 2 reaches 200 ° C., the partition valve between the preparation chamber and reaction chamber CB1 is opened. The covering layer 80 / the amorphous films 71 to 7m−1 / n type single crystal silicon substrate 301 / the antireflection film 2 are transferred from the preparation chamber to the reaction chamber CB1.

When covering layer 80 / amorphous film 71-7m-1 / n type single crystal silicon substrate 301 / antireflection film 2 is transferred to reaction chamber CB1, 10 sccm of SiH ₄ gas and 100 sccm of H ₂ gas are used. Pour into the reaction chamber CB1 (see Table 1), and set the pressure in the reaction chamber CB1 to a range of 13.3 Pa to 665 Pa. The RF power source applies RF power in the range of 16 to 80 mW / cm ² to the parallel plate electrodes through the matching unit. As a result, plasma is generated in the reaction chamber CB1, and a non-doped layer 88 made of i-type a-Si is deposited on the entire back surface of the n-type single crystal silicon substrate 301.

When the film thickness of the non-doped layer 88 is 5 to 10 nm, the application of RF power to the parallel plate electrodes in the reaction chamber CB1 is stopped, and the supply of SiH ₄ gas and H ₂ gas to the reaction chamber CB1 is stopped, and the exhaust gas is exhausted. The reaction chamber CB1 is evacuated to 1 × 10 ⁻⁵ Pa or less by the mechanism. Then, the gate valve is opened, and the non-doped layer 88 / coating layer 80 / amorphous films 71-7m-1 / n-type single crystal silicon substrate 301 / antireflection film 2 are transferred from the reaction chamber CB1 to the reaction chamber CB2.

Thereafter, 2 sccm of SiH ₄ gas, 42 sccm of H ₂ gas, and hydrogen-diluted 12 sccm of B ₂ H ₆ gas were allowed to flow into the reaction chamber CB2 (see Table 1), and the pressure in the reaction chamber CB2 was changed to 13.3 Pa˜ The range is set to 665 Pa. The RF power source applies RF power in the range of 16 to 80 mW / cm ² to the parallel plate electrodes through the matching unit.

  As a result, plasma is generated in the reaction chamber CB2, and a p-type impurity layer 89 made of p-type a-Si is deposited on the non-doped layer 88. As a result, an amorphous film 90 for the amorphous films 61 to 6 m is formed on the entire back surface of the n-type single crystal silicon substrate 301 (see step (g ′) in FIG. 10).

When the thickness of the p-type impurity layer 89 is 5 to 10 nm, the application of RF power to the parallel plate electrodes in the reaction chamber CB2 is stopped, and the reaction chamber CB2 for SiH ₄ gas, H ₂ gas, and B ₂ H ₆ gas is used. The reaction chamber CB2 is evacuated to 1 × 10 ⁻⁵ Pa or less by an exhaust mechanism. Then, the gate valve is opened, and amorphous film 90 / amorphous films 71-7m-1 / covering layer 80 / amorphous films 71-7m-1 / n-type single crystal silicon substrate 301 / antireflection film 2 are formed. Transported from reaction chamber CB2 to take-out chamber, amorphous film 90 / amorphous films 71-7m-1 / covering layer 80 / amorphous films 71-7m-1 / n-type single crystal silicon substrate 301 / antireflection The membrane 2 is cooled to room temperature and then removed.

  The extracted amorphous film 90 / amorphous films 71 to 7m-1 / covering layer 80 / amorphous films 71 to 7m-1 / n-type single crystal silicon substrate 301 / covering layer 80 of the antireflection film 2 Are removed with an acidic etchant. As a result, the amorphous films 61 to 6m are formed in the concave portions 301B of the n-type single crystal silicon substrate 301, and the amorphous films 21 to 2m-1 are formed in the convex portions 301A of the n-type single crystal silicon substrate 301. A structure is produced (see step (h ′) in FIG. 10).

  Thereafter, Ag is vapor-deposited on the amorphous films 61 to 6m and 71 to 7m-1 sides to form the electrodes 3 and 4, respectively. Thus, the photoelectric conversion element 200 is completed (see step (i ′) in FIG. 10).

  As described above, by making the dimension in the in-plane direction DR1 of the coating layer 80 smaller than the dimension in the in-plane direction DR1 of the amorphous films 71 to 7m−1, in the step (g ′), the non-doped layer 88 ( = I-type a-Si) can be improved in coverage, and p-type a-Si deposited thereafter and n-type a-Si already deposited are more reliably electrically connected. Can be separated.

  The covering layer 80 may have the above-described tapered shape 41 at the end in the in-plane direction DR1 of the n-type single crystal silicon substrate 301. Thereby, the amorphous films 61 to 6 m can be formed with good coverage in the step (h ′).

  The power generation mechanism of the photoelectric conversion element 200 is the same as the power generation mechanism of the photoelectric conversion element 100 described above. Therefore, the photoelectric conversion element 200 is also a back contact type photoelectric conversion element.

  In the photoelectric conversion element 200, the amorphous films 61 to 6m including the p-type impurity layer 102 are n after the back side of the n-type single crystal silicon substrate 301 is removed over a depth of 20 nm to 5 μm. It is formed in contact with the back surface (= concave portion 301B) of the type single crystal silicon substrate 301 (see steps (f ′), (g ′), (h ′)).

  As a result, the amorphous films 61 to 6m including the p-type impurity layer 102 are formed on the back surface (= recessed portion 301B) of the n-type single crystal silicon substrate 301 from which the plasma damage layer when the amorphous film 60 is formed is removed. Since the amorphous films 71 to 7m−1 are formed in contact with the back surface of the n-type single crystal silicon substrate 301 having no plasma damage (= convex portion 301A), the holes are caused by plasma damage. The electrons reach the electrode 3 through the amorphous films 61 to 6m from the back surface of the n-type single crystal silicon substrate 301 from which the layer has been removed, and electrons are amorphous from the back surface of the n-type single crystal silicon substrate 301 without plasma damage. It reaches the electrode 4 through the membranes 71 to 7m-1.

  Therefore, in the photoelectric conversion element 200, the conduction characteristic with respect to carriers (electrons and holes) can be improved, and the conversion efficiency of the photoelectric conversion element 200 can be improved.

  Other explanations in the second embodiment are the same as those in the first embodiment.

  In the above description, the photoelectric conversion elements 100 and 200 including the n-type single crystal silicon substrate 1 and 301 as the single crystal silicon substrate have been described. However, the photoelectric conversion element according to the embodiment of the present invention is a p-type as the single crystal silicon substrate. A photoelectric conversion element including a single crystal silicon substrate may be used.

  In this case, the amorphous films 11 to 1m and 61 to 6m are formed as non-doped layers (= i-type a-Si or the like) / n-type impurity layers (= n-type a-Si or the like) or n-type impurity layers (= n The amorphous films 21-2m-1, 71-7m-1 are made of non-doped layers (= i-type a-Si, etc.) / P-type impurity layers (= p-type a-Si, etc.). Or a p-type impurity layer (= p-type a-Si or the like). That is, the amorphous films 11-1m and 61-6m are made of an amorphous film including at least an n-type impurity layer, and the amorphous films 21-2m-1, 71-7m-1 are at least p-type impurities. It consists of an amorphous film including a layer.

  The combination of the amorphous films 11-1m and the amorphous films 21-2m-1 and the combination of the amorphous films 61-6m and the amorphous films 71-7m-1 are shown in FIG. The same four combinations. In this case, the p-type impurity layers 102 and 103 may be read as n-type impurity layers, and the n-type impurity layers 202 and 203 may be read as p-type impurity layers.

  In addition, a photoelectric conversion element including a p-type single crystal silicon substrate is manufactured according to the above-described steps (a) to (i) or steps (a), (b), (c ′) to (i ′).

  In the first embodiment, amorphous films 21 to 2m−1 including n-type impurity layer 202 (or n-type impurity layer 203) are formed in p-type impurity layer 102 (or in the thickness direction of n-type single crystal silicon substrate 1). The photoelectric conversion element 100 formed at a position deeper than the amorphous films 11 to 1m including the p-type impurity layer 103) has been described.

  In the second embodiment, the amorphous films 61 to 6 m including the p-type impurity layer 102 (or the p-type impurity layer 103) are converted into the n-type impurity layer 202 (or the thickness direction of the n-type single crystal silicon substrate 301). The photoelectric conversion element 200 formed at a position deeper than the amorphous films 71 to 7m-1 including the n-type impurity layer 203) has been described.

  Therefore, the photoelectric conversion element according to the embodiment of the present invention is provided in contact with one surface of the semiconductor substrate made of single crystal silicon having the first conductivity type, and opposite to the first conductivity type. A first amorphous film including at least a first impurity layer having a second conductivity type, and is in contact with one surface of the semiconductor substrate adjacent to the first amorphous film in an in-plane direction of the semiconductor substrate; And a second amorphous film including at least a second impurity layer having the first conductivity type, and an interface between one of the first and second amorphous films and the semiconductor substrate is It suffices to exist in a position different from the interface between the other of the first and second amorphous films and the semiconductor substrate in the thickness direction of the semiconductor substrate.

  When n-type single crystal silicon substrate 1, 301 is used, the first conductivity type is n-type, and the second conductivity type is p-type. When a p-type single crystal silicon substrate is used, the first conductivity type is p-type, and the second conductivity type is n-type.

  Moreover, the manufacturing method of the photoelectric conversion element by embodiment of this invention has the back surface structure similar to the photoelectric conversion elements 100 and 200 mentioned above, and manufactures the photoelectric conversion element using a p-type single crystal silicon substrate Any method can be used. Therefore, in the method of manufacturing a photoelectric conversion element according to the embodiment of the present invention, the second conductivity opposite to the first conductivity type is in contact with one surface of the semiconductor substrate made of single crystal silicon having the first conductivity type. One of a first amorphous film including at least a first impurity layer having a conductivity type and a second amorphous film including at least a second impurity layer having a first conductivity type. A first step of forming a crystalline film; a second step of removing a portion of one amorphous film in the in-plane direction of the semiconductor substrate; and a portion of the semiconductor substrate in contact with the portion; A third step of forming a coating layer on the remainder of the crystalline film, and a first step of forming the other amorphous film of the first and second amorphous films on one surface and the coating layer of the semiconductor substrate. It is only necessary to include the step 4 and the fifth step of removing the coating layer.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

  The present invention is applied to a photoelectric conversion element and a manufacturing method thereof.

  1,301 n-type single crystal silicon substrate, 1A, 301A convex part, 1B, 301B concave part, 2 antireflection film, 3, 4 electrodes, 11-1m, 11A, 11B, 20, 21-2m-1, 21, 21B , 60, 61-6 m, 71-7 m-1 amorphous film, 30, 70 resist pattern, 40, 80 coating layer, 41 taper shape, 100, 200 photoelectric conversion element, 101, 201 non-doped layer, 102, 103 p Type impurity layer, 202, 203 n-type impurity layer.

Claims (8)

A semiconductor substrate made of single crystal silicon having a first conductivity type;
A first amorphous film provided in contact with one surface of the semiconductor substrate and including at least a first impurity layer having a second conductivity type opposite to the first conductivity type;
A first impurity layer provided at least in contact with one surface of the semiconductor substrate adjacent to the first amorphous film in an in-plane direction of the semiconductor substrate and including at least a second impurity layer having the first conductivity type; Two amorphous films,
The interface between one of the first and second amorphous films and the semiconductor substrate is the interface between the other of the first and second amorphous films and the semiconductor substrate in the thickness direction of the semiconductor substrate. Exists in a different position ,
A part of the second amorphous film is in contact with a surface on which an electrode of the first amorphous film adjacent to the second amorphous film is disposed in an in-plane direction of the semiconductor substrate. A taper shape that is disposed on a part of the first amorphous film and gradually decreases in thickness toward the outside of the second amorphous film in an in-plane direction of the semiconductor substrate. A photoelectric conversion element. The interface between the second amorphous film and the semiconductor substrate is closer to the light incident side of the semiconductor substrate than the interface between the first amorphous film and the semiconductor substrate in the thickness direction of the semiconductor substrate. position, the photoelectric conversion element according to claim 1. A semiconductor substrate made of single crystal silicon having a first conductivity type;
A first amorphous film provided in contact with one surface of the semiconductor substrate and including at least a first impurity layer having a second conductivity type opposite to the first conductivity type;
A first impurity layer provided at least in contact with one surface of the semiconductor substrate adjacent to the first amorphous film in an in-plane direction of the semiconductor substrate and including at least a second impurity layer having the first conductivity type; Two amorphous films,
The interface between one of the first and second amorphous films and the semiconductor substrate is the interface between the other of the first and second amorphous films and the semiconductor substrate in the thickness direction of the semiconductor substrate. Exists in a different position,
A part of the first amorphous film is in contact with a surface on which an electrode of the second amorphous film adjacent to the first amorphous film is disposed in an in-plane direction of the semiconductor substrate. A taper shape that is disposed on a part of the second amorphous film and gradually decreases in thickness toward the outside of the first amorphous film in an in-plane direction of the semiconductor substrate. A photoelectric conversion element. The interface between the first amorphous film and the semiconductor substrate is closer to the light incident side of the semiconductor substrate than the interface between the second amorphous film and the semiconductor substrate in the thickness direction of the semiconductor substrate. The photoelectric conversion element according to claim 3, which is located. The first amorphous film includes:
A first non-doped layer provided in contact with one surface of the semiconductor substrate and having an i-type conductivity;
Including the first impurity layer provided in contact with the first non-doped layer,
The second amorphous film is
A second non-doped layer provided in contact with one surface of the semiconductor substrate and having an i-type conductivity;
The photoelectric conversion device according to claim 1, further comprising: the second impurity layer provided in contact with the second non-doped layer. A first impurity layer provided at least in contact with one surface of a semiconductor substrate made of single crystal silicon having a first conductivity type, and including at least a first impurity layer having a second conductivity type opposite to the first conductivity type; A first step of forming one of the amorphous film and the second amorphous film including at least the second impurity layer having the first conductivity type;
A second step of removing a part of the one amorphous film in an in-plane direction of the semiconductor substrate and a part of the semiconductor substrate in contact with the part;
A third step of forming a coating layer on the remaining portion of the one amorphous film;
4 to form the one surface of the semiconductor substrate, the other amorphous film of the first and second amorphous film in contact with a portion of the remainder of the coating layer and the one amorphous film And the process of
A fifth step of removing the coating layer ,
In the third step, the dimension of the coating layer in the in-plane direction of the semiconductor substrate is smaller than the dimension of the remaining portion of the one amorphous film in the in-plane direction of the semiconductor substrate, A method for manufacturing a photoelectric conversion element, wherein an end portion in an in-plane direction is formed so that a film thickness is gradually reduced toward an outside of the coating layer in an in-plane direction of the semiconductor substrate. Forming the first amorphous film in contact with one surface of the semiconductor substrate in the first step;
Removing a part of the first amorphous film and a part of the semiconductor substrate in contact with the part in the second step;
In the fourth step, one surface of the semiconductor substrate, forming a second amorphous film in contact with a portion of the remainder of the coating layer and the first amorphous film, according to claim 6 The manufacturing method of the photoelectric conversion element of description. Forming the second amorphous film in contact with one surface of the semiconductor substrate in the first step;
Removing a part of the second amorphous film and a part of the semiconductor substrate in contact with the part in the second step;
In the fourth step, one surface of the semiconductor substrate, forming the first amorphous film in contact with a portion of the remainder of the coating layer and the second amorphous film, according to claim 6 The manufacturing method of the photoelectric conversion element of description.

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