CN102437243B - Heterojunction with intrinsic thin layer (HIT) solar cell structure with heterogeneous floating junction back passivation, and preparation process thereof - Google Patents
Heterojunction with intrinsic thin layer (HIT) solar cell structure with heterogeneous floating junction back passivation, and preparation process thereof Download PDFInfo
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Abstract
The invention relates to the technical field of solar cells, in particular to a heterojunction with intrinsic thin layer (HIT) solar cell structure with heterogeneous floating junction back passivation, and a preparation process thereof. P-type amorphous silicon layers are deposited on the upper surface and the lower surface of an N-type crystal silicon substrate so as to form heterogeneous P-N junction structures; a mask is manufactured on the heterogeneous P-N junction structure on the lower surface; selective etching is performed so as to form isolated heterogeneous P-N junction structures; the mask layer is removed and an insulation thin film layer is deposited on the lower surface; a mask is manufactured on the insulation thin film layer; secondary selective etching is performed, so that the side surface and the back surface of the heterogeneous P-N junction structure on the lower surface of the N-type crystal silicon substrate are encircled by the insulation thin film layer, and a floating junction back passivation structure is formed; and an N-type amorphous silicon back electrode and a P-type amorphous silicon floating junction back passivation structure are strictly separated from each other by the insulation thin film layer. Compared with an HIT standard process and a structure of the Sanyo, the HIT solar cell structure has the advantages that: the floating P-N junction back passivation structure is introduced into the back surface of the N-type crystal silicon, so that the surface compounding rate is lower and the open-circuit voltage is higher.
Description
Technical field
The present invention relates to technical field of solar batteries, particularly HIT solar battery structure and the preparation technology thereof of the passivation of a kind of heterogeneous floating junction back of the body.
Background technology
Solar power generation is the green clean energy resource of at present tool potentiality, and the high performance solar batteries sheet is the core of solar power generation.Solar cell industry and the highest battery material of maturity are still crystal silicon cell at present, but the following solar battery technology of realizing that par networks should be based on the solar cell of thin film technique.In existing high-efficiency crystal silicon cell technology, back of the body passivating technique difference is maximum.The quality of crystalline silicon back of the body degree of passivation not only affects the long wave incident light response of solar cell, the height of open circuit voltage, even can also affect the temperature characterisitic of solar cell, thereby the crystalline silicon component performance is had significant impact.
There is the attenuation problem of efficiency in the amorphous silicon battery of based thin film technology fully, its reason is that the light absorbing zone of amorphous silicon membrane battery is the amorphous silicon layer of hundreds of nanometer thickness, and under long-time illumination, can produce the photoproduction metastable state in amorphous silicon solar cell, this photoproduction metastable state can make the compound increase of photo-generated carrier, and the quantum efficiency that reduces amorphous silicon film battery is the S-W effect.Sanyo has proposed a kind of new structure, namely utilizes crystalline silicon to do light absorbing zone, with amorphous silicon, does simultaneously passivation layer and P, N doped layer, has so just avoided the efficiency attenuation problem of amorphous silicon, has utilized again the superperformance of amorphous silicon membrane.Sanyo claims the structure of this crystalline silicon double-sided deposition amorphous silicon doped layer to be HIT structure (Heterojunction with Intrinsic Thin layer) and to prepare efficiency up to 23% heterojunction HIT battery.The reason of its battery-efficient rate is that (1) utilizes crystalline silicon to do light absorbing zone, avoided photo attenuation problem (2) amorphous silicon of amorphous silicon film battery to have the band gap of the band gap of hydrogen passivation effect (3) amorphous silicon greater than crystalline silicon, thereby at the P-N of amorphous silicon and crystalline silicon knot or N-N+ is high mixes-electrostatic field that the low-mix knot not only has a homojunction also has the effective field that is caused by affinity difference.
The mainstream technology of crystalline silicon back of the body passivation is to mix-low-mix knot (high-low junction) back of the body passivating technique with the height of P-P+ or the doping of N-N+ homogeneity at present.The two-sided HIT battery of Sanyo is namely to adopt this back of the body passivation scheme, and deposition N+ amorphous silicon layer on N-type crystal silicon substrate, form N-N+ back of the body electric field.Another kind of back of the body passivation scheme is that the back of the body passivating structure that adopts the P-N that floats to tie is PERF solar battery structure (passivated emitter, rear floating p-n junction), it also forms a diffusion P-N knot below the SiO2 layer when the crystal silicon substrate back adopts the localization homogeneity to diffuse to form height-low knot and thermal oxidation SiO2 passivation.Because tie below the SiO2 layer at the P-N place, the discord back electrode directly contacts, thereby this P-N knot is also referred to as floating junction (floating junction).The research of PERF battery shows that the passivation of the desirable floating junction back of the body has than SiO2 layer and better carries on the back passivation effect, and have lower recombination-rate surface, open circuit voltage reaches 720mV.
Summary of the invention
Technical problem to be solved by this invention is: HIT solar battery structure and the preparation technology thereof of the passivation of a kind of heterogeneous floating junction back of the body are provided, improve the back of the body passivation effect of HIT solar cell, and then improve generating efficiency.
the technical solution adopted for the present invention to solve the technical problems is: the HIT solar battery structure of a kind of heterogeneous floating junction back of the body passivation, upper surface and lower surface part at N-type crystal silicon substrate arrange P type amorphous silicon layer, form the hetru P-N junction structure, the hetru P-N junction structure of lower surface part is insulated the thin layer isolation, form floating junction back of the body passivating structure, the back electrode of the lower surface of N-type crystal silicon substrate consists of the N-type amorphous silicon layer that is arranged under N-type crystal silicon substrate, and back electrode and the mutual electric insulation of hetru P-N floating junction back of the body passivating structure, has conductive electrode layer on the back electrode of the lower surface of the hetru P-N junction structure of N-type crystal silicon substrate top surface and N-type crystal silicon substrate.Insulating thin layer can adopt insulating film material common in the HIT manufacturing process, and as the ZnO insulating thin layer, In2O3 insulating thin layer etc., even can adopt the amorphous silicon membrane layer of intrinsic.
Also have intrinsic amorphous silicon layer between P type amorphous silicon layer and N-type crystal silicon substrate in floating junction back of the body passivating structure, also have intrinsic amorphous silicon layer between N-type amorphous silicon layer and N-type crystal silicon substrate in back electrode.The introducing of the intrinsic amorphous silicon layer in floating junction back of the body passivating structure is mainly the hydrogen passivation effect that utilizes amorphous silicon hydride, reduces few sub-recombination rate.
For further having increased the back of the body passivation effect of floating junction, conductive electrode layer covers floating junction back of the body passivating structure when covering back electrode.
Transparency conductive electrode layer 7 can be the ZnO of Al doping or the In2O3 of Sn doping etc.,, consistent with the HIT manufacturing process of routine.The ZnO of Al doping is AZO transparency conductive electrode layer, and the In2O3 of Sn doping is ITO transparency conductive electrode layer.
the preparation technology of the HIT solar battery structure of a kind of heterogeneous floating junction back of the body passivation, at first, upper at N-type crystal silicon substrate, lower surface all forms the hetru P-N junction structure, then, to make mask on the hetru P-N junction structure of lower surface, carry out selective etch, continue the deposition insulating thin layer at lower surface after removing mask layer, then make mask on insulating thin layer, carry out selective etch for the second time, make side and the back side of the hetru P-N junction structure of N-type crystal silicon substrate lower surface all by this insulating thin layer, be surrounded, form floating junction back of the body passivating structure, then, utilize mask on insulating thin layer at the lower surface of N-type crystal silicon substrate, other zones except floating junction back of the body passivating structure make the back electrode that the N-type amorphous silicon layer forms, make the transparency conductive electrode layer on the back electrode of the lower surface of last hetru P-N junction structure in N-type crystal silicon substrate top surface and N-type crystal silicon substrate.
Mask is generally made by operations such as photoresist photoetching, development, oven dry.
Technique has following steps:
A) utilize the plasma chemical vapor deposition technique deposition to levy amorphous silicon layer at the upper surface of N-type crystal silicon substrate and lower surface, the thickness of intrinsic amorphous silicon layer be 0 nanometer to 10 nanometers, the doping content of N-type crystal silicon substrate is 10
15-10
17cm
-3
B) utilize plasma chemical vapor deposition technique deposition P type amorphous silicon layer at the upper surface of N-type crystalline silicon substrate and lower surface, the thickness of P type amorphous silicon layer be 5 nanometers to 20 nanometers, the doping content of P type amorphous silicon layer is at 1E18cm
-3To 1E20cm
-3
C) spin coating one deck photoresist layer overleaf,, by exposure, develop, at the required photoetching offset plate figure of P type amorphous silicon layer definition;
D) utilize photoresist layer, by the intrinsic amorphous silicon layer of corrosive liquid to lower surface, P type amorphous silicon layer corrodes, until then N-type crystal silicon substrate removes photoresist layer;
E) at N-type crystal silicon substrate back deposition insulating thin layer, the thickness of deposition need to add greater than lower surface place intrinsic amorphous silicon layer the gross thickness of P type amorphous silicon layer.Insulating thin layer can adopt insulating film material common in the HIT manufacturing process, and as the ZnO insulating thin layer, In2O3 insulating thin layer etc., even can continue deposition intrinsic amorphous silicon membrane layer.
F) spin coating one deck photoresist layer overleaf,, by exposure, develop, and the required photoresist mask pattern of definition on insulating thin layer, post-develop are carved the width of glue mask need to be greater than the width of lower surface P type amorphous silicon layer;
G) utilize corrosive liquid etching insulating thin layer, form the floating junction back of the body passivating structure that surrounds lower surface intrinsic amorphous silicon layer, P type amorphous silicon layer;
H) deposit one deck intrinsic amorphous silicon layer at N-type crystal silicon substrate back, the thickness of intrinsic amorphous silicon layer is that 0 nanometer is to 10 nanometers again;
I) deposit one deck N-type amorphous silicon layer at N-type crystal silicon substrate back again, form back electrode, the thickness of N-type amorphous silicon layer is to 20 nanometers, and the doping content of N-type amorphous silicon layer is that 1E18 is to 1E20cm
-3
J) utilize organic reagent to remove photoresist layer, expose insulating thin layer;
K) at front and back deposit transparent conductive electrode layer such as the AZO of N-type crystal silicon substrate, ITO etc., the thickness of transparency conductive electrode layer in 80 nanometers to 300 nanometers, the resistivity of transparency conductive electrode layer arrives 1E-5 Ω cm at 1E-3, the transparency conductive electrode layer not only covers above the N-type amorphous silicon layer, also cover hetru P-N floating junction back of the body passivating structure, so far, the HIT battery structure that complete hetru P-N floating junction back of the body passivation strengthens forms.
The invention has the beneficial effects as follows: compare HIT standard technology and the structure of Sanyo,
1, the present invention has introduced unsteady P-N knot back of the body passivating structure at the N-type crystal silicon back side.Traditional SiO2 passivation is compared in the P-N knot back of the body passivation of floating or N-N+ is high mixes-passivation of the low-mix knot back of the body, and the P-N knot back of the body passivating technique that floats has lower recombination-rate surface, and open circuit voltage is also better.
2, the floating junction back of the body of the present invention passivation utilizes insulating thin layer to realize the electricity isolation completely of P-N heterojunction.Because the transparency conductive electrode layer material of HIT can be the ZnO transparency conductive electrode layer of Al doping, the In2O3 of Sn doping, so the insulating thin layer selection is wide general, can be the amorphous silicon membrane layer of intrinsic, can be also ZnO or In2O3 insulating thin layer, existing technique of compatible HIT all.Even can adopt the combination of multi-layer insulation film layer, maximize floating junction back of the body passivation effect.
3, the present invention has added 2 road photoetching processes on basis in the HIT of Sanyo technique, has formed the hetru P-N floating junction structure with better back of the body passivation effect at lower surface, can further improve opening of battery and press and whole efficiency.
Description of drawings
The present invention is further described below in conjunction with drawings and Examples.
Fig. 1 is the structural representation of step a of the present invention;
Fig. 2 is the structural representation of step b of the present invention;
Fig. 3 is the structural representation of step c of the present invention;
Fig. 4 is the structural representation of steps d of the present invention;
Fig. 5 is the structural representation of step e of the present invention;
Fig. 6 is the structural representation of step f of the present invention;
Fig. 7 is the structural representation of step g of the present invention;
Fig. 8 is the structural representation of step h of the present invention;
Fig. 9 is the structural representation of step I of the present invention;
Figure 10 is the structural representation of step j of the present invention;
Figure 11 is the structural representation of step k of the present invention;
In figure, 1.N type crystal silicon substrate, 2. intrinsic amorphous silicon layer, 3.P type amorphous silicon layer, 4. photoresist layer, 5. insulating thin layer, 6.N type amorphous silicon layer, 7. transparency conductive electrode layer.
Embodiment
HIT solar battery structure and the preparation technology thereof of this heterogeneous floating junction back of the body passivation, its basic ideas are all to deposit P type amorphous silicon layer 3 formation hetru P-N junction structures at the upper surface of N-type crystal silicon substrate 1 and lower surface, floating of the P-N knot at N-type crystal silicon substrate 1 back side realized by vapour deposition insulating thin layer 5, and back electrode is still realized with the N-type amorphous silicon deposition.N-type amorphous silicon back electrode is realized strictly separating by insulating thin layer 5 with P type amorphous silicon floating junction back of the body passivating structure, has guaranteed good floating junction back of the body passivation effect.
At first, different from the HIT battery process flow process of Sanyo, this technological process is at the upper and lower surface while of N-type crystal silicon substrate 1 deposition of amorphous silicon P-N heterostructure layer.The N-type crystal silicon substrate 1 of Fig. 1, intrinsic amorphous silicon layer 2, the P type amorphous silicon layer 3 upper and lower P-N heterojunction of common formation.The top heterogeneous emitter of becoming solar cell of P-N, and following P-N heterojunction only plays the passivation of the floating junction back of the body.The introducing of intrinsic amorphous silicon layer 2 is mainly the hydrogen passivation effect that utilizes amorphous silicon hydride, reduces few sub-recombination rate.
Then,, with the P-N heterojunction etching of lower surface, then deposit and etching insulating thin layer 5.Insulating thin layer can adopt insulating film material common in the HIT manufacturing process, and as the ZnO insulating thin layer, In2O3 insulating thin layer etc., even can continue deposition intrinsic amorphous silicon membrane layer.The insulating thin layer 5 of Fig. 1 is with intrinsic amorphous silicon layer 2, and lower surface and the side of P type amorphous silicon layer 3 surround fully, forms hetru P-N floating junction back of the body passivating structure.Hetru P-N floating junction back of the body passivating structure has than N-N+ homogeneity back of the body electric field better carries on the back passivation effect, can greatly reduce the few sub-recombination rate at the back side.
Again then, the heterogeneous dorsum electrode layer of deposition N-N+, draw light induced electron, the solar battery structure of complete.As shown in Figure 1, back electrode consists of intrinsic amorphous silicon layer 2 and N-type amorphous silicon layer 6.To N-type crystalline silicon substrate 1 and N-type amorphous silicon layer 6, conduction band can be with mismatch very little, can form good back electrode.
Finally, at the upper and lower surface deposition transparency conductive electrode layer 7 of total, as shown in Figure 1.Transparency conductive electrode layer 7 can be that the ZnO of Al doping is that the In2O3 that AZO or Sn adulterate is ITO etc.Transparency conductive electrode layer 7 not only covers above the N-N+ dorsum electrode layer, also cover on hetru P-N floating junction back of the body passivating structure, thereby the photogenic voltage of N-N+ dorsum electrode layer also is applied on hetru P-N floating junction back of the body passivating structure, form the MIS back of the body passivating structure of metal-insulator layer-semiconductor layer, further increased the back of the body passivation effect of floating junction.
The preparation technology of the HIT solar battery structure of this heterogeneous floating junction back of the body passivation, HIT technique with respect to Sanyo, only increased the twice photoetching process, but brought hetru P-N floating junction back of the body passivating structure, thereby can greatly improve the open circuit voltage of HIT battery structure and reduce crystalline silicon back of the body recombination-rate surface.
Concrete steps are as follows:
A) upper surface and the lower surface at N-type crystal silicon substrate 1 utilizes plasma chemical vapor deposition technique PECVD deposition intrinsic amorphous silicon layer 2, as shown in Figure 2.The thickness of intrinsic amorphous silicon layer 2 is that 0 nanometer is to 10 nanometers.0 nanometer does not namely have intrinsic amorphous silicon layer 2, and this may reduce the passivation effect on surface.The doping content of N-type crystal silicon substrate 1 is 10
15-10
17cm
-3, be generally 10
16cm
-3
B) upper surface and the lower surface in N-type crystalline silicon substrate 1 utilizes plasma chemical vapor deposition technique PECVD deposition P type amorphous silicon layer 3, as shown in Figure 3.The thickness of P type amorphous silicon layer 3 be 5 nanometers to 20 nanometers, generally get 10 nanometers.The doping content of P type amorphous silicon layer 3 is at 1E18cm
-3To 1E20cm
-3
C) spin coating one deck photoresist layer 4 overleaf,, by exposure, develop, at the P type amorphous silicon layer 3 required photoetching offset plate figures of definition, as shown in Figure 4.
D) utilize the photoresist layer 4 of Fig. 4, to the intrinsic amorphous silicon layer 2 of lower surface, P type amorphous silicon layer 3 corrodes, until then N-type crystal silicon substrate 1 utilizes acetone and absolute ethyl alcohol to remove photoresist layer 4, as shown in Figure 5.The corrosion solvent can be HF, HNO3 mixed solution.Etching apparatus can adopt the cleaning equipment of single-sided corrosion.
E) at N-type crystal silicon substrate 1 backside deposition insulating thin layer 5, the thickness of deposition need to add the gross thickness of P type amorphous silicon layer 3 greater than intrinsic amorphous silicon layer 2, generally can be taken as 30 nanometers.As shown in Figure 6.Insulating thin layer 5 can adopt insulating film material common in the HIT manufacturing process, and as the ZnO insulating thin layer, In2O3 insulating thin layer etc., even can continue deposition intrinsic amorphous silicon membrane layer as insulating thin layer.
F) spin coating one deck photoresist layer 4 overleaf,, by exposure, develop, the required photoetching agent pattern of definition on insulating thin layer 5, as shown in Figure 7.The width of post-develop glue at quarter need to be greater than the width of lower surface P type amorphous silicon layer 3, as shown in Figure 7.
G) utilize HF acid, HNO3 acid waits corrosive liquid etching insulating thin layer 5, forms the heterogeneous unsteady P-N junction structure that surrounds lower surface intrinsic amorphous silicon layer 2, P type amorphous silicon layer 3, as shown in Figure 8.
H) deposit again one deck intrinsic amorphous silicon layer 2 at N-type crystal silicon substrate 1 back side, as shown in Figure 9.The thickness of intrinsic amorphous silicon layer 2 is that 0 nanometer is to 10 nanometers.0 nanometer does not namely have intrinsic amorphous silicon layer 2, and this may reduce the passivation effect on surface.
I) deposit again one deck N-type amorphous silicon layer 6 at N-type crystal silicon substrate 1 back side, form back electrode, as shown in figure 10.The thickness of N-type amorphous silicon layer 6, in 5 to 20 nanometers, is generally 10 nanometers.The doping content of N-type amorphous silicon layer 6 is that 1E18 is to 1E20cm
-3Because the conduction band of N-type crystal silicon substrate 1 and N-type amorphous silicon layer 6 can be with difference very little, light induced electron can be easy to by N-type amorphous silicon layer 6, so the electric conductivity of this back electrode is good.
J) remove photoresist layer 4 by organic reagent, expose insulating thin layer 5, as shown in figure 11.
K) front and back at N-type crystal silicon substrate 1 utilizes physical vapour deposition (PVD) PVD deposition techniques transparency conductive electrode layer 7, as shown in figure 12.Transparency conductive electrode layer 7 can be that the ZnO of Al doping is that the In2O3 that AZO or Sn adulterate is ITO etc.The thickness of transparency conductive electrode layer 7 in 80 nanometers to 300 nanometers.The resistivity of transparency conductive electrode layer 7 arrives 1E-5 Ω cm at 1E-3.Transparency conductive electrode layer 7 not only covers above N-type amorphous silicon layer 6, also cover on hetru P-N floating junction back of the body passivating structure, thereby the photogenic voltage of N-N+ dorsum electrode layer also is applied on hetru P-N floating junction back of the body passivating structure, form the MIS back of the body passivating structure of metal-insulator layer-semiconductor layer, further increased the back of the body passivation effect of floating junction.So far, the HIT battery structure of complete hetru P-N floating junction back of the body passivation enhancing forms.
Claims (3)
1. the preparation technology of the HIT solar battery structure of heterogeneous floating junction back of the body passivation, it is characterized in that: at first, upper at N-type crystal silicon substrate (1), lower surface all forms the hetru P-N junction structure, then, make mask on the hetru P-N junction structure of lower surface, carry out selective etch, make lower surface form local hetru P-N junction structure, continue deposition insulating thin layer (5) at lower surface after removing mask layer, at the upper mask of making of insulating thin layer (5), carry out selective etch for the second time, make side and the back side of the hetru P-N junction structure of N-type crystal silicon substrate (1) lower surface all be insulated thin layer (5) encirclement, form hetru P-N floating junction back of the body passivating structure, then, utilize mask on insulating thin layer (5) at the lower surface of N-type crystal silicon substrate (1), other zones except hetru P-N floating junction back of the body passivating structure make the back electrode that N-type amorphous silicon layer (6) forms, remove finally all mask layers, make conductive electrode layer on the back electrode of the lower surface of the hetru P-N junction structure of N-type crystal silicon substrate (1) upper surface and N-type crystal silicon substrate (1).
2. heterogeneous floating junction according to claim 1 is carried on the back the preparation technology of the HIT solar battery structure of passivation, and it is characterized in that: described mask is made by photoresist.
3. heterogeneous floating junction according to claim 1 and 2 is carried on the back the preparation technology of the HIT solar battery structure of passivation, it is characterized in that: have following processing step:
A) upper surface and the lower surface at N-type crystal silicon substrate (1) utilizes plasma chemical vapor deposition technique deposition intrinsic amorphous silicon layer (2), the thickness of intrinsic amorphous silicon layer (2) be 0 nanometer to 10 nanometers, the doping content of N-type crystal silicon substrate (1) is 10
15-10
17cm
-3
B) utilize plasma chemical vapor deposition technique deposition P type amorphous silicon layer (3) at the upper surface of N-type crystal silicon substrate (1) and lower surface, the thickness of P type amorphous silicon layer (3) be 5 nanometers to 20 nanometers, the doping content of P type amorphous silicon layer (3) is at 1E18cm
-3To 1E20cm
-3
C) spin coating one deck photoresist layer (4) overleaf,, by exposure, develop, at the required photoetching offset plate figure of P type amorphous silicon layer (3) definition;
D) utilize photoresist layer (4), by the intrinsic amorphous silicon layer (2) of corrosive liquid to lower surface, P type amorphous silicon layer (3) corrodes, until N-type crystal silicon substrate (1) is then removed photoresist layer (4);
E) at N-type crystal silicon substrate (1) backside deposition insulating thin layer (5), the thickness of deposition need to add greater than intrinsic amorphous silicon layer (2) gross thickness of P type amorphous silicon layer (3), insulating thin layer (5) adopts common insulating film material in the HIT manufacturing process, comprise ZnO insulating thin layer, In2O3 insulating thin layer, perhaps the amorphous silicon membrane layer of Direct precipitation intrinsic is as this insulating thin layer;
F) spin coating one deck photoresist layer (4) overleaf,, by exposure, develop, and at the required photoetching agent pattern of the upper definition of insulating thin layer (5), post-develop is carved the width of glue need to be greater than the width of lower surface P type amorphous silicon layer (3);
G) utilize corrosive liquid etching insulating thin layer (5), form the hetru P-N floating junction back of the body passivating structure that surrounds lower surface intrinsic amorphous silicon layer (2), P type amorphous silicon layer (3);
H) deposit one deck intrinsic amorphous silicon layer (2) at N-type crystal silicon substrate (1) back side, the thickness of intrinsic amorphous silicon layer (2) is that 0 nanometer is to 10 nanometers again;
I) deposit one deck N-type amorphous silicon layer (6) at N-type crystal silicon substrate (1) back side again, form back electrode, the thickness of N-type amorphous silicon layer (6) is in 5 to 20 nanometers, and the doping content of N-type amorphous silicon layer (6) is that 1E18 is to 1E20cm
-3
J) utilize organic reagent to remove photoresist layer (4), expose insulating thin layer (5);
K) at the front and back deposit transparent conductive electrode layer (7) of N-type crystal silicon substrate (1), the thickness of transparency conductive electrode layer (7) in 80 nanometers to 300 nanometers, the resistivity of transparency conductive electrode layer (7) arrives 1E-5 Ω cm at 1E-3, transparency conductive electrode layer (7) not only covers above N-type amorphous silicon layer (6), also cover hetru P-N floating junction back of the body passivating structure, transparency conductive electrode layer 7 is the ZnO of Al doping or the In2O3 of Sn doping, so far, the HIT battery structure of complete hetru P-N floating junction back of the body passivation enhancing forms.
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