CN102437243B - Heterojunction with intrinsic thin layer (HIT) solar cell structure with heterogeneous floating junction back passivation, and preparation process thereof - Google Patents

Abstract

The invention relates to the technical field of solar cells, in particular to a HIT solar cell structure with heterogeneous floating junction back passivation and its preparation process, which deposits P-type amorphous silicon on both the upper surface and the lower surface of an N-type crystalline silicon substrate layer to form a heterogeneous PN junction structure, make a mask on the heterogeneous PN junction structure on the lower surface, perform selective etching to form an isolated heterogeneous PN structure, then remove the mask layer and continue to deposit an insulating film layer on the lower surface, and then Make a mask on the insulating film layer, and perform the second selective etching, so that the side and back of the heterogeneous PN junction structure on the lower surface of the N-type crystalline silicon substrate are surrounded by the insulating film layer, forming a floating junction back passivation structure, the N-type amorphous silicon back electrode and the P-type amorphous silicon floating junction back passivation structure are strictly separated by an insulating film layer. Compared with Sanyo's HIT standard process and structure, the present invention introduces a floating PN junction back passivation structure on the back of N-type crystalline silicon, so it has a lower surface recombination rate and better open circuit voltage.

Description

Structure and fabrication process of HIT solar cells with heterogeneous floating junction back passivation

technical field

The invention relates to the technical field of solar cells, in particular to a HIT solar cell structure with heterogeneous floating junction back passivation and a preparation process thereof.

Background technique

Solar power generation is currently the most potential green and clean energy, and high-efficiency solar cells are the core of solar power generation. At present, the battery material with the highest industrialization and maturity of solar cells is still crystalline silicon cells, but the solar cell technology that will achieve parity in the grid in the future should be solar cells based on thin-film technology. Among the existing high-efficiency crystalline silicon cell technologies, the rear passivation technology has the greatest difference. The degree of back passivation of crystalline silicon not only affects the long-wave incident light response and open circuit voltage of solar cells, but also affects the temperature characteristics of solar cells, which has a major impact on the performance of crystalline silicon components.

There is a problem of attenuation of efficiency in amorphous silicon solar cells based entirely on thin-film technology. The reason is that the light-absorbing layer of amorphous silicon thin-film solar cells is an amorphous silicon layer with a thickness of several hundred nanometers. A photogenerated metastable state will be generated, which will increase the recombination of photogenerated carriers and reduce the quantum efficiency of amorphous silicon thin film cells, that is, the S-W effect. Sanyo Corporation proposed a new structure, that is, using crystalline silicon as the light absorbing layer, and using amorphous silicon as the passivation layer and P, N doped layers at the same time, thus avoiding the problem of efficiency attenuation of amorphous silicon, and using The good properties of amorphous silicon thin film. Sanyo calls the structure of depositing amorphous silicon doped layers on both sides of crystalline silicon a HIT structure (Heterojunction with IntrinsicThin layer) and has prepared a heterojunction HIT cell with an efficiency of up to 23%. The reason for the high efficiency of the cell is (1) the use of crystalline silicon as the light absorbing layer avoids the light-induced attenuation problem of amorphous silicon thin-film cells (2) amorphous silicon has a hydrogen passivation effect (3) the band gap of amorphous silicon It is larger than the band gap of crystalline silicon, so the P-N junction or N-N+ high-doped-low-doped junction of amorphous silicon and crystalline silicon not only has the electrostatic field of the homojunction but also has an effective field caused by the difference in affinity.

At present, the mainstream technology of crystalline silicon back passivation is the high-low junction back passivation technology with P-P+ or N-N+ homogeneous doping. Sanyo's double-sided HIT battery adopts this back passivation scheme, depositing an N+ amorphous silicon layer on an N-type crystalline silicon substrate to form an N-N+ back electric field. Another back passivation solution is to use the back passivation structure of the floating P-N junction, that is, the PERF solar cell structure (passivatedemitter, rear floating p-n junction), which uses localized homogeneous diffusion on the back of the crystalline silicon substrate to form a high-low junction. At the same time as thermal oxidation of SiO2 passivation, a diffused P-N junction is also formed under the SiO2 layer. Since the P-N junction is under the SiO2 layer and does not directly contact the back electrode, the P-N junction is also called a floating junction. The research of PERF battery shows that the ideal floating junction back passivation has better back passivation effect than SiO2 layer, has a lower surface recombination rate, and the open circuit voltage reaches 720mV.

Contents of the invention

The technical problem to be solved by the present invention is to provide a HIT solar cell structure with heterogeneous floating junction back passivation and its preparation process, improve the back passivation effect of the HIT solar cell, and further improve the power generation efficiency.

The technical solution adopted by the present invention to solve the technical problem is: a HIT solar cell structure with heterogeneous floating junction back passivation, in which a P-type amorphous silicon layer is partially arranged on the upper surface and the lower surface of the N-type crystalline silicon substrate, A heterogeneous P-N junction structure is formed. The local heterogeneous P-N junction structure on the lower surface is isolated by an insulating film layer to form a floating junction back passivation structure. The back electrode on the lower surface of the N-type crystalline silicon substrate is arranged on the N-type crystalline silicon substrate. The bottom N-type amorphous silicon layer is formed, and the back electrode and the heterogeneous P-N floating junction back passivation structure are electrically insulated from each other. The heterogeneous P-N junction structure on the upper surface of the N-type crystalline silicon substrate and the N-type crystalline silicon substrate There is a conductive electrode layer on the back electrode on the lower surface. The insulating film layer can use common insulating film materials in the HIT process, such as ZnO insulating film layer, In2O3 insulating film layer, etc., and even an intrinsic amorphous silicon film layer can be used.

There is also an intrinsic amorphous silicon layer between the P-type amorphous silicon layer and the N-type crystalline silicon substrate in the floating junction back passivation structure, and there is also an intrinsic amorphous silicon layer between the N-type amorphous silicon layer and the N-type crystalline silicon substrate in the back electrode. With intrinsic amorphous silicon layer. The introduction of the intrinsic amorphous silicon layer in the floating junction back passivation structure mainly utilizes the hydrogen passivation effect of hydrogenated amorphous silicon to reduce the minority carrier recombination rate.

To further increase the back passivation effect of the floating junction, the conductive electrode layer covers the back passivation structure of the floating junction while covering the back electrode.

The transparent conductive electrode layer 7 can be Al-doped ZnO or Sn-doped In2O3, etc., which is consistent with the conventional HIT process. Al-doped ZnO is the AZO transparent conductive electrode layer, and Sn-doped In2O3 is the ITO transparent conductive electrode layer.

A preparation process of a HIT solar cell structure with heterogeneous floating junction back passivation. First, a heterogeneous P-N junction structure is formed on the upper and lower surfaces of an N-type crystalline silicon substrate, and then the heterogeneous P-N junction structure on the lower surface is Fabricate a mask on the structure, perform selective etching, continue to deposit an insulating film layer on the lower surface after removing the mask layer, then make a mask on the insulating film layer, and perform a second selective etching to make the N-type crystalline silicon lining The side and the back side of the heterogeneous P-N junction structure on the lower surface are all surrounded by the insulating film layer to form a floating junction back passivation structure, and then, using the mask on the insulating film layer on the lower surface of the N-type crystalline silicon substrate, except In other areas outside the floating junction back passivation structure, the back electrode composed of N-type amorphous silicon layer is made, and finally the heterogeneous P-N junction structure on the upper surface of the N-type crystalline silicon substrate and the back surface of the lower surface of the N-type crystalline silicon substrate A transparent conductive electrode layer is made on the electrode.

The mask is generally made through processes such as photoresist lithography, development, and drying.

The process has the following steps:

a) On the upper surface and the lower surface of the N-type crystalline silicon substrate, the intrinsic amorphous silicon layer is deposited by plasma chemical vapor deposition technology. The thickness of the intrinsic amorphous silicon layer is 0 nanometers to 10 nanometers, and the N-type crystalline silicon substrate The doping concentration is 10 ¹⁵ -10 ¹⁷ cm ^-3 ;

b) Depositing a P-type amorphous silicon layer on the upper and lower surfaces of the N-type crystalline silicon substrate by plasma chemical vapor deposition technology, the thickness of the P-type amorphous silicon layer is 5 nanometers to 20 nanometers, and the P-type amorphous silicon The doping concentration of the layer is from 1E18cm ^-3 to 1E20cm ^-3 ;

c) Spin-coat a photoresist layer on the back side, and define the required photoresist pattern on the P-type amorphous silicon layer by exposing and developing;

d) using the photoresist layer to etch the intrinsic amorphous silicon layer and the P-type amorphous silicon layer on the lower surface through an etching solution until the N-type crystalline silicon substrate is reached, and then removing the photoresist layer;

e) Depositing an insulating thin film layer on the back of the N-type crystalline silicon substrate, the deposited thickness needs to be greater than the total thickness of the intrinsic amorphous silicon layer plus the P-type amorphous silicon layer at the lower surface. The insulating thin film layer can adopt common insulating thin film materials in the HIT process, such as ZnO insulating thin film layer, In2O3 insulating thin film layer, etc., and even the intrinsic amorphous silicon thin film layer can be deposited continuously.

f) Spin-coat a photoresist layer on the back side, and define the required photoresist mask pattern on the insulating film layer through exposure and development. After development, the width of the photoresist mask needs to be larger than that of the lower surface P-type non- The width of the crystalline silicon layer;

g) Etching the insulating film layer with an etching solution to form a floating junction back passivation structure surrounding the intrinsic amorphous silicon layer and the P-type amorphous silicon layer on the lower surface;

h) Depositing an intrinsic amorphous silicon layer on the back of the N-type crystalline silicon substrate, the thickness of the intrinsic amorphous silicon layer being 0 nanometers to 10 nanometers;

i) Deposit a layer of N-type amorphous silicon layer on the back of the N-type crystalline silicon substrate to form a back electrode. The thickness of the N-type amorphous silicon layer is up to 20 nanometers, and the doping concentration of the N-type amorphous silicon layer is 1E18 to 1E20cm ^-3 ;

j) using an organic reagent to remove the photoresist layer to expose the insulating film layer;

k) Deposit a transparent conductive electrode layer such as AZO, ITO, etc. on the front and back of the N-type crystalline silicon substrate. The thickness of the transparent conductive electrode layer is 80 nanometers to 300 nanometers, and the resistivity of the transparent conductive electrode layer is 1E-3 to 1E -5Ωcm, the transparent conductive electrode layer not only covers the N-type amorphous silicon layer, but also covers the heterogeneous P-N floating junction back passivation structure. So far, a complete HIT battery structure with enhanced heterogeneous P-N floating junction back passivation has been formed. .

The beneficial effects of the present invention are: compared with Sanyo's HIT standard process and structure,

1. The present invention introduces a floating P-N junction back passivation structure on the back of N-type crystalline silicon. Floating P-N junction back passivation Compared with traditional SiO2 passivation or N-N+ high-doped-low-doped junction back passivation, the floating P-N junction back passivation technology has a lower surface recombination rate and better open circuit voltage.

2. The back passivation of the floating junction of the present invention utilizes an insulating film layer to realize complete electrical isolation of the P-N heterojunction. Since the transparent conductive electrode layer material of HIT can be Al-doped ZnO transparent conductive electrode layer, Sn-doped In2O3, so the insulating film layer has a wide range of options, which can be intrinsic amorphous silicon film layer, or ZnO or The In2O3 insulating film layer is compatible with the existing process of HIT. Even a combination of multiple insulating film layers can be used to maximize the floating junction back passivation effect.

3. The present invention adds two photolithography processes to Sanyo's HIT process, and forms a heterogeneous P-N floating junction structure with better back passivation effect on the lower surface, which can further improve the opening voltage and overall efficiency of the battery.

Description of drawings

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Fig. 1 is the structural representation of step a of the present invention;

Fig. 2 is the structural representation of step b of the present invention;

Fig. 3 is the structural representation of step c of the present invention;

Fig. 4 is the structural representation of step d of the present invention;

Fig. 5 is the structural representation of step e of the present invention;

Fig. 6 is the structural representation of step f of the present invention;

Fig. 7 is the structural representation of step g of the present invention;

Fig. 8 is a structural schematic diagram of step h of the present invention;

Fig. 9 is a structural schematic diagram of step i of the present invention;

Fig. 10 is a schematic structural diagram of step j of the present invention;

Fig. 11 is a schematic structural diagram of step k of the present invention;

In the figure, 1. N-type crystalline silicon substrate, 2. Intrinsic amorphous silicon layer, 3. P-type amorphous silicon layer, 4. Photoresist layer, 5. Insulating film layer, 6. N-type amorphous silicon layer Layer, 7. Transparent conductive electrode layer.

Detailed ways

The HIT solar cell structure and preparation process of the heterogeneous floating junction back passivation, the basic idea is to deposit a P-type amorphous silicon layer 3 on the upper surface and the lower surface of the N-type crystalline silicon substrate 1 to form a heterogeneous P-N junction Structure, the floating of the P-N junction on the back of the N-type crystalline silicon substrate 1 is realized by vapor deposition of the insulating film layer 5, while the back electrode is still realized by N-type amorphous silicon deposition. The N-type amorphous silicon back electrode and the P-type amorphous silicon floating junction back passivation structure are strictly separated by the insulating film layer 5, which ensures a good floating junction back passivation effect.

First, unlike Sanyo's HIT battery process, this process deposits an amorphous silicon P-N heterostructure layer on the upper and lower surfaces of the N-type crystalline silicon substrate 1 at the same time. The N-type crystalline silicon substrate 1, the intrinsic amorphous silicon layer 2 and the P-type amorphous silicon layer 3 in FIG. 1 together form an upper and a lower P-N heterojunction. The upper P-N heterojunction is the emitter of the solar cell, while the lower P-N heterojunction only functions as a floating junction back passivation. The introduction of the intrinsic amorphous silicon layer 2 mainly utilizes the hydrogen passivation effect of hydrogenated amorphous silicon to reduce the minority carrier recombination rate.

Then, the P-N heterojunction on the lower surface is etched, and then the insulating thin film layer 5 is deposited and etched. The insulating thin film layer can adopt common insulating thin film materials in the HIT process, such as ZnO insulating thin film layer, In2O3 insulating thin film layer, etc., and even the intrinsic amorphous silicon thin film layer can be deposited continuously. The insulating film layer 5 in FIG. 1 completely surrounds the intrinsic amorphous silicon layer 2 and the lower surface and side surfaces of the P-type amorphous silicon layer 3 to form a heterogeneous P-N floating junction rear passivation structure. The heterogeneous P-N floating junction back passivation structure has a better back passivation effect than the N-N+ homogeneous back electric field, and can greatly reduce the minority carrier recombination rate on the back.

Then, deposit an N-N+ heterogeneous back electrode layer to extract photogenerated electrons to form a complete solar cell structure. As shown in FIG. 1 , the back electrode is composed of an intrinsic amorphous silicon layer 2 and an N-type amorphous silicon layer 6 . For the N-type crystalline silicon substrate 1 and the N-type amorphous silicon layer 6, the energy band mismatch of the conduction band is very small, and a good back electrode can be formed.

Finally, a transparent conductive electrode layer 7 is deposited on the upper and lower surfaces of the entire structure, as shown in FIG. 1 . The transparent conductive electrode layer 7 may be Al-doped ZnO, ie AZO, or Sn-doped In2O3, ie ITO. The transparent conductive electrode layer 7 not only covers the N-N+ back electrode layer, but also covers the heterogeneous P-N floating junction back passivation structure, so the photovoltaic of the N-N+ back electrode layer is also applied to the heterogeneous P-N floating junction back passivation structure. On the structure, a MIS back passivation structure of metal-insulator layer-semiconductor layer is formed, which further increases the back passivation effect of the floating junction.

The preparation process of the HIT solar cell structure with heterogeneous floating junction back passivation, compared with Sanyo's HIT process, only adds two photolithography processes, but brings a heterogeneous P-N floating junction back passivation structure, which can be greatly improved. Improve the open circuit voltage of the HIT battery structure and reduce the recombination rate of the crystalline silicon back surface.

Specific steps are as follows:

a) Depositing an intrinsic amorphous silicon layer 2 on the upper and lower surfaces of the N-type crystalline silicon substrate 1 by using plasma chemical vapor deposition technology PECVD, as shown in FIG. 2 . The thickness of the intrinsic amorphous silicon layer 2 is 0 nm to 10 nm. 0 nm means that there is no intrinsic amorphous silicon layer 2, which may reduce the passivation effect of the surface. The doping concentration of the N-type crystalline silicon substrate 1 is 10 ¹⁵ -10 ¹⁷ cm ^-3 , generally 10 ¹⁶ cm ^-3 .

b) Depositing a P-type amorphous silicon layer 3 on the upper surface and the lower surface of the N-type crystalline silicon substrate 1 by using plasma chemical vapor deposition technology PECVD, as shown in FIG. 3 . The thickness of the P-type amorphous silicon layer 3 is 5 nm to 20 nm, generally 10 nm. The doping concentration of the P-type amorphous silicon layer 3 is from 1E18cm ^-3 to 1E20cm ^-3 .

c) Spin-coat a layer of photoresist layer 4 on the back, and define the required photoresist pattern on the P-type amorphous silicon layer 3 through exposure and development, as shown in FIG. 4 .

d) Utilize the photoresist layer 4 of FIG. 4 to etch the intrinsic amorphous silicon layer 2 and the P-type amorphous silicon layer 3 on the lower surface until the N-type crystalline silicon substrate 1, and then use acetone and absolute ethanol The photoresist layer 4 is removed, as shown in FIG. 5 . The corrosion solvent can be HF, HNO3 mixed solution. Corrosion equipment can use single-sided corrosion cleaning equipment.

e) Deposit an insulating film layer 5 on the back of the N-type crystalline silicon substrate 1. The deposited thickness needs to be greater than the total thickness of the intrinsic amorphous silicon layer 2 plus the P-type amorphous silicon layer 3, which can generally be taken as 30 nanometers. As shown in Figure 6. The insulating thin film layer 5 can adopt common insulating thin film materials in the HIT process, such as ZnO insulating thin film layer, In2O3 insulating thin film layer, etc., and can even continue to deposit intrinsic amorphous silicon thin film layer as the insulating thin film layer.

f) Spin-coat a layer of photoresist layer 4 on the back, and define the required photoresist pattern on the insulating film layer 5 through exposure and development, as shown in FIG. 7 . The width of the photoresist after development needs to be greater than the width of the P-type amorphous silicon layer 3 on the lower surface, as shown in FIG. 7 .

g) Utilize HF acid, HNO3 acid and other etching solutions to etch the insulating film layer 5 to form a heterogeneous floating P-N junction structure surrounding the intrinsic amorphous silicon layer 2 and the P-type amorphous silicon layer 3 on the lower surface, as shown in Figure 8 .

h) Depositing an intrinsic amorphous silicon layer 2 on the back of the N-type crystalline silicon substrate 1 , as shown in FIG. 9 . The thickness of the intrinsic amorphous silicon layer 2 is 0 nm to 10 nm. 0 nm means that there is no intrinsic amorphous silicon layer 2, which may reduce the passivation effect of the surface.

i) An N-type amorphous silicon layer 6 is deposited on the back of the N-type crystalline silicon substrate 1 to form a back electrode, as shown in FIG. 10 . The thickness of the N-type amorphous silicon layer 6 is 5 to 20 nanometers, generally 10 nanometers. The doping concentration of the N-type amorphous silicon layer 6 is 1E18 to 1E20 cm ⁻³ . Since the conduction band difference between the N-type crystalline silicon substrate 1 and the N-type amorphous silicon layer 6 is very small, photo-generated electrons can easily pass through the N-type amorphous silicon layer 6, so the conductivity of the back electrode is good.

j) Removing the photoresist layer 4 with an organic reagent to expose the insulating film layer 5, as shown in FIG. 11 .

k) Depositing a transparent conductive electrode layer 7 on the front and back of the N-type crystalline silicon substrate 1 by physical vapor deposition PVD technology, as shown in FIG. 12 . The transparent conductive electrode layer 7 may be Al-doped ZnO, ie AZO, or Sn-doped In2O3, ie ITO. The thickness of the transparent conductive electrode layer 7 is 80 nm to 300 nm. The resistivity of the transparent conductive electrode layer 7 is 1E-3 to 1E-5 Ωcm. The transparent conductive electrode layer 7 not only covers the N-type amorphous silicon layer 6, but also covers the passivation structure of the heterogeneous P-N floating junction, so the photovoltaic of the N-N+ back electrode layer is also applied to the heterogeneous P-N floating junction. On the passivation structure, a metal-insulator layer-semiconductor layer MIS back passivation structure is formed, which further increases the back passivation effect of the floating junction. So far, a complete heterogeneous P-N floating junction back passivation-enhanced HIT cell structure has been formed.

Claims (3)

1. the preparation technology of the HIT solar battery structure of heterogeneous floating junction back of the body passivation, it is characterized in that: at first, upper at N-type crystal silicon substrate (1), lower surface all forms the hetru P-N junction structure, then, make mask on the hetru P-N junction structure of lower surface, carry out selective etch, make lower surface form local hetru P-N junction structure, continue deposition insulating thin layer (5) at lower surface after removing mask layer, at the upper mask of making of insulating thin layer (5), carry out selective etch for the second time, make side and the back side of the hetru P-N junction structure of N-type crystal silicon substrate (1) lower surface all be insulated thin layer (5) encirclement, form hetru P-N floating junction back of the body passivating structure, then, utilize mask on insulating thin layer (5) at the lower surface of N-type crystal silicon substrate (1), other zones except hetru P-N floating junction back of the body passivating structure make the back electrode that N-type amorphous silicon layer (6) forms, remove finally all mask layers, make conductive electrode layer on the back electrode of the lower surface of the hetru P-N junction structure of N-type crystal silicon substrate (1) upper surface and N-type crystal silicon substrate (1).

2. heterogeneous floating junction according to claim 1 is carried on the back the preparation technology of the HIT solar battery structure of passivation, and it is characterized in that: described mask is made by photoresist.

3. heterogeneous floating junction according to claim 1 and 2 is carried on the back the preparation technology of the HIT solar battery structure of passivation, it is characterized in that: have following processing step:

A) upper surface and the lower surface at N-type crystal silicon substrate (1) utilizes plasma chemical vapor deposition technique deposition intrinsic amorphous silicon layer (2), the thickness of intrinsic amorphous silicon layer (2) be 0 nanometer to 10 nanometers, the doping content of N-type crystal silicon substrate (1) is 10 ¹⁵-10 ¹⁷cm ^-3

B) utilize plasma chemical vapor deposition technique deposition P type amorphous silicon layer (3) at the upper surface of N-type crystal silicon substrate (1) and lower surface, the thickness of P type amorphous silicon layer (3) be 5 nanometers to 20 nanometers, the doping content of P type amorphous silicon layer (3) is at 1E18cm ^-3To 1E20cm ^-3

C) spin coating one deck photoresist layer (4) overleaf,, by exposure, develop, at the required photoetching offset plate figure of P type amorphous silicon layer (3) definition;

D) utilize photoresist layer (4), by the intrinsic amorphous silicon layer (2) of corrosive liquid to lower surface, P type amorphous silicon layer (3) corrodes, until N-type crystal silicon substrate (1) is then removed photoresist layer (4);

E) at N-type crystal silicon substrate (1) backside deposition insulating thin layer (5), the thickness of deposition need to add greater than intrinsic amorphous silicon layer (2) gross thickness of P type amorphous silicon layer (3), insulating thin layer (5) adopts common insulating film material in the HIT manufacturing process, comprise ZnO insulating thin layer, In2O3 insulating thin layer, perhaps the amorphous silicon membrane layer of Direct precipitation intrinsic is as this insulating thin layer;

F) spin coating one deck photoresist layer (4) overleaf,, by exposure, develop, and at the required photoetching agent pattern of the upper definition of insulating thin layer (5), post-develop is carved the width of glue need to be greater than the width of lower surface P type amorphous silicon layer (3);

G) utilize corrosive liquid etching insulating thin layer (5), form the hetru P-N floating junction back of the body passivating structure that surrounds lower surface intrinsic amorphous silicon layer (2), P type amorphous silicon layer (3);

H) deposit one deck intrinsic amorphous silicon layer (2) at N-type crystal silicon substrate (1) back side, the thickness of intrinsic amorphous silicon layer (2) is that 0 nanometer is to 10 nanometers again;

I) deposit one deck N-type amorphous silicon layer (6) at N-type crystal silicon substrate (1) back side again, form back electrode, the thickness of N-type amorphous silicon layer (6) is in 5 to 20 nanometers, and the doping content of N-type amorphous silicon layer (6) is that 1E18 is to 1E20cm ^-3

J) utilize organic reagent to remove photoresist layer (4), expose insulating thin layer (5);

K) at the front and back deposit transparent conductive electrode layer (7) of N-type crystal silicon substrate (1), the thickness of transparency conductive electrode layer (7) in 80 nanometers to 300 nanometers, the resistivity of transparency conductive electrode layer (7) arrives 1E-5 Ω cm at 1E-3, transparency conductive electrode layer (7) not only covers above N-type amorphous silicon layer (6), also cover hetru P-N floating junction back of the body passivating structure, transparency conductive electrode layer 7 is the ZnO of Al doping or the In2O3 of Sn doping, so far, the HIT battery structure of complete hetru P-N floating junction back of the body passivation enhancing forms.

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