JP6008905B2 - Optical semiconductor device - Google Patents

Description

  The present invention relates to an optical semiconductor device in which an optical semiconductor chip is incorporated in a metal package.

  In an optical semiconductor device used for transmitting and receiving light, an optical semiconductor chip such as a semiconductor laser, a light emitting diode, or a photodiode is placed in a metal package, and a lead for taking out an electrical signal and the optical semiconductor chip are placed in the metal package. In many cases, it has the structure connected with the metal wire. In addition, as a metal package of an optical semiconductor device, a TO (Transistor Outline) type package that can be easily connected to an optical fiber and has high versatility is widely used.

  On the other hand, with the recent increase in demand for Internet communication, the speed of optical fiber communication devices has been increased. In an optical semiconductor device, a technique for accommodating an optical semiconductor chip and a multifunctional semiconductor component in a single package is necessary in order to prevent the deterioration of the S / N ratio accompanying the increase in speed and to provide a high-performance optical semiconductor element. It is said that.

  Patent Documents 1 and 2 disclose techniques for accommodating a plurality of semiconductor components in one package using an insulating flexible substrate.

Japanese Patent Laid-Open No. 9-232500 Japanese Patent Laid-Open No. 10-4510

  However, the conventional techniques disclosed in Patent Documents 1 and 2 above are techniques applied to a large package different from the package used in the optical semiconductor device, and have different purposes or problems from the present invention. is there. Hereinafter, problems to be solved by the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic diagram showing the connection between the optical semiconductor device 1 using the TO-type package and the optical fiber 40. The TO type package includes a base 3 and a cap 2. The cap 2 is provided with a lens 5 for transmitting and receiving light to and from the optical fiber 40. An optical semiconductor chip is disposed inside the TO type package, and is electrically connected to the lead 4 inserted through the inner surface from the outer surface of the base 3.

  FIG. 2 is a schematic diagram showing an AA cross section (see FIG. 1) of an optical semiconductor device that receives an optical signal and converts it into an electrical signal. A photodiode chip 6 bonded on the submount 7 is installed on the component arrangement surface 3 b on the inner surface of the base 3. Metal wiring is provided on the surface of the submount 7 and is electrically connected to the photodiode chip 6. On the component placement surface 3b, a semiconductor component 8 such as a preamplifier and TIA (Trans Impedance Amplifier), and a passive component 9 such as a capacitor and a resistor are arranged.

  The photodiode 6 bonded on the submount 7 is connected to the lead 4 by the metal wire 10 through the semiconductor component 8 or the passive component 9. Light incident on the photodiode 6 from the optical fiber 40 is converted into an electrical signal by the photodiode 6, amplified by the semiconductor component 8, and taken out by the lead 4. The lead 4 is inserted into an opening 4b provided penetrating from the outer surface of the base 3 to the component placement surface 3b. The lead 4 is insulated from the base 3 by an insulating glass sintered body 12.

  FIG. 3 is a schematic diagram showing the component arrangement of the TO type package shown in FIG. Five leads 4 including leads not shown in FIGS. 1 and 2 are arranged in the component arrangement surface 3 b of the base 3. A lead 4 and a glass sintered body 12 covering the periphery of the lead 4 are sealed in the five openings 4 b provided in the base 3. Further, a submount 7 to which a photodiode 6 is bonded, a semiconductor component 8 and a passive component 9 are arranged and connected by a metal wire 10.

  In order to receive a high-speed optical signal in the above optical semiconductor device, it is effective to replace the semiconductor component 8 with a multi-functional semiconductor component and eliminate a loss when an electric signal is transmitted between a plurality of functional elements. When accommodating a multifunctional semiconductor component in a TO-type package, it is necessary to dispose a semiconductor component whose chip size has been increased for multifunctional purposes and a newly required passive component. Therefore, it becomes a problem to secure a space for arranging these components in a limited space on the component arrangement surface 3b of the base 3.

  In a small TO-type package, the ratio of the area of the opening 4b to which the sintered glass body 12 is sealed in the component placement surface 3b is increased. On the other hand, no part can be placed on the glass sintered body 12. For this reason, the substantial space for component arrangement is limited. Further, when the number of leads 4 is increased as a new input terminal in order to accommodate multifunctional semiconductor components, the space is further reduced.

  In addition, the increase in the number of components to be accommodated complicates the wiring with metal wires, and causes a problem that it is difficult to arrange components without crossing between metal wires.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to realize an optical semiconductor device that solves the above-described problems and includes a multifunctional semiconductor component and enables transmission and reception of high-speed optical signals.

In order to solve the above problems, an optical semiconductor device according to the present invention includes a metal package that includes a cap and a base, and has an internal space between the cap and the base. The metal package is inserted into a plurality of openings penetrating from the outer surface to the inner surface of the base, and leads having end portions protruding into the space, and an insulator filling each of the plurality of openings and covering the side surfaces of the leads, Have. Furthermore, an insulating film that covers the inner surface of the base and covers the insulator to the vicinity of the side surface of the lead, a semiconductor component disposed on the insulating film, and disposed around the semiconductor component on the insulating film. Passive components. At least one of the semiconductor component and the passive component is at least partially disposed on the insulator via the insulating film. The lead penetrates the insulating film and is electrically connected to the semiconductor component or the passive component via a metal wire.

In another aspect of the present invention, an optical semiconductor device includes a metal package including a cap and a base, and having an internal space between the cap and the base. The metal package is inserted into a plurality of openings penetrating from the outer surface to the inner surface of the base, and leads having end portions protruding into the space, and an insulator filling each of the plurality of openings and covering the side surfaces of the leads, Have. Furthermore, a semiconductor component disposed on the inner surface of the base, an insulating film covering the inner surface of the base excluding a portion where the semiconductor component is disposed, and covering the insulator to the vicinity of the side surface of the lead, and the insulating film And a passive component disposed on the top. At least a part of the passive component is disposed on the insulator via the insulating film. The lead penetrates the insulating film and is electrically connected to the semiconductor component or the passive component via a metal wire.

  According to the present invention, since the insulator covering the side surface of the lead is covered with the insulating film, the space in which the components can be arranged is expanded on the inner surface of the base. Thereby, it is possible to arrange a semiconductor component having a large chip size and a plurality of passive components.

  According to the optical semiconductor device of the present invention, a high-speed optical signal can be transmitted and received by including a multifunctional semiconductor component.

It is the schematic diagram which showed the connection of the optical semiconductor device which concerns on this invention, and an optical fiber. It is a schematic diagram which shows the AA cross section of the optical semiconductor device which concerns on a prior art. It is the schematic diagram which showed the components arrangement | positioning of the optical semiconductor device which concerns on a prior art. It is the schematic diagram which showed the components arrangement | positioning of the optical semiconductor device which concerns on this invention. It is a schematic diagram which shows the BB cross section of the optical semiconductor device which concerns on this invention. It is a schematic diagram which shows the state which adhere | attached the insulating film on the base of the optical semiconductor device which concerns on this invention. It is a schematic diagram which shows CC cross section of the optical semiconductor device which concerns on this invention. It is the schematic diagram which showed the components arrangement | positioning of the optical semiconductor device which concerns on this invention. It is the schematic diagram which showed the calculation model for the impedance matching which concerns on this invention. It is a schematic diagram which shows another Example which concerns on this invention. It is a schematic diagram which shows DD cross section of the optical semiconductor device which concerns on this invention. It is a schematic diagram which shows the insulating film used for another Example which concerns on this invention. It is a schematic diagram which shows the insulating film used for another Example which concerns on this invention. It is a schematic diagram which shows the insulating film used for another Example which concerns on this invention. It is a schematic diagram which shows the insulating film used for another Example which concerns on this invention. It is a schematic diagram which shows the insulating film used for another Example which concerns on this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same parts in the drawings are denoted by the same reference numerals, detailed description thereof will be omitted as appropriate, and different parts will be described as appropriate.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 4 is a schematic diagram showing the component arrangement on the inner surface of the base 3 according to the optical semiconductor device of the present invention. In the present invention, the insulating film 14 covers the entire component placement surface 3 b of the base 3. The insulating film 14 covers up to the vicinity of the lead 4 and covers most of the glass sintered body 12. As a method for adhering the insulating film 14 to the base 3, a resin adhesive may be used, or an adhesive paste may be used. Further, as will be described later, a metal pattern can be formed on the back surface, which is the bonding surface of the insulating film 14, and can be bonded by solder.

  As shown in the figure, a photodiode chip 6 bonded on the submount 7, a semiconductor component 8 b having a function of TIA and LIA (Limiting Amplifier), and a passive component 9 are disposed on the insulating film 14. . The submount 7 to which the photodiode chip 6 is bonded is also a semiconductor component, but will be described separately in the following description.

  In the present invention, the insulating film 14 covers most of the area occupied by the opening 4b to which the glass sintered body 12 is sealed. As a result, the area where the components can be arranged is expanded, and it is possible to arrange the semiconductor component 8b and the plurality of passive components 9 which are multifunctional and have an increased chip size.

  FIG. 5 schematically shows a BB cross section of the base 3 shown in FIG. An insulating film 14 is disposed on the component placement surface 3 b of the base 3. The lead 4 passes through an opening 15 provided in the insulating film 14 and projects an end portion on the surface of the insulating film 14.

  In this embodiment, the diameter of the opening 15 is about 0.4 m, and the diameter of the lead 4 is about 0.2 mm. Therefore, the gap generated between the lead 4 and the opening 15 is about 0.1 mm. On the other hand, the diameter of the opening 4b provided in the base 3 is about 1.0 mm. That is, the doughnut-shaped portion having a width of 0.3 mm of the opening 4 b excluding the gap of 0.1 mm and the lead 4 having a diameter of 0.2 mm is covered with the insulating film 14.

  Further, as shown in FIG. 5, the semiconductor component 8 b, the photodiode 6 bonded to the submount 7, and the passive component 9 are disposed on the insulating film 14.

  FIG. 6 is a schematic view showing a state in which the insulating film 14 on which the metal patterns 17 and 18 are formed is bonded to the component placement surface 3 b of the base 3. A metal pattern 17 in the figure is a GND pattern, and is electrically connected to the back surface metal pattern 22 and the base 3 through a through hole 21 described later. On the other hand, the metal pattern 18 is a wiring pattern provided for wiring between the lead 4 and the output terminal of the semiconductor component 8b.

  FIG. 7 is a schematic diagram showing a CC cross section of the base 3 shown in FIG. An insulating film 14 is bonded on the component placement surface 3 b of the base 3. A back metal pattern 22 is formed on the entire back surface of the insulating film 14. The component placement surface 3b of the base 3 and the back surface of the insulating film 14 are electrically connected by being bonded with solder or conductive paste. A ground terminal 23 is attached to the outer surface of the base 3, and the base 3 and the back surface metal pattern 22 are held at the ground potential when the optical semiconductor device is used.

  The GND pattern 17 formed on the surface of the insulating film 14 is electrically connected to the back surface metal pattern 22 through the through hole 21. Therefore, the GND pattern 17 becomes a ground potential when the optical semiconductor device is used. On the other hand, the through hole 21 is not provided between the wiring pattern 18 formed on the surface of the insulating film 14 and the back surface metal pattern 22. The wiring pattern 18 is a microstrip line that faces the back surface metal pattern 22 with the insulating film 14 interposed therebetween.

  By forming the back surface metal pattern 22 over the entire back surface of the insulating film 14, the entire back surface is held at the ground potential. As a result, the stray capacitance of the microstrip line formed on the surface of the insulating film 14 becomes a constant value determined by the thickness and dielectric constant of the insulating film 14. Thereby, the frequency characteristic of the electric circuit formed on the surface of the insulating film 14 is stabilized, and the performance of the optical semiconductor device is improved.

  FIG. 8 is a schematic view showing a state in which components are arranged on the insulating film 14 shown in FIG. A photodiode 6 bonded to the submount 7 and a semiconductor component 8b are disposed. In addition, the passive component 9 is disposed on the GND pattern 17, and a metal wire is connected between the lead 4, the submount 7, and the semiconductor component 8b. These connections are wiring for supplying a driving voltage from the lead 4 to the photodiode 6 and the semiconductor component 8b.

  An optical signal incident on the optical semiconductor device from the optical fiber is converted into an electrical signal by the photodiode 6. The submount 7 and the semiconductor component 8b are connected by a metal wire 10 that transmits an electrical signal converted in the photodiode 6 to the semiconductor component 8b. The signal output terminal 8c of the semiconductor component 8b and the end 18a of the wiring pattern are also connected by the metal wire 10. The other end 18 b of the wiring pattern 18 is connected to the lead 4.

  The electrical signal output from the output terminal 8c of the semiconductor component 8b is transmitted through the wiring pattern 18 and output from the lead 4 to the outside. At this time, impedance matching can be achieved in order to reduce reflection of electric signals between the wiring pattern 18, the semiconductor component 8 b, and the leads 4. Thereby, the transmission loss of an electric signal can be reduced and the performance of the optical semiconductor device can be improved.

  For example, if the semiconductor component 8b is an amplifier having the functions of TIA and LIA, the characteristic impedance at the output terminal 8c is designed to be 50Ω. Therefore, impedance matching can be achieved if the shape of the wiring pattern 18 is designed so that the characteristic impedance as a strip line is 50Ω at the end 18a of the wiring pattern. On the other hand, since the impedance of the lead 4 is about 35Ω, the shape may be designed so that the characteristic impedance of the wiring pattern 18 becomes 35Ω at the other end point 18b.

  FIG. 9 is a schematic diagram showing a model used for calculation of impedance. A wiring pattern (microstrip line) 18 having a line width W is disposed on the surface of the insulating film 14, and a back metal pattern 22 is provided on the entire back surface. The length of the microstrip line 18 is calculated as infinite.

Table 1 shows the result of simulation using the model shown in FIG. The thickness of the insulating film 14 is 50 μm, and the dielectric constant is 3.2 of polyimide film. The line widths W of the microstrip line 18 with the characteristic impedance Z (Ω) of 35Ω and 50Ω are 0.18 mm and 0.1 mm, respectively. From this result, it can be seen that impedance matching can be achieved if the width of the wiring pattern 18 on the lead 4 side is 0.18 mm and the width of the wiring pattern 18 on the semiconductor element 8b (amplifier) side is 0.1 mm.

  The above impedance matching is performed in both of the two wiring patterns 18 shown in FIG.

  Further, in the component arrangement shown in FIG. 8, the wiring between the submount 7 and the semiconductor component 8 b to which the electric signal is transmitted, the wiring between the semiconductor component 8 b and the wiring pattern 18, and the wiring pattern 18 and the lead 4 It is necessary to shorten the metal wire 10 forming the wiring. As the metal wire 10 becomes longer, the characteristic impedance of that portion increases and the transmission loss of electric signals increases. In addition, since the loop shape of the metal wire connecting the parts becomes different and the variation in characteristic impedance increases, there arises a problem that the performance of the optical semiconductor device in the high frequency band is not stable.

  According to the present invention, since the degree of freedom of component placement is great, the submount 7 and the semiconductor component 8b can always be placed close to each other, and the above problem can be avoided. Further, by interposing the wiring pattern 18, it is possible to connect the end 18 a of the wiring pattern 18 and the semiconductor component 8 b and the other end 18 b of the wiring pattern 18 and the lead 4 with a short metal wire. It becomes.

  In the conventional technique in which the output terminal 8c of the semiconductor component 8b and the lead 4 are directly connected by the metal wire 10, it is necessary to arrange the output terminal of the semiconductor component 8b and the lead 4 close to each other in order to shorten the metal wire 10. there were. For this purpose, expensive dedicated parts designed in consideration of the arrangement of the leads 4 and the arrangement position of the semiconductor parts 8b have to be used. On the other hand, in the present invention, the problem can be avoided by changing the wiring pattern 18 according to the semiconductor component 8b, and a general-purpose component can be used.

  FIG. 10 is a schematic view showing another aspect of the present invention. Of the elements related to the reference numerals shown in the figure, the same elements as those in FIG. Further, the display of the passive component 9 to be arranged on the GND pattern 17 is also omitted.

  In the present embodiment, the insulating film 14 bonded onto the component placement surface 3b of the base 3 is a multilayer film in which two insulating films 14a and 14b are laminated. Interlayer wiring 25 is provided at the interface between the insulating films 14a and 14b. Interlayer wiring 25 connecting the metal patterns 26 and 27 formed on the surface of the insulating film 14b is indicated by broken lines in the drawing.

  The semiconductor component 8b of this embodiment is a general-purpose component, and the voltage supply terminal is at the position indicated by 31 in the figure. On the other hand, the drive voltage is supplied from the lead 4c shown in the drawing. In such a case, even if an attempt is made to form a wiring pattern on the surface of the insulating film 14b, an appropriate pattern cannot be formed because the submount 7 or the semiconductor component 8b becomes an obstacle. Moreover, even if it connects with a metal wire, the submount 7 or the semiconductor component 8b also becomes an obstacle. Therefore, the problem can be solved by wiring using the interlayer wiring 25 provided in the multilayer film.

  FIG. 11 is a schematic diagram showing a DD cross section of the base 3 in the embodiment shown in FIG. On the component arrangement surface 3b of the base 3, a multilayer film 14 in which insulating films 14a and 14b are laminated is arranged. A back surface metal pattern 22 is provided on the back surface of the multilayer film 14 and is bonded to the base 3 using solder or conductive paste. Further, an interlayer wiring 25 is provided at the interface between the insulating films 14a and 14b, and is electrically connected to the metal patterns 26 and 27 formed on the surface of the insulating film 14b through the through holes 21. .

  Further, the passive component 9 is disposed on the metal pattern 26. (The passive component 9 in this case is a resistor.) The passive component 9 is connected to the lead 4 c by a metal wire 10. On the other hand, the metal pattern 27 is connected to the voltage supply terminal 31 of the semiconductor component 8 b by the metal wire 10. Thereby, the lead 4c and the voltage supply terminal 31 of the semiconductor component 8b can be connected regardless of the arrangement of the submount 7 or the semiconductor component 8b.

  12-15 is the schematic diagram which showed the insulating film 14 used for another Example of this invention. The elements related to the reference numerals shown in the figure and common to the above-described embodiment will not be described.

  FIG. 12 shows an opening 32 provided in a portion where the semiconductor component 8b is arranged in addition to the insulating film 14 shown in FIG. The opening 32 is slightly larger than the outer shape of the semiconductor component 8b, and is provided for directly bonding the semiconductor component 8b to the component placement surface 3b of the base 3. Such an insulating film 14 is used when the back surface of the semiconductor component 8b needs to be at the ground potential, and the performance of the semiconductor component 8b is easily affected by fluctuations in the ground potential.

  FIG. 13 is a schematic view of the insulating film 14 provided with an opening 33 for bonding both the submount 7 to which the photodiode 6 is bonded and the semiconductor component 8 b to the component placement surface 3 b of the base 3. When the performance of the optical semiconductor device fluctuates due to a potential difference between the ground potential connecting the terminals of the photodiode 6 and the ground potential on the back surface of the semiconductor component 8b, the terminals of the photodiode 6 For the purpose of maintaining the back surface of the semiconductor component 8b at the same ground potential, the insulating film 14 shown in FIG. 13 is used.

  FIG. 14 is a schematic diagram showing the insulating film 14 in which the wiring patterns 18 and 35 are provided on the surface of the insulating film 14. The wiring pattern 35 is used for wiring between a plurality of components. As shown by the broken line in the figure, this is effective when the mutual arrangement of the passive component 9 with respect to the semiconductor component is separated and the wiring length of the metal wire is increased or the number of components is increased.

  FIG. 15 is a schematic diagram showing the insulating film 14 in which the alignment mark 37 is arranged. An alignment mark 37 is disposed as a target for alignment when parts are arranged and metal wires are bonded using an automatic machine.

  FIG. 16 shows the insulating film 14 according to the embodiment using only the wiring pattern 18 for wiring the semiconductor component 8 b and the lead 4. When desired performance is obtained by wiring between the semiconductor component 8b and the lead 4 and the wiring pattern 18 with the short metal wire 10 and matching the impedance between the semiconductor component 8b and the lead 4 and the wiring pattern 18, It can be used conveniently.

  As a material of the insulating film 14 according to the present invention, a polyimide film, an LPC (liquid crystal polymer) film, or the like can be used. The LPC film is preferable for an electric signal in a high frequency band because the dielectric loss of the high frequency signal is small. However, since the LPC film is inferior in heat resistance, there is a problem that usable solder is limited.

  The insulating film 14 can be manufactured by the following method. A through hole 21 is formed by a micro drill in an insulating film such as polyimide having copper foil laminated on both sides. In order to electrically connect the front and back copper foils, TH (through hole) plating by copper plating is performed. Next, a pattern is formed by photolithography and etching. Further, the opening 15 for inserting the lead 4 is processed using a micro drill, and finally the outer shape is punched out.

  The metal wire described in the above embodiment is, for example, a gold wire. In addition, although an example of an optical semiconductor device including a photodiode and a semiconductor component (amplifier) has been described, the optical semiconductor device according to a combination of a surface emitting laser or a light emitting diode and a driver IC can also be implemented.

  The preferred embodiments of the present invention have been described in detail above. However, the optical semiconductor device according to the present invention is not limited to the above-described embodiments, and is within the scope of the gist of the present invention described in the claims. Various modifications and changes are possible.

DESCRIPTION OF SYMBOLS 1 Optical semiconductor device 2 Cap 3 Base 3b Component arrangement surface 4 Lead 4b Opening 6 Photodiode 7 Submount 8, 8b Semiconductor component 9 Passive component 10 Metal wire 12 Glass sintered body 14 Insulating film (multilayer film)
17 Metal pattern (GND pattern)
18 Metal pattern (wiring pattern, microstrip line)
21 Through hole 22 Back metal pattern 25 Interlayer wiring

Claims (5)

A metal package comprising a cap and a base and having an internal space between the cap and the base,
A lead inserted into a plurality of openings penetrating from the outer surface to the inner surface of the base, and an end projecting into the space; and
An insulator filling each of the plurality of openings and covering a side surface of the lead;
A metal package having
An insulating film that covers the inner surface of the base and covers the insulator to the vicinity of the side surface of the lead;
A semiconductor component disposed on the insulating film;
Passive components arranged around the semiconductor component on the insulating film;
With
At least one of the semiconductor component and the passive component is at least partially disposed on the insulator via the insulating film ,
The lead is an optical semiconductor device that penetrates the insulating film and is electrically connected to the semiconductor component or the passive component via a metal wire . A metal package comprising a cap and a base and having an internal space between the cap and the base,
A lead inserted into a plurality of openings penetrating from the outer surface to the inner surface of the base, and an end projecting into the space; and
An insulator filling each of the plurality of openings and covering a side surface of the lead;
A metal package having
A semiconductor component disposed on the inner surface of the base;
Covering the inner surface of the base excluding the portion where the semiconductor component is disposed, and covering the insulator to the vicinity of the side surface of the lead; and
Passive components disposed on the insulating film;
With
The passive component is at least partially disposed on the insulator via the insulating film ,
The lead is an optical semiconductor device that penetrates the insulating film and is electrically connected to the semiconductor component or the passive component via a metal wire . The insulating film has a metal pattern on the surface opposite to the inner surface of the base,
The optical semiconductor device according to claim 1, wherein the lead is electrically connected to the semiconductor component via the metal wire and the metal pattern. The insulating film has a metal pattern on the surface opposite to the inner surface of the base,
The optical semiconductor device according to claim 1, wherein the metal pattern is electrically connected to a ground terminal.   The optical semiconductor device according to claim 4, wherein the passive component is disposed on the metal pattern.

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