JP2013239531A - Thin film transistor, manufacturing method of the same, display device, image sensor, x-ray sensor and x-ray digital imaging equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lamination type thin film transistor capable of achieving high light stability (ΔVth≤1 V for light irradiation of λ=420nm), and suppressing hump effect in Vg-Id characteristic.SOLUTION: A thin film transistor 1 comprises: a first region A containing a composition represented by InGaZnO(a>0,b≥0,c>0,d>0, a+b+c=1) and satisfying b≤91a/74-17/40 as the oxide semiconductor layer; and second region A2 arranged on a side farther from the gate electrode than the first region and containing a composition represented by InGaZnO(e>0,f>0,g>0,h>0, and e+f+g=1), satisfying f/(e+f)≥0.80 and being different from that of the first region.

Description

  The present invention relates to a thin film transistor and a manufacturing method thereof, a display device, an image sensor, an X-ray sensor, and an X-ray digital imaging device.

  In recent years, research and development of thin film transistors (TFTs) using an In—Ga—Zn—O-based (hereinafter referred to as IGZO) oxide semiconductor thin film as an active layer (channel layer) have been active. An oxide semiconductor thin film can be formed at a low temperature, has higher mobility than amorphous silicon, and is transparent to visible light. Therefore, a flexible thin film transistor is formed on a substrate such as a plastic plate or a film. Is possible.

  Here, Table 1 shows a comparison of field effect mobility and process temperature of various transistor characteristics.

As shown in Table 1, a thin film transistor whose active layer is polysilicon can obtain a mobility of about 100 cm ² / Vs. However, since the process temperature is as high as 450 ° C. or higher, it can be applied only to a substrate having high heat resistance. It cannot be formed and is not suitable for low cost, large area, and flexibility. In addition, since the thin film transistor whose active layer is amorphous silicon can be formed at a relatively low temperature of about 300 ° C., the selectivity of the substrate is wider than that of polysilicon, but only a mobility of about 1 cm ² / Vs can be obtained at most. Not suitable for fine display applications.
On the other hand, from the viewpoint of low-temperature film formation, thin film transistors whose organic active layer is organic can be formed at 100 ° C. or lower, and therefore are expected to be applied to flexible display applications using plastic film substrates with low heat resistance. The mobility is only as high as that of amorphous silicon.

For example, in Patent Document 1, a high mobility layer containing an oxide of IZO, ITO, GZO, or AZO is disposed on the side close to the gate electrode as the active layer, and Zn is contained on the side far from the gate electrode. A thin film transistor having an oxide layer is disclosed.
A thin film transistor using an oxide semiconductor, particularly an oxide semiconductor containing In, Ga, and Zn, as an active layer has a property that a threshold voltage is negatively shifted when irradiated with light having a wavelength shorter than 460 nm. Has been reported (see Non-Patent Document 1).

JP 2010-21555 A

C.S.Chuang et al., SID 08 DIGEST, P-13

  The blue light-emitting layer used in organic EL and liquid crystals shows broad light emission having a peak of about λ = 450 nm, but the tail of the emission spectrum of blue light of the organic EL element continues to 420 nm, and the blue color filter has a wavelength of 400 nm. Considering that about 70% of the light passes through, it is required that the characteristic deterioration with respect to light irradiation in a wavelength region smaller than 450 nm is low. If the optical band gap of the IGZO film is relatively narrow and the region has optical absorption, there arises a problem that the threshold shift of the transistor occurs.

On the other hand, with the increase in size and resolution of displays, there is a demand for higher mobility of thin film transistors for driving the display. Covering with amorphous silicon and conventional IGZO elements (mobility of about 10 cmA ² / Vs) High-function displays that cannot be performed are being proposed.
As one of the methods for realizing such high mobility, there is a TFT having a structure in which a plurality of active layers made of oxide semiconductors are stacked. However, in such a stacked TFT, deterioration of characteristics against light irradiation is caused. No attempt has been made to improve the light irradiation stability essentially without providing a protective layer or the like for reducing or a blocking layer on the active layer.

Here, for example, when a threshold shift amount (ΔVth) for 420 nm light irradiation is set to 1 V or less as an index of stability to light irradiation, a stacked TFT satisfying ΔVth ≦ 1V for 420 nm light irradiation is formed. It is difficult to realize.
In Patent Document 1, an IZO system or the like is used as a current path layer and a high mobility TFT can be realized, but the light irradiation characteristics are not mentioned.
Non-Patent Document 1 evaluates deterioration of characteristics with respect to light irradiation with respect to a conventional IGZO single-film TFT element. However, if the above numerical value is used as a reference, the characteristics of light irradiation stability are still insufficient. is there.

In addition, when the stacked TFT structure is adopted, it is assumed that a large number of defect levels that contribute to deterioration of light stability are likely to be formed at the stacked interface due to damage during film formation. Further, in general, in the stacked structure, carrier mobility occurs due to stacking of the active layers, so that a hamp effect that causes an increase in off-current is likely to occur, which causes deterioration of light stability and on / off characteristics of the TFT. .
Under such circumstances, it is difficult to suppress the hamp effect while realizing high light stability in the stacked TFT.

  The present invention realizes high light stability (ΔVth ≦ 1V with respect to light irradiation at λ = 420 nm) and suppresses the hump effect in the Vg-Id characteristic, and a relatively simple manufacturing process of the thin film transistor And a display device, an image sensor, an X-ray sensor, and an X-ray digital imaging device.

In order to achieve the above object, the following invention is provided.
<1> As the oxide semiconductor layer of a thin film transistor having a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode, In _(a) Ga _(b) Zn _(c) O _{( d)} a first region having a composition represented by (a> 0, b ≧ 0, c> 0, d> 0, and a + b + c = 1) and satisfying b ≦ 91a / 74-17 / 40, and In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0, and a region farther from the gate electrode than the first region; E + f + g = 1), a film forming step of forming a second region having a composition different from that of the first region and satisfying f / (e + f) ≧ 0.80,
A heat treatment step of performing a heat treatment at 300 ° C. or higher in an oxidizing atmosphere after the film forming step;
The manufacturing method of the thin-film transistor which has this.

<2> The method for producing a thin film transistor according to <1>, wherein a heat treatment temperature in the heat treatment step is 400 ° C. or higher.

<3> The method for manufacturing a thin film transistor according to <1> or <2>, wherein the atmosphere in the heat treatment step is a dry atmosphere having a moisture content in the whole atmosphere of −36 ° C. or less in terms of dew point temperature.

<4> A gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode,
The oxide semiconductor layer is represented by In _(a) Ga _(b) Zn _(c) O _(d) (a> 0, b ≧ 0, c> 0, d> 0, and a + b + c = 1). a first region having a composition satisfying b ≦ 91a / 74-17 / 40, and disposed on a side farther from the gate electrode than the first region, and In _(e) Ga _(f) Zn _(g) O _(H) (e> 0, f> 0, g> 0, h> 0, and e + f + g = 1), the composition is different from that of the first region, and f / (e + f) ≧ 0.80. A thin film transistor including a second region having a filling composition.

<5> The composition of the first region is
c ≦ 3/5,
b> 0,
b ≧ 3a / 7-3 / 14,
b ≧ 9a / 5−53 / 50,
b ≦ −8a / 5 + 33/25, and
b ≦ 91a / 74-17 / 40
The thin-film transistor as described in <4> in the range which satisfy | fills.

<6> The composition of the first region is
b ≦ 17a / 23-28 / 115,
b ≧ 3a / 37,
b ≧ 9a / 5−53 / 50, and
b ≦ 1/5
The thin-film transistor as described in <4> in the range which satisfy | fills.

<7> The thin film transistor according to <4>, wherein the composition of the first region is b = 0.

<8> The thin film transistor according to <7>, wherein the composition of the first region is 0.4 ≦ a ≦ 0.75.

<9> The thin film transistor according to <7>, wherein the composition of the first region is 0.4 ≦ a ≦ 0.5.

<10> The thin film transistor according to any one of <4> to <9>, wherein the film thickness of the second region is more than 10 nm and less than 70 nm.

<11> The thin film transistor according to any one of <4> to <10>, wherein the film thickness of the first region is 5 nm or more and less than 10 nm.

<12> The thin film transistor according to any one of <4> to <11>, wherein the oxide semiconductor layer is amorphous.

<13> A display device comprising the thin film transistor according to any one of <4> to <12>.
<14> An image sensor comprising the thin film transistor according to any one of <4> to <12>.
<15> An X-ray sensor comprising the thin film transistor according to any one of <4> to <12>.
<16> An X-ray digital imaging apparatus comprising the X-ray sensor according to <15>.

  According to the present invention, a stacked thin film transistor that achieves high light stability (ΔVth ≦ 1V with respect to light irradiation at λ = 420 nm) and suppresses the hump effect in the Vg-Id characteristic, and the thin film transistor are relatively simple. A method of manufacturing a thin film transistor that can be manufactured by a manufacturing process, a display device, an image sensor, an X-ray sensor, and an X-ray digital imaging device are provided.

It is the schematic which shows the structure of an example (bottom gate-top contact type) of the thin-film transistor which concerns on this invention. It is the schematic which shows the structure of an example (top gate-bottom contact type) of the thin-film transistor which concerns on this invention. It is a cross-sectional STEM image which shows (A) immediately after lamination | stacking of an IGZO laminated film, and (B) after 600 degreeC annealing treatment. It is the schematic of the light irradiation characteristic evaluation method. It is a figure which shows the A2 layer composition dependence of Vg-Id characteristic. It is a figure which shows the change of the Vg-Id characteristic under the light irradiation in Example 3. FIG. It is a schematic sectional drawing which shows a part of liquid crystal display device of embodiment. It is a schematic block diagram of the electrical wiring of the liquid crystal display device of FIG. It is a schematic sectional drawing which shows a part of organic EL display apparatus of embodiment. It is a schematic block diagram of the electrical wiring of the organic electroluminescent display apparatus of FIG. It is a schematic sectional drawing which shows a part of X-ray sensor array of embodiment. It is a schematic block diagram of the electrical wiring of the X-ray sensor array of FIG. FIG. 3 is a diagram illustrating a composition range of a first region in an oxide semiconductor layer of a thin film transistor of the present invention, and a composition and mobility of the first region in an oxide semiconductor layer of an example and a comparative example, using a ternary phase diagram method. .

  Hereinafter, with reference to the attached drawings, a thin film transistor and a manufacturing method thereof according to an embodiment of the present invention, and a display device, a sensor, and an X-ray sensor (digital imaging device) including the thin film transistor according to the embodiment of the present invention will be specifically described. I will explain it. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals and description thereof is omitted as appropriate.

<Thin film transistor>
The thin film transistor of the present invention (referred to as “TFT” as appropriate) has a function of switching a current between a source electrode and a drain electrode by applying a voltage to a gate electrode and controlling a current flowing in an oxide semiconductor layer. A gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode, and the oxide semiconductor layer is In _(a) Ga _(b) Zn _(c) O _(d) (A> 0, b ≧ 0, c> 0, d> 0, and a first region having a composition represented by a + b + c = 1 and satisfying b ≦ 91a / 74−17 / 40, and the first region In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0, and e + f + g = 1) And satisfies f / (e + f) ≧ 0.80, and the first region The thin film transistor includes a second region having a composition different from the composition.

  In general, in the case of a stacked thin film transistor having an active layer as a stacked structure, carriers flow into a region having a high electron affinity from a region having a low electron affinity due to the magnitude relationship of the electron affinity of each region. When carrier inflow into the first region relatively close to the gate electrode occurs, a parasitic conduction path may be formed in addition to the main channel path generated at the interface between the first region and the gate insulating film. . The presence of such parasitic conduction causes a hump effect in the Vg-Id characteristic and deteriorates the On / Off ratio. In addition, if the number of carriers in the parasitic conduction path increases due to light irradiation, or the carriers photoexcited in another layer are trapped near the parasitic conduction path, the off-current increases and the rising voltage of the current in the transistor shifts. Cause light instability.

On the other hand, the thin film transistor of the present invention is a stacked thin film transistor having first and second oxide semiconductor regions, and the first region close to the gate electrode is composed of an IGZO layer or an IZO layer having a specific composition, The second region located farther than the first region with respect to the electrode is composed of an IGZO layer and has a Ga content (atomic ratio In: Ga: Zn so as to satisfy Ga / (In + Ga) ≧ 0.80. = 0.4: 1.6: 1), high light stability is realized while suppressing the hamp effect.
In the thin film transistor of the present invention, even if carrier inflow from the second region to the first region occurs, the carrier concentration in the second region is kept extremely low because the Ga content in the second region is increased. In the case where the present inventors confirmed by hole measurement, the carrier concentration of the second region is 1.0 × 10 ¹⁴ cm ⁻³ or less. Therefore, the formation of a parasitic conduction path into the first region due to carrier inflow is suppressed. Therefore, in the TFT of the present invention, an increase in off current and a change in rising voltage due to light irradiation can be suppressed, and high light stability can be realized.

  Embodiments of the present invention will be described below with reference to the drawings. The TFT shown in FIGS. 1 and 2 will be specifically described as a representative example, but the present invention can also be applied to TFTs of other forms (structures).

The element structure of the TFT of the present invention may be either a so-called bottom gate type (also referred to as an inverted staggered structure) or a top gate type (also referred to as a staggered structure) based on the position of the gate electrode. The top gate type is a form in which a gate electrode is disposed on the upper side of the gate insulating film and an active layer is formed on the lower side of the gate insulating film when the substrate on which the TFT is formed is the lowermost layer. The bottom gate type is a form in which a gate electrode is disposed below the gate insulating film and an active layer is formed above the gate insulating film.
Further, based on a contact portion between the oxide semiconductor layer and the source and drain electrodes (referred to as “source / drain electrodes” as appropriate), either a so-called top contact type or bottom contact type may be employed. The bottom contact type is a mode in which the source / drain electrodes are formed before the active layer and the lower surface of the active layer is in contact with the source / drain electrodes. The top contact type is a mode in which the active layer is more than the source / drain electrodes. In this embodiment, the upper surface of the active layer is in contact with the source / drain electrodes.
In addition to the above, the TFT according to the present invention can have various configurations, and may appropriately have a configuration including a protective layer on the active layer and an insulating layer on the substrate.

FIG. 1 is a sectional view schematically showing the configuration of a thin film transistor 1 according to the first embodiment of the present invention, and FIG. 2 is a schematic view showing the configuration of the thin film transistor 2 according to the second embodiment of the present invention. In each thin-film transistor 1 and 2 of FIG. 1 and FIG. 2, the same code | symbol is attached | subjected to the common element.
The thin film transistor 1 of the first embodiment shown in FIG. 1 is a bottom gate-top contact type transistor, and the thin film transistor 2 of the second embodiment shown in FIG. 2 is a top gate-bottom contact type transistor. In the embodiment shown in FIGS. 1 and 2, the arrangement of the gate electrode 16, the source electrode 13, and the drain electrode 14 with respect to the oxide semiconductor layer 12 is different, but the function of each element given the same reference numeral is the same. Similar materials can be applied.

The thin film transistors 1 and 2 according to the embodiment of the present invention include a gate electrode 16, a gate insulating film 15, an oxide semiconductor layer 12, a source electrode 13, and a drain electrode 14, and the oxide semiconductor layer 12 includes The first region A1 and the second region A2 are provided from the side closer to the gate electrode 16 in the film thickness direction. The first region A1 and the second region A2 constituting the oxide semiconductor layer 12 are continuously formed, and an insulating layer, an electrode layer, or the like is provided between the first region A1 and the second region A2. Layers other than the oxide semiconductor layer are not interposed, and are formed of an oxide semiconductor film.
Hereinafter, each component including the substrate on which the TFTs 1 and 2 of the present invention are formed will be described in detail.

(substrate)
There is no restriction | limiting in particular about the shape of the board | substrate 11 for forming the thin-film transistor of this invention, a magnitude | size, etc., According to the objective, it can select suitably. The structure of the substrate 11 may be a single layer structure or a laminated structure.
For example, a substrate made of an inorganic material such as glass or YSZ (yttrium stabilized zirconium), a resin, a resin composite material, or the like can be used. Among these, a substrate made of a resin or a resin composite material is preferable in terms of light weight and flexibility. Specifically, polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polybutylene naphthalate, polystyrene, polycarbonate, polysulfone, polyethersulfone, polyarylate, allyl diglycol carbonate, polyamide, polyimide, polyamideimide, polyetherimide, Fluorine resin such as polybenzazole, polyphenylene sulfide, polycycloolefin, norbornene resin, polychlorotrifluoroethylene, liquid crystal polymer, acrylic resin, epoxy resin, silicone resin, ionomer resin, cyanate resin, crosslinked fumaric acid diester, cyclic polyolefin, A substrate made of synthetic resin such as aromatic ether, maleimide-olefin, cellulose, episulfide compound, etc. It is below.

  Also, a substrate made of a composite plastic material of the aforementioned synthetic resin or the like and silicon oxide particles, or a composite plastic material of the aforementioned synthetic resin or the like and the metal nanoparticles, inorganic oxide nanoparticles or inorganic nitride nanoparticles, etc. A substrate made of a composite plastic material of the above-mentioned synthetic resin and the like and carbon fiber or carbon nanotube, a substrate made of a composite plastic material of the above-mentioned synthetic resin and the glass fake, glass fiber or glass bead, A substrate made of a composite plastic material of the above-described synthetic resin and the like and a clay mineral or particles having a mica-derived crystal structure, and a laminated plastic having at least one bonding interface between the thin glass and any of the above-described synthetic resins By laminating the substrate, inorganic layer and organic layer (the aforementioned synthetic resin) alternately, at least once Insulating the surface by subjecting a substrate made of a composite material having a barrier interface to the above, a stainless steel substrate, a metal multilayer substrate in which stainless steel and a dissimilar metal are laminated, an aluminum substrate or a surface to an oxidation treatment (for example, anodizing treatment) An aluminum substrate with an oxide film with improved properties can be used.

  The resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like. The resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion with the lower electrode, and the like.

  The thickness of the substrate 11 is preferably 50 μm or more and 500 μm or less when a flexible substrate is used. When the thickness of the substrate 11 is 50 μm or more, the flatness of the substrate itself is further improved. When the thickness of the substrate 11 is 500 μm or less, the flexibility of the substrate itself is further improved and the use as a substrate for a flexible device becomes easier. In addition, since the thickness which has sufficient flatness and flexibility changes with the materials which comprise the board | substrate 11, it is necessary to set the thickness according to board | substrate material, but the range is the range of 50 micrometers-500 micrometers in general. is there.

(Oxide semiconductor layer)
The oxide semiconductor layer 12 includes a first region A1 (referred to as “A1 layer” as appropriate) and a second region A2 (referred to as “A2 layer” as appropriate) from the order close to the gate electrode 16. The gate electrode 16 is disposed opposite to the gate insulating film 15. The first region A1 is represented by In _(a) Ga _(b) Zn _(c) O _(d) (a> 0, b ≧ 0, c> 0, d> 0, and a + b + c = 1). It is an IGZO layer or an IZO layer having a composition satisfying b ≦ 91a / 74-17 / 40. On the other hand, the second region A2 located on the side farther than the first region A1 with respect to the gate electrode 16, that is, on the side opposite to the surface in contact with the gate insulating film 15 of the first region A1, is In _{(e )} Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0, and e + f + g = 1), and f / (e + f) ≧ 0.80 An IGZO layer that fills and has a different composition from the first region A1.

-First region-
The first region A1 is represented by In _(a) Ga _(b) Zn _(c) O _(d) (a> 0, b ≧ 0, c> 0, d> 0, a + b + c = 1), and b ≦ It is an IGZO layer (when b> 0) or an IZO layer (when b = 0) having a composition satisfying 91a / 74-17 / 40.

-The first region is the IGZO layer-
When the composition of the first region A1 is b> 0, that is, an IGZO layer, c ≦ 3/5, b> 0, b ≧ 3a / 7-3 / 14, b ≧ 9a / 5−53 / 50, It is desirable that the composition range is b ≦ −8a / 5 + 33/25 and b ≦ 91a / 74−17 / 40 (where a + b + c = 1). In such a composition region, since the first region A1 has a higher electron affinity than the second region A2, the conduction channel is formed in the first region A1. Since the carrier mobility is also high in the composition region, a high mobility exceeding 20 cm ² / Vs is also realized.

  Note that since the film of the composition of the first region A1 having the above composition also has a high carrier concentration, when the film of the first region A1 alone is used as an active layer, sufficiently low off-current and switching characteristics can be obtained. Have difficulty.

The first region A1 is b ≦ 17a / 23−28 / 115, b ≧ 3a / 37, b ≧ 9a / 5−53 / 50, b ≦ 1/5 (provided that a + b + c = 1). It is desirable. If the composition of the first region A1 is within the composition range, a field-effect mobility of more than 30 cm ² / Vs can be realized.

-The first region is the IZO layer-
When the composition of the first region A1 is b = 0, that is, an IZO layer, the composition of the first region A1 is preferably in the composition range of 0.4 ≦ a ≦ 0.75. In such a composition range, since the first region A1 has a higher electron affinity than the second region A2, the conduction channel in the stacked thin film transistor is formed in the first region A1. In the region A1 having the above composition, the carrier mobility is also high, so that a high mobility exceeding 30 cm ² / Vs is also realized.

Furthermore, it is desirable that the first region A1 is in the composition range represented by 0.4 ≦ a ≦ 0.5. If it exists in the said composition range, the field effect mobility over 30 cm < ² > / Vs and normally-off (Id in Vg = 0V are 1 * 10 < ^-9 > A or less) can also be made compatible.

The thickness of the first region A1 is desirably less than 10 nm. For the first region A1, it is preferable to use an IZO film that can easily achieve high mobility or an extremely in-rich IGZO film. However, since such a high mobility film has a high carrier concentration, it has a large threshold value and a negative side. There is a possibility to shift to. If the thickness of the first region A1 is 10 nm or more, the total carrier concentration in the active layer is excessive, and pinch-off becomes difficult.
On the other hand, the thickness of the first region A1 is preferably 5 nm or more from the viewpoint of obtaining uniformity and high mobility of the oxide semiconductor layer 12.

-Second region-
The second region A2 of the oxide semiconductor layer 12 is located on the side farther than the first region A1 with respect to the gate electrode 16, that is, on the side opposite to the surface in contact with the gate insulating film 15 of the first region A1. In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0, and e + f + g = 1), and f / (e + f) An IGZO layer satisfying ≧ 0.80 and having a composition different from that of the first region A1.

  Since the second region A2 is an IGZO layer having an extremely high Ga content with respect to In, it is possible to suppress the inflow of carriers into the first region A1 and the formation of the parasitic conduction path associated therewith, and thus high light stability. Can be realized.

  The thickness of the second region A2 is desirably 30 nm or more. If the thickness of the second region A2 is 30 nm or more, a reduction in off-current can be expected more reliably. On the other hand, if the thickness of the second region A2 is 10 nm or less, there is a risk of increasing the off-current or degrading the S value. The thickness of the second region A2 is preferably less than 70 nm. If the thickness of the second region is 70 nm or more, a reduction in off-current can be expected, but the resistance between the source / drain electrode layer and the first region A1 increases, resulting in a decrease in mobility. There is a risk of inviting. Accordingly, the thickness of the second region A2 is desirably more than 10 nm and less than 70 nm.

-Whole oxide semiconductor layer-
The film thickness (total film thickness) of the entire oxide semiconductor layer 12 is preferably about 10 to 200 nm, more preferably 35 nm or more and less than 80 nm, from the viewpoint of film uniformity and patterning properties.

The oxide semiconductor layer 12 (the first region A1 and the second region A2) is preferably amorphous. If the first and second regions A1 and A2 are amorphous films, there is no crystal grain boundary and a highly uniform film can be obtained.
Note that whether or not the laminated film composed of the first and second regions A1 and A2 is amorphous can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, it can be determined that the laminated film is amorphous.

The carrier concentration of the oxide semiconductor layer 12 can be controlled not only by the composition modulation of the regions A1 and A2, but also by the oxygen partial pressure control during film formation.
Specifically, the oxygen concentration can be controlled by controlling the oxygen partial pressure during film formation in the first and second regions A1 and A2. If the oxygen partial pressure at the time of film formation is increased, the carrier concentration can be reduced, and a reduction in off-current can be expected accordingly. On the other hand, if the oxygen partial pressure during film formation is lowered, the carrier concentration can be increased, and accordingly, the field effect mobility can be expected to increase. Further, for example, by performing a treatment of irradiating oxygen radicals or ozone after forming the first region A1, it is possible to promote the oxidation of the film and reduce the amount of oxygen vacancies in the first region A1. .

  Further, by doping a part of Zn of the oxide semiconductor layer 12 composed of the first and second regions A1 and A2 with element ions having a wider band gap, the light irradiation stability accompanying the increase of the optical band gap can be improved. Can be granted. Specifically, the band gap of the film can be increased by doping Mg. For example, by doping Mg in each region of the A1 layer and A2 layer, the band gap can be increased while maintaining the band profile of the laminated film, compared to a system in which the composition ratio of only In, Ga, and Zn is controlled. It is.

  Since the blue light-emitting layer used in organic EL exhibits broad light emission having a peak at about λ = 450 nm, if the optical band gap of the IGZO film is relatively narrow and the region has optical absorption, A threshold shift occurs. Therefore, it is preferable that the material used for the channel layer has a larger band gap, particularly for a thin film transistor used for driving an organic EL.

  Further, the carrier density in each of the first and second regions A1 and A2 can be arbitrarily controlled by cation doping. In order to increase the carrier density, a material that easily becomes a cation having a relatively large valence (eg, Ti, Ta, etc.) may be doped. However, when doping a cation having a large valence, the number of constituent elements of the oxide semiconductor film increases, which is disadvantageous in terms of simplifying the film formation process and reducing the cost. ) To control the carrier density.

(Source / drain electrodes)
The source electrode 13 and the drain electrode 14 are not particularly limited with respect to materials and structures as long as they have high conductivity. For example, metal such as Al, Mo, Cr, Ta, Ti, Au, Ag, metal oxide conductive such as Al-Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), etc. The source / drain electrodes 13 and 14 can be formed as a single layer or a laminated structure of two or more layers such as a film.

  When the source electrode 13 and the drain electrode 14 are made of the metal or metal oxide, the thickness is 10 nm or more and 1000 nm or less in consideration of the film forming property, the patterning property by etching or lift-off method, the conductivity, and the like. It is preferable to set it to 50 nm or more and 100 nm or less.

(Gate insulation film)
The gate insulating film 15 is a layer that separates the gate electrode 16 from the oxide semiconductor 12 and the source / drain electrodes 13 and 14, and has a high insulating property. For example, SiO ₂ , SiNx, An insulating film such as SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , HfO _2, or an insulating film containing two or more of these compounds can be used.

  Note that the gate insulating film 15 needs to have a sufficient thickness in order to reduce leakage current and improve voltage resistance. On the other hand, if the thickness is too large, the drive voltage increases. Although depending on the material, the thickness of the gate insulating film 15 is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.

(Gate electrode)
The gate electrode 16 is not particularly limited as long as it has high conductivity. For example, metal such as Al, Mo, Cr, Ta, Ti, Au, Ag, metal oxide conductive such as Al-Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), etc. A gate electrode can be formed using a single layer or a stacked structure of two or more layers such as a film.

  When the gate electrode 16 is composed of the above metal or metal oxide, the thickness is preferably 10 nm or more and 1000 nm or less in consideration of film forming property, patterning property by etching or lift-off method, conductivity, and the like. 50 nm or more and 200 nm or less is more preferable.

<Method for Manufacturing Thin Film Transistor>
Next, a manufacturing method of the bottom gate-top contact type thin film transistor 1 shown in FIG. 1 will be described. In addition, each constituent material, thickness, etc. are as described above, and will be omitted in the following description to avoid duplication.

(Formation of gate electrode)
First, the substrate 11 is prepared, and a layer other than the thin film transistor 1 is formed on the substrate 11 as necessary, and then the gate electrode 16 is formed.
The gate electrode 16 is a material used from, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of the suitability of For example, after the electrode film is formed, the gate electrode 16 is formed by patterning into a predetermined shape by etching or a lift-off method. At this time, it is preferable to pattern the gate electrode 16 and the gate wiring simultaneously.

(Formation of gate insulating film)
After forming the gate electrode 16, the gate insulating film 15 is formed.
The gate insulating film 15 is a material used from a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as a CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of the suitability of For example, the gate insulating film 15 may be patterned into a predetermined shape by photolithography and etching.

(Formation of oxide semiconductor layer)
Next, the oxide region 12 is formed in the order of the first region A1 and the second region A2 at a position facing the gate electrode 16 on the gate insulating film 15.
A method for forming the first and second regions A1 and A2 constituting the oxide semiconductor layer 12 is not particularly limited, but it is preferable to form the film by a sputtering method. The sputtering method has a high deposition rate and can form a highly uniform film; therefore, an oxide semiconductor film with a large area can be formed at low cost. When forming a film by sputtering, for example, when forming an IGZO film, a complex oxide target that has been adjusted in advance to have a desired cation composition may be used, or In ₂ O ₃ , Ga ₂ O ₃ , ZnO ternary co-sputtering may be used.
The substrate temperature during film formation may be arbitrarily selected according to the substrate, but when a resin flexible substrate is used, the substrate temperature is preferably closer to room temperature in order to prevent deformation of the substrate.

In the case where the first region A1 is an IGZO-based oxide semiconductor, for example, In _(a) Ga _(b) Zn _(c) O _(d) , (c ≦ _3/5) B> 0, b ≧ 3a / 7-3 / 14, b ≧ 9a / 5−53 / 50, b ≦ −8a / 5 + 33/25, b ≦ 91a / 74−17 / 40 (provided that a + b + c = 1) )) And a region farther from the gate electrode 16 than the first region A1, and represented by In _(e) Ga _(f) Zn _(g) O _(h) , A second region A2 satisfying f / (e + f) ≧ 0.80 and having a composition different from that of the first region A1 is formed.

On the other hand, in the case where the first region A1 is an IZO-based oxide semiconductor, the oxide semiconductor layer 12 is formed of, for example, In _(a) Zn _(c) O _(d) , (a> 0, c> 0). , A + c = 1, preferably 0.4 ≦ a ≦ 0.75), and arranged on the side farther from the gate electrode 16 than the first region A1, and In _(e) Ga _{(F) A} second region A2 represented by Zn _(g) O _(h) , satisfying f / (e + f) ≧ 0.80, and having a composition different from that of the first region A1, is formed.

Note that the film formation in the second region A2 is temporarily stopped after the film formation in the first region A1, and after the oxygen partial pressure in the film formation chamber and the power applied to the target are changed, the film formation is resumed. Alternatively, the oxygen partial pressure in the deposition chamber and the power applied to the target may be changed quickly or slowly without stopping the deposition.
Further, the target may be a method of changing the input power by using the target used at the time of film formation in the first area A1, or switching the film formation from the first area A1 to the second area A2. At this time, a method may be used in which power supply to the target used for film formation in the first region A1 is stopped and power is applied to different targets including In, Ga, and Zn, or the first region A1. In addition to the target used for the film formation, a method of additionally applying power to a plurality of targets may be used.
The substrate temperature at the time of forming the second region A2 may be arbitrarily selected according to the substrate, but when a resin flexible substrate is used, as in the case of forming the first region A1, The substrate temperature is preferably closer to room temperature.

When the regions A1 and A2 are formed by sputtering, the oxide semiconductor layer 12 is preferably formed continuously without being exposed to the atmosphere. By forming the oxide semiconductor layer 12 without exposing it to the air, impurities can be prevented from being mixed between the regions A1 and A2, and as a result, more excellent transistor characteristics can be obtained. In addition, since the number of film forming steps can be reduced, the manufacturing cost can also be reduced.
Note that in this embodiment, when the bottom-gate thin film transistor 1 is manufactured, the oxide semiconductor layer 12 is formed in the order of the first region A1 and the second region A2, and the top-gate type thin film transistor 1 shown in FIG. When the thin film transistor 2 is manufactured, the second region A2 and the first region A1 may be formed in this order.

(Post annealing)
After forming oxide films to be the first and second regions A1 and A2, it is preferable to perform heat treatment (post-annealing) at 300 ° C. or higher in an oxidizing atmosphere, and more preferably 400 ° C. or higher. . When the heat treatment temperature is 400 ° C. or higher, the light irradiation stability can be extremely increased (for example, | ΔVth | ≦ 0.1 V for light irradiation of 420 nm).
On the other hand, when heat treatment is performed at a temperature of 600 ° C. or higher, cation mutual diffusion occurs between the first region A1 and the second region A2, and the two regions cross each other. In this case, it is difficult to concentrate conductive carriers only in the first region A1. Therefore, it is desirable that the heat treatment temperature in the post-annealing step is less than 600 ° C. Note that whether or not cation mutual diffusion occurs in the first region A1 and the second region A2 can be confirmed, for example, by performing analysis by cross-sectional TEM.

  FIG. 3 is a cross-sectional STEM image of a laminated film in which five layers of an IGZO film with Ga / (In + Ga) = 0.75 and an IGZO film with Ga / (In + Ga) = 0.25 are laminated. Immediately after stacking (before annealing treatment), the figure (right) shows that the annealing temperature is 600 ° C. Although it can be confirmed from FIG. 3 that the laminated structure of the IGZO film maintains the laminated structure to some extent even when annealed at 600 ° C., it can be seen that the contrast is blurred at the interface of different cation compositions. This suggests that heterogeneous interdiffusion has begun to occur, and the upper limit temperature in the heat treatment step is desirably 600 ° C. or lower.

Further, in the method for manufacturing a thin film transistor of the present invention, it is desirable to anneal in a dry atmosphere in which the moisture content contained in the entire atmosphere is −36 ° C. or less (absolute humidity 0.21 g / m ⁻³ or less) in terms of dew point temperature. . By performing the annealing in such a dry atmosphere, the light stability can be improved as compared with the case of performing the annealing in a wet atmosphere (for example, in the air).

  Next, the oxide semiconductor layer 12 is patterned. Patterning can be performed by photolithography and etching. Specifically, an oxide semiconductor layer is formed by forming a resist pattern on the remaining portion by photolithography and etching the exposed portion with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid, and acetic acid. Twelve patterns are formed.

(Formation of source / drain electrodes)
Next, a metal film for forming the source / drain electrodes 13 and 14 is formed on the oxide semiconductor layer 12.
Each of the source electrode 13 and the drain electrode 14 is, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as CVD or a plasma CVD method, or the like. The film may be formed according to a method appropriately selected in consideration of suitability with the material to be used.
For example, the metal film is patterned into a predetermined shape by etching or a lift-off method, and the source electrode 13 and the drain electrode 14 are formed. At this time, it is preferable to pattern the source / drain electrodes 13 and 14 and the wiring (not shown) connected to these electrodes 13 and 14 simultaneously.
Through the above procedure, the thin film transistor 1 illustrated in FIG. 1 can be manufactured.

By using the method of manufacturing a thin film transistor of the present invention, high mobility and high light irradiation stability can be obtained without using a protective layer or the like on the active layer for reducing characteristic deterioration against light irradiation. A protective layer as described above may be provided on the active layer. For example, by providing a protective layer that absorbs and reflects light in the ultraviolet region (wavelength 400 nm or less), the stability against light irradiation can be further improved.

  The thin film transistor of the present invention has high light irradiation stability while suppressing the hamp effect, and can be applied to various devices. Both the display device and the sensor of the present invention using the thin film transistor of the present invention exhibit good characteristics due to low power consumption. The “characteristic” referred to here is a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.

<Liquid crystal display device>
FIG. 7 shows a schematic sectional view of a part of a liquid crystal display device which is an embodiment of a display device including the thin film transistor of the present invention, and FIG. 8 shows a schematic configuration diagram of the electric wiring.

  As shown in FIG. 7, the liquid crystal display device 5 of this embodiment includes a top gate-bottom contact type thin film transistor 2 shown in FIG. 2 and a pixel lower portion on the gate electrode 16 protected by the passivation layer 54 of the thin film transistor 2. A liquid crystal layer 57 sandwiched between the electrode 55 and the opposed upper electrode 56 and an RGB color filter 58 for developing different colors corresponding to each pixel are provided, respectively on the substrate 11 side and the color filter 58 of the TFT 2. In this configuration, polarizing plates 59a and 59b are provided.

  As shown in FIG. 8, the liquid crystal display device 5 of this embodiment includes a plurality of gate lines 51 that are parallel to each other and data lines 52 that are parallel to each other and intersect the gate lines 51. Here, the gate wiring 51 and the data wiring 52 are electrically insulated. The thin film transistor 2 is provided in the vicinity of the intersection between the gate line 51 and the data line 52.

  The gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 51, and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 52. The drain electrode 14 of the thin film transistor 2 is electrically connected to the pixel lower electrode 55 through a contact hole 19 provided in the gate insulating film 15 (a conductor is embedded in the contact hole 19). The pixel lower electrode 55 and the grounded counter electrode 56 constitute a capacitor 53.

  In the liquid crystal device of this embodiment shown in FIG. 7, the top gate type thin film transistor is provided. However, the thin film transistor used in the liquid crystal device which is the display device of the present invention is not limited to the top gate type, A bottom-gate thin film transistor may be used.

  Since the thin film transistor of the present invention has high mobility, high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen. In particular, when the active layer (oxide semiconductor layer) 12 is amorphous, variations in device characteristics can be suppressed, and an excellent display quality with a large screen and no unevenness can be realized. In addition, since the characteristic shift is small, the gate voltage can be reduced, and thus the power consumption of the display device can be reduced.

<Organic EL display device>
As an embodiment of the display device including the TFT of the present invention, FIG. 9 shows a schematic sectional view of a part of an active matrix type organic EL display device, and FIG. 10 shows a schematic configuration diagram of electrical wiring.
There are two types of driving methods for organic EL display devices: a simple matrix method and an active matrix method. The simple matrix method has an advantage that it can be manufactured at low cost. However, since the pixels are emitted by selecting one scanning line at a time, the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size. The active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel. However, since there is no problem that the number of scanning lines cannot be increased unlike the simple matrix method, it is suitable for high definition and large screen.

  In the active matrix type organic EL display device 6 of this embodiment, a top gate-top contact type thin film transistor is provided as a driving TFT 2a and a switching TFT 2b on a substrate 60 provided with a passivation layer 61a. On the thin film transistors 2a and 2b, an organic light emitting element 65 comprising an organic light emitting layer 64 sandwiched between a lower electrode 62 and an upper electrode 63 is provided, and the upper surface is also protected by a passivation layer 61b.

  As shown in FIG. 9, the organic EL display device 6 of the present embodiment includes a plurality of gate wirings 66 that are parallel to each other, and a data wiring 67 and a driving wiring 68 that are parallel to each other and intersect the gate wiring 66. I have. Here, the gate wiring 66, the data wiring 67, and the driving wiring 68 are electrically insulated. The gate electrode 16 a of the switching thin film transistor 2 b is connected to the gate line 66, and the source electrode 13 b of the switching thin film transistor 2 b is connected to the data line 67. The drain electrode 14b of the switching thin film transistor 2b is connected to the gate electrode 16a of the driving thin film transistor 2a, and the driving thin film transistor 2a is kept on by using the capacitor 69. The source electrode 13 a of the driving thin film transistor 2 a is connected to the driving wiring 68, and the drain electrode 14 a is connected to the organic EL light emitting element 65.

  The organic EL device of this embodiment shown in FIG. 9 also includes the top gate type thin film transistors 2a and 2b. However, the thin film transistor used in the organic EL device which is the display device of the present invention is a top gate type. Without limitation, a bottom-gate thin film transistor may be used.

  Since the thin film transistor of the present invention has high mobility, display with low power consumption and high quality is possible. Therefore, according to the present invention, a flexible organic EL display device having excellent display quality can be provided.

  In the organic EL display device shown in FIG. 9, the top electrode 63 may be a top emission type with a transparent electrode, or the bottom electrode 62 and each electrode of the TFTs 2a and 2b may be a transparent electrode. Good.

<X-ray sensor>
FIG. 11 shows a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention, and FIG. 12 shows a schematic configuration diagram of the electric wiring.
The X-ray sensor 7 of this embodiment includes a thin film transistor 2 and a capacitor 70 formed on a substrate 11, a charge collection electrode 71 formed on the capacitor 70, an X-ray conversion layer 72, and an upper electrode 73. Configured. A passivation film 75 is provided on the thin film transistor 2.

  The capacitor 70 has a structure in which an insulating film 78 is sandwiched between a capacitor lower electrode 76 and a capacitor upper electrode 77. The capacitor upper electrode 77 is connected to one of the source electrode 13 and the drain electrode 14 (the drain electrode 14 in FIG. 11) of the thin film transistor 2 through a contact hole 79 provided in the insulating film 78.

  The charge collection electrode 71 is provided on the capacitor upper electrode 77 in the capacitor 70 and is in contact with the capacitor upper electrode 77. The X-ray conversion layer 72 is a layer made of amorphous selenium and is provided so as to cover the thin film transistor 2 and the capacitor 70. The upper electrode 73 is provided on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72.

  As shown in FIG. 12, the X-ray sensor 7 of this embodiment includes a plurality of gate wirings 81 that are parallel to each other and a plurality of data wirings 82 that intersect with the gate wirings 81 and are parallel to each other. Here, the gate wiring 81 and the data wiring 82 are electrically insulated. The thin film transistor 2 is provided in the vicinity of the intersection between the gate line 81 and the data line 82.

  The gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 81, and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 82. The drain electrode 14 of the thin film transistor 2 is connected to the charge collecting electrode 71, and the charge collecting electrode 71 constitutes a capacitor 70 together with the grounded counter electrode 76.

  In the X-ray sensor 7 of this configuration, X-rays are irradiated from the upper part (upper electrode 73 side) in FIG. 11, and electron-hole pairs are generated in the X-ray conversion layer 72. By applying a high electric field to the X-ray conversion layer 72 by the upper electrode 73, the generated charges are accumulated in the capacitor 70 and read out by sequentially scanning the thin film transistor 2.

Since the X-ray sensor of the present invention includes the thin film transistor 2 having a high on-current and excellent reliability, the S / N is high and the sensitivity characteristic is excellent. Therefore, the X-ray sensor has a wide dynamic when used in an X-ray digital imaging apparatus. A range image is obtained.
In particular, the X-ray digital imaging apparatus of the present invention is suitable not only for still image shooting but also for an X-ray digital imaging apparatus that can perform fluoroscopy with a moving image and still image shooting. Further, when the first region A1 and the second region A2 constituting the active layer in the thin film transistor 2 are amorphous, an image with excellent uniformity can be obtained.

  The X-ray sensor of this embodiment shown in FIG. 11 is provided with a top gate type thin film transistor. However, the thin film transistor used in the sensor of the present invention is not limited to the top gate type, and the bottom gate type. A thin film transistor may be used.

Experimental examples are described below, but the present invention is not limited to these examples.
The present inventors can achieve both high light irradiation stability (| ΔVth | ≦ 1 V (with respect to light irradiation of 420 nm)) while suppressing the hamp effect by stacking oxide semiconductors having a specific composition. Was verified using the following experiment.

<A2 layer composition dependency of TFT characteristics>
It was verified by fabricating a TFT having the following structure that high light stability can be obtained by stacking an oxide semiconductor film having a specific composition in an active layer of a thin film transistor.
First, the following bottom gate and top contact type thin film transistors were fabricated.

As the substrate, a highly doped p-type silicon substrate (manufactured by Mitsubishi Materials Corporation) having a SiO ₂ oxide film of 100 nm formed on the surface thereof was used.

  Next, as described later, a first region (A1 layer) and a second region (A2 layer) were sequentially stacked on the p-type silicon substrate as an oxide semiconductor layer. Sputtering conditions other than the composition of each region are as follows, and are common in the subsequent experiments.

(Sputtering conditions for the first region A1)
Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature; room temperature, oxygen partial pressure / argon partial pressure; 0.067

(Sputtering conditions for the second region A2)
Ultimate vacuum: 6 × 10 ⁻⁶ Pa
Deposition pressure: 4.4 × 10 ⁻¹ Pa
Deposition temperature; room temperature, oxygen partial pressure / argon partial pressure; 0.033

  After the formation of the oxide semiconductor layer by sputtering, an electrode layer made of Ti (10 nm) / Au (40 nm) was formed on the laminated film by sputtering using a metal mask. After the electrode layer was formed, post-annealing was performed in an atmosphere of 400 ° C. and oxygen partial pressure of 100%.

  As described above, TFTs of Examples 1 to 15, Examples A to C, and Comparative Examples 1 to 4 were obtained as bottom-gate thin film transistors having a channel length of 180 μm and a channel width of 1 mm, and the following evaluations were performed.

[Mobility]
Using the semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies), the transistor characteristics (Vg-Id characteristics) and the mobility μ were measured for the TFTs of Examples 1 to 15, A and B and Comparative Examples 1 to 4 that were produced. went.
Vg-Id characteristics are measured by fixing the drain voltage (Vd) to 10 V, sweeping the gate voltage (Vg) within the range of -30 V to +30 V, and measuring the drain current (Id) at each gate voltage (Vg). I went to do it. The off current was defined as a current value at Vg = 0 V in the Vg-Id characteristic.
The mobility is linear mobility from the Vg-Id characteristic in the linear region obtained by sweeping the gate voltage (Vg) in the range of -30V to + 30V with the drain voltage (Vd) fixed at 1V. Is calculated and written.

[Light irradiation stability]
After evaluating the Vg-Id characteristics of the fabricated TFTs, the stability of the TFT characteristics against light irradiation was evaluated by irradiating wavelength-variable monochrome light. FIG. 4 shows an outline of TFT characteristic measurement under monochromatic light irradiation. As shown in FIG. 4, each TFT was placed on the probe stage stage 200, and after flowing dry air for 2 hours or more, TFT characteristics were measured under the dry air atmosphere. The irradiation intensity of the monochrome light source is 10 μW / cm ² , the wavelength λ is in the range of 360 to 700 nm, and the light irradiation is performed by comparing the Vg-Id characteristics when the monochrome light is not irradiated and the Vg-Id characteristics when the monochrome light is irradiated. Stability (ΔVth) was evaluated. The measurement conditions for TFT characteristics under monochrome light irradiation were fixed at Vds = 10 V and measured by sweeping the gate voltage in the range of Vg = -15 to 15V. Unless otherwise specified below, all measurements are performed after irradiating with monochromatic light for 10 minutes. The threshold shift amount ΔVth for light irradiation of 420 nm was used as an indicator of the light stability of the TFT.

(When the first region is IGZO)
In the oxide semiconductor layer, first, as the first region A1, In _(a) Ga _(b) Zn _(c) O _(d) (a = 37/60, b = 3/60, c = 20/60, d> 0) was sputtered with a thickness of 5 nm.
In the state where the composition of the A1 layer is fixed, the A2 layer is represented by In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0). An IGZO layer having a thickness of 50 nm was formed by sputtering. The composition of the A2 layer was modulated as shown in Table 2 below. The oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere. Sputtering of each region A1, A2 was performed using ternary co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target. The film thickness adjustment of each region A1, A2 was performed by adjusting the film formation time.
The sputtering conditions of the second region (A2 layer) and the characteristics of the fabricated TFT are shown in Table 2 below.

FIG. 5 shows the IV characteristics of the TFTs of Examples 1 to 3 and Comparative Example 1 when irradiated with monochrome light (wavelength: 420 nm). In addition, the said evaluation method is common in a following example.
From FIG. 5, it can be seen that in the case of Comparative Example 1 where f / (e + f) = 0.75, the hump effect in which bumps appear in the IV characteristics is remarkable due to the influence of the parasitic conduction path. On the other hand, in the case of Example 1-3 in which f / (e + f) ≧ 0.80, it can be seen that the hump effect is suppressed.

  FIG. 6 shows the Vg-Id characteristics of the TFT manufactured in Example 3 under monochromatic light irradiation in the range of 360 to 700 nm. As can be seen from FIG. 6, in the TFT of Example 3, the hamp effect is suppressed regardless of the wavelength of light irradiation, and the threshold shift (ΔVth) is small.

(When the first region is an IZO system)
As the first region A1, In _(a) Zn _(c) O _(d) , (a = 0.5, c = 0.5, d> 0) was formed by sputtering with a thickness of 5 nm. In the state where the composition of the A1 layer is fixed, as the A2 layer, In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0), The represented IGZO layer was formed by sputtering with a thickness of 50 nm. The composition of the A2 layer was modulated as shown in Table 2 below. The oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere. Sputtering of each region was performed by ternary co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target in the regions A1 and A2. The film thickness in each region was adjusted by adjusting the film formation time.
The sputtering conditions of the second region (A2 layer) and the characteristics of the fabricated TFT are shown in Table 3 below.

Table 2 summarizes TFT characteristics when the first region is an IGZO system. In Example 1-3, the mobility is more than 20 cm ² / Vs, and the threshold shift amount with respect to light irradiation of 420 nm is used. Are 0.1 V or less, and the results are extremely light stable.
Further, Table 3 shows the results when the first region is the IZO system, but the same results as in the IGZO system were obtained.
Therefore, when the composition of the A1 layer is fixed, it can be seen from the above examples that the ham effect can be suppressed by controlling the composition of the A2 layer, and as a result, both high mobility and light stability can be achieved.

<A1 layer composition dependency of TFT characteristics>
(When the first region is IGZO)
Next, the second region is fixed to the IGZO layer (f / (e + f) = 0.85), and the first region A1 is IGZO-based (In _(a) Ga _(b) Zn _(c) O _(d) Table 4 summarizes the TFT characteristics when the composition was modulated in (4).

From Table 4, the composition of the A1 layer is b ≦ 91a / 74-17 / 40, b ≧ 3a / 7-3 / 14, c ≦ 3/5, b ≧ 9a / 5−53 / 50, b ≦ −8a. In the composition range (Example 7-15) represented by / 5 + 33/25 (where a + b + c = 1), it can be seen that a TFT having a field effect mobility of 20 cm ² / Vs or more can be produced. Further, if it is within the composition range represented by b ≦ 17a / 23−28 / 115, b ≧ 3a / 37, b ≧ 9a / 5−53 / 50, b ≦ 1/5 (provided that a + b + c = 1). It can be seen that a TFT having a field effect mobility of 30 cm ² / Vs or more can be manufactured.

  On the other hand, in Examples A to C in which the In content was increased, a high field effect mobility was obtained, but since the carrier concentration was in an excessive state, the threshold was set to Example 7 by light irradiation at 420 nm. It is shifted to the minus side more greatly than -15 TFT. These elements of Examples AC are not desirable from the viewpoint of low power consumption, for example, as compared to the elements of Examples 7-15.

  In the comparative examples 3 and 4 where the composition of the A1 layer is a> 0, b ≧ 0, c> 0, d> 0, a + b + c = 1, and b ≦ 91a / 74−17 / 40, 420 nm Although the threshold shift amount due to light irradiation is small, the TFT has insufficient mobility.

(When the first region is an IZO system)
When the second region is fixed to the IGZO layer (f / (e + f) = 0.85) and the first region A1 is compositionally modulated in the IZO system (In _(a) Zn _(c) O _(d) ) The TFT characteristics are summarized in Table 5 below.

From Table 5, if the IZO system is used for the first region and is within the composition range represented by 0.40 ≦ a ≦ 0.75 (composition range composed of Examples 16-20), the field effect migration It can be seen that TFTs with a degree of over 30 cm ² / Vs can be manufactured. Further, it can be seen that a normally-off TFT can be manufactured with a field effect mobility of more than 30 cm ² / Vs within the composition range represented by 0.40 ≦ a ≦ 0.50.
On the other hand, when the In ratio (a) is increased more than this (Example D), the carrier concentration is in an excessive state, and the threshold value takes a relatively large negative value. On the other hand, when the In ratio (a) is decreased from the desired composition range (Comparative Example 7), it is found that the TFT has extremely low mobility, and it is difficult to manufacture a high mobility element.
When the cation composition of the second region A2 is fixed as described above, the composition of the first region (IGZO-based, IZO-based) in the laminated TFT structure is modulated, so that high mobility can be achieved within a specific composition range. It was found that TFT characteristics can be obtained.

  Regarding the TFTs manufactured in Examples and Comparative Examples, the composition range of the first region A1 is shown in FIG. 13 by the ternary phase diagram method.

<Dependence of TFT characteristics on A2 layer thickness>
Subsequently, in order to examine how the film thickness of the second region A2 affects the TFT characteristics, the following bottom gate and top contact type thin film transistors were manufactured as Examples 21 to 23 and Example E. At this time, the composition of the A1 layer was a = 37/60, b = 3/60, and c = 20/60, and the composition of the A2 layer was the IGZO layer (f / (e + f) = 0.85). A transistor was manufactured in which the thickness of the A1 layer was 5 nm and only the thickness of the A2 layer was changed to 10 nm, 30 nm, 50 nm, and 70 nm. Table 6 shows the thickness of the A2 layer and the TFT characteristics.

  Thus, it was found that when the thickness of the A2 layer is 10 nm or less, the mobility increases, but the S value deteriorates (over 1 V / decade) and the off-current tends to increase. On the other hand, if the thickness of the A2 layer is 30 nm or more, the S value is good (1 V / decade or less), and a reduction in off current can be expected. Therefore, it was found that when the composition of the first region is the same, the film thickness of the second region is preferably more than 10 nm, preferably 30 nm or more. Further, since the mobility slightly decreased when the film thickness of the second region was 70 nm, it was found that the film thickness of the second region A2 is more preferably less than 70 nm.

<Dependence of TFT characteristics on A1 layer thickness>
In order to investigate how the film thickness of A1 affects the TFT characteristics, bottom gate and top contact type thin film transistors shown in Table 7 below were fabricated as Examples 24 and 25. At this time, the composition of the A1 layer was a = 37/60, b = 3/60, and c = 20/60, and the composition of the A2 layer was an IGZO layer (f / (e + f) = 0.85). In Example 25, the thickness of the A1 layer was 10 nm.

  From Table 7, it can be seen that when the film thickness of the A1 layer is 10 nm, the field-effect mobility is sufficiently secured, but the threshold value shifts to the negative side and the off-current tends to increase. This is because an oxide semiconductor layer having a high carrier concentration is used for the A1 layer. If the thickness of the A1 layer is increased, the total carrier concentration increases and pinch-off becomes difficult. Therefore, it was found that the thickness of the A1 layer is desirably less than 10 nm.

  From the above, it can be seen that a TFT having high mobility and high light stability in the composition / film thickness of the characteristics can be manufactured by modulating the composition and film thickness of the layered structure A1 and A2 layers of the active layer. It was.

<Depends on TFT post-annealing treatment conditions>
In order to confirm how the TFT characteristics and light stability change depending on the post-annealing treatment conditions, the same TFT structure and composition as in Example 21 were used, and the post-annealing conditions were changed as shown in Table 8 below.

  From the above results, it can be seen that high mobility and high light stability are compatible at 300 ° C. or higher in an oxidizing atmosphere. On the other hand, when annealing was performed in an inert gas such as argon, the hamp effect was significant and the photostability was not high. This is because, when annealed in an inert gas, oxygen is desorbed from the active layer surface and inside, and a low-resistance parasitic conduction path is generated on the active layer surface and inside, thereby generating a hump effect. It is considered a thing. Therefore, it has been found that it is desirable to anneal in an oxidizing atmosphere in the heat treatment step.

Further, it can be seen from Example 26 and Example 27 that high light stability can be obtained under the heat treatment conditions of 300 ° C. or higher even in the same annealing atmosphere, and at the same time, heat treatment temperatures of 400 ° C. or higher from Examples 27, 29, and 30. In this case, it was found that the light stability can be extremely improved (ΔVth amount is 0.1 V or less with respect to light irradiation of 420 nm).
In addition, from the results of Example 27 and Example 28, the case where annealing is performed in the atmosphere (about 50% humidity) when annealed in a 100% oxygen atmosphere (supplied from a gas cylinder and humidity is 1% or less) Therefore, it is desirable to anneal in a dry atmosphere where the moisture content contained in the entire atmosphere is -36 ° C. or less (absolute humidity 0.21 g / m ⁻³ or less) in terms of dew point temperature. I understood that.
Further, for example, comparison between Example 27 and Example 32 shows that light stability is slightly improved with 100% oxygen at 100% oxygen and 20% oxygen even at the same dew point temperature. In addition, from Examples 28, 33, and 34, it can be seen that the light stability is improved by reducing the humidity.

  Although the use of the thin film transistor of the present invention described above is not particularly limited, for example, in a display device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) display device, an inorganic EL display device, etc.) as an electro-optical device. It is suitable as a drive element.

  Further, the thin film transistor of the present invention is a device such as a flexible display that can be manufactured by a low-temperature process using a resin substrate, an image sensor such as a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor), and an X-ray sensor. It is suitably used as a drive element (drive circuit) in various electronic devices such as sensors and MEMS (Micro Electro Mechanical System).

  Both the display device and the sensor of the present invention using the thin film transistor of the present invention exhibit good characteristics due to low power consumption. The “characteristic” referred to here is a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.

DESCRIPTION OF SYMBOLS 1, 2 Thin film transistor 11 Substrate 12 Oxide semiconductor layer 13 Source electrode 14 Drain electrode 15 Gate insulating film 16 Gate electrode A1 1st area | region A2 of oxide semiconductor layer 2nd area | region of oxide semiconductor layer

Claims (16)

As the oxide semiconductor layer of a thin film transistor having a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode, In _(a) Ga _(b) Zn _(c) O _(d) ( a> 0, b ≧ 0, c> 0, d> 0, and a + b + c = 1), and a first region having a composition satisfying b ≦ 91a / 74−17 / 40, and the first region In _(e) Ga _(f) Zn _(g) O _(h) (e> 0, f> 0, g> 0, h> 0, and e + f + g = 1), a film forming step of forming a second region having a composition different from that of the first region and satisfying f / (e + f) ≧ 0.80;
A heat treatment step of performing a heat treatment at 300 ° C. or higher in an oxidizing atmosphere after the film forming step;
The manufacturing method of the thin-film transistor which has this.   The method of manufacturing a thin film transistor according to claim 1, wherein a heat treatment temperature in the heat treatment step is 400 ° C. or higher.   3. The method for manufacturing a thin film transistor according to claim 1, wherein the atmosphere in the heat treatment step is a dry atmosphere having a moisture content in the entire atmosphere of −36 ° C. or less in terms of dew point temperature. A gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode;
The oxide semiconductor layer is represented by In _(a) Ga _(b) Zn _(c) O _(d) (a> 0, b ≧ 0, c> 0, d> 0, and a + b + c = 1). a first region having a composition satisfying b ≦ 91a / 74-17 / 40, and disposed on a side farther from the gate electrode than the first region, and In _(e) Ga _(f) Zn _(g) O _(H) (e> 0, f> 0, g> 0, h> 0, and e + f + g = 1), the composition is different from that of the first region, and f / (e + f) ≧ 0.80. A thin film transistor including a second region having a filling composition. The composition of the first region is:
c ≦ 3/5,
b> 0,
b ≧ 3a / 7-3 / 14,
b ≧ 9a / 5−53 / 50,
b ≦ −8a / 5 + 33/25, and
b ≦ 91a / 74-17 / 40
The thin film transistor according to claim 4, which is in a range satisfying The composition of the first region is:
b ≦ 17a / 23-28 / 115,
b ≧ 3a / 37,
b ≧ 9a / 5−53 / 50, and
b ≦ 1/5
The thin film transistor according to claim 4, which is in a range satisfying   The thin film transistor according to claim 4, wherein the composition of the first region is b = 0.   The thin film transistor according to claim 7, wherein a composition of the first region is 0.4 ≦ a ≦ 0.75.   The thin film transistor according to claim 7, wherein a composition of the first region is 0.4 ≦ a ≦ 0.5.   The thin film transistor according to any one of claims 4 to 9, wherein the film thickness of the second region is more than 10 nm and less than 70 nm.   The thin film transistor according to any one of claims 4 to 10, wherein the film thickness of the first region is not less than 5 nm and less than 10 nm.   The thin film transistor according to claim 4, wherein the oxide semiconductor layer is amorphous.   The display apparatus provided with the thin-film transistor of any one of Claims 4-12.   The image sensor provided with the thin-film transistor of any one of Claims 4-12.   The X-ray sensor provided with the thin-film transistor of any one of Claims 4-12.   An X-ray digital imaging apparatus comprising the X-ray sensor according to claim 15.