JP5672734B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, development of semiconductor devices using semiconductor heterojunctions has been promoted. As one of such semiconductor devices, for example, a high electron mobility transistor (HEMT) is known. As such a semiconductor device, a horizontal type in which electrons flow in the direction along the semiconductor stack interface and a vertical type in which electrons flow in the semiconductor stack direction are known.

JP 2006-269825 A JP 2003-051508 A JP 2008-205146 A

Applied Physics Express, 2008, Vol. 1, No. 1 1,011105 Applied Physics Express, 2008, Vol. 1, No. 1 2,021104

  A vertical semiconductor device that allows electrons to flow in the direction of semiconductor stacking can have a smaller planar size than a horizontal type, and the breakdown voltage can be controlled by the thickness in the direction of semiconductor stacking. is there.

  However, in such a vertical semiconductor device in which electrons flow in the stacking direction of the semiconductor, the resistance of the current path becomes high or the operation utilizing the heterojunction characteristics cannot be performed depending on the stacking form of the semiconductor. There was a case.

According to one aspect of the present invention, a substrate, an n-type first semiconductor layer formed above the substrate, and an n-type or undoped second semiconductor layer formed above the first semiconductor layer; , said second semiconductor layer a gate electrode formed in the second formed above the semiconductor layer, n-type above the third semiconductor layer of undoped third semiconductor layer or the fourth semiconductor layer of undoped wherein the door, said a laminated semiconductor in which the two-dimensional electron gas in the third semiconductor layer is produced, a source electrode connected to said stack in a semiconductor, seen including a drain electrode connected to the substrate, wherein The first semiconductor layer and the third semiconductor layer have a first electron affinity and a third electron affinity, respectively, and the second semiconductor layer is a second electron smaller than the first electron affinity and the third electron affinity. Having an affinity, and the fourth semiconductor layer is The fourth electron affinity is smaller than the third electron affinity, extends from the source electrode along the two-dimensional electron gas in the third semiconductor layer to the vicinity of the gate electrode, and further from the vicinity of the gate electrode to the second A semiconductor device is provided in which a current path extending to the drain electrode through a semiconductor layer is formed .

  According to the disclosed semiconductor device, it is possible to effectively utilize the characteristics of the semiconductor to be used and to reduce the resistance of the current path.

It is explanatory drawing of a semiconductor device. It is a principal part cross-sectional schematic diagram of an example of a semiconductor device. It is a figure which shows the example of a layout of a semiconductor device. It is an example (the 1) of the band figure of a semiconductor device. It is an example (the 2) of the band figure of a semiconductor device. It is a principal part cross-sectional schematic diagram of another example of a semiconductor device. It is explanatory drawing of the component separation of the resistance in the source electrode vicinity of a semiconductor device. It is a figure which shows the structure of the semiconductor device used for simulation. It is a figure which shows the relationship between the drain voltage when changing gate voltage, and drain current.

FIG. 1 is an explanatory diagram of a semiconductor device. Note that FIG. 1 schematically shows a cross-section of an essential part of an example of a semiconductor device.
A semiconductor device 1 shown in FIG. 1 has a structure in which a plurality of semiconductor layers are stacked on a substrate 2. Here, the case where the electron drift layer 4, the electron block layer 5, the electron transit layer 6, the electron supply layer 7 and the surface protective layer 8 are laminated in this order on the substrate 2 via the buffer layer 3 is illustrated. ing.

  In these layers, an opening 9 that penetrates the surface protective layer 8, the electron supply layer 7, the electron transit layer 6, and the electron block layer 5 and reaches the inside of the electron drift layer 4 is formed. A gate electrode 11 is formed in the opening 9 via an insulating film 10. The insulating film 10 extends from the inner surface of the opening 9 to the upper surface of the surface protective layer 8. The upper surfaces of the gate electrode 11 and the insulating film 10 are covered with an insulating film 12.

  The semiconductor device 1 has a source electrode 13 that sandwiches a gate electrode 11. FIG. 1 illustrates a pair of source electrodes 13. The source electrode 13 is formed so as to penetrate the insulating films 10 and 12 and the surface protective layer 8 and have a lower end portion reaching the electron supply layer 7. Each source electrode 13 is connected by a source wiring 14. The semiconductor device 1 has a drain electrode 15 formed on the back surface of the substrate 2 (the surface opposite to the side where the source electrode 13 and the like are disposed).

  In such a semiconductor device 1, the electron transit layer 6 and the electron supply layer 7 are in the vicinity of the interface with the electron supply layer 7 in the electron transit layer 6 along the interface due to their heterojunction. A two-dimensional electron gas (2DEG) 16 is generated.

  In selecting the material of each semiconductor layer included in the semiconductor device 1, for example, for the electron transit layer 6 and the electron supply layer 7, a material having an electron affinity smaller in the electron supply layer 7 than in the electron transit layer 6 is selected. A material having an electron affinity smaller than that of the electron transit layer 6 is selected for the electron block layer 5. A material having an electron affinity greater than that of the electron block layer 5 is selected for the electron drift layer 4.

  During operation of the semiconductor device 1, electrons entering the electron supply layer 7 from the source electrode 13 contact 2DEG 16 in the electron transit layer 6 as indicated by a thick arrow in FIG. In the direction along the heterojunction interface between the layer 6 and the electron supply layer 7). In the semiconductor device 1, when the potential of the gate electrode 11 is 0 V, the electron flow from the electron transit layer 6 to the electron drift layer 4 is blocked by the electron block layer 5.

  In the semiconductor device 1, when electrons flow from the electron transit layer 6 to the electron drift layer 4 and current flows between the source electrode 13 and the drain electrode 15, predetermined positive voltages are respectively applied to the gate electrode 11 and the drain electrode 15. Applied. In the semiconductor device 1, when a positive voltage is applied to the gate electrode 11, the potentials of the insulating film 10 and the electron block layer 5 are lowered, and an electron path (channel) is formed, which is indicated by a thick arrow in FIG. As described above, electrons flow from the electron transit layer 6 to the electron drift layer 4. The electrons that have flowed through the electron drift layer 4 are extracted to the drain electrode 15 to which a positive voltage is applied.

Hereinafter, the semiconductor device as described above will be described more specifically.
FIG. 2 is a schematic cross-sectional view of an essential part of an example of a semiconductor device.
The semiconductor device 1a shown in FIG. 2 uses an n-type substrate 2a as a substrate. As the n-type substrate 2a, for example, an n-type silicon (Si) substrate, an n-type silicon carbide (SiC) substrate, or an n-type gallium nitride (GaN) substrate can be used. For example, the n-type substrate 2a is doped with a relatively high concentration of n-type impurities.

  In the semiconductor device 1a, an n-type aluminum gallium nitride (AlGaN) layer 3a (n-AlGaN) as a buffer layer is formed on such an n-type substrate 2a. An n-type GaN layer 4a (n-GaN) serving as an electron drift layer is formed on the n-type AlGaN layer 3a, and an n-type AlGaN layer 5a (n−) serving as an electron block layer is formed on the n-type GaN layer 4a. AlGaN) is formed. An undoped GaN layer 6a (i-GaN) serving as an electron transit layer is formed on the n-type AlGaN layer 5a, and an n-type or undoped AlGaN layer 7a serving as an electron supply layer is formed on the undoped GaN layer 6a. (AlGaN) is formed. On the AlGaN layer 7a, an n-type GaN layer 8a (n-GaN) serving as a surface protective layer is formed. As described above, the semiconductor device 1a is formed using a nitride semiconductor layer, which can take a wurtzite crystal structure, such as GaN and AlGaN as a semiconductor layer.

Here, the n-type AlGaN layer 3a serving as a buffer layer is doped with, for example, Si as an n-type impurity. The doping amount of Si in the n-type AlGaN layer 3a can be, for example, about 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ . The thickness of the n-type AlGaN layer 3a can be, for example, about 0.1 μm to 1 μm. The Al composition of the n-type AlGaN layer 3a can be set to 0.2 (20%), for example. Further, the Al composition of the n-type AlGaN layer 3a can be inclined so as to decrease toward the n-type GaN layer 4a side. For example, the Al composition at the junction interface between the n-type AlGaN layer 3a and the n-type substrate 2a is set to 0.2, and the Al composition is gradually decreased toward the n-type GaN layer 4a to join the n-type GaN layer 4a. The Al composition is made zero at the interface. Thereby, the energy gap at the junction interface with the n-type GaN layer 4a can be reduced and the accumulation of electrons can be suppressed while the n-type AlGaN layer 3a has a function as a buffer layer.

The n-type GaN layer 4a serving as the electron drift layer is doped with, for example, Si as an n-type impurity. The doping amount of Si in the n-type GaN layer 4a can be, for example, about 1 × 10 ¹⁶ / cm ³ to 1 × 10 ²⁰ / cm ³ . The thickness of the n-type GaN layer 4a can be, for example, about 1 μm to 5 μm. If the thickness of the n-type GaN layer 4a is less than 1 μm, sufficient breakdown voltage cannot be secured depending on the operating conditions of the semiconductor device 1a, such as when the semiconductor device 1a is applied to a power device that requires high breakdown voltage. there is a possibility. On the other hand, if the n-type GaN layer 4a is thicker than 5 μm, there is a possibility that the current density during operation (on-time) may decrease due to an increase in resistance.

For example, Si is doped as an n-type impurity in the n-type AlGaN layer 5a serving as an electron block layer. The doping amount of Si in the n-type AlGaN layer 5a can be, for example, about 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ . The thickness of the n-type AlGaN layer 5a can be, for example, about 0.1 μm to 1 μm. The Al composition of the n-type AlGaN layer 5a can be set to 0.3 (30%), for example. Further, the Al composition of the n-type AlGaN layer 5a can be inclined so as to increase toward the undoped GaN layer 6a side. For example, the Al composition is 0 at the junction interface between the n-type AlGaN layer 5a and the n-type GaN layer 4a, the Al composition is gradually increased toward the undoped GaN layer 6a side, and at the junction interface with the undoped GaN layer 6a. The Al composition is set to 0.3. Accordingly, it is possible to reduce the energy gap at the junction interface with the n-type GaN layer 4a and suppress the accumulation of electrons while providing the n-type AlGaN layer 5a with a function as an electron blocking layer.

The thickness of the undoped GaN layer 6a serving as the electron transit layer can be, for example, about 0.1 μm to 1 μm.
The thickness of the AlGaN layer 7a serving as the electron supply layer can be set to 30 nm, for example. The Al composition of the AlGaN layer 7a can be set to 0.2 (20%), for example. When the AlGaN layer 7a is n-type, for example, Si, which is an n-type impurity, may be doped by about 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ .

In the AlGaN / GaN heterojunction structure such as the undoped GaN layer 6a and the AlGaN layer 7a, 2DEG16a is caused by the spontaneous polarization charge caused by the asymmetry of the crystals of both layers and the piezopolarization charge generated at the interface between the two layers. Is generated. 2DEG 16a is generated in the undoped GaN layer 6a in the vicinity of the interface with the AlGaN layer 7a at a high concentration along the interface depending on the Al composition. Further, since the region where electrons exist is the undoped GaN layer 6a, there are few electron scatterers and high mobility can be realized. For example, a sheet electron concentration of 2 × 10 ¹³ / cm ² and a mobility of 1800 cm ² / V / s can be easily obtained. The sheet resistance at this time can be reduced to 200Ω / □ by optimizing the composition of the AlGaN layer 7a. Further, since 2DEG 16a concentrates in the vicinity of the AlGaN / GaN heterojunction interface, a carrier concentration exceeding 1 × 10 ²⁰ / cm ³ in volume density can be realized.

The n-type GaN layer 8a serving as the surface protective layer prevents the Al of the AlGaN layer 7a from being exposed and contributes to improving the reliability of the semiconductor device 1a. The thickness and doping concentration of the n-type GaN layer 8a are set so that the n-type GaN layer 8a itself is depleted during operation of the semiconductor device 1a and does not become a current path. The n-type GaN layer 8a is doped with Si as an n-type impurity, for example. The doping amount of Si in the n-type GaN layer 8a can be, for example, about 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁹ / cm ³ . The thickness of the n-type GaN layer 8a can be about 6 nm, for example.

  In this example, GaN and AlGaN are used as nitride semiconductors, but InGaN and InAlGaN containing indium (In) can also be used in the same manner, and similar functions can be obtained. .

  In the nitride semiconductor layer as described above, an opening 9a that penetrates through the n-type GaN layer 8a, the AlGaN layer 7a, the undoped GaN layer 6a, and the n-type AlGaN layer 5a and reaches the inside of the n-type GaN layer 4a is formed. ing. The width of the opening 9a can be, for example, about 100 nm to 100 μm.

In the opening 9a, a gate electrode 11a is formed of nickel (Ni) or a material mainly composed of Ni, gold (Au) or a material mainly composed of Au, or the like through an insulating film 10a. As the insulating film 10a, a silicon nitride (SiN) film, a silicon oxide (SiO ₂ ) film, a silicon oxynitride film (SiON) film, an aluminum oxide film (AlO _x ), a hafnium oxide (HfO _x ) film, or the like is used. it can. The insulating film 10a extends from the inner surface of the opening 9a to the upper surface of the n-type GaN layer 8a. The thickness of the insulating film 10a can be, for example, about 1 nm to 1000 nm. The upper surfaces of the gate electrode 11a and the insulating film 10a are covered with an insulating film 12a such as a SiN film.

  The semiconductor device 1a has a source electrode 13a that sandwiches the gate electrode 11a. FIG. 2 illustrates a pair of source electrodes 13a. The source electrode 13a is formed so as to penetrate through the insulating films 10a and 12a and the n-type GaN layer 8a and have a lower end portion reaching the AlGaN layer 7a. For example, the source electrode 13a is first formed of a laminated structure of titanium (Ti) and aluminum (Al), alloyed by a subsequent heat treatment, and a part thereof is diffused into the AlGaN layer 7a. As a result, the source electrode 13a that is in ohmic contact with the 2DEG 16a is formed.

  The source electrode 13a is preferably formed so as not to penetrate the AlGaN layer 7a. When the source electrode 13a is formed by penetrating the AlGaN layer 7a, 2DEG 16a is not generated in the portion where the source electrode 13a and the undoped GaN layer 6a are in contact with each other, and the carrier concentration is higher than that in the case where the AlGaN layer 7a is not penetrated. It is because it will fall. However, even if the source electrode 13a penetrates the AlGaN layer 7a and reaches the undoped GaN layer 6a below it, the source region 13a in ohmic contact with the generated 2DEG 16a is obtained although the generation region of the 2DEG 16a is reduced. Is possible.

A plurality of source electrodes 13a are formed across the gate electrode 11a, and each source electrode 13a is connected by a source line 14a.
Further, on the back surface of the n-type substrate 2a (the surface opposite to the side where the source electrode 13a and the like are disposed), for example, in the case of a GaN substrate, a drain electrode 15a formed of a laminated structure of Ti and Al is formed. Has been. Since the drain electrode 15a has a large area, the metal limit for making ohmic contact is loose.

  FIG. 2 illustrates a single GaN-based vertical transistor as the semiconductor device 1a. In the case of the semiconductor device 1a including a plurality of GaN-based vertical transistors, the plurality of GaN-based vertical transistors are laid out so as to be arranged in one direction or in two directions orthogonal to each other.

FIG. 3 is a diagram illustrating a layout example of a semiconductor device.
3A and 3B illustrate a layout in which a plurality of GaN-based vertical transistors included in the semiconductor device 1a are arranged in two directions orthogonal to each other. 3A and 3B schematically illustrate the semiconductor device 1a including a plurality of GaN-based vertical transistors excluding the source wiring 14a as illustrated in FIG. 2 in plan view. Yes. FIG. 2 described above schematically shows a cross section corresponding to the position of the line MM in FIGS. 3 (A) and 3 (B). Here, the layout of the semiconductor device 1a will be described focusing on the positional relationship between the source electrode 13a and the gate electrode 11a.

  In the semiconductor device 1a including a plurality of GaN-based vertical transistors, as shown in FIGS. 3A and 3B, the plurality of source electrodes 13a are arranged in two directions S and T orthogonal to each other. Laid out. Of these source electrodes 13a, a pair of adjacent source electrodes 13a becomes the source electrode 13a of one GaN-based vertical transistor (the pair of source electrodes 13a shown in FIG. 2).

  The gate electrode 11a is laid out between adjacent source electrodes 13a. For example, as shown in FIG. 3A, the gate electrode 11a is a slit that extends linearly in the direction S so as to pass between the group of source electrodes 13a arranged in the direction S. Can be laid out. Further, for example, as shown in FIG. 3B, the gate electrode 11a is formed between the source electrode 13a groups arranged in the direction S and between the source electrode 13a groups arranged in the direction T. , It can also be laid out in a grid so as to pass through both.

Next, the operation of the semiconductor device 1a having the above configuration will be described.
4 and 5 are examples of band diagrams of the semiconductor device.
4 and 5 show examples of band diagrams of the semiconductor device 1a using the n-type AlGaN layer 7a as the electron supply layer. The n-type substrate 2a of the semiconductor device 1a shown in FIGS. 4 and 5 is an n-type Si substrate. The n-type substrate 2a, the n-type AlGaN layer 3a, the n-type GaN layer 4a and the n-type AlGaN layer 5a have the highest dopant concentration in the n-type substrate 2a (n ⁺⁺ ), and then the highest in the n-type AlGaN layer 3a (n ⁺ ), The n-type GaN layer 4a and the n-type AlGaN layer 5a are made lower (n ⁻ ).

  FIGS. 4B and 4C show a region relatively distant from the gate electrode 11a (region close to the source electrode 13a) in the semiconductor device 1a having such a configuration as shown in FIG. The band figure of the direction Y1 to show is shown. Here, FIG. 4B is a band diagram when the voltage applied to the drain electrode 15 (drain voltage Vd) is 0 V and the voltage applied to the gate electrode 11 a (gate voltage Vg) is 0 V. FIG. 4C is a band diagram when the drain voltage Vd is 50V and the gate voltage Vg is 0V.

  Further, FIGS. 4D and 4E show a region relatively close to the gate electrode 11a (a region away from the source electrode 13a) in the semiconductor device 1a having the above-described configuration, as shown in FIG. A band diagram in the direction Y2 shown in FIG. Here, FIG. 4D is a band diagram in the case where the drain voltage Vd is 50V and the gate voltage Vg is 0V. FIG. 4E is a band diagram when the drain voltage Vd is 50V and the gate voltage Vg is 4V.

  5B and 5C show the undoped GaN layer 6a and its vicinity (region surrounded by a dotted line) in FIG. 5A in the semiconductor device 1a configured as described above. The band figure of the direction X shown is shown. Here, FIG. 5B is a band diagram when the drain voltage Vd is 50V and the gate voltage Vg is 0V. FIG. 5C is a band diagram when the drain voltage Vd is 50V and the gate voltage Vg is 4V.

The operation of the semiconductor device 1a will be described with reference to FIGS.
First, the case where both the drain voltage Vd and the gate voltage Vg shown in FIG. 4B are 0V will be described. In this case, although 2DEG 16a is generated in the undoped GaN layer 6a due to the heterojunction with the AlGaN layer 7a, electron transfer from the undoped GaN layer 6a to the n-type GaN layer 4a is blocked by the n-type AlGaN layer 5a. Is done. Therefore, the flow of electrons from the source electrode 13a to the drain electrode 15a is suppressed.

  When the gate voltage Vg is 0 V and the drain voltage Vd is 50 V, the conduction band energy Ec of the n-type GaN layer 4a, the n-type AlGaN layer 3a, and the n-type substrate 2a is shown in FIGS. As shown in FIG. 4D, the state is greatly lowered from the state shown in FIG.

  At this time, in the region relatively close to the source electrode 13a, as shown in FIGS. 4C and 5B, 2DEG 16a is generated in the undoped GaN layer 6a. However, the movement of electrons entering the undoped GaN layer 6a through the source electrode 13a and the AlGaN layer 7a to the n-type GaN layer 4a is blocked by the n-type AlGaN layer 5a. Therefore, the flow of electrons from the source electrode 13a to the drain electrode 15a is suppressed. On the other hand, in the region relatively close to the gate electrode 11a, as shown in FIGS. 4D and 5B, the conduction band energy Ec of the undoped GaN layer 6a becomes Fermi level Ef due to the influence of the insulating film 10a. It is lifted further and the generation of 2DEG 16a is suppressed. Therefore, the flow of electrons from the source electrode 13a to the drain electrode 15a is suppressed.

  Thus, in the semiconductor device 1a, when the gate voltage Vg is 0V, the flow of current between the source electrode 13a and the drain electrode 15a is suppressed. That is, the semiconductor device 1a is a normally-off type.

  On the other hand, when the drain voltage Vd is 50 V and the gate voltage Vg is 4 V, as shown in FIG. 5C, the conduction band energy Ec of the insulating film 10a decreases, and the undoped GaN layer 6a and The conduction band energy Ec of the n-type AlGaN layer 5a is lowered. Thereby, a high concentration of 2DEG 16a is generated in the undoped GaN layer 6a in the vicinity of the insulating film 10a. As the high-concentration 2DEG 16a is generated in the undoped GaN layer 6a in the vicinity of the insulating film 10a, the electrons in the undoped GaN layer 6a are n-type AlGaN whose conduction band energy Ec is lowered as shown in FIG. It flows over the barrier of the layer 5a and flows to the n-type GaN layer 4a. That is, by applying the gate voltage Vg, a channel is formed in the vicinity of the insulating film 10a. Then, the electrons that have flowed to the n-type GaN layer 4a further flow through the n-type AlGaN layer 3a and the n-type substrate 2a whose conduction band energy Ec has been lowered by applying the drain voltage Vd, and are extracted to the drain electrode 15a.

Thus, in the semiconductor device 1a, a current flows between the source electrode 13a and the drain electrode 15a when the gate voltage Vg is applied.
Here, the operation has been described by taking the semiconductor device 1a using GaN or AlGaN as an example. However, even when InGaN or InAlGaN is used, the semiconductor device should operate in the same manner as described here. Can do.

  As described above, in the semiconductor device 1a, the stacked semiconductor layer is formed above the n-type GaN layer 4a of the electron drift layer that forms the vertical current path through the n-type AlGaN layer 5a of the electron block layer. To do. As the laminated semiconductor layer, a layer in which an AlGaN layer 7a as an electron supply layer is formed on an undoped GaN layer 6a as an electron transit layer and 2DEG 16a is generated in the vicinity of the interface is used. Thus, during operation of the semiconductor device 1a, a high concentration of 2DEG 16a can be generated in the undoped GaN layer 6a. Further, since there are few electron scatterers in the undoped GaN layer 6a, high mobility can be obtained. As a result, the resistance of the current path during the operation of the semiconductor device 1a can be reduced. The semiconductor device 1a can be formed using n-type or undoped GaN or AlGaN as the semiconductor layer.

Here, another example of a semiconductor device is described as an example.
FIG. 6 is a schematic cross-sectional view of an essential part of another example of the semiconductor device.
A semiconductor device 100 shown in FIG. 6 includes an n-type GaN layer 103, a p-type GaN layer 104, and an n-type GaN layer 105 on an n-type substrate 101 such as an n-type SiC substrate via an aluminum nitride (AlN) layer 102. Has a formed structure. In the semiconductor device 100, the AlN layer 102 functions as a buffer layer, the n-type GaN layer 103 functions as an electron drift layer, the p-type GaN layer 104 functions as an electron block layer, and the n-type GaN layer 105 functions as an electron transit layer. The semiconductor device 100 further includes a gate electrode 106 penetrating the p-type GaN layer 104, a source electrode 107 connected to the n-type GaN layer 105, and a drain electrode 108 formed on the back surface of the n-type substrate 101. . The periphery of the gate electrode 106 is covered with insulating films 109 and 110. Each source electrode 107 is connected by a source wiring 111.

  In the semiconductor device 100, the movement of electrons entering the n-type GaN layer 105 from the source electrode 107 to the n-type GaN layer 103 is applied to the p-type GaN layer 104 near the insulating film 109 by applying a voltage to the gate electrode 106. This is done by forming a channel.

  Such a vertical semiconductor device 100 includes a GaN layer having a pn junction therein, that is, an n-type GaN layer 103 and a p-type GaN layer 104, and a p-type GaN layer 104 and an n-type GaN layer 105. . Therefore, the diffusion of the p-type dopant in the p-type GaN layer 104, particularly the upward diffusion to the n-type GaN layer 105, may prevent the formation of the n-type layer as designed. Furthermore, the n-type GaN layer 105 that is a part of the current path may increase the resistance of the current path in the semiconductor device 100 due to the presence of the dopant. Further, in the semiconductor device 100, it is not possible to effectively use the polarization charge, which is one of the characteristics of a nitride semiconductor that can take a wurtzite crystal structure such as GaN.

  On the other hand, in the semiconductor device 1a described above, since the n-type AlGaN layer 5a is used as the electron blocking layer, the diffusion of the p-type dopant as described above does not occur. In the semiconductor device 1a, the resistance can be reduced by using a heterojunction of the AlGaN layer 7a that generates the 2DEG 16a and the undoped GaN layer 6a.

  Here, FIG. 7 is an explanatory diagram of resistance component separation in the vicinity of the source electrode of the semiconductor device. FIG. 7A is a diagram of the semiconductor device 100, that is, a case where the source electrode 107 is connected to the n-type GaN layer 105. FIG. 7B shows the semiconductor device 1a, that is, the case where the source electrode 13a is connected to the AlGaN layer 7a in the heterojunction between the AlGaN layer 7a and the undoped GaN layer 6a.

  In FIG. 7A, the distance L between the portion of the source electrode 107 entering the n-type GaN layer 105 and the insulating film 109, and entering the AlGaN layer 7a of the source electrode 13a in FIG. The distance L between the portion and the insulating film 10a is 2 μm. 7A shows the connection resistance between the source electrode 107 and the n-type GaN layer 105, and FIG. 7B shows the source electrode 13a and the AlGaN layer 7a / undoped GaN layer 6a heterojunction (2DEG16a). Connection resistance is shown. In FIG. 7A, R12 indicates resistance (lateral resistance) when electrons move laterally in the n-type GaN layer 105, and in FIG. 7B, electrons laterally move in the undoped GaN layer 6a. The resistance (lateral resistance) when moving to is shown.

  Table 1 shows the connection resistance R11 and the lateral resistance R12 of the semiconductor devices 100 and 1a.

First, in the semiconductor device 100 of FIG. 7A, when the donor concentration Nd of the n-type GaN layer 105 is 1 × 10 ¹⁸ / cm ³ , the connection resistance R11 between the source electrode 107 and the n-type GaN layer 105 is , About 0.2Ωmm. At this time, the lateral resistance R12 of the n-type GaN layer 105 is about 3.5 Ωmm because the mobility is about 350 cm ² / V / s. When the donor concentration Nd of the n-type GaN layer 105 is increased to 5 × 10 ¹⁸ / cm ³ , the mobility is reduced to about 275 cm ² / V / s, so that the connection resistance R11 is about 0.15 Ωmm, the lateral direction The resistance R12 is about 0.9 Ωmm.

  On the other hand, in the semiconductor device 1a of FIG. 7B, since the source electrode 13a contacts the 2DEG 16a immediately below the AlGaN layer 7a, the connection resistance R11 is about 0.3Ωmm and the lateral resistance R12 is about 0.5Ωmm. . In the total resistance of the connection resistance R11 and the lateral resistance R12, the resistance of the semiconductor device 1a of FIG. 7B can be reduced by about 25% to 75% compared to the semiconductor device 100 of FIG. 7A. .

  In the field of semiconductor devices, an attempt is often made to reduce the resistance (ON resistance) during operation between the source electrode and the drain electrode. Here, in a semiconductor device such as a power device in which a relatively large voltage is applied to the drain electrode, a certain distance may be secured between the source electrode and the drain electrode in order to ensure a breakdown voltage. However, the on-resistance increases as the distance between the source electrode and the drain electrode increases. That is, the on-resistance may be increased in order to ensure a certain breakdown voltage. On the other hand, even in such a semiconductor device, since the voltage applied between the source electrode and the gate electrode is relatively small, it is rarely devised to increase the withstand voltage. However, the resistance between the source electrode and the gate electrode also occupies a part of the on-resistance of the entire semiconductor device. Therefore, reducing the resistance between the source electrode and the gate electrode contributes to reducing the on-resistance of the semiconductor device.

  According to the knowledge of FIG. 7 and Table 1 above, in the semiconductor device 1a using the heterojunction of the AlGaN layer 7a and the undoped GaN layer 6a, compared to the semiconductor device 100, a part of the resistance (source electrode 13a) And the resistance between the gate electrode 11a) can be kept low. Therefore, the semiconductor device 1a having a low on-resistance can be realized. Alternatively, since the resistance between the source electrode 13a and the gate electrode 11a can be reduced, the distance between the source electrode 13a and the drain electrode 15a is increased, so that the semiconductor device 1a with higher breakdown voltage can be realized.

  Further, in the semiconductor device 1a, the p-type GaN layer 104 is not used as an electron block layer unlike the semiconductor device 100, and the n-type AlGaN layer 5a is used as an electron block layer. Therefore, in the semiconductor device 1a, as described above, there is no problem due to the diffusion of the p-type dopant. An example of the simulation result when AlGaN is used for the electron block layer is shown in FIGS.

FIG. 8 shows the structure of the semiconductor device used for the simulation. FIG. 9 is a diagram showing the relationship between the drain voltage and the drain current when the gate voltage is changed.
As shown in FIG. 8, as a semiconductor device 30 to be simulated, for simplicity, an undoped AlGaN layer 32 (electron block layer) and an n-type GaN layer 33 (electrons) are formed on an n-type GaN layer 31 (electron drift layer). A structure in which a traveling layer is laminated is used. The Al composition of the undoped AlGaN layer 32 is 0.4 (40%). In the semiconductor device 30, the insulating film 34 and the gate electrode 35 are disposed so as to penetrate the n-type GaN layer 33 and the undoped AlGaN layer 32 and reach the n-type GaN layer 31, and the source is formed on the n-type GaN layer 33. A drain electrode 37 is disposed under the electrode 36 and the n-type GaN layer 31. Here, the insulating film 34 is a SiN film having a thickness of 100 nm.

  An example of the result of simulation using such a semiconductor device 30 is shown in FIG. FIG. 9 shows the relationship between the drain voltage Vd and the drain current Id when the gate voltage Vg is changed in the range of 0V to 5V.

  From FIG. 9, when the gate voltage Vg is a relatively low value such as 0V, 1V, and 2V, the drain current Id does not flow at all or even when the drain voltage Vd is applied. That is, under such conditions, the movement of electrons entering the n-type GaN layer 33 from the source electrode 36 to the n-type GaN layer 31 is blocked by the undoped AlGaN layer 32.

  When the gate voltage Vg is set to a relatively high value such as 3V, 4V, and 5V, the drain current Id flows while the drain voltage Vd is applied. That is, under such conditions, the potential of the insulating film 34 is lowered by the gate voltage Vg, the potential of the undoped AlGaN layer 32 in contact therewith is lowered, and a channel is formed in the undoped AlGaN layer 32 in the vicinity of the insulating film 34. Thereby, electrons entering the n-type GaN layer 33 from the source electrode 36 move to the n-type GaN layer 31 beyond the undoped AlGaN layer 32.

  From the results of FIG. 9, it can be seen that the normally-off operation can be performed even in the semiconductor device 30 using AlGaN as the electron block layer shown in FIG. Even when the type and thickness of the insulating film 34 are changed, although the threshold value of the gate voltage Vg for turning on the semiconductor device 30 changes, the same result as in FIG. 9 can be obtained. Even if AlGaN is used for the electron block layer instead of GaN, it is possible to form a semiconductor device that performs normally-off operation.

Next, an example of a method for manufacturing the semiconductor device 1a as described above will be described.
In forming the semiconductor device 1a having the configuration shown in FIG. 2, first, the n-type AlGaN layer 3a, the n-type GaN layer 4a, the n-type AlGaN layer 5a, the undoped GaN layer 6a, and the AlGaN are formed on the n-type substrate 2a. A layer 7a and an n-type GaN layer 8a are sequentially formed.

Each layer can be formed by using a metal organic chemical vapor deposition (MOCVD) method. In the MOCVD method, for example, ammonia (NH ₃ ) gas is used as the N element source gas. Further, as the group III element source gas, for example, an organic group III compound source such as trimethylaluminum (TMA) or trimethylgallium (TMG) is used. In the case of forming an InAlGaN layer or an InGaN layer, for example, trimethylindium (TMI) is used as a source gas of In element. When doping an n-type impurity, for example, silane (SiH ₄ ) is used.

For example, the n-type AlGaN layer 3a can be formed under the conditions of a TMG flow rate of 1 sccm to 50 sccm, a TMA flow rate of 1 sccm to 50 sccm, an NH ₃ flow rate of 20 slm, a pressure of 1000 Torr, and a temperature of 1100 ° C. The n-type GaN layer 4a, the n-type AlGaN layer 5a, the undoped GaN layer 6a, the AlGaN layer 7a, and the n-type GaN layer 8a can also be formed by the MOCVD method under predetermined conditions.

  After each semiconductor layer is formed by the MOCVD method, an opening 9a that penetrates the n-type GaN layer 8a, the AlGaN layer 7a, the undoped GaN layer 6a, and the n-type AlGaN layer 5a and reaches the n-type GaN layer 4a is formed. The opening 9a is first formed on the n-type GaN layer 8a by forming a resist pattern having an opening in a region where the opening 9a is to be formed, and performing etching using the resist pattern as a mask. Can do. After the opening 9a is formed, the resist pattern is removed.

  Next, the insulating film 10a is formed. For example, a SiN film is formed as the insulating film 10a. The SiN film can be formed by a plasma CVD method. The insulating film 10a is formed, for example, so as to fill the opening 9a and cover the surface of the n-type GaN layer 8a.

  Then, an opening for the gate electrode 11a is formed on the insulating film 10a formed in the opening 9a, leaving the insulating film 10a on the inner surface of the opening 9a. The insulating film 10a on the inner surface of the opening 9a functions as a gate insulating film. Further, in the region where the source electrode 13a is to be formed, an opening for the source electrode 13a that reaches the AlGaN layer 7a through the insulating film 10a and the n-type GaN layer 8a is formed.

  The opening for the source electrode 13a is preferably formed so as not to reach the undoped GaN layer 6a under the AlGaN layer 7a from the viewpoint of securing the area of the 2DEG16 generation region. Further, the opening for the source electrode 13a may not necessarily be dug into the AlGaN layer 7a as long as the AlGaN layer 7a is exposed at the bottom of the opening.

  The openings for the gate electrode 11a and the source electrode 13a can be formed by etching using a resist pattern having openings in predetermined regions as masks.

  The insulating film 10a is formed on the inner surface of the opening 9a and the surface of the n-type GaN layer 8a after forming the opening 9a, leaving a space for forming the gate electrode 11a (corresponding to the opening for the gate electrode 11a). You may make it form selectively. In that case, an opening for the source electrode 13a may be formed so as to penetrate the insulating film 10a on the surface of the n-type GaN layer 8a and the n-type GaN layer 8a and reach the AlGaN layer 7a.

  After the openings for the gate electrode 11a and the source electrode 13a are formed, the gate electrode 11a is formed in the opening for the gate electrode 11a, and the source electrode 13a is formed in the opening for the source electrode 13a.

  The source electrode 13a can be formed using, for example, Ti and Al. In that case, after forming the Ti film, an Al film is formed thereon. The source electrode 13a can be formed by, for example, film formation using a photolithography technique and a vapor deposition technique, and subsequent lift-off. After forming the Ti film and the Al film, heat treatment is performed to form an alloy. As a result, the source electrode 13a is formed in ohmic contact with the 2DEG 16a formed by the heterojunction of the AlGaN layer 7a and the undoped GaN layer 6a.

  The gate electrode 11a can be formed using, for example, Ni or a material mainly composed of Ni. The gate electrode 11a can be formed by, for example, film formation using a photolithography technique and a vapor deposition technique, and subsequent lift-off.

After the formation of the gate electrode 11a and the source electrode 13a, an insulating film 12a serving as a surface protective film for the gate electrode 11a is formed using a SiN film or the like.
Thereafter, the back surface of the n-type substrate 2a is polished as necessary to make the n-type substrate 2a have a predetermined thickness. Then, the source wiring 14a connected to the source electrode 13a is formed on the front surface side of the n-type substrate 2a, and the drain electrode 15a is formed on the back surface of the n-type substrate 2a. Thereby, the semiconductor device 1a having the configuration illustrated in FIGS. 2 and 3 can be obtained.

  The semiconductor device 1a including the GaN-based vertical transistor has been described above. By using GaN and AlGaN having a large band gap, the semiconductor device 1a can be applied to a device that requires a relatively high breakdown voltage, such as a power device.

  In a power device that requires a high breakdown voltage, the breakdown voltage can be adjusted by the distance between the source electrode 13a and the drain electrode 15a in both the vertical type and the horizontal type. In the vertical semiconductor device 1a, the breakdown voltage can be adjusted by the thickness of a semiconductor layer such as an electron drift layer provided between the source electrode 13a on the front surface side and the drain electrode 15a on the back surface side, that is, the size in the vertical direction.

  On the other hand, in a horizontal type semiconductor device in which a source electrode and a drain electrode are provided on the surface side, the lateral size (planar size of the semiconductor device (chip)) is increased when attempting to secure the distance between the electrodes based on the breakdown voltage. Sometimes it gets bigger. As a result, the number of chips acquired from one wafer may decrease, and the manufacturing cost for one chip may increase.

According to the semiconductor device 1a described above, the breakdown voltage can be adjusted by the size in the vertical direction, and therefore, a predetermined breakdown voltage can be secured while suppressing an increase in the size in the horizontal direction.
In the semiconductor device 1a, a vertical structure is employed, and an on-resistance that can be increased by increasing the distance between the source electrode 13a and the drain electrode 15a in order to secure a withstand voltage. By adopting a structure, it is possible to keep it low. That is, the on-resistance of the semiconductor device 1a is reduced by using high-concentration carriers generated by the AlGaN / GaN heterojunction structure. As a result, a semiconductor device 1a having a high breakdown voltage, low loss, and low on-resistance can be realized.

  Further, since the semiconductor device 1a is formed using n-type or undoped GaN or AlGaN, it suppresses the problem of impurity diffusion as when a p-type dopant is intentionally introduced, and has high performance and high quality. The semiconductor device 1a can be realized.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Appendix 1) a substrate,
A first semiconductor layer formed above the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A first electrode formed in the second semiconductor layer;
A stacked semiconductor formed on the second semiconductor layer, including a third semiconductor layer and a fourth semiconductor layer on the third semiconductor layer, wherein a two-dimensional electron gas is generated in the third semiconductor layer;
A second electrode connected to the laminated semiconductor;
A third electrode connected to the substrate;
A semiconductor device comprising:

  (Supplementary Note 2) The first semiconductor layer and the third semiconductor layer have a first electron affinity and a third electron affinity, respectively, and the second semiconductor layer is based on the first electron affinity and the third electron affinity. 2. The semiconductor device according to appendix 1, wherein the fourth semiconductor layer has a fourth electron affinity that is smaller than the third electron affinity.

  (Supplementary note 3) The first semiconductor layer is n-type, the second semiconductor layer is n-type or undoped, the third semiconductor layer is undoped, and the fourth semiconductor layer is n-type or undoped. 3. The semiconductor device according to 1 or 2.

  (Supplementary Note 4) The first semiconductor layer and the third semiconductor layer include nitrogen and gallium as constituent elements, and the second semiconductor layer and the fourth semiconductor layer include nitrogen, aluminum, and gallium as constituent elements. 4. The semiconductor device according to any one of appendices 1 to 3, wherein:

(Additional remark 5) The semiconductor device of Additional remark 4 characterized by the aluminum composition of the said 2nd semiconductor layer becoming high toward the said 3rd semiconductor layer.
(Supplementary note 6) The supplementary notes 1 to 5, wherein the second semiconductor layer has a first opening, and the first electrode is formed in the first opening via an insulating film. The semiconductor device according to any one of the above.

(Supplementary Note 7) Each of the first semiconductor layer and the third semiconductor layer has a second opening and a third opening that are continuous with the first opening,
The semiconductor device according to appendix 6, wherein the insulating film and the first electrode are formed across the first opening, the second opening, and the third opening.

(Appendix 8) A step of forming a first semiconductor layer above a substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a stacked semiconductor including a third semiconductor layer and a fourth semiconductor layer on the third semiconductor layer on the second semiconductor layer, wherein a two-dimensional electron gas is generated in the third semiconductor layer; ,
Forming a first electrode in the second semiconductor layer;
Forming a second electrode connected to the laminated semiconductor;
Forming a third electrode connected to the substrate;
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 9) The method further includes a step of forming a first opening in the second semiconductor layer,
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the first electrode is formed in the formed first opening through an insulating film.

(Additional remark 10) It further includes the process of forming the 2nd opening part and 3rd opening part which are connected to the 1st opening part in the 1st semiconductor layer and the 3rd semiconductor layer, respectively.
The method for manufacturing a semiconductor device according to appendix 9, wherein the insulating film and the first electrode are formed across the first opening, the second opening, and the third opening.

1, 1a, 30, 100 Semiconductor device 2 Substrate 2a, 101 n-type substrate 3 buffer layer 3a, 5a n-type AlGaN layer 4 electron drift layer 4a, 8a, 31, 33, 103, 105 n-type GaN layer 5 electron block layer 6 Electron traveling layer 6a Undoped GaN layer 7 Electron supply layer 7a AlGaN layer 8 Surface protective layer 9, 9a Opening 10, 10a, 12, 12a, 34, 109, 110 Insulating film 11, 11a, 35, 106 Gate electrode 13, 13a, 36, 107 Source electrode 14, 14a, 111 Source wiring 15, 15a, 37, 108 Drain electrode 16, 16a 2DEG
32 Undoped AlGaN layer 102 AlN layer 104 p-type GaN layer

Claims (5)

A substrate,
An n-type first semiconductor layer formed above the substrate;
A second semiconductor layer n-type or undoped formed above the first semiconductor layer,
A gate electrode formed in the second semiconductor layer;
The second formed above the semiconductor layer, and a fourth semiconductor layer above the n-type or undoped said third semiconductor layer of undoped third semiconductor layer, a two-dimensional electron gas in the third semiconductor layer A laminated semiconductor where
A source electrode connected to said stack in a semiconductor,
A drain electrode connected to the substrate;
Only including,
The first semiconductor layer and the third semiconductor layer have a first electron affinity and a third electron affinity, respectively, and the second semiconductor layer is a second smaller than the first electron affinity and the third electron affinity. Having an electron affinity, and the fourth semiconductor layer has a fourth electron affinity smaller than the third electron affinity;
A current path extending from the source electrode along the two-dimensional electron gas in the third semiconductor layer to the vicinity of the gate electrode and further extending from the vicinity of the gate electrode to the drain electrode through the second semiconductor layer is formed. A semiconductor device. The first semiconductor layer and the third semiconductor layer include nitrogen and gallium as constituent elements, and the second semiconductor layer and the fourth semiconductor layer include nitrogen, aluminum, and gallium as constituent elements. The semiconductor device according to claim 1 .   3. The semiconductor device according to claim 2, wherein at least one of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer contains indium. Said second semiconductor layer has a first opening, the first opening, via the insulating film, according to any one of claims 1 to 3, characterized in that the gate electrode is formed Semiconductor device. Forming an n-type first semiconductor layer above the substrate;
Forming an n-type or a second semiconductor layer of undoped above the first semiconductor layer,
Above the second semiconductor layer, and a n-type or fourth semiconductor layer of undoped above the third semiconductor layer of undoped and said third semiconductor layer, a two-dimensional electron gas in the third semiconductor layer is produced Forming a laminated semiconductor to be formed;
Forming a gate electrode in the second semiconductor layer;
Forming a source connected electrode in the stacking the semiconductor,
Forming a drain electrode connected to the substrate;
Only including,
The first semiconductor layer and the third semiconductor layer have a first electron affinity and a third electron affinity, respectively, and the second semiconductor layer is a second smaller than the first electron affinity and the third electron affinity. Having an electron affinity, and the fourth semiconductor layer has a fourth electron affinity smaller than the third electron affinity;
A current path extending from the source electrode along the two-dimensional electron gas in the third semiconductor layer to the vicinity of the gate electrode and further extending from the vicinity of the gate electrode to the drain electrode through the second semiconductor layer is formed. A method for manufacturing a semiconductor device.

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