JP5666410B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a fuse using planarization by an SOG film.

  In analog ICs that require high-precision specifications, laser trimming that consists of a thin film that can be melted connected to a thin film resistor made of polycrystalline silicon, for example, to absorb variations in the characteristics of transistors and resistors due to manufacturing variations Generally, measures are taken to adjust the combination pattern of resistors by cutting the fuse for laser irradiation by laser irradiation, and drop it to the target value of the circuit.

  When creating such a fuse, it is usually between a nitride film or multilayer wiring that is a protective film covering such a thin film so that the laser can be efficiently applied to the thin film such as aluminum or polycrystalline silicon. The interlayer film is largely removed by etching. At this time, in the semiconductor device using the planarization by the SOG film, the SOG film is exposed on the cross section of the etching opening. Since the SOG film easily allows moisture to pass through, the moisture that has entered from the etching opening moves to the internal element region through the SOG film, and causes instability (NBTI) and wiring corrosion due to the negative voltage application of the PMOS transistor at a high temperature. .

  In the past, as a method for suppressing moisture from entering the internal element from the fuse opening via the SOG film, it has been proposed to provide a convex step called a seal ring of an aluminum wiring around the fuse opening. In the planarization process using the SOG film, the seal ring on the fuse has a convex step higher than the surrounding unevenness. Therefore, the SOG film thickness on the seal ring after the SOG coating becomes thinner than the surroundings, and the above-mentioned during the etch back The SOG film on the seal ring on the fuse is completely removed. Therefore, the layer of the SOG film connected to the internal element from the fuse opening is divided on the seal ring, so that the intrusion of moisture from the fuse opening through the SOG film on the fuse can be blocked. (For example, see Patent Document 1)

JP 05-21605 A

  However, in this method, the convex step on the seal ring between the fuses is not necessarily a step higher than the surroundings, and the SOG film may remain depending on the conditions. If the SOG film remains on the seal ring between the fuses, the SOG film exposed on the side surface of the fuse opening is connected to the SOG film remaining on the seal ring between the fuses and fuses. Moisture directly enters the internal element from the fuse opening through the SOG film, causing fluctuations in the characteristics of the internal element and corrosion. An object of the present invention is to provide a semiconductor device having a more reliable fuse structure by blocking the moisture intrusion path of the SOG film as described above.

  In order to solve the above problems, the present invention provides the following semiconductor device.

  First, a semiconductor device having a fuse, a first region connected to a convex region provided on a semiconductor substrate, a fuse wiring provided across the convex region, and fuse terminals provided at both ends of the fuse wiring. A semiconductor device including a metal wiring and a fuse opening provided above the fuse wiring and provided in the convex region smaller than the convex region in plan view.

Further, the film thickness of the convex region of the semiconductor device is set to be larger than the film thickness of the first metal wiring.
The convex region is a semiconductor device made of an insulating film.

  With the above configuration, since no SOG film remains on the fuse, there is no risk of moisture entering the internal element from the fuse opening even after fuse trimming, and the semiconductor has stable characteristics over a long period of time. It can be a device.

It is a top view of the fuse concerning the embodiment of the present invention. It is a cross-sectional schematic diagram of the fuse showing the embodiment of the present invention (AA ′ cross-section of FIG. 1). FIG. 2 is a schematic cross-sectional view of the fuse showing the embodiment of the present invention (cross-section BB ″ in FIG. 1). (A) It is a figure which shows the manufacture flow of the fuse which shows embodiment of this invention (AA 'cross section of FIG. 1). (B) It is a figure which shows the manufacture flow of the fuse which shows the 1st Embodiment of this invention (BB 'cross section of FIG. 1). (A) It is a figure (AA 'cross section of FIG. 1) which shows the manufacture flow of the fuse which shows embodiment of this invention following FIG. (B) FIG. 5 is a diagram illustrating a manufacturing flow of the fuse showing the embodiment of the present invention (cross-section BB ′ in FIG. 1) following FIG. 4. (A) It is a figure (AA 'cross section of FIG. 1) which shows the manufacture flow of the fuse which shows embodiment of this invention following FIG. (B) It is a figure which shows the manufacture flow of the fuse which shows embodiment of this invention following FIG. 5 (BB 'cross section of FIG. 1).

  FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.

  A semiconductor device having a fuse consisting of a fuse wiring and a fuse terminal, wherein a TEOS film 14 underlaying a convex region is provided below the fuse wiring 4, and the fuse wiring 4 is provided so as to straddle the TEOS film 14. . A fuse opening 13 in a region smaller than the TEOS film 14 is provided above the fuse wiring 4. Further, the first metal wiring 7 is electrically connected to the fuse terminals 15 provided at both ends of the fuse wiring 14 in the region where the TEOS film 14 is not present. Here, the TEOS film 14 is formed to be thicker than the first metal wiring 7.

  FIG. 2 is a schematic cross-sectional view taken along the line AA ′ of FIG.

  An insulating film 2 is provided on the silicon substrate 1, and a convex region made of the TEOS film 14 is provided on the insulating film 2 so as to overlap with the region of the fuse opening 13. A fuse wiring 4 is provided via a gate insulating film 3 covering the insulating film 2 and the TEOS film 14, and an oxide film 5 is covered on the fuse wiring 4 and the gate insulating film 3. A first interlayer insulating film 6 is provided on the oxide film 5, and fuse terminals 15 and first metal wiring 7 provided at both ends of the fuse wiring 4 through contact holes formed in the first interlayer insulating film 6. Are electrically connected. A second interlayer insulating film 8, an SOG film 9, and a third interlayer insulating film 10 are provided on the first metal wiring 7. However, since the SOG film 9 is formed so as to be accumulated only in the recess, the TEOS It does not exist in a certain area of the film 14. Therefore, the SOG film 9 is not exposed in the region of the fuse opening 13.

  Although not shown, a via hole is formed in a part of the second interlayer insulating film 8, the third interlayer insulating film 10, and the oxide film 5 to reach the first metal wiring 7 through the third interlayer insulating film 8, On the interlayer insulating film 10, a second metal wiring that is joined to the first metal wiring 7 through a via hole is provided. A passivation film 11 and a polyimide film 12 are provided on the second metal wiring and the third interlayer insulating film 10, the passivation film 11 and the polyimide film 12 are removed at the fuse opening 13, and a third film is formed on the bottom surface of the fuse opening. The interlayer insulating film 10 is exposed.

  Below the fuse opening 13, the fuse wiring 4 is provided via the third interlayer insulating film 10 and the oxide film 5. In the subsequent fuse trimming process, the fuse wiring 4 is cut by laser light incident from the fuse opening 13 to obtain a desired resistance. In the present invention, the semiconductor device having the fuse having the above-described shape is used. Therefore, even if the third interlayer insulating film, the oxide film 5 and a part of the fuse wiring are removed in the fuse trimming process, the SOG film 9 is not exposed. For this reason, there is no concern that moisture enters the internal element from the fuse opening through the SOG film, causing the characteristic fluctuation and corrosion of the internal element, and a semiconductor device having stable characteristics over a long period of time is obtained. it can. Furthermore, since there is a thick TEOS film 14 under the fuse wiring 4, it also has an effect of suppressing the propagation of laser light damage to the semiconductor substrate 1 and internal elements.

FIG. 3 is a schematic cross-sectional view taken along the line BB ′ of FIG.
A TEOS film 14 is laid under the fuse opening 13 so as to overlap with the fuse opening 13. In addition to the fuse wiring 4, the oxide film 5, the first interlayer insulating film 6, and the second interlayer insulating film 8 are formed between the third interlayer insulating film 10 and the TEOS film 14 on the bottom surface of the fuse opening 13. Thus, the SOG film 9 does not exist. The SOG film 9 is only located in the recess of the internal element away from the fuse opening 13 and the TEOS film 14, and the third interlayer insulating film, the oxide film 5 and a part of the fuse wiring are removed in the fuse trimming process. However, there is no concern that moisture is caused to the internal element through the SOG film.

Next, a manufacturing method will be described with reference to FIGS. 4 to 6 showing a manufacturing flow of a semiconductor device showing an embodiment of the present invention.
For example, on the surface of a P-type silicon substrate 1 having a resistance of 20 to 30 Ωcn, the insulating film 2 is formed using a thermal oxidation method with an oxide film having a thickness of 6000 mm, for example. Next, the TEOS film 14 is deposited using a CVD method at 7000 mm, for example, and then the gate oxide film 3 is formed using a thermal oxidation method with an oxide film having a thickness of 200 mm, for example. Next, as the fuse wiring 4, for example, polycrystalline silicon is deposited by a CVD method with a film thickness of 4000 mm, and then the resistance is reduced by on-implantation, and then formed into a desired shape using photolithography and dry etching.

  Next, as the oxide film 5, for example, a TEOS film is deposited with a thickness of 1000 mm by a CVD method. Next, as the first interlayer insulating film 6, for example, a BPSG film is deposited to a thickness of 5000 mm by the CVD method. Next, contact opening for joining the first metal wiring 7 and the fuse terminals 15 at both ends of the fuse wiring 4 is performed using photolithography and dry etching (see FIG. 4).

  Next, the first metal wiring 7 is deposited using a sputtering method with an Al—Si—Cu film having a thickness of 5000 mm, for example, and formed into a desired shape using photolithography and dry etching. Next, the second interlayer insulating film 8 is deposited as a TEOS film, for example, with a film thickness of 7000 mm by the CVD method. Next, the SOG film 9 is formed by spin coating, for example, with a thickness of 3000 mm (see FIG. 5).

  Next, the SOG film 9 is etched back to the surface of the first metal wiring by using dry etching, for example. Next, for example, a TEOS film 4000 is deposited as the third interlayer insulating film 10 by using the CVD method. Although not shown, after forming a via hole that reaches the first metal wiring 7 through the second interlayer insulating film 8, the third interlayer insulating film 9, and the oxide film 5, the first metal is formed through the via hole. A second metal wiring joined to the wiring 7 is formed on the third interlayer insulating film 10. Next, as the passivation film 11, for example, a nitride film is deposited to a thickness of 9500 mm by using the CVD method. Next, the polyimide film 12 is formed by spin coating with a film thickness of 12 μm, for example, and only the region of the fuse opening 13 is removed using photolithography (see FIG. 6).

  Next, using the polyimide film 12 as a mask, the passivation film 11, the third interlayer insulating film 10, and the first interlayer insulating film 6 are removed by dry etching, whereby the semiconductor device shown in FIG. 1 can be obtained.

Reference Signs List 1 silicon substrate 2 insulating film 3 gate oxide film 4 fuse wiring 5 oxide film 6 first interlayer insulating film 7 first metal wiring 8 second interlayer insulating film 9 SOG film 10 third interlayer insulating film 11 passivation film 12 polyimide film 13 fuse Opening 14 TEOS film 15 Fuse terminal

Claims (3)

A semiconductor substrate;
An insulating film provided on the semiconductor substrate;
A convex region provided so as to overlap the insulating film including a region to be a fuse opening;
A fuse wire which is provided on the insulating film across the front Kitotsu region,
A first interlayer insulating film overlying the fuse wiring,
Electrically connected to that first metal wiring and the fuse terminals provided at both ends of the fuse wire through a contact hole formed in the first interlayer insulating film,
A second interlayer insulating film provided on the first metal wiring and the first interlayer insulating film and an SOG film provided in a recess of the second interlayer insulating film;
A third interlayer insulating film provided on the planarized SOG film and the second interlayer insulating film;
A passivation film provided on the third interlayer insulating film;
Removing the passivation film, and in a plan view, the fuse opening provided in the convex region smaller than the convex region;
Tona is,
A semiconductor device characterized in that the SOG film does not exist on the convex region .   The semiconductor device according to claim 1, wherein the film thickness of the convex region is larger than the film thickness of the first metal wiring. The semiconductor device according to claim 1, wherein the convex region is made of an insulating film.

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