JP3459529B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and more particularly to a DRAM (Dynamic Random).
The present invention relates to a bonding pad forming technique in a multilayer wiring structure such as an access memory) process.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit device has a multi-layered structure, and a flattening process of a semiconductor substrate using an SOG film (spin on glass) is frequently performed. Conventional DR
Some bonding pads in a multi-layer wiring structure such as an AM process have a structure in which two metal wiring layers are stacked on one metal wiring layer.

That is, as shown in FIG. 9, a first-layer metal wiring 53 is formed on a base film 52 formed on a semiconductor substrate 51, and a TEOS film (tetraethoxysilane) 54 is formed on the metal wiring 53. , An SOG film (spin on glass) 55 and a TEOS film 56 are formed, and then a contact hole 58 is formed in the interlayer insulating film 57, and the metal wiring of the first layer is formed through the contact hole 58. The metal wiring 59 of the second layer is formed so as to overlap 53, and the bonding pad 60 is formed from the metal wiring 53 of the first layer and the metal wiring 59 of the second layer.

[0004]

In the step of forming the bonding pad 60 described above, in order to achieve planarization, S
When the etchback of the OG film 55 is performed, if the etchback amount is reduced and the planarization is prioritized, as shown in FIG. 8, the SOG is formed on the metal wiring 53 of the first layer (contact hole 58 forming region). Since the film 55 remains, when the contact hole 58 is formed in a later step, the SOG film 55 is exposed on the side wall of the contact hole 58 as shown in FIG.
Therefore, the life of the second-layer metal wiring 59 is shortened due to degassing from the SOG film 55. In particular, a large current may flow through the bonding pad lead-out portion, and as described above, exposing the SOG film to this portion is a serious problem. However, if the etch back amount is increased, the planarization will be impaired. Therefore, conventionally, there has been no effective means for solving all of these problems.

The present applicant has already applied for a technique in which a dummy pattern is provided under the contact hole in order to eliminate the exposure of the SOG film in the contact hole in the peripheral circuit portion in the DRAM process (special feature). Wishhei 8-831
It is described in the specification attached to No. 8. ). However, even if this technique is applied to the bonding pad portion, the problem that the SOG film is exposed cannot be solved. That is, since the bonding pad portion has a large area of the first layer metal wiring, a dummy pattern under the metal wiring as shown in the technique of the prior application (see the dummy pattern 61 shown by dotted lines in FIGS. 8 and 9). The metal wiring of the first layer is entirely lifted up even if is installed, and it is not possible to reduce the accumulation of the SOG film.
As shown in, the SOG film 55 is left on the metal wiring 53 of the first layer (contact hole formation region) without interruption,
I couldn't solve the above problem.

Therefore, the present invention relates to the formation of the bonding pad in the multi-layer wiring structure. Even if the etch back amount of the SOG film is reduced so as not to impair the planarization, the S in the contact hole portion for forming the bonding pad is formed.
It prevents the OG film from being exposed and allows the second layer near the bonding pad to be exposed.
It is an object of the present invention to solve the problem of deterioration of wiring life of metal wiring of a layer.

[0007]

Therefore, in a semiconductor integrated circuit device of the present invention, a multilayer wiring structure including at least an SOG film in an interlayer insulating film between a first layer metal wiring and a second layer metal wiring. In the semiconductor integrated circuit device, the dummy pattern is arranged below the peripheral edge of the bonding pad, and the peripheral edge of the bonding pad is lifted.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a dummy pattern is formed in a bonding pad forming region on a base film deposited on a semiconductor substrate so as to surround at least a lower peripheral portion of the bonding pad. After the entire surface is covered with the interlayer insulating film, the first layer metal wiring is formed. Then, an interlayer insulating film including at least an SOG film is formed so as to cover the metal wiring of the first layer, a contact hole is formed in the interlayer insulating film in the bonding pad formation region, and then the contact hole is formed. By forming the second-layer metal wiring contacting the first-layer metal wiring via the bonding pad, the bonding pad is formed by lifting at least the peripheral portion of the bonding pad by the dummy pattern.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor integrated circuit device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings of FIGS. FIG. 1 is a first cross-sectional view showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, in which 1 is a semiconductor substrate, and a LOCOS oxide film is formed on the semiconductor substrate 1 as a base film by field oxidation, for example. After forming 2, a polysilicon film is formed on the entire surface,
The first dummy pattern 3 is formed by patterning the polysilicon film by a known patterning technique. Although the first dummy pattern 3 is essentially unnecessary as a device configuration, it is formed in order to improve the stability of the formation of the bonding pad 14 which will be formed in a later step described later. Is formed in a frame shape so as to surround the lower peripheral edge in the bonding pad 14 (see the plan view showing the positional relationship between the bonding pad 14 and the dummy patterns 3 and 5 in FIG. 7). Also,
The first dummy pattern 3 is formed of a polysilicon film for forming a gate electrode in a memory cell portion (not shown).

Next, as shown in FIG. 2, TEOS is formed on the entire surface.
Film, a first layer interlayer insulating film 4 made of a BPSG film, and then, for example, a polysilicon film and a tungsten silicide film (WSix) are formed on the interlayer insulating film 4, and then the polysilicon film and the tungsten silicide film. The second dummy pattern 5 is formed by patterning (WSix). Incidentally, although the second dummy pattern 5 is originally not necessary as the device configuration,
The dummy pattern 5 is also formed in order to improve the stability of the formation of the bonding pad 14 like the first dummy pattern 3, and the second dummy pattern 5 is also bonded in the same manner as the first dummy pattern 3. Pad 1
4 is formed so as to surround the lower part of the peripheral edge. The second dummy pattern 5 is formed of a polysilicon film for forming a bit line and a tungsten silicide film (WSix) in a memory cell portion (not shown).

Next, as shown in FIG. 3, after forming a second interlayer insulating film 6 made of a TEOS film and a BPSG film so as to cover the second dummy pattern 5, the interlayer insulating film 6 is formed. Then, the first-layer metal wiring 7 is formed. This process is
First, a titanium film (Ti film) and a titanium nitride film (TiN film) are formed as barrier metal films, and then a metal film (Al-Si-Cu film) is formed by a sputtering method to form a metal wiring of the first layer. Form 7.

Next, as shown in FIG. 4, a third interlayer insulating film 11 including a TEOS film 8, an SOG film 9 and a TEOS film 10 is formed on the metal wiring 7. In this step, first, after forming the TEOS film 8, the SOG film 9 is formed in order to improve the flatness, and the entire surface is etched back.
At this time, due to the existence of the first dummy pattern 3 and the second dummy pattern 5 described above, the contact hole 12 described later is formed.
Since the SOG film 9 in the opening portion is thin, the SOG film 9 in the peripheral portion of the bonding pad can be completely shaved off even with a small amount of etch back during the above-described entire surface etch back process (opening of the contact hole shown in FIG. 4). Terminal A
See). Then, when the TEOS film 10 is further formed,
The end A portion of the opening of the contact hole is a TEO layer of the lower layer.
The SOG film 9 does not exist in a state where the S film 8 and the upper TEOS film 10 overlap each other. Therefore, after forming a resist film (not shown) on the interlayer insulating film 11,
When the contact hole 12 for contacting is formed on the metal wiring 7 of the first layer by using the resist film as a mask, as shown in FIG.
The TEOS film 10 is formed so as to overlap the S film 8,
The SOG film 9 is retracted from the peripheral edge of the contact hole 12.

Subsequently, as shown in FIG. 6, Al- which contacts the metal wiring 7 through the contact hole 12.
Forming a second layer of metal wiring 13 made of a Si-Cu film,
By patterning the metal wiring 13 of the second layer, a bonding pad 14 composed of the metal wiring 7 of the first layer and the metal wiring 13 of the second layer overlapping the metal wiring 7 of the first layer is formed. It

As described above, in the present invention, the opening end A of the contact hole 12 formed on the first metal wiring 7 is formed.
By arranging the dummy patterns 3 and 5 below the portion, the SOG film 9 can be removed so that the SOG film 9 does not exist at the end A of the opening even with a small etch back amount, and the contact hole 12 is formed in this portion. Even if formed, SOG on the side wall
The film 9 is not exposed.

Further, although not shown, a passivation film such as a SiN film is formed to complete a semiconductor integrated circuit device having a two-layer Al wiring structure. As described above, in the present invention, the dummy patterns 3 and 5 are arranged below the peripheral edge of the bonding pad 14 and the peripheral edge of the bonding pad 14 is lifted, so that the SOG film accumulation on the bonding pad 14 can be significantly reduced as compared with the conventional case. Therefore, less SO
Even if the G film is etched back, the SOG film can be prevented from being exposed to the side wall of the contact hole 12, and the bonding pad 14
It is possible to solve the problem that the wiring life of the second-layer metal wiring 13 in the vicinity is deteriorated.

The dummy patterns 3 and 5 of the present invention are
Wiring under the first layer metal wiring, for example, a gate electrode under the first layer metal wiring in the memory cell portion in the DRAM process, bit linear film formation, etc. can be performed without increasing the number of steps for forming a film dedicated to the dummy pattern. The first dummy pattern 3 and the second dummy pattern 5 can be configured.
Are not necessarily required together, and the bonding pad 1
SO in the end A portion of the opening of the contact hole 12 for forming 4
It suffices to eliminate the accumulation of the G film, and a single structure or a two-stage structure can be freely selected. As an example of the embodiment, for example, when only the second dummy pattern 5 made of the same film as the bit linear film formation of 2500Å is selected, the line width of the dummy pattern 5 is about 4 μm.
If a line having a length of about m to 5 μm is formed in the peripheral portion of the bonding pad 14 in the shape of a frame, the SOG film 9 may not remain at the end A of the opening of the contact hole 12 as described above. It has been proved that when the line width of No. 5 becomes about 10 μm, the break of the SOG film 9 at the end A of the opening disappears and the conventional problem cannot be solved. As a matter of course, it is necessary to change the line width condition depending on the difference in the film thickness of the dummy pattern 5, and if the two-stage structure of the first dummy pattern 3 and the second dummy pattern 5 is adopted, the line of the dummy pattern The width can be made even thinner.

[0017]

As described above, according to the present invention, the dummy pattern is arranged below the peripheral edge of the bonding pad and the peripheral edge portion of the bonding pad is lifted, so that the SOG film accumulation on the bonding pad portion is much larger than the conventional one. Since it is possible to prevent the SOG film from being exposed to the side wall portion of the contact hole even with a small amount of SOG film etchback, electromigration of the wiring near the bonding pad and the second layer can be performed without impairing the planarization. It is possible to solve the problem of deterioration of the wiring life of metal wiring.

[Brief description of drawings]

FIG. 1 is a first sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device of the embodiment of the present invention.

FIG. 3 is a third cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device of the embodiment of the present invention.

FIG. 4 is a fourth cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device of the embodiment of the present invention.

FIG. 5 is a fifth cross-sectional view showing the method of manufacturing the semiconductor integrated circuit device of the embodiment of the present invention.

FIG. 6 is a sixth cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device of the embodiment of the present invention.

FIG. 7 is a plan view showing a bonding pad portion of the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a conventional semiconductor integrated circuit device.

FIG. 9 is a sectional view showing a conventional semiconductor integrated circuit device.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/60 301

Claims (4)

(57) [Claims] 1. Between a lower metal wiring and an upper metal wiring
The first insulating film, the SOG film, and the second insulating film in this order.
In a semiconductor integrated circuit device having a multilayer wiring structure having a first interlayer insulating film formed by stacking layers, bonding pads are provided on the upper layer metal wiring and the lower layer.
By forming a dummy pattern under the lower metal wiring on the periphery of the bonding pad via the second interlayer insulating film, and by lifting the peripheral portion of the bonding pad. A semiconductor integrated circuit device characterized in that the end portions of the first insulating film and the second insulating film overlap each other. Wherein said dummy pattern includes at least the
The semiconductor integrated circuit device according to claim 1, wherein the bonding pad is formed in a frame shape below a peripheral edge of the bonding pad . 3. The semiconductor integrated circuit device according to claim 1, wherein the dummy pattern is formed of the same film as the gate electrode of the memory cell portion or the bit linear film formation. 4. A bonding pad circumference is formed on a bonding pad forming region on a base film formed on a semiconductor substrate.
A step of forming a dummy pattern so as to surround the lower edge in a frame shape, a step of forming a lower layer metal wiring after covering the entire surface with a second interlayer insulating film, and a step of covering the lower layer metal wiring. At least first
The insulating film, the SOG film, and the second insulating film are laminated in this order.
A step of forming a first interlayer insulating film, and a step of forming a contact hole in the first interlayer insulating film in the bonding pad formation region and then contacting the lower metal wiring through the contact hole. By forming metal wiring, at least the bonding pad
A step of forming a peripheral edge portion of the bonding pad so that a peripheral edge portion is lifted by the dummy pattern and the end portions of the first insulating film and the second insulating film are overlapped with each other. Manufacturing method of integrated circuit device.