JP5655931B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5655931B2 JP5655931B2 JP2013504506A JP2013504506A JP5655931B2 JP 5655931 B2 JP5655931 B2 JP 5655931B2 JP 2013504506 A JP2013504506 A JP 2013504506A JP 2013504506 A JP2013504506 A JP 2013504506A JP 5655931 B2 JP5655931 B2 JP 5655931B2
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- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
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Description
図1は、実施の形態1にかかる半導体装置を示す断面図である。図1に示す半導体装置は、逆耐圧型MOSFETである。図1に示す逆耐圧型MOSFETにおいて、ドリフト層となるn型基板1のおもて面側には、pベース領域2、n+ソース領域3、n-コンタクト領域4、ゲート絶縁膜5、ゲート電極6および層間絶縁膜7などからなるMOSゲート構造が設けられている。
図9は、実施の形態2にかかる半導体装置を示す断面図である。図9に示す半導体装置は、逆耐圧型MOSFETである。実施の形態2にかかる逆耐圧型MOSFETは、実施の形態1にかかる逆耐圧型MOSFETにおいて、n型基板1の側面8にp-型半導体領域が設けられている。また、n型基板1の裏面に選択的にp-型半導体領域が設けられている。
図14は、実施の形態3にかかる半導体装置を示す断面図である。図14に示す半導体装置は、逆耐圧型MOSFETである。図14に示す逆耐圧型MOSFETは、実施の形態2にかかる逆耐圧型MOSFETにおいて、n型基板1の側面8にのみp-型半導体領域が設けられている。つまり、実施の形態3に示す逆耐圧型MOSFETには、n型基板1の裏面にp拡散領域が設けられていない。
図15は、実施の形態4にかかる半導体装置を示す断面図である。図15に示す半導体装置は、逆耐圧型IGBTである。図15に示す逆耐圧型IGBTにおいて、ドリフト層となるn型基板51のおもて面側には、pベース領域52、n+エミッタ領域53、n-コンタクト領域54、ゲート絶縁膜55、ゲート電極56および層間絶縁膜57などからなるMOSゲート構造が設けられている。また、n型基板51のおもて面側の端部には、p-型のFLR58が設けられている。
図24,25は、実施の形態5にかかる半導体装置の製造方法について示す断面図である。図24,25を参照して、実施の形態4にかかる逆耐圧型IGBTの製造方法の別の一例について示す。実施の形態5においては、実施の形態4においてチップ77の側面および裏面に同時に行っていたイオン注入78およびアニールを(図21参照)、チップ77の側面の表面層に分離層を形成するためのイオン注入およびアニールと、チップ77の裏面にコレクタ領域を形成するためのイオン注入およびアニールとに分けて行ってもよい。
次に、本発明にかかる半導体装置を作製する際のSiCウェハの割れ率を検証した。図26は、本発明にかかる半導体装置の製造方法における半導体ウェハの割れ率を示す特性図である。まず、SiCウェハを用いて、実施の形態1,2,4に従い、それぞれ逆阻止型半導体装置を作製した(以下、第1〜3の試料とする)。
次に、本発明にかかる半導体装置の逆バイアス時の電気的特性について検証した。図27,28は、本発明にかかる半導体装置の電気的特性を示す特性図である。図27には、逆バイアス印加時の測定結果を示す。図28には、順バイアス印加時の測定結果を示す。まず、実施例1と同様に、第1〜3の試料を作製した。そして、第1,2の試料において、逆バイアス電圧印加時のドレイン−ソース間電圧を測定した。第3の試料において、逆バイアス電圧印加時のコレクタ−エミッタ間電圧を測定した。図27,28において、第1〜3の試料の測定電圧を電圧Vceと示す。
13 接着層
14 支持基板
16 V溝
17 チップ
18 電極膜
Claims (7)
- 炭化珪素からなる半導体ウェハのおもて面におもて面素子構造を形成する工程と、
前記半導体ウェハの、前記おもて面素子構造が形成されたおもて面に支持基板を貼り合わせる工程と、
前記半導体ウェハに、裏面側から溝を形成する工程と、
前記溝の側壁および前記半導体ウェハの裏面に電極膜を成膜し、当該半導体ウェハと当該電極膜とによるショットキー接合を形成する工程と、
前記半導体ウェハから前記支持基板を剥離する工程と、
を含み、
前記溝を形成する工程は、
前記半導体ウェハの裏面の表面に選択的にレジストマスクを形成する工程と、
前記レジストマスクをマスクとしてドライエッチングをおこない、当該レジストマスクの開口部に露出する半導体ウェハを貫通するように除去する工程と、からなり、
前記溝の幅は、前記半導体ウェハの裏面から当該半導体ウェハの深さ方向に向かって徐々に狭くなることを特徴とする半導体装置の製造方法。 - 炭化珪素からなる第1導電型の半導体ウェハのおもて面におもて面素子構造を形成する工程と、
前記半導体ウェハの、前記おもて面素子構造が形成されたおもて面に支持基板を貼り合わせる工程と、
前記半導体ウェハに、裏面側から溝を形成する工程と、
前記溝の側壁に第2導電型不純物を注入する工程と、
前記溝の側壁に注入された第2導電型不純物を活性化し、当該溝の側壁の表面層に第2導電型の第1の半導体領域を形成する工程と、
前記半導体ウェハの裏面に電極膜を成膜し、当該半導体ウェハと当該電極膜とによるショットキー接合を形成する工程と、
前記半導体ウェハから前記支持基板を剥離する工程と、
を含み、
前記溝を形成する工程は、
前記半導体ウェハの裏面の表面に選択的にレジストマスクを形成する工程と、
前記レジストマスクをマスクとしてドライエッチングをおこない、当該レジストマスクの開口部に露出する半導体ウェハを貫通するように除去する工程と、からなり、
前記溝の幅は、前記半導体ウェハの裏面から当該半導体ウェハの深さ方向に向かって徐々に狭くなることを特徴とする半導体装置の製造方法。 - 前記半導体ウェハに前記溝を形成した後、前記半導体ウェハの裏面に選択的に第2導電型不純物を注入する工程と、
前記半導体ウェハの裏面に注入された第2導電型不純物を活性化し、当該半導体ウェハの裏面の表面層に選択的に第2導電型の第2の半導体領域を形成する工程と、
をさらに含むことを特徴とする請求項2に記載の半導体装置の製造方法。 - 前記おもて面素子構造は、電界効果トランジスタのおもて面素子構造であり、
前記電極膜は、ドレイン電極であることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置の製造方法。 - 炭化珪素からなる第1導電型の半導体ウェハのおもて面におもて面素子構造を形成する工程と、
前記半導体ウェハの、前記おもて面素子構造が形成されたおもて面に支持基板を貼り合わせる工程と、
前記半導体ウェハに、裏面側から溝を形成する工程と、
前記半導体ウェハの裏面に第2導電型不純物を注入する工程と、
前記半導体ウェハの裏面に注入された第2導電型不純物を活性化し、当該半導体ウェハの裏面の表面層に第2導電型の第3の半導体領域を形成する工程と、
前記溝の側壁に第2導電型不純物を注入する工程と、
前記溝の側壁に注入された第2導電型不純物を活性化し、当該溝の側壁の表面層に第2導電型の第1の半導体領域を形成する工程と、
前記溝の側壁および前記半導体ウェハの裏面に電極膜を成膜し、前記第1の半導体領域および前記第3の半導体領域と当該電極膜とによるショットキー接合を形成する工程と、
前記半導体ウェハから前記支持基板を剥離する工程と、
を含み、
前記溝を形成する工程は、
前記半導体ウェハの裏面の表面に選択的にレジストマスクを形成する工程と、
前記レジストマスクをマスクとしてドライエッチングをおこない、当該レジストマスクの開口部に露出する半導体ウェハを貫通するように除去する工程と、からなり、
前記溝の幅は、前記半導体ウェハの裏面から当該半導体ウェハの深さ方向に向かって徐々に狭くなることを特徴とする半導体装置の製造方法。 - 前記半導体ウェハの裏面に第2導電型不純物を注入するとともに、前記溝の側壁に第2導電型不純物を注入した後、前記半導体ウェハの裏面および前記溝の側壁に注入された第2導電型不純物を活性化することを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記おもて面素子構造は、絶縁ゲート型バイポーラトランジスタのおもて面素子構造であり、
前記電極膜は、コレクタ電極であることを特徴とする請求項5または6に記載の半導体装置の製造方法。
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JP6102171B2 (ja) * | 2012-10-17 | 2017-03-29 | 富士電機株式会社 | 炭化珪素mos型半導体装置の製造方法 |
EP3508450A1 (en) | 2013-03-15 | 2019-07-10 | Nanoco Technologies, Ltd. | Cu2xsnq4 nanoparticles |
JP6221710B2 (ja) | 2013-12-10 | 2017-11-01 | 住友電気工業株式会社 | 半導体装置の製造方法 |
JP6335717B2 (ja) * | 2014-08-20 | 2018-05-30 | 昭和電工株式会社 | 半導体デバイス |
JP2017103406A (ja) * | 2015-12-04 | 2017-06-08 | 株式会社ディスコ | ウエーハの加工方法 |
CN114823859A (zh) | 2015-12-11 | 2022-07-29 | 罗姆股份有限公司 | 半导体装置 |
EP3182463A1 (en) * | 2015-12-17 | 2017-06-21 | ABB Technology AG | Reverse blocking power semiconductor device |
WO2018034127A1 (ja) * | 2016-08-19 | 2018-02-22 | ローム株式会社 | 半導体装置 |
WO2018034250A1 (ja) * | 2016-08-19 | 2018-02-22 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
JP7135443B2 (ja) * | 2018-05-29 | 2022-09-13 | 富士電機株式会社 | 炭化ケイ素半導体装置及びその製造方法 |
US11532551B2 (en) * | 2018-12-24 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package with chamfered semiconductor device |
CN113784663A (zh) | 2019-05-01 | 2021-12-10 | 巴德阿克塞斯系统股份有限公司 | 穿刺装置、包括该穿刺装置的穿刺系统及其方法 |
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