JP5513416B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

(In the present invention, it means a broad S emiconductor O n I nsulator, does not mean narrow sense S ilicon O n I nsulator) The present invention SOI relates to a semiconductor integrated circuit structure, particularly in the semiconductor substrate (bulk wafer) The present invention relates to forming a CMOS type semiconductor integrated circuit composed of N-channel and P-channel MIS field effect transistors with increased mobility of electrons and holes by an easy manufacturing process.

Figure 31 is a schematic side sectional view of a conventional semiconductor device, SIMOX (S eparation by Im planted Ox ygen) method CMOS type semiconductor consisting of N-channel and P-channel MIS field effect transistor of the strained SOI structure formed using 1 shows a part of an integrated circuit, 61 is a p-type Si substrate, 62 is a p-type SiGe layer, 63 is an n-type SiGe layer, 64 is a buried silicon oxide film (SiO ₂ ), and 65 is an element isolation region (SiO ₂ ), 66 is a p-type strained Si layer, 67 is an n-type strained Si layer, 68 is an n ⁺ -type source region, 69 is an n-type source region, 70n-type drain region, 71n ⁺ -type drain region, 72p ⁺ Type drain region, 73p ⁺ type source region, 74 is a gate oxide film, 75 is a gate electrode, 76 is a sidewall, 77 is a PSG film, 7 Reference numeral 8 denotes an insulating film, 79 denotes a barrier metal, 80 denotes a conductive plug, 81 denotes an interlayer insulating film, 82 denotes a barrier metal, 83 denotes a Cu wiring, and 84 denotes a barrier insulating film.
In the figure, an element is introduced through a buried oxide film 64 (SIMOX method) formed by high-temperature heat treatment by implanting oxygen ions into a p-type SiGe layer 62 laminated on a p-type silicon substrate 61. A p-type strained SOI substrate composed of a p-type strained Si layer 66 on a p-type SiGe layer 62 isolated in an island shape by an isolation region (SiO ₂ ) 65 and n on the n-type SiGe layer 63. An n-type strained SOI substrate composed of a strain-type strained Si layer 67 is formed. In the p-type strained SOI substrate, n-type source / drain regions (69, 70) self-aligned with the gate electrode 75 are formed on the sidewalls 76. MIS field effect tiger LDD (L ightly D oped D rain ) structure of the n-channel consisting of self-aligned formed ^{n +} -type source and drain regions (68, 71) Register is formed, consisting of the p ⁺ -type source and drain regions are self-aligned formed in the side wall 76 which is self-aligned formed on the gate electrode 75 (72, 73) in the n-type strained SOI substrate of P-channel MIS field effect of A transistor is formed. Further, a Cu wiring 83 having a barrier metal 82 is connected to the n ⁺ type source / drain region (68, 71) and the p ⁺ type source / drain region (72, 73) through a barrier metal 79 and a conductive brag 80, respectively. A desired voltage is applied.
Therefore, the junction drain can be formed by forming a source / drain region surrounded by an insulating film, the breakdown voltage of the source / drain region can be improved, the threshold voltage can be reduced by improving the subthreshold characteristics, and the contact region to the strained SOI substrate can be removed. Thus, compared to a CMOS comprising MIS field effect transistors formed on a normal bulk wafer, the speed, power consumption and integration can be increased.
In addition, since a MIS field effect transistor can be formed on a strained SOI substrate in which a strained Si layer is laminated on a SiGe layer, strain can be formed in the Si layer due to tensile stress caused by the SiGe layer having a large lattice constant, thereby increasing mobility. , Speeding up becomes possible.
However, since both the N-channel MIS field-effect transistor and the P-channel MIS field-effect transistor are formed on the strained SOI substrate in which the strained Si layer is laminated on the SiGe layer, the mobility of electrons and holes can be improved. Although there is a difference of about 4 times in the mobility of electrons and holes from the beginning, although there is a high speed, there is a disadvantage that the on / off special balance of switching speed is bad. The channel width of the MIS field effect transistor has to be widened, making it difficult to achieve high integration.
The N channel MIS field effect transistor and the P channel MIS field effect transistor both form a strained Si layer. However, in the plane orientation of the Si layer that increases the hole mobility of the P channel MIS field effect transistor, the N channel MIS There is also a drawback that the mobility of electrons in the field effect transistor is lowered.
In addition, since the SIMOX method is used as a means for creating an SOI structure, it is necessary to purchase an extremely expensive high-dose ion implantation machine, and a long-time manufacturing process for implanting high-dose oxygen ions. The problem of high cost due to the need for a large-diameter wafer of 10 inches to 12 inches, the problem of instability of characteristics due to the repair of crystal defects by oxygen ion implantation, and the thick embedding even when ion implantation of high dose oxygen There are also disadvantages such as the problem that it is difficult to reduce the capacitance with the lower layer region because an oxide film cannot be obtained.
Also, no measures have been taken against the problem that the speed characteristics at high temperatures deteriorate due to the temperature rise caused by the heat generated by the speedup of the MIS field effect transistor, and the speed characteristics in the guaranteed temperature range cannot be guaranteed. It was.

Applied Physics Vol.72 No.9 (2003) 1130-1135

The problem to be solved by the present invention, as shown in the conventional example,
(1) Since the SOI structure is formed by the SIMOX method, the cost is considerably high, and it can be used only for special purpose products with high added value, and the technology applicable to inexpensive general-purpose products is scarce.
(2) Since it is difficult to control the thinning of the SOI substrate in a large-diameter wafer, it is difficult to form a fully depleted SOI substrate, and it is difficult to obtain stability of characteristics of a large number of built-in MIS field effect transistors. .
(3) In the strained Si layer, the plane orientation that increases the mobility of electrons and holes is different, and in the plane orientation that increases the mobility of holes in the P-channel MIS field effect transistor, the mobility of electrons in the N-channel MIS field effect transistor. Will decrease.
(4) Due to the temperature rise due to heat generated by increasing the speed of the MIS field-effect transistor, the mobility is lowered due to carrier scattering and the like, and the speed characteristics at high temperatures are deteriorated, so it is difficult to guarantee speed in the guaranteed temperature range. .
Such problems are becoming more prominent, and it is difficult to achieve higher speed, higher performance, and higher reliability simply by forming a MIS field effect transistor having a fine strained SOI structure with the current technology. is there.

The above problem is that a second semiconductor layer (Ge) made of a second semiconductor (Ge) selectively bonded to a semiconductor substrate (Si) made of a first semiconductor (Si) through an insulating film. Ge) is provided with a MIS field effect transistor of one conductivity type (P channel), and a part of the semiconductor substrate where the second semiconductor layer is not provided via the insulating film partially having a hole. An MIS field effect transistor of an opposite conductivity type (N channel) is provided in a first semiconductor layer (a semiconductor layer made of a SiGe layer sandwiching a strained Si layer from the left and right) provided by selective epitaxial growth from the semiconductor substrate. This is solved by the semiconductor device of the present invention.

As described above, according to the present invention, two different semiconductor layers (single crystal Ge) are formed on an Si substrate via an insulating film by an easy process using a Si substrate bonded with a single crystal Ge substrate. Layer and a SiGe layer sandwiching a single crystal strained Si layer from the left and right), and a P-channel MIS field-effect transistor or an N-channel MIS field-effect transistor can be formed on each of these two semiconductor layers. Characteristics of the SOI structure MIS field effect transistor, that is, the reduction of the junction capacitance of the source / drain region (substantially zero), the reduction of the depletion layer capacitance, the breakdown voltage improvement of the source / drain region and the improvement of the subthreshold characteristic. Reduction is possible.
The thickness of the SiGe layer (first semiconductor layer) sandwiching the bonded Ge layer (second semiconductor layer) and the strained Si layer from the left and right is determined by the thickness of the growing silicon nitride film (Si ₃ N ₄ ). Therefore, it is possible to easily form a fully-depleted thin-film semiconductor layer that can be used for manufacturing with a large-diameter wafer.
In a P-channel MIS field effect transistor, a channel region can be formed in the bonded single crystal Ge layer. In an N-channel MIS field effect transistor, the crystallinity right above the vacancy without an underlying insulating film is good. Since a channel region can be formed only in a single-crystal strained Si layer, a CMOS type semiconductor comprising a short-channel N-channel and P-channel MIS field-effect transistor formed in a BODOSOLESOI structure (name details will be described later) having stable characteristics An integrated circuit can be formed.
In addition, a P-channel MIS field effect transistor can be formed in a Ge layer (about 5 times that formed in a Si layer) that can greatly improve the hole mobility, and a strained Si layer that can increase the electron mobility is sandwiched between them. Since an N-channel MIS field effect transistor can be formed in the SiGe layer, it is possible to obtain an extremely well-balanced high-speed CMOS that is not affected by the characteristics of the other MIS field effect transistor.
In addition, the capacitance between the channel region and the semiconductor substrate when the N-channel MIS field effect transistor is operating can be greatly reduced by providing a hole as compared with the SOI structure of a normal silicon oxide film. Is possible.
Also, by providing a heat-dissipating hole immediately below the strained Si layer on which the N-channel MIS field effect transistor is formed, the temperature rise due to heat generated by the high-speed operation of the N-channel MIS field-effect transistor is suppressed, and It is also possible to improve the deterioration of speed characteristics.
As a result, high-speed, high-capacity communication, portable information terminals, various electronic mechanical devices, space-related devices, etc. can be manufactured, and it is possible to manufacture semiconductor integrated circuits with a wide guaranteed temperature range. A CMOS type semiconductor integrated circuit having integration can be obtained.
The present inventors named the art of bonding on the insulating film and the two-step transverse (horizontal) direction epitaxial semiconductor layer (Bo nding S emiconductor and Do uble L ateral E pitaxial S emiconductor O n I nsulator) structure, hereinafter the The technology is abbreviated as BODOSOLESOI.

Schematic side sectional view of the first embodiment of the semiconductor device of the present invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of 1st Example in the semiconductor device of this invention Schematic side sectional view of the second embodiment of the semiconductor device of the present invention Schematic side sectional view of the third embodiment of the semiconductor device of the present invention Schematic side sectional view of the fourth embodiment of the semiconductor device of the present invention Schematic side sectional view of the fifth embodiment of the semiconductor device of the present invention. Schematic side sectional view of the sixth embodiment of the semiconductor device of the present invention. Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Process sectional drawing of the manufacturing method of the 6th Example in the semiconductor device of this invention Schematic side sectional view of the seventh embodiment of the semiconductor device of the present invention Schematic side sectional view of a conventional semiconductor device

A Ge layer (second semiconductor layer) which is bonded to a silicon (Si) substrate via a silicon nitride film and a silicon oxide film, thinned, and insulated and isolated in an island shape is provided on the Ge layer. A P-channel MIS electric field in which a gate electrode is provided via a gate insulating film, a side wall is provided on the side wall of the gate electrode, and a p ⁺ -type source / drain region is provided in the Ge layer in self-alignment with the side wall. An effect transistor is formed, and on the other hand, an epitaxial structure comprising a SiGe layer on both sides sandwiching a strained Si layer directly above the vacancy through a silicon nitride film on a Si substrate and a silicon oxide film having a vacancy in part. A semiconductor layer (first semiconductor layer) is provided so as to be insulated and isolated in an island shape, a gate electrode is provided directly above the strained Si layer via a gate insulating film, and a gate electrode is provided on the side wall of the gate electrode. The SiGe layer is provided with an n-type source / drain region self-aligned with the gate electrode and the n ⁺ -type source / drain region is provided with a side wall, and an approximately channel region is formed in the strained Si layer. A CMOS type semiconductor integrated circuit having a high mobility in which an N-channel MIS field effect transistor having an LDD structure is formed.

Hereinafter, the present invention will be specifically described with reference to the illustrated embodiments.
Throughout the drawings, the same object is denoted by the same reference numeral. However, the diagonal lines in the side sectional view are shown only on the main insulating film, and the wiring is drawn with a slight back-and-forth displacement, and the horizontal and vertical sizes are accurate to show the main part of the invention. The dimensions are not shown.
1 to 12 show a first embodiment of a semiconductor device according to the present invention. FIG. 1 is a schematic sectional side view, and FIGS.
FIG. 1 shows a part of a CMOS type semiconductor integrated circuit including a short-channel N-channel and P-channel MIS field-effect transistor formed using a silicon (Si) substrate and having a BODOSOLESOI structure, where 1 is 10 ¹⁵ cm. P-type silicon (Si) substrate of about ⁻³ , 2 is a silicon nitride film (Si ₃ N ₄ ) of about 50 nm, 3 is a silicon oxide film (SiO ₂ ) of about 200 nm, and 4 is an element isolation region of about 50 nm silicon nitride film _{(Si 3 N} 4), it is pore 5, 6 ¹⁰ 17 ^{cm -3} of about p-type lateral (horizontal) direction the epitaxial SiGe layer, 7 ¹⁰ 17 ^{cm -3} of about p-type beside ( horizontal) epitaxial strained Si layer, Ge layer bonded to n-type of about ¹⁰ 17 ^{cm -3} is 8, 9 buried silicon oxide film _(SiO 2), 10 10 ²⁰ cm ^-3 of about ^{n +} -type source region, n-type source region of about 5 × ¹⁰ 17 ^{cm -3} is 11, 12 about 5 × ¹⁰ 17 ^{cm -3} of n-type drain region, 13 ¹⁰ 20 cm ^-3 of ^{n +} -type drain region, the ¹⁰ 20 ^{cm -3} of about ^{p +} -type drain region 14, 15 ¹⁰ 20 ^{cm -3} of about ^{p +} -type source region 16 is 5nm approximately the gate oxide film (HfO ₂ ), 17 is a gate electrode (WSi / polySi) having a length of about 35 nm and a thickness of about 100 nm, 18 is a sidewall (SiO ₂ ) of about 25 nm, 19 is a phosphosilicate glass (PSG) film of about 400 nm, and 20 is 20nm approximately silicon nitride film _{(Si 3} N 4), 21 is 10nm approximately barrier metal (TiN), 22 is a conductive plug (W), 23 is 500nm approximately interlayer insulation Film (SiOC), 24 is 10nm approximately barrier metal (TaN), 25 is 500nm approximately Cu wiring (including Cu seed layer), 26 denotes a 20nm approximately barrier insulating film _(Si 3 _{N 4).}
In the figure, a silicon nitride film (Si ₃ N ₄ ) 2 is provided on the p-type silicon substrate 1 on the left half of the p-type silicon substrate 1, and on the silicon nitride film (Si ₃ N ₄ ) 2. the part silicon oxide film _(SiO 2) 3 having pores 5 are provided, on the silicon oxide film _(SiO 2) 3 sandwiches the strained Si layer 7 of p-type immediately above the holes 5, A semiconductor layer (a first semiconductor layer formed by epitaxial growth in the lateral (horizontal) direction) having a structure having p-type SiGe layers 6 on the left and right sides is provided in an island shape. A gate electrode (WSi / polySi) 17 is provided directly above the p-type strained Si layer 7 via a gate oxide film (HfO ₂ ) 16, and a sidewall 18 is provided on the side wall of the gate electrode 17. The SiGe layer 6 is provided with an approximately n-type source / drain region (11, 12) and an n ⁺ -type source / drain region (10, 13), and the p-type strained Si layer 7 is provided with an approximate channel region. (In actuality, the n-type source / drain regions (11, 12) are slightly diffused in the lateral direction, but at least the p-type strained Si layer 7 immediately above the holes 5 is affected by the lower silicon oxide film. The n ⁺ -type source / drain regions (10, 13) are connected to the barrier metal (TaN) via the conductive plug (W) 22 having the barrier metal (TiN) 21 respectively. ) An N-channel MIS field effect transistor having an LDD structure to which a Cu wiring 25 having 24 is connected is formed. On the other hand, the right half of the silicon substrate 1 of p-type, silicon nitride film _{(Si 3 N} 4) 2 is provided on the silicon substrate 1 of p-type, on the silicon nitride film _{(Si 3 N} 4) 2 is A silicon oxide film (SiO ₂ ) 3 is provided, and an n-type Ge layer 8 (second semiconductor layer) bonded and isolated in an island shape is provided on the silicon oxide film (SiO ₂ ) 3. It has been. A gate electrode (WSi / polySi) 17 is provided on a part of the n-type Ge layer 8 via a gate oxide film (HfO ₂ ) 16, and a sidewall 18 is provided on the side wall of the gate electrode 17. the Ge layer 8 forms self-aligned ^{p +} -type source and drain regions (14, 15) is provided on the side walls 18, the ^{p +} -type source and drain regions (14, 15), each barrier metal (TiN) A P-channel MIS field effect transistor is formed in which a Cu wiring 25 having a barrier metal (TaN) 24 is connected through a conductive plug (W) 22 having 21. (The Cu wiring 25 is also connected to the gate electrode 17 but is omitted in FIG. 1).
Therefore, two different semiconductor layers (single crystal Ge) are formed on the Si substrate through an insulating film by an easy process (a manufacturing method will be described in detail later) using a Si substrate on which a single crystal Ge substrate is bonded. Layer and a SiGe layer sandwiching a single crystal strained Si layer), a P-channel MIS field-effect transistor or an N-channel MIS field-effect transistor can be formed in each of these two semiconductor layers, and a fully depleted SOI Characteristics peculiar to the MIS field effect transistor having the structure, that is, reduction of the junction capacitance of the source / drain region (substantially zero), reduction of the depletion layer capacitance, improvement of the breakdown voltage of the source / drain region and reduction of the threshold voltage due to improvement of the subthreshold characteristics Is possible.
The thickness of the SiGe layer (first semiconductor layer) sandwiching the bonded Ge layer (second semiconductor layer) and the strained Si layer can be determined by the thickness of the grown silicon nitride film (Si ₃ N ₄ ). Therefore, it is possible to easily form a fully-depleted thin-film semiconductor layer that can be manufactured by a large-diameter wafer.
In a P-channel MIS field effect transistor, a channel region can be formed in the bonded single crystal Ge layer. In an N-channel MIS field effect transistor, the crystallinity right above the vacancy without an underlying insulating film is good. Since a channel region can be formed only in a single-crystal strained Si layer, it is possible to form a CMOS type semiconductor integrated circuit composed of short-channel N-channel and P-channel MIS field-effect transistors formed in a BODOSOLESOI structure having stable characteristics. Is possible.
In addition, a P-channel MIS field effect transistor can be formed in a Ge layer (about 5 times that formed in a Si layer) that can greatly improve the hole mobility, and a strained Si layer that can increase the electron mobility is sandwiched between them. Since an N-channel MIS field effect transistor can be formed in the SiGe layer, it is possible to obtain an extremely well-balanced high-speed CMOS that is not affected by the characteristics of the other MIS field effect transistor.
In addition, the capacitance between the channel region and the semiconductor substrate when the N-channel MIS field effect transistor is operating can be greatly reduced by providing a hole as compared with the SOI structure of a normal silicon oxide film. Is possible.
Also, by providing a heat-dissipating hole immediately below the strained Si layer on which the N-channel MIS field effect transistor is formed, the temperature rise due to heat generated by the high-speed operation of the N-channel MIS field-effect transistor is suppressed, and It is also possible to improve the deterioration of speed characteristics.
As a result, high-speed, high-capacity communication, portable information terminals, various electronic mechanical devices, space-related devices, etc. can be manufactured, and it is possible to manufacture semiconductor integrated circuits with a wide guaranteed temperature range. A CMOS type semiconductor integrated circuit having integration can be obtained.

  Next, the manufacturing method of the first embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. However, here, only the manufacturing method related to the formation of the semiconductor device of the present invention is described, and the description of the manufacturing method related to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. To do.

FIG.
A silicon oxide film (SiO ₂ ) 3 of about 200 nm is grown on the n-type Ge substrate 8 by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 2 is grown by about 50 nm by chemical vapor deposition. Next, the n-type Ge substrate in which the silicon oxide film (SiO ₂ ) 3 and the silicon nitride film (Si ₃ N ₄ ) 2 are grown on the p-type Si substrate 1 by heat treatment at a temperature of 900 ° C. or less upside down. 8 is pasted together. Then chemical mechanical polishing (abbreviated as C hemical M echanical P olishing after CMP), thinning the n-type Ge substrate 8 to about 50nm.

FIG.
Next, the n-type Ge substrate 8 is selectively anisotropically etched by using a resist (not shown) as a mask layer to form an n-type Ge layer 8 by using a normal lithography technique using an exposure drawing apparatus. . Next, the resist (not shown) is removed. Next, a silicon nitride film (Si ₃ N ₄ ) 4 is grown by about 50 nm by chemical vapor deposition. Next, chemical mechanical polishing is performed, and the silicon nitride film (Si ₃ N ₄ ) 4 on the n-type Ge layer 8 is removed and planarized. Thus, the n-type Ge layer 8 (second semiconductor layer) is insulated and separated in an island shape.

FIG.
Next, a silicon oxide film (SiO ₂ ) 27 of about 5 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon oxide film (SiO ₂ ) 27, a silicon nitride film (Si ₃ N ₄ ) 4, a silicon oxide film (SiO ₂₎ ) 3 and the silicon nitride film (Si ₃ N ₄ ) 2 are sequentially subjected to anisotropic dry etching to form openings. Next, the resist (not shown) is removed.

FIG.
Next, a p-type longitudinal (vertical) epitaxial SiGe layer 28 is grown on the exposed p-type silicon substrate 1. Next, chemical mechanical polishing is performed to planarize the p-type vertical (vertical) epitaxial SiGe layer 28 protruding from the flat surface of the silicon oxide film (SiO ₂ ) 27. Next, a tungsten film 29 of about 50 nm is grown by selective chemical vapor deposition.

FIG.
Next, using an ordinary lithography technique by an exposure drawing apparatus, the silicon oxide film (SiO ₂ ) 27 and the silicon nitride film (Si ₃ N ₄ ) 4 are sequentially anisotropic dry etched using a resist (not shown) as a mask layer. Then, an opening is formed. Next, the resist (not shown) is removed. Next, a p-type lateral (horizontal) direction epitaxial SiGe layer 6 (Ge concentration of about 30%) is grown on the side surface of the exposed p-type longitudinal (vertical) direction epitaxial SiGe layer 28 to fill the opening. The remaining silicon nitride film (Si ₃ N ₄ ) 4 serves as an element isolation region. Next, the surface of the p-type lateral (horizontal) epitaxial SiGe layer 6 is oxidized at about 800 ° C. to grow a silicon oxide film (SiO ₂ ) 30 of about 5 nm.

FIG.
Next, using the silicon oxide film (SiO ₂ ) 27 and the silicon oxide film (SiO ₂ ) 30 as a mask layer, the tungsten film 29 and the p-type longitudinal (vertical) epitaxial SiGe layer 28 are sequentially subjected to anisotropic dry etching to form holes. Forming part. Next, a silicon oxide film (SiO ₂ ) 9 of about 60 nm is grown by chemical vapor deposition. Next, a silicon oxide film (SiO ₂ ) 9 on the flat surface of the silicon nitride film (Si ₃ N ₄ ) 4, the p-type lateral (horizontal) direction epitaxial SiGe layer 6, and the n-type Ge layer 8, a silicon oxide film (SiO ₂ ) ₂ ) 27 and the silicon oxide film (SiO ₂ ) 30 are subjected to chemical mechanical polishing (CMP) to bury the silicon oxide film (SiO ₂ ) 9 flatly in the opening. (Since the opening width is about 100 nm, the silicon oxide film (SiO ₂ ) 9 can be buried sufficiently. This region is also a part of the element isolation region.)

FIG.
Next, a silicon oxide film (SiO ₂ ) 31 of about 100 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon oxide film (SiO ₂ ) 31, a p-type lateral (horizontal) epitaxial SiGe layer 6 and a silicon oxide film ( SiO ₂ ) 3 is selectively and selectively anisotropically dry etched to form an opening that exposes part of the silicon nitride film (Si ₃ N ₄ ) 2. Next, the resist (not shown) is removed.

FIG.
Next, a p-type lateral (horizontal) epitaxial Si layer is grown between the exposed side surfaces of the p-type lateral (horizontal) epitaxial SiGe layer 6, and a p-type lateral (horizontal) epitaxial layer having vacancies 5 in the lower portion is grown. A strained Si layer 7 is formed. (At this time, a single crystal silicon layer having no influence of the base is formed immediately above the vacancy 5. The semiconductor layer having the structure of the SiGe layer 6 sandwiching the strained Si layer 7 from the left and right serves as the first semiconductor layer. Next, using a normal lithography technique by an exposure drawing apparatus, the silicon oxide film (SiO ₂ ) 31 is anisotropically dry etched using a resist (not shown) as a mask layer, and a part of the n-type Ge layer 8 is obtained. An opening is formed in Next, the resist (not shown) is removed.

FIG.
Next, a gate oxide film (HfO ₂ ) 16 of about 5 nm is grown by chemical vapor deposition. Next, a polycrystalline silicon film (polySi) of about 50 nm is grown by chemical vapor deposition. Next, a tungsten silicide film (WSi) of about 50 nm is grown by sputtering. Next, chemical mechanical polishing is performed to remove the tungsten silicide film (WSi), the polycrystalline silicon film (polySi), and the gate oxide film (HfO ₂ ) on the silicon oxide film (SiO ₂ ) 31, and p-type lateral (horizontal). The directional epitaxial strained Si layer 7 and the n-type Ge layer 8 are embedded flatly in the openings.

FIG.
Next, the silicon oxide film (SiO ₂ ) 31 is removed by etching. Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, boron (for threshold voltage control) is implanted into the p-type lateral (horizontal) epitaxial strained Si layer 7 using a resist (not shown) as a mask layer. Using the resist (not shown) and the gate electrode (WSi / polySi) 17 as a mask layer, phosphorus ions are implanted for forming the n-type source / drain regions (11, 12). Next, the resist (not shown) is removed. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. Next, a silicon oxide film (SiO ₂ ) of about 25 nm is grown by chemical vapor deposition. Next, whole surface anisotropic dry etching is performed to form a side wall (SiO ₂ ) 18 only on the side wall of the gate electrode (WSi / polySi) 17. Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, an n ⁺ type source / drain region (10,) is formed using a resist (not shown), a sidewall (SiO ₂ ) 18 and a gate electrode (WSi / polySi) 17 as a mask layer. 13) Perform arsenic ion implantation for formation. Next, the resist (not shown) is removed. Next, using a normal lithography technique by an exposure drawing apparatus, boron (for threshold voltage control) is implanted into the n-type Ge layer 8 using a resist (not shown) as a mask layer. Boron ion implantation for forming the p ⁺ type source / drain regions (14, 15) is successively performed using the resist (not shown), the sidewall (SiO ₂ ) 18 and the gate electrode (WSi / polySi) 17 as mask layers. Do it. Next, the resist (not shown) is removed. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. Then annealing is performed by RTP (R apid T hermal P rocessing ) method, n-type source drain region (11, 12), ^{n +} -type source and drain regions (10, 13) and the ^{p +} -type source and drain regions (14, 15) Form.

FIG.
Next, a PSG film 19 having a thickness of about 400 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed and planarization is performed. Next, a silicon nitride film (Si ₃ N ₄ ) 20 of about 20 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, the silicon nitride film (Si ₃ N ₄ ) 20 and the PSG film 19 are sequentially anisotropic dry etched using a resist (not shown) as a mask layer to form a via. To do. Next, the resist (not shown) is removed. Next, TiN 21 serving as a barrier metal is grown by sputtering. Next, tungsten (W) 22 is grown by chemical vapor deposition. Next, a conductive plug (W) 22 having a barrier metal (TiN) 21 is formed by chemical mechanical polishing (CMP).

FIG.
Next, an interlayer insulating film (SiOC) 23 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique by an exposure drawing apparatus, the interlayer insulating film (SiOC) 23 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 20 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 24 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is embedded in the opening portion flatly, and a Cu wiring 25 having a barrier metal (TaN) 24 is formed. Next, a silicon nitride film (Si ₃ N ₄ ) 26 serving as a Cu barrier insulating film is grown by chemical vapor deposition, and the short channel N-channel and P-channel MIS field effect transistors formed in the BODOSOLESOI structure of the present invention are formed. A CMOS type semiconductor integrated circuit is completed.

FIG. 13 is a schematic cross-sectional side view of the second embodiment of the semiconductor device of the present invention, which is a CMOS including a short channel N-channel and P-channel MIS field effect transistor using a silicon (Si) substrate and formed in a BODOSOLESOI structure. 1 to 16 and 18 to 26 are the same as those in FIG. 1, 32 is a polycide gate electrode (CoSi ₂ / polySi), and 33 is a salicide layer (CoSi ₂ ). Show.
In this figure, N-channel and P-channel MIS field effects having substantially the same structure as in FIG. 1 except that a polycide gate electrode (CoSi ₂ / polySi) and a salicide layer (CoSi ₂ ) to be a metal source / drain are formed. A transistor is formed.
In this embodiment, the same effect as in the first embodiment can be obtained, and the manufacturing method is somewhat complicated. However, since the resistance of the source / drain region can be reduced, higher speed can be achieved.

FIG. 14 shows a fourth embodiment of the semiconductor device according to the present invention, which is a CMOS type semiconductor integrated circuit including a short channel N-channel and P-channel MIS field effect transistor using a silicon (Si) substrate and having a BODOSOLESIO structure. 1 to 16, 18 to 26 are the same as in FIG. 1, 34 is a phosphosilicate glass (PSG) film, and 35 is a gate electrode (Al).
In this figure, the structure is almost the same as in FIG. 1 except that the phosphosilicate glass (PSG) film is formed in two layers and the gate electrode is formed of low resistance Al (formed by a so-called damascene process). N-channel and P-channel MIS field effect transistors are formed.
In this embodiment, the same effect as in the first embodiment can be obtained, and the manufacturing method is somewhat complicated. However, the resistance of the gate electrode can be reduced by low resistance Al, so that the speed can be further increased. .

FIG. 15 is a schematic cross-sectional side view of a fourth embodiment of the semiconductor device of the present invention, which is a CMOS including a short channel N-channel and P-channel MIS field effect transistor formed in a BODOSOLEI SOI structure using a silicon (Si) substrate. 1 to 5 and 8 to 26 are the same as those in FIG. 1, 36 is a p-type lateral (horizontal) epitaxial Si layer, and 37 is a p-type lateral (horizontal). ) Direction epitaxial Si layer.
In the figure, in the N-channel MIS field effect transistor, N-channel and P-channel MIS field effect transistors having substantially the same structure as those in FIG. 1 are formed except that the semiconductor layer is formed only of an epitaxial Si layer.
In this embodiment, the same effect as in the first embodiment can be obtained, and the manufacturing method is somewhat simple. However, since the strained Si layer is not used, the high speed performance is slightly inferior.

FIG. 16 is a schematic cross-sectional side view of a fifth embodiment of the semiconductor device of the present invention, which is a CMOS including a short channel N-channel and P-channel MIS field effect transistor using a silicon (Si) substrate and having a BODOSOLESOI structure. 1 to 6 and 8 to 26 are the same as those in FIG. 1, 38 is a p-type lateral (horizontal) epitaxial SiGe layer, and 39 is a p-type vertical (vertical). ) Direction epitaxial strained Si layer.
In the figure, in the N-channel MIS field effect transistor, a semiconductor layer in which a strained Si layer is stacked on a SiGe layer is formed, and the gate electrode is formed to have a small thickness. N-channel and P-channel MIS field effect transistors having substantially the same structure as 1 are formed.
In this embodiment, the manufacturing method is somewhat complicated, but the same effect as in the first embodiment can be obtained.

FIGS. 17 to 29 show a sixth embodiment of the semiconductor device of the present invention. FIG. 17 is a schematic sectional side view and FIGS. 18 to 29 are sectional views of the manufacturing method.
FIG. 17 is a schematic cross-sectional side view of a sixth embodiment of the semiconductor device of the present invention. A CMOS including a short channel N-channel and P-channel MIS field effect transistor using a silicon (Si) substrate and having a BODOSOLESOI structure. 1 to 5, 8 to 16, and 18 to 26 are the same as those in FIG. 1, 34 and 35 are the same as those in FIG. 14, and 40 is a silicon oxide film (SiO 2). ₂ ) and 41 are silicon nitride films (Si ₃ N ₄ ), 42 is a p-type lateral (horizontal) epitaxial strained Si layer, 43 is a p-type lateral (horizontal) epitaxial Si layer, and 44 is p-type The bonded Ge layer is shown.
In the figure, in an N-channel MIS field effect transistor, a p-type bonded Ge layer is provided directly below the strained Si layer immediately below the gate electrode, to give strain to the strained Si layer. , Vacancies are formed on both sides of the Ge layer, Si layers are provided on both sides of the strained Si layer instead of the SiGe layer, and a part of the element isolation region is a silicon nitride film ( Si ₃ N ₄₎ instead be formed of two layers of silicon oxide film (SiO ₂₎ and silicon nitride film _(Si 3 _{N 4)} in the, P-channel MIS in relation to the structure of the N-channel MIS field effect transistor The thickness of the gate electrode of the field effect transistor is formed thick, the phosphosilicate glass (PSG) film is formed in two layers, and the gate electrode is formed of low resistance Al. Rukoto N-channel and P-channel MIS field effect transistor (a so-called formation by the damascene process) than almost the same structure as FIG. 1 are formed.
In this embodiment, the same effect as that of the first embodiment can be obtained, and the manufacturing method is somewhat complicated. However, the resistance of the gate electrode can be reduced by low resistance Al, and the strained Si layer can be reduced from the lower Ge layer. It is possible to further increase the lattice constant, and further increase the mobility of electrons, and so on, so that the speed can be further increased.

Next, a manufacturing method of the sixth embodiment in the semiconductor device according to the present invention will be described with reference to FIGS.
After the process of FIG. 2 shown in the first embodiment is performed, the next process of FIG. 18 is performed.

FIG.
Next, the n-type Ge substrate 8 is selectively anisotropically etched by using a resist (not shown) as a mask layer to form an n-type Ge layer 8 by using a normal lithography technique using an exposure drawing apparatus. . Next, the resist (not shown) is removed. Next, a silicon nitride film (Si ₃ N ₄ ) 4 is grown by about 50 nm by chemical vapor deposition. Next, chemical mechanical polishing is performed, and the silicon nitride film (Si ₃ N ₄ ) 4 on the n-type Ge layer 8 is removed and planarized. Thus, the Ge layer 8 (second semiconductor layer) is insulated and isolated in an island shape. (At this time, the n-type Ge layer 8 is also formed at the location where the N-channel MIS field effect transistor is formed.)

FIG.
Next, a silicon oxide film (SiO ₂ ) 40 of about 5 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 41 of about 45 nm is grown by chemical vapor deposition. Next, boron ions for controlling the threshold voltage are applied to the n-type Ge layer 8 where the P-channel MIS field-effect transistor is to be formed using a resist (not shown) as a mask layer using a normal lithography technique using an exposure drawing apparatus. Make an injection. Next, the resist (not shown) is removed. Next, using normal lithography technology by an exposure drawing apparatus, a resist (not shown) is used as a mask layer, and a boron layer for p-type formation of the n-type Ge layer 8 where the N-channel MIS field effect transistor is to be formed is used. Ion implantation is performed. (After the heat treatment, the p-type Ge layer 44 is obtained.) Next, the resist (not shown) is removed. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 41, a silicon oxide film (SiO ₂ ) 40, a silicon nitride film (Si ₃ N ₄ ) 4, silicon oxide film (SiO ₂ ) 3 and silicon nitride film (Si ₃ N ₄ ) 2 are sequentially subjected to anisotropic dry etching to form an opening. Next, the resist (not shown) is removed.

FIG.
Next, a p-type vertical (vertical) epitaxial Si layer 45 is grown on the exposed p-type silicon substrate 1. Next, chemical mechanical polishing is performed to planarize the p-type longitudinal (vertical) epitaxial Si layer 45 protruding from the flat surface of the silicon nitride film (Si ₃ N ₄ ) 41. Next, a tungsten film 29 of about 50 nm is grown by selective chemical vapor deposition.

FIG.
Next, using an ordinary lithography technique by an exposure drawing apparatus, a silicon nitride film (Si ₃ N ₄ ) 41 and a silicon oxide film (SiO ₂ ) 40 are sequentially anisotropic dry etched using a resist (not shown) as a mask layer. Then, an opening is formed. Next, the resist (not shown) is removed. Next, a p-type lateral (horizontal) direction epitaxial strained Si layer 42 is grown on the exposed side surface of the p-type longitudinal (vertical) direction epitaxial Si layer 45 to fill the opening. Next, the surface of the p-type lateral (horizontal) epitaxial strained Si layer 42 is oxidized at about 800 ° C. to grow a silicon oxide film (SiO ₂ ) 30 of about 5 nm.

FIG.
Next, with the silicon nitride film (Si ₃ N ₄ ) 41 and the silicon oxide film (SiO ₂ ) 30 as mask layers, the tungsten film 29 and the p-type longitudinal (vertical) epitaxial Si layer 45 are sequentially anisotropically dry etched, An opening is formed. (At this time, the p-type silicon substrate 1 is also slightly etched, but there is no particular problem.) Next, a silicon oxide film (SiO ₂ ) 9 of about 60 nm is grown by chemical vapor deposition. Next, the silicon oxide film (SiO ₂ ) 9 and the silicon oxide film (SiO ₂ ) 30 on the flat surface of the silicon nitride film (Si ₃ N ₄ ) 41 and the p-type lateral (horizontal) epitaxial strained Si layer 42 are chemically treated. Mechanical polishing (CMP) is performed, and a silicon oxide film (SiO ₂ ) 9 is flatly embedded in the opening. (Since the opening width is about 100 nm, the silicon oxide film (SiO ₂ ) 9 can be buried sufficiently. This region is also a part of the element isolation region.)

FIG.
Next, a silicon oxide film (SiO ₂ ) 46 of about 5 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 47 of about 100 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, using a resist (not shown) as a mask layer, a silicon nitride film (Si ₃ N ₄ ) 47, a silicon oxide film (SiO ₂ ) 46, a p-type lateral (horizontal) The directionally strained Si layer 42 and the p-type Ge layer 44 are sequentially anisotropic dry etched to form stepped openings.

FIG.
Next, using a normal lithography technique by an exposure drawing apparatus, a resist covering the left half (a portion where an N-channel MIS field effect transistor is formed, not shown) and a resist (not shown) in the previous process are used as mask layers. The nitride film (Si ₃ N ₄ ) 41 and the silicon oxide film (SiO ₂ ) 40 are sequentially subjected to anisotropic dry etching. (Location where P-channel MIS field-effect transistor is formed) Next, both resists (not shown) are removed.

FIG.
Next, a p-type lateral (horizontal) epitaxial Si layer 43 is grown on both side surfaces of the exposed p-type lateral (horizontal) epitaxial strained Si layer 42. (At this time, vacancies 5 are formed below a part of the p-type lateral (horizontal) epitaxial Si layer 43, that is, on both sides of the p-type Ge layer 44.) Here, the N-channel MIS field effect silicon nitride film left in place to form a transistor _{(Si 3} N 4) 47 and a silicon oxide film _(SiO 2) 46, P-channel MIS field effect silicon nitride film transistor left in place to form the _(Si 3 N ₄ ) 47, silicon oxide film (SiO ₂ ) 46, silicon nitride film (Si ₃ N ₄ ) 41 and silicon oxide film (SiO ₂ ) 40 become a dummy gate electrode and a dummy gate oxide film, respectively.

FIG.
Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, using a normal lithography technique by an exposure drawing apparatus, boron ions for threshold voltage control are implanted into the p-type lateral (horizontal) epitaxial strained Si layer 42 using a resist (not shown) as a mask layer. Using the resist (not shown) and the dummy gate electrode 47 as a mask layer, phosphorus ions are implanted for forming the n-type source / drain regions (11, 12). Next, the resist (not shown) is removed. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. Next, a silicon oxide film (SiO ₂ ) of about 25 nm is grown by chemical vapor deposition. Next, whole surface anisotropic dry etching is performed to form side walls (SiO ₂ ) 18 only on the side walls of the dummy gate electrode and the dummy gate oxide films (40, 41, 46, 47). Next, a silicon oxide film (SiO ₂ , not shown) for ion implantation of about 5 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique by an exposure drawing apparatus, for forming an n ⁺ -type source / drain region (10, 13) using a resist (not shown), a sidewall (SiO ₂ ) 18 and a dummy gate electrode 47 as a mask layer Arsenic ion implantation. Next, the resist (not shown) is removed. Next, a p ⁺ type source / drain region (using a resist (not shown), sidewalls (SiO ₂ ) 18, and dummy gate electrodes (41, 46, 47)) as mask layers using a normal lithography technique by an exposure drawing apparatus. 14, 15) Boron ion implantation is performed. Next, the resist (not shown) is removed. Next, the silicon oxide film (SiO ₂ , not shown) for ion implantation is removed by etching. Next, annealing is performed by the RTP method to form an n-type source / drain region (11, 12), an n ⁺ -type source / drain region (10, 13), and a p ⁺ -type source / drain region (14, 15).

FIG.
Next, a PSG film 34 of about 150 nm is grown by chemical vapor deposition. Then, chemical mechanical polishing (CMP) is performed and planarization is performed. Next, the remaining silicon nitride film (Si ₃ N ₄ ) 47, silicon oxide film (SiO ₂ ) 46, silicon nitride film (Si ₃ N ₄ ) 41 and silicon oxide film (SiO ₂ ) 40 are sequentially anisotropic dry etched. Then, an opening is formed on the p-type lateral (horizontal) epitaxial strained Si layer 42 and the n-type Ge layer 8.

FIG.
Next, a gate oxide film (HfO ₂ ) 16 of about 5 nm is grown by chemical vapor deposition. Next, aluminum (Al) 35 of about 150 nm is grown by sputtering. Next, chemical mechanical polishing is performed to remove the aluminum (Al) 35 and the gate oxide film (HfO ₂ ) on the PSG film 34, and the p-type lateral (horizontal) epitaxial strained Si layer 42 and the n-type Ge layer 8 are formed. Embed flatly in the aperture.

FIG.
Next, a PSG film 19 of about 300 nm is grown by chemical vapor deposition. Next, a silicon nitride film (Si ₃ N ₄ ) 20 of about 20 nm is grown by chemical vapor deposition. Next, the silicon nitride film (Si ₃ N ₄ ) 20, the PSG film 19, and the PSG film 34 are sequentially subjected to anisotropic dry etching using a resist (not shown) as a mask layer by using a normal lithography technique by an exposure drawing apparatus. , Forming a via. Next, the resist (not shown) is removed. Next, TiN 21 serving as a barrier metal is grown by sputtering. Next, tungsten (W) 22 is grown by chemical vapor deposition. Next, a conductive plug (W) 22 having a barrier metal (TiN) 21 is formed by chemical mechanical polishing (CMP).

FIG.
Next, an interlayer insulating film (SiOC) 23 of about 500 nm is grown by chemical vapor deposition. Next, using an ordinary lithography technique by an exposure drawing apparatus, the interlayer insulating film (SiOC) 23 is anisotropically dry-etched using a resist (not shown) as a mask layer to form an opening. (At this time, the silicon nitride film (Si ₃ N ₄ ) 20 becomes an etching stopper film.) Next, the resist (not shown) is removed. Next, a barrier metal (TaN) 24 of about 10 nm is grown by chemical vapor deposition. Next, a Cu seed layer is grown by sputtering. Next, Cu of about 500 nm is grown by electrolytic plating. Next, chemical mechanical polishing (CMP) is performed, Cu is embedded in the opening portion flatly, and a Cu wiring 25 having a barrier metal (TaN) 24 is formed. Next, a silicon nitride film (Si ₃ N ₄ ) 26 serving as a Cu barrier insulating film is grown by chemical vapor deposition, and the short channel N-channel and P-channel MIS field effect transistors formed in the BODOSOLESOI structure of the present invention are formed. A CMOS type semiconductor integrated circuit is completed.

FIG. 30 is a schematic cross-sectional side view of a seventh embodiment of the semiconductor device of the present invention, a CMOS including a short channel N-channel and P-channel MIS field effect transistor formed in a BODOSOLEI SOI structure using a silicon (Si) substrate. 1 to 4, 8 to 16 and 18 to 26 are the same as in FIG. 1, 34 and 35 are the same as in FIG. 14, and 40 to 42 are in FIG. 17. The same thing, 48 shows a p-type lateral (horizontal) direction epitaxial SiGe layer.
In the figure, a p-type lateral (horizontal) epitaxial SiGe layer 48 is formed instead of the p-type lateral (horizontal) epitaxial Si layer 43, and a Ge layer 44 having no vacancy on both sides is formed. N-channel and P-channel MIS field effect transistors having substantially the same structure as in FIG. 17 are formed except that is formed.
In this embodiment, the same effects as in the first embodiment can be obtained, and the manufacturing method is somewhat complicated. However, the resistance of the gate electrode can be reduced by low resistance Al, the lower Ge layer and the SiGe on both sides. The lattice constant of the strained Si layer can be further increased from the layer, and the mobility of electrons can be further increased, so that further increase in speed is possible.

In the above embodiment, the case where a germanium (Ge) substrate is bonded to a silicon substrate is described. However, the semiconductor is not limited to a germanium (Ge) substrate, and any semiconductor can be used as long as it has a high hole mobility. The present invention is established even if the substrates may be bonded together or the compound semiconductor substrate may be bonded.
When a semiconductor layer is grown, not only by the normal chemical vapor deposition, but also by the ECR plasma CVD method, the molecular beam growth method (MBE), or the metal organic chemical vapor deposition method (MOCVD). The layer crystal growth method (ALE) may be used or any other crystal growth method may be used.
The gate electrode, the gate oxide film, the barrier metal, the conductive plug, the wiring, the insulating film, the conductive film, and the like are not limited to the above embodiments, and any material may be used as long as it has similar characteristics. .
In addition, although all of the above embodiments describe the case where an enhancement type MIS field effect transistor is formed, a depletion type MIS field effect transistor may be formed. In this case, an epitaxial semiconductor layer having the opposite conductivity type is grown, or an epitaxial semiconductor layer having a similar structure is formed by growing an epitaxial semiconductor layer and then ion-implanting an impurity of the opposite conductivity type to convert the conductivity type. A MIS field effect transistor may be formed.

The present invention is aimed at a CMOS semiconductor integrated circuit that is extremely fast, highly reliable, and highly integrated. However, the present invention is not limited to a high speed, and is used for all semiconductor integrated circuits equipped with MIS field effect transistors. Is possible.
Moreover, it can be used not only as a semiconductor integrated circuit but also as a single individual semiconductor element.
The MIS field-effect transistor as well, may be available other field effect transistors, such as a liquid crystal for a TFT (T hin F ilm T ransistor ).

1 p-type silicon (Si) substrate 2 silicon nitride film (Si ₃ N ₄ )
3 Silicon oxide film (SiO ₂ )
4 Silicon nitride film in element isolation region (Si ₃ N ₄ )
5 Hole 6 p-type lateral (horizontal) direction epitaxial SiGe layer 7 p-type lateral (horizontal) direction epitaxial strained Si layer 8 n-type bonded Ge layer 9 embedded silicon oxide film (SiO ₂ )
10 n ⁺ type source region 11 n type source region 12 n type drain region 13 n ⁺ type drain region 14 p ⁺ type drain region 15 p ⁺ type source region 16 Gate oxide film (HfO ₂ )
17 Gate electrode (WSi / polySi)
18 Side wall (SiO ₂ )
19 Phosphorsilicate glass (PSG) film 20 Silicon nitride film (Si ₃ N ₄ )
21 Barrier metal (TiN)
22 Conductive plug (W)
23 Interlayer insulation film (SiOC)
24 Barrier metal (TaN)
25 Cu wiring (including Cu seed layer)
26 Barrier insulating film (Si ₃ N ₄ )
27 Silicon oxide film (SiO ₂ )
28 p-type vertical (vertical) epitaxial SiGe layer 29 selective chemical vapor deposition conductive film (W)
30 Silicon oxide film (SiO ₂ )
31 Silicon oxide film (SiO ₂ )
32 Polycide gate electrode (CoSi ₂ / polySi)
33 Salicide layer (CoSi ₂ )
34 Phosphorsilicate glass (PSG) film 35 Gate electrode (Al)
36 p-type lateral (horizontal) direction epitaxial Si layer 37 p-type lateral (horizontal) direction epitaxial Si layer 38 p-type lateral (horizontal) direction epitaxial SiGe layer 39 p-type longitudinal (vertical) direction epitaxial strained Si layer 40 Silicon oxide film (SiO ₂ )
41 Silicon nitride film (Si ₃ N ₄ )
42 p-type lateral (horizontal) direction epitaxial strained Si layer 43 p-type lateral (horizontal) direction epitaxial Si layer 44 p-type bonded Ge layer 45 p-type longitudinal (vertical) direction epitaxial Si layer 46 silicon oxide Film (SiO ₂ )
47 Silicon nitride film (Si ₃ N ₄ )
48 p-type lateral (horizontal) epitaxial SiGe layer

Claims (4)

Are bonded through an insulating film on a semiconductor substrate made of a first semiconductor, one conductivity type of the MIS field effect transistor is provided in the second semiconductor layer of a second semiconductor which is selectively formed, the At least the first semiconductor layer is provided by selective epitaxial growth from the semiconductor substrate through the insulating film partially having vacancies on the semiconductor substrate at a location where the second semiconductor layer is not provided. A semiconductor device, wherein an MIS field effect transistor of opposite conductivity type is provided in a first semiconductor layer containing a semiconductor.   The first semiconductor layer includes a semiconductor layer portion provided with a rough channel region immediately above the vacancy and a semiconductor layer portion provided with a rough source / drain region directly above the insulating film. 2. The semiconductor device according to claim 1, wherein a lattice constant of a semiconductor layer portion provided with the semiconductor layer portion is smaller than a lattice constant of the semiconductor layer portion provided with the approximate source / drain region.   The semiconductor device according to claim 1, wherein the first semiconductor is silicon, and the second semiconductor is germanium. The second semiconductor substrate made of the second semiconductor is bonded to the first semiconductor substrate made of the first semiconductor with an insulating film interposed therebetween, thinned, and selectively separated into an island shape to thereby form the second semiconductor substrate. Forming a second semiconductor layer made of a semiconductor, and selectively removing the insulating film in a portion where the second semiconductor layer is not provided, and vertically (vertically) from the exposed first semiconductor substrate; Forming a directional epitaxial semiconductor layer; exposing a part of a side surface of the vertical (vertical) epitaxial semiconductor layer; and selectively forming a lateral (horizontal) epitaxial semiconductor layer on the insulating film; The vertical (vertical) direction epitaxial semiconductor layer is removed, and a buried insulating film is formed in the formed opening, whereby the lateral (horizontal) direction epitaxial semiconductor layer is isolated and isolated in an island shape. Forming a conductor layer; and forming an interlayer insulating film on the first and second semiconductor layers, and then selectively forming the interlayer insulating film, a portion of the first semiconductor layer immediately below, and Removing a part of the insulating film; growing a lateral (horizontal) epitaxial semiconductor layer between the exposed side surfaces of the first semiconductor layer; repairing the removed first semiconductor layer; Forming a hole in the first semiconductor layer, and forming the first semiconductor layer on the insulating film partially having the hole, and forming the second semiconductor layer on the insulating film. A method of manufacturing a semiconductor device.

Images