JP5446143B2 - Disturbance suppression device, disturbance suppression device control method, disturbance suppression control device, and rotary direct drive motor - Google Patents

Description

The present invention relates to a disturbance suppression device that estimates and suppresses disturbances received by a controlled object, and in particular, an error that occurs when a fractional part is rounded down in arithmetic processing performed in a Q filter that constitutes a disturbance observer that estimates disturbances. The present invention relates to a disturbance suppression device, a disturbance suppression device control method, a disturbance suppression control device, and a rotary direct drive motor that are suitable for reducing noise.

  2. Description of the Related Art Conventionally, for example, as a method of compensating for disturbance of a motor that is a control target, a method of estimating a disturbance received by a motor using a disturbance observer and suppressing the influence of the disturbance using the estimated disturbance is often used. Here, the disturbance observer includes an inverse system (inverse function) to be controlled and a Q filter (mainly a low-pass filter). The Q filter is configured by software (program) as a digital filter, for example, and the filter processing is performed by software using an arithmetic device such as a DSP (Digital Signal Processor) or a processor. In particular, in the filter process, an arithmetic process using a fixed-point number instead of a floating-point number is performed in consideration of use of a low-cost processor. In this calculation process, generally, the decimal part of the fixed-point number after the calculation is discarded.

As a technique for suppressing the influence of a disturbance received by a controlled object using a disturbance observer as described above, for example, there is an actuator control device in a disk device described in Patent Document 1.
JP 2001-210032 A

When the fractional part of the fixed-point number of the calculation result in the filtering process is discarded through experiments or the like, the inventors of the present invention do not cause the DC gain of the control system to be 1 due to the error of the truncated part, and the disturbance It has been found that there is a phenomenon that cannot be estimated correctly.
Hereinafter, based on FIG. 4, a problem that occurs when the decimal part of the fixed-point number of the calculation result is discarded in the control system including the disturbance observer will be specifically described.

As shown in FIG. 4, the control system including the disturbance observer includes an adder 12, a control object 14 such as a direct drive motor (hereinafter referred to as a DD motor), and a disturbance observer 16. . Here, G (s) in FIG. 4 indicates the transfer function of the controlled object 14.
The adder 12 adds the control command signal τ to the control target 14 and the disturbance observer signal τd ′ from the disturbance observer 16. This addition signal is input to the controlled object 14 under the influence of a disturbance τd such as vibration or shock during the process. On the other hand, the addition signal before being affected by the disturbance is input to the disturbance observer 16. An output signal (for example, position signal θ) from the control target 14 is mixed with observation noise N, and an output signal mixed with the observation noise N is input to the disturbance observer 16.

The disturbance observer 16 includes an inverse system 20 to be controlled, a subtraction unit 22, and a Q filter unit 26. Here, Q (s) in Figure 4 shows the de-I digital filter having the function of a low-pass filter, "Gn-1 (s)" is the transfer function of the inverse system (inverse function of G (s)) Show.
The output signal mixed with the observation noise N from the control target 14 is input to the inverse system 20, and the control command signal for the control target 14 to output the output signal by the transfer function "Gn-1 (s)". Converted to. Further, this control command signal (hereinafter referred to as an estimated control command signal) is subtracted from the addition signal from the adder 12 in the subtraction unit 22. This subtraction signal (difference signal) is a signal indicating an estimated value of the disturbance (hereinafter referred to as an estimated disturbance signal τd *). This estimated disturbance signal τd * is input to the Q filter unit 26 that functions as a low-pass filter (actually, it is input to an arithmetic unit such as a DSP via an A / D converter). The Q filter unit 26 removes unnecessary frequency components (high-frequency components) including the frequency domain of the observed noise N from the estimated disturbance signal τd * by an arithmetic process using a fixed-point number filter coefficient, and generates a disturbance observer signal. τd ′ is generated and output to the adder 12. In the calculation process in the Q filter unit 26, the decimal part of the fixed-point number of the calculation result is rounded down in order to reduce the processing load. Therefore, the estimated disturbance value after the filtering process is the fractional part truncated, and this signal is output to the adder 12 as the disturbance observer signal τd ′.

  Now, the magnitude of the disturbance τd is “n”, an arithmetic error “δ” occurs due to the fractional part being cut off in the filter processing of the Q filter unit 26, and the output value (disturbance observer value) of the Q filter unit 26 is “ n + δ ”. In this state, when “−δ” is input as the control command value to the adder 12 ((1) in FIG. 4) and “n + δ” is input as the disturbance observer value (estimated disturbance value) (FIG. 4). In (2)), the adder 12 performs these addition processes (“−δ + n + δ = n”) ((3) in FIG. 4). The signal of the addition result “n” is affected by disturbance in the middle of being sent to the controlled object 14, but since the estimated disturbance value “n” has already been added in the adder 12, the disturbance and estimated disturbance “ n ”cancel each other and become“ 0 ”((4) in FIG. 4). As a result, a signal indicating the control command value “0” is input to the controlled object 14 ((5) in FIG. 4). On the other hand, in the inverse system 20, when the output value of the control target 14 reaches the target value, the control command value “0” is used here to calculate the estimated control command value by performing second order differentiation of the output value. In this case, the estimated control command value can be regarded as “0” ((6) in FIG. 4). Therefore, since “0” is subtracted from “n” in the subtracting unit 22 (“n−0 = n”), the estimated value of the disturbance is “n” ((7) in FIG. 4). That is, in this state, although the output value of the controlled object 14 has not reached the control target value, it has reached the target value.

From the above, when the Q filter is inserted in the disturbance observer loop, if the decimal part of the fixed-point number is truncated in the filter processing, the DC gain becomes 1 due to the error caused by the truncation. It can be understood that there is a problem that the operation of the control target 14 is stopped before the output value of the control target 14 reaches the target value.
Therefore, the present invention has been made paying attention to such an unsolved problem of the conventional technique, and when the fractional part of the fixed-point number is rounded down in the arithmetic processing in the Q filter constituting the disturbance observer. An object of the present invention is to provide a disturbance suppression device, a disturbance suppression device control method, a disturbance suppression control device, and a rotary direct drive motor that are suitable for reducing the influence of the error that occurs.

[Invention 1] In order to achieve the above object, the disturbance suppressing device of the invention 1 includes a disturbance observer for generating a disturbance observer signal for suppressing the influence of disturbance received by a rotary direct drive motor, and the rotary type A disturbance suppression device including an addition signal generation unit that generates an addition signal of a control command signal to a direct drive motor and the disturbance observer signal,
The disturbance observer, indicates an estimate of the disturbance on the basis of the angular position signal and the sum signal is a signal indicating a rotational angular position of the rotary direct drive motor to the output of the rotary direct drive motor and the estimated disturbance signal generator for generating an estimated disturbance signal, a digital IIR (Infinit e Impulse Response) by arithmetic processing using a filter, undesired frequency domain signal contained in the estimated disturbance signal having a filter coefficient of a fixed-point number And a Q filter unit that selectively removes components,
The Q filter unit rounds the decimal part of the fixed-point number after the arithmetic processing using the filter coefficient to the integer part of the fixed-point number so that the DC gain of the control system including the disturbance suppressing device becomes 1 In addition, a decimal part truncation means for truncating the decimal part is provided.

With such a configuration, when the angular position signal from the rotary direct drive motor is input and the addition signal from the addition signal generation unit is input, the disturbance observer estimates the disturbance based on these input signals. Then, an estimated disturbance signal indicating the estimated disturbance is generated. When the estimated disturbance signal is generated, the Q filter unit performs a filtering process on the estimated disturbance signal, selectively removes unnecessary frequency components from the estimated disturbance signal, and the signal components after the removal Is output as a disturbance observer signal. In the filter processing, calculation processing using a filter coefficient of a fixed-point number is executed, and the fixed value after the calculation processing is performed so that the DC gain of the control system including the disturbance suppression device becomes 1 in the decimal rounding means. The decimal part of the decimal point is rounded down to the integer part and then rounded down.

As a result, a more accurate estimated disturbance value can be obtained, so that the error tends to be smaller than the minimum control command value, and the occurrence of the error canceling out the control command value can be reduced.
Here, rounding the fractional part to an integer part is a process corresponding to rounding off in decimal. That is, when the most significant digit of the decimal part is 5 or more, 1 is rounded up to the least significant digit of the integer part, and when it is 4 or less, the process is not rounded up (for example, “35.542 → 36”, “35.432 → 35 ").

  Specifically, for example, a 32-bit fixed-point number (decimal part m) is obtained by multiplying a 16-bit input value (no decimal part) by a filter coefficient that is a 16-bit fixed-point number (decimal part m-bit). Bit) is output as the operation result. In this case, the rounding process is, for example, a process of adding 1 to the most significant bit in m bits of the decimal part of a 32-bit fixed-point number. Thereby, when the most significant bit of m bits is “1”, 1 is added to the least significant bit of the integer part (32−m bits). In other words, the decimal part is rounded up to the integer part, as rounded off to the decimal. In this case, since the integer part includes a part of the information even if the decimal part is truncated, an error due to rounding occurs, but the error (the amount of information to be lost) is compared with the case of simply truncating. Can be small. On the other hand, when the most significant digit of m bits is “0”, rounding up to the integer part does not occur and the decimal part is simply discarded. In other words, since the decimal part is a numerical value equal to or less than “4” as rounded off to a decimal number, no round-up occurs.

The truncation of the decimal part is a process of shifting the bits of the integer part by the number of bits of the decimal part (m bits) in the lower direction (process of dividing by 2 ^m ). At this time, for example, data of the lower 16 bits after the shift is used as the data of the operation result.
In addition, the Q filter may be configured by, for example, a filter circuit configured by hardware such as an electronic circuit, or a digital filter hardware and software that digitizes signal data and performs software processing by arithmetic processing. Is a possible filter. In the former case, a signal is directly input to the filter circuit, and only a signal component having a desired frequency among the input signals is selectively passed through the circuit elements. In the latter case, the control signal is converted into numerical data using an A / D converter or the like, and other signal components are left so that a signal component of a desired frequency remains from the control signal by arithmetic processing of an arithmetic unit such as a DSP. It becomes processing to remove. Hereinafter, the same applies to the disturbance suppression device control method of the invention 5 and the disturbance suppression control device of the invention 6.

[Invention 2] Further, the disturbance suppression apparatus according to the invention 2 is the disturbance suppression apparatus according to the invention 1, wherein the Q filter unit selectively removes a signal component in a frequency region higher than a predetermined frequency in the estimated disturbance signal. Has a filter function.
With such a configuration, the Q filter unit can remove harmonic components (noise components) such as modeling error and observation noise included in the estimated disturbance signal, so that the disturbance can be estimated with high accuracy, The occurrence of malfunctions due to noise components can be reduced.

[Invention 3] Further, the disturbance suppressing device of Invention 3 is the disturbance suppressing device of Invention 1 or 2, wherein the estimated disturbance signal generating unit is an inverse function of a transfer function of the rotary direct drive motor and the angular position. An estimated control command signal generating means for generating an estimated control command signal, which is a control command signal including a disturbance component, necessary for the rotary direct drive motor to output the angular position signal using the signal A differential signal generating means for generating an estimated disturbance signal that is a differential signal between the estimated control command signal and the addition signal;
In the Q filter unit, the disturbance observer signal is generated by filtering the difference signal.

With such a configuration, the estimated disturbance signal generating section, the inverse of the transfer function of the rotary direct drive motors, obtain the angle position signal from the actual angle position signals of the rotary direct drive motor Therefore, an estimated control command signal can be obtained. This estimated control command signal includes disturbance components, observation noise, and modeling errors that are difficult to model, and subtracts the estimated control command signal from the sum signal of the control command signal and the disturbance observer signal. Thus, the disturbance component can be estimated. Then, in the filtering process of the Q filter unit, unnecessary frequency domain signal components such as observation noise are removed from the estimated disturbance component signal, and the decimal part of the fixed-point number of the operation result is converted to the integer part of the fixed-point number. Disturbance observer signals can be generated by rounding down and rounding down.
This makes it possible to estimate the disturbance received by the rotary direct drive motor with higher accuracy.

[Invention 4] On the other hand, in order to achieve the above object, a disturbance suppression apparatus control method according to Invention 4 includes a disturbance observer for generating a disturbance observer signal for suppressing the influence of disturbance received by a rotary direct drive motor, and A disturbance suppression device control method for controlling a disturbance suppression device including an addition signal generation unit that generates an addition signal of a control command signal to the rotary direct drive motor and the disturbance observer signal,
The disturbance observer, indicates an estimate of the disturbance on the basis of the angular position signal and the sum signal is a signal indicating a rotational angular position of the rotary direct drive motor to the output of the rotary direct drive motor and the estimated disturbance signal generator for generating an estimated disturbance signal, a digital IIR (Infinit e Impulse Response) by arithmetic processing using a filter, undesired frequency domain signal contained in the estimated disturbance signal having a filter coefficient of a fixed-point number And a Q filter unit that selectively removes components,
The Q filter unit causes the decimal part of the fixed-point number to be rounded to the integer part of the fixed-point number in the arithmetic processing so that the DC gain of the control system including the disturbance suppressing device is 1, and the decimal part is Includes a fractional truncation step for truncation.
If it is such a structure, the effect | action and effect equivalent to the disturbance suppression apparatus of the said invention 1 will be acquired.

[Invention 5] In order to achieve the above object, the disturbance suppression type control device of the invention 5, a signal indicating the rotational angular position of the rotary direct drive motor to the output of the rotary direct drive motor An error signal generation unit that generates an error signal indicating an error of a certain angular position signal with respect to a target signal; a control command signal generation unit that generates a control command signal to be given to the rotary direct drive motor based on the error signal; A disturbance observer for generating a disturbance observer signal for suppressing the influence of the disturbance received by the rotary direct drive motor, and an addition signal generator for generating an addition signal of the control command signal and the disturbance observer signal; A disturbance suppression type control device including the disturbance suppression device according to any one of the first to third aspects.
If it is such a structure, the effect | action and effect equivalent to the disturbance suppression apparatus of any one of the said invention 1 thru | or 3 will be acquired.

  As described above, according to the disturbance suppressing device, the disturbance suppressing device control method, and the disturbance suppressing control device of the present invention, in the filter processing for removing unnecessary frequency components in the Q filter unit of the disturbance observer, fixed-point arithmetic is performed. When removing the decimal part from the fixed-point number of the result, the decimal part is rounded to the integer part, so the error caused by truncating the decimal part can be reduced, and this error causes malfunction The effect that it can reduce etc. is acquired.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 3 are diagrams showing an embodiment of a disturbance suppressing device, a disturbance suppressing device control method, and a disturbance suppressing control device according to the present invention.
First, the configuration of a disturbance suppression control apparatus according to the present invention will be described with reference to FIG. FIG. 1 is a control block diagram showing a configuration of a disturbance suppression control apparatus 100 according to the present embodiment.
As shown in FIG. 1, the disturbance suppression control apparatus 100 includes a controller 10, an adder 12, a controlled object 14, and a disturbance observer 16. In the present embodiment, the control object 14 will be described as a DD motor that rotates a motor with a torque command signal as an input and outputs an angular position signal θ.

The controller 10 has a transfer function C, generates a control command signal τ indicating a torque command value to the DD motor 14 based on the output value (θ) of the controlled object 14 and the control target value θ _t, and This is output to the adder 12.
The adder 12 generates an addition signal of the control command signal τ from the controller 10 and the disturbance observer signal τd ′ from the disturbance observer 16, and outputs this to the controlled object 14. This addition signal “τ + τd ′” is influenced by the disturbance τd before reaching the control object 14 and becomes “τ + τd′−τd”. That is, all disturbances are canceled when “τd′−τd = 0”.

The control target 14 has an input / output relationship indicated by a transfer function G (s), performs a rotation operation of the motor based on the control command signal τ, and outputs an output signal indicating a rotation angle position (θ) after the operation. It outputs to the disturbance observer 16 and the controller 10.
The disturbance observer 16 serves to suppress the influence of the disturbance τd mixed in the control command signal τ, and includes an inverse system 20, a subtraction unit 22, and a Q filter unit 24.

The inverse system 20 is an inverse system of the control target 14 having “1 / Gn (s)”, which is an inverse function of the transfer function G (s) of the control target 14, as an output signal from the control target 14. With θ as an input, it is converted and an estimated control command signal τ * indicating an estimated value of the control command value is output.
In this embodiment, the inverse system 20 includes a not shown A / D converter for converting an analog signal to a de I digital signal, function of the control system with input-output relationship of the "1 / Gn (s)" Is configured to include a dedicated program for causing a processor (not shown here) to implement the program and a processor that executes the program.

The subtracting unit 22 converts an addition signal “τ + τd ′” from the adder 12 into a digital signal (not shown), a digital addition signal “τ + τd ′” from the A / D converter, Based on the digital estimated control command signal τ * from the inverse system 20, τ * is subtracted from “τ + τd ′” to generate a digital estimated disturbance signal τd *.
The Q filter unit 24 has a dedicated program (digital filter Q (s)) for realizing a low-pass filter function in a processor (not shown here) (not shown) and a processor (same as the inverse system 20) that executes this program. And a D / A converter (not shown).

Specifically, the estimated disturbance value τd * (hereinafter referred to as u (k)) and the estimated disturbance value τd ′ (after filtering) of the kth sample (k = 1, 2, 3,...). This is hereinafter referred to as y (k)), the estimated disturbance value τd * (hereinafter referred to as u (k−1)) of the (k−1) th sample, and the estimated disturbance value τd after filtering. Using '(hereinafter referred to as y (k−1)) and a fixed-point number filter coefficient A, the arithmetic processing is performed according to the following expression (1). Thus, processing equivalent to a low-pass filter that removes unnecessary signal components (high-frequency components) from the estimated disturbance signal τd * is executed. Further, the signal thus obtained is converted into an analog signal by a D / A converter, and this signal is output to the adder 12 as a disturbance observer signal τd ′.

y (k) = A {u (k) + u (k-1)} + (1-2A) y (k-1) (1)

In the above equation (1), y (k−1) is an estimated disturbance value (disturbance observer value) τd ′ after the filter processing of the (k−1) th sample.

In the present embodiment, the above equation (1) is further expanded as the following equation (2) to reduce the number of multiplications from two to one, thereby reducing the load on the processor.

y (k) = A {u (k) + u (k-1) -2y (k-1)} + y (k-1)... (2)

That is, in the present embodiment, the digital filter Q (s) is a first-order IIR (Infinite Impulse Response) filter.

Next, the filtering process of the digital filter Q (s) will be described in detail with reference to FIG. Here, FIG. 2 is a functional block diagram showing filter processing of the digital filter Q (s).
As shown in FIG. 2, the digital filter Q (s) includes a first delay unit 24a, an addition / subtraction unit 24b, a coefficient multiplication unit 24c, an addition unit 24d, a first division unit 24e, and a second delay unit 24f. And a second division unit 24g.

  The first delay unit 24a is a functional block that reads data from a buffer memory (delay element) such as a RAM, and in the filter processing of the kth sample, the nth bit of the (k-1) th sample held in the buffer memory The estimated disturbance value τd * (u (k−1)) of (n is a natural number of 2 or more) is read and output to the adder / subtractor 24b. Further, after outputting u (k−1), the input value u (k) of the kth sample is stored in the buffer memory.

  The adder / subtractor 24b includes the estimated disturbance value u (k) of the kth sample from the subtractor 22, the estimated disturbance value u (k-1) of the (k-1) th sample from the first delay unit 24a, and ( k-1) Addition / subtraction with 2y (k-1) obtained by doubling the estimated disturbance value after the filter processing of the sample is performed, and the calculation result is output to the coefficient multiplication unit 24c. Specifically, u (k) and u (k−1) are added according to the above equation (2), and 2y (k−1) is subtracted from the addition result.

  The coefficient multiplying unit 24c converts an n-bit fixed-point number filter coefficient A having an m-bit (m is a natural number of n> m) stored in a storage medium (not shown) such as a ROM into an addition / subtraction unit 24b. Is multiplied by the operation result “X = u (k) + u (k−1) −2y (k−1)”, and the multiplication result “X · A” is output to the adder 24d. The calculation result “X · A” is a 2n-bit fixed-point number having an integer part (2 × n−m) bits and a fractional part m bits.

The adder 24d adds the estimated disturbance value y (k−1) (2n bits) after the filter processing one sample before from the second delay unit 24f to the calculation result “X · A (2n bits)” of the coefficient multiplier 24c. ) And the addition result “X · A + y (k−1) = y (k)” is output to the division unit 24e and the second delay unit 24f, respectively.
The first division unit 24e rounds the m-bit fractional part in the addition result y (k) (2n bits) of the addition unit 24d into an integer part of (2n−m) bits and divides by 2 ^m (the integer part is m The fractional part is truncated by shifting to the right. Specifically, after adding 1 to the most significant bit of the m-bit decimal part, the decimal part is truncated by shifting the integer part to the right by m bits. Thereby, when the most significant bit of the decimal part is 1, rounding up occurs, and the information of the decimal part is added to the integer part. On the other hand, when the most significant bit is 0, rounding up does not occur, which is the same as conventional rounding down. That is, when the most significant bit is 0, it is determined that the value of the decimal part is smaller than the command value and is ignored.

Furthermore, in the present embodiment, the lower n bits of data after truncation (after bit shift) are D / A converted and output to the adder 12 as the estimated disturbance value τd ′ of the filter processing result.
The second delay unit 24f is a functional block that reads data from a buffer memory (delay element) such as a RAM, and in the filter processing of the kth sample, y ((k-1) th sample y () held in the buffer memory. k-1) is read and output to the division unit 24g. Further, after outputting y (k−1), the input value y (k) of the kth sample is stored in the buffer memory.

The second division unit 24g rounds the m-bit fractional part in y (k-1) (2n bits) of the (k-1) -th sample from the second delay unit 24f to an integer part of (2n-m) bits. In addition, by dividing by 2 ^{− (m−1)} (the integer part is shifted to the right of (m−1) bits), y (k−1) is doubled and the decimal part is discarded. Specifically, after adding 1 to the most significant bit of the m-bit decimal part, the integer part is shifted to the right by (m-1) bits to double y (k-1) and the decimal. Truncate part. Thereby, when the most significant bit of the decimal part is 1, rounding up occurs, and the information of the decimal part is added to the integer part. On the other hand, when the most significant bit is 0, rounding up does not occur, which is the same as conventional rounding down.

Furthermore, in this embodiment, the lower n bits of data after rounding down the decimal part are output to the adder / subtractor 24b.
Next, the operation of this embodiment will be described with reference to FIG.
Here, FIGS. 3A to 3C are diagrams showing the flow of arithmetic processing of the coefficient multiplier 24c and the adder 24d, and FIGS. 3C to 3D are diagrams showing conventional division processing. (E)-(g) is a figure which shows the rounding process of this invention, and a division process.

  When a control command signal τ indicating a torque command value is output from the controller 10, the output control command signal τ is input to the adder 12. Further, the disturbance observer signal τd 'is input from the disturbance observer 16 to the adder 12, and the control command signal τ and the disturbance observer signal τd' are added. The addition signal “τ + τd ′” is output toward the controlled object 14 (DD motor) and the disturbance observer 16, but the added signal output toward the controlled object 14 is affected by the disturbance τd on the way, “Τ + τd′−τd” is input to the control object 14. The controlled object 14 rotates the motor based on this “τ + τd′−τd”. If “τd′−τd = 0”, the disturbance is completely canceled. The control object 14 detects the rotational angle position after the motor rotation by a position detector such as a resolver (not shown), and outputs the detected angular position signal θ to the disturbance observer 16 and the controller 10 as an output signal. To do. At this time, the observation noise N is mixed in the output signal.

When the angular position signal θ from the control target 14 is input, the disturbance observer 16 first A / D-converts the angular position signal θ by an A / D converter (not shown) in the inverse system 20. Then, a conversion process using an algorithm indicating the transfer function “1 / G _n (s)” is executed by executing a program by a DSP (not shown) to convert the angular position signal θ into the estimated control command signal τ *. . The estimated control command signal τ * is output to the subtracting unit 22.

  When the addition signal is input from the adder 12, the subtraction unit 22 first converts the addition signal into a digital signal by an A / D converter (not shown). Then, by executing the program by the DSP, the estimated disturbance command signal “τd * = τ + τd′−τ *” is obtained by subtracting the estimated control command signal τ * input from the inverse system 20 from the digital addition signal “τ + τd ′”. This is generated and output to the Q filter unit 24.

When the estimated disturbance signal τd * is input from the subtractor 22, the Q filter unit 24 executes a program that realizes the function of the digital filter Q (s) by a DSP (not shown), and applies the estimated disturbance signal τd * to the estimated disturbance signal τd *. Filter processing having a low-pass filter function.
Hereinafter, the operation will be described assuming that u (k), which is τd * of the kth sample, is input.
In accordance with the input timing of u (k), u (k−1), which is the previous sample input value, is read by the first delay unit 24a and input to the adder / subtractor 24b. On the other hand, from the second division unit 24g, 2y (k-1) obtained by doubling the filter processing result y (k-1) for the input value one sample before is added or subtracted in accordance with the input timing of u (k). Is input to the unit 24b. As a result, the adder / subtractor 24b executes an arithmetic process of “X = u (k) + u (k−1) −2y (k−1)”. The calculation result X is input to the coefficient multiplier 24c.

Hereinafter, u (k), u (k-1), and y (k-1) will be described as 16-bit data.
As shown in FIG. 3A, when the 16-bit X (no fractional part) that is the calculation result of the adder / subtractor 24b is input to the coefficient multiplying unit 24c, the coefficient multiplying unit 24c reads from the ROM (not shown), as shown in FIG. As shown in FIG. 5, a filter coefficient A (decimal part 15 bits), which is a 16-bit fixed-point number, is read out. Then, the input X and the read filter coefficient A are multiplied to calculate “X · A”, which is a 32-bit fixed-point number. The calculation result “X · A” is input to the adder 24d.

As illustrated in FIG. 3C, the adder 24 d reads “y (k−1) (32) read by the second delay unit 24 f into“ X · A ”(32 bits) from the coefficient multiplier 24 c. Bit). The addition result “y (k) = X · A + y (k−1)” (32 bits) is input to the first division unit 24e.
The first division unit 24e shifts the 17-bit integer part in y (k) of 32 bits to the right by 15 bits, thereby truncating the 15-bit fractional part (bits to the right of ▲ in the figure). Here, as shown in FIG. 3D, when the integer part is simply shifted to the right by 15 bits without performing rounding processing, conventional truncation processing is performed.

  As shown in FIG. 3E, the first division unit 24e of the present embodiment firstly sets “1” to the most significant bit (14th bit) in the 15-bit fractional part of 32 bits y (k). Is added. In the example of FIG. 3E, since the most significant bit of the decimal part is “1”, rounding up occurs as shown in FIG. That is, 1 is added to the least significant bit (15th bit) in the 17-bit integer part, and “0” in the 15th bit becomes “1”. In this way, processing equivalent to decimal rounding is performed.

Further, the first division unit 24e executes a process of dividing y (k) (32 bits) after rounding by “2 ¹⁵ ” in order to round down the fractional part. Specifically, as shown in FIG. 3G, the integer part is shifted to the right by 15 bits. Then, the lower 16-bit data after the shift is output as the output y (k) ′ of the digital filter Q (s).
This y (k) ′ is converted into an analog disturbance observer signal τd ′ by a D / A converter (not shown) and output to the adder 12. Since τd ′ includes only a calculation error smaller than a calculation error due to simple truncation, it is possible to reduce the occurrence of the control command value and the calculation error canceling each other.

For example, the maximum error in the present embodiment can be reduced to “0111111111111111” as compared with the conventional maximum error in which all 15 bits of the decimal part are 1 “111111111111111”.
On the other hand, y (k−1) (32 bits), which is the output of the adder 24d one sample before in the second delay unit 24f, is input to the second divider 24g, and similarly to the first divider 24e, A rounding process for adding 1 to the most significant bit of the 15-bit decimal part is performed.

Further, the second division unit 24g doubles y (k−1) after the rounding process and rounds down the fractional part thereof, so that “2 ¹⁴ ” is applied to y (k−1) (32 bits). ”Is executed. Specifically, the integer part of y (k−1) is shifted to the right by 14 bits. Then, the lower 16-bit data after the shift is output to the adder / subtractor 24b.
As described above, the disturbance suppression control apparatus 100 according to the present embodiment uses the fixed decimal arithmetic using the filter coefficient A in the filter processing of the digital filter Q (s) in the Q filter unit 24 constituting the disturbance observer 16. It is possible to add 1 to the most significant bit of the decimal part when truncating the decimal part of the subsequent fixed-point number.

As a result, the calculation error can be reduced as compared with the conventional case where the decimal part is simply discarded, and the occurrence of cancellation of the control command value and the calculation error can be reduced.
In the above embodiment, the control object 14 corresponds to the control object of any one of the inventions 1, 3, 4, and 5, and the disturbance observer 16 is the disturbance observer according to any one of the inventions 1, 4, and 5. The component including the disturbance observer 16 and the adder 12 corresponds to the disturbance suppressing device according to any one of the first to fourth aspects, and the adder 12 is any one of the first, fourth, and fifth aspects. The inverse system 20 and the subtraction unit 22 correspond to the estimated disturbance signal generation unit described in any one of the first, third, and fourth aspects, and the Q filter unit 24 corresponds to the first aspect. Corresponding to the Q filter unit described in any one of 1 to 4, the controller 10 corresponds to the error signal generation unit and the control command signal generation unit described in the fifth aspect.

Moreover, in the said embodiment, the process which rounds off the decimal part of the fixed-point number of a calculation result in the Q filter part 24 after rounding off is the fraction part truncation means of invention 1, or the decimal part of invention 4. Corresponds to the truncation step.
In the above embodiment, each process of the disturbance observer 16 is performed by causing the arithmetic unit to execute a dedicated program. However, the present invention is not limited to this, and the process that executes each process mainly by hardware. It is also good.

In the above embodiment, the digital filter Q (s) is a primary IIR filter. However, the present invention is not limited to this, and a secondary or higher order IIR filter may be used.
Moreover, in the said embodiment, although this invention was applied to feedback control of DD motor, you may apply not only to this but to motors other than a DD motor, and control objects other than a motor.

It is a control block diagram which shows the structure of the disturbance suppression control apparatus 100 which concerns on this Embodiment. It is a functional block diagram which shows the filter process of digital filter Q (s). (A)-(c) is a figure which shows the flow of the arithmetic processing of the coefficient multiplication part 24c and the addition part 24d, (c)-(d) is a figure which shows the conventional division process, (e) (G) is a figure which shows the rounding process of this invention, and a division process. It is a control block diagram which shows the structure of the conventional disturbance suppression type | mold control apparatus.

Explanation of symbols

100 Disturbance Suppression Control Device 10 Controller 12 Adder 14 Control Object 16 Disturbance Observer 20 Inverse System 22 Subtraction Units 24 and 26 Q Filter Unit

Claims (6)

A disturbance observer for generating a disturbance observer signal for suppressing the influence of the disturbance experienced by the rotary direct drive motor, the control command signal to the rotary direct drive motor and an addition signal of the disturbance observer signal A disturbance suppression device including an addition signal generation unit to generate,
The disturbance observer, indicates an estimate of the disturbance on the basis of the angular position signal and the sum signal is a signal indicating a rotational angular position of the rotary direct drive motor to the output of the rotary direct drive motor and the estimated disturbance signal generator for generating an estimated disturbance signal, a digital IIR (Infinit e Impulse Response) by arithmetic processing using a filter, undesired frequency domain signal contained in the estimated disturbance signal having a filter coefficient of a fixed-point number And a Q filter unit that selectively removes components,
The Q filter unit rounds the decimal part of the fixed-point number after the arithmetic processing using the filter coefficient to the integer part of the fixed-point number so that the DC gain of the control system including the disturbance suppressing device becomes 1 In addition, a disturbance suppressing device comprising a decimal part truncation means for truncating the decimal part.   The disturbance suppressing device according to claim 1, wherein the Q filter unit has a function of a low-pass filter that selectively removes a signal component in a frequency region higher than a predetermined frequency in the estimated disturbance signal. The estimated disturbance signal generator, using said angular position signal and the inverse of the transfer function of the rotary direct drive motor, for the rotary direct drive motor to output the angular position signal Required estimation control command signal generating means for generating an estimated control command signal that is a control command signal including a disturbance component, and a difference signal for generating an estimated disturbance signal that is a difference signal between the estimated control command signal and the addition signal Generating means,
3. The disturbance suppression device according to claim 1, wherein the disturbance observer signal is generated by filtering the difference signal in the Q filter unit. 4. A disturbance observer for generating a disturbance observer signal for suppressing the influence of the disturbance experienced by the rotary direct drive motor, the control command signal to the rotary direct drive motor and an addition signal of the disturbance observer signal A disturbance suppression device control method for controlling a disturbance suppression device including an addition signal generation unit to generate,
The disturbance observer, indicates an estimate of the disturbance on the basis of the angular position signal and the sum signal is a signal indicating a rotational angular position of the rotary direct drive motor to the output of the rotary direct drive motor and the estimated disturbance signal generator for generating an estimated disturbance signal, a digital IIR (Infinit e Impulse Response) by arithmetic processing using a filter, undesired frequency domain signal contained in the estimated disturbance signal having a filter coefficient of a fixed-point number And a Q filter unit that selectively removes components,
The Q filter unit causes the decimal part of the fixed-point number to be rounded to the integer part of the fixed-point number in the arithmetic processing so that the DC gain of the control system including the disturbance suppressing device is 1, and the decimal part is A disturbance control apparatus control method comprising a fractional part truncation step for truncation. An error signal generator for generating an error signal indicating an error for rotary direct drive motor output to the rotary-type direct drive motor target signal of the angular position signal is a signal indicating a rotational angular position of the error generating a control command signal generating unit for generating a control command signal so as to provide the rotary direct drive motor based on the signal, the disturbance observer signal for suppressing the influence of the disturbance experienced by the said rotary direct drive motor A disturbance suppression type control device comprising a disturbance observer, and an addition signal generation unit that generates an addition signal of the control command signal and the disturbance observer signal,
A disturbance suppression control apparatus comprising the disturbance suppression apparatus according to any one of claims 1 to 3. A rotary direct drive motor comprising the disturbance suppressing control device according to claim 5.

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