JP5444382B2 - Resin-sealed semiconductor device - Google Patents

Description

  The present invention relates to a resin-encapsulated semiconductor device, and more particularly, to a semiconductor device that obtains a plurality of resin-encapsulated semiconductor devices by collectively molding a plurality of semiconductor chips mounted on a wiring substrate and then dividing the wiring substrate. It is related to effective technology.

  In JP-A-11-214588 (Patent Document 1), a plurality of semiconductor chips are mounted on a TAB tape and resin-sealed, and then the resin and TAB tape are cut and cut individually to cut out a plurality of resins. A method of manufacturing a type semiconductor device is described.

  In the above publication, as a measure for preventing the cutting positions of the resin and the TAB tape from shifting, a part of the copper wiring formed on the outer periphery of the land portion of the TAB tape is used, and light is reflected by the copper wiring. Thus, a technique for displaying a cutting position and accurately recognizing the position is disclosed.

JP 11-214588 A

  The present inventor has developed a technique for manufacturing a plurality of resin-encapsulated semiconductor devices by collectively sealing a plurality of semiconductor chips mounted in a matrix on a wiring board and then dividing the wiring board. It is in.

  When such a manufacturing method is adopted, the individual resin-encapsulated semiconductor devices that have become finished products must be connected to the original wiring in order to quickly analyze the defects of products resulting from the manufacturing process and identify the locations where defects occur. It is necessary to be able to easily identify the position on the substrate even after the wiring substrate is divided.

  As a method, for example, when encapsulating a plurality of semiconductor chips mounted on a wiring board by encapsulating address information on an ejector pin of a mold die used for resin sealing of a semiconductor chip, the resin sealing It is conceivable that address information of a different pattern is given to each region of one type semiconductor device.

  However, the above method has the trouble that the address information of a different pattern for each type of product has to be engraved on the mold, and when using the standard specification (existing) mold of the requested manufacturer It cannot be applied.

  It is an object of the present invention to manufacture individual resin-encapsulated semiconductors when a plurality of resin-encapsulated semiconductor devices are manufactured by resin-encapsulating a plurality of semiconductor chips mounted on a circuit board and then dividing the circuit board. It is an object of the present invention to provide a technique for easily identifying the position of the apparatus on the original wiring board even after the wiring board is divided.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

The resin-encapsulated semiconductor device according to one aspect of the present application includes an upper surface, a plurality of first pads formed on the upper surface, a first solder resist formed on the upper surface, a lower surface opposite to the upper surface, and the lower surface A plurality of second pads formed on the lower surface, an index pattern formed on the lower surface, an address information pattern formed on the lower surface, a second solder resist formed on the lower surface, and between the upper surface and the lower surface A wiring board having side surfaces;
A main surface, a plurality of bonding pads formed on the main surface, and a back surface opposite to the main surface; a semiconductor chip mounted on the upper surface of the wiring board;
A resin having a main surface and side surfaces, and sealing the semiconductor chip,
Each of the upper surface of the wiring board and the main surface of the resin is a quadrangle,
Each side of the resin is flush with each side of the wiring board,
Each of the plurality of first pads is exposed from the first solder resist,
Each of the plurality of second pads and the index pattern are exposed from the second solder resist,
The address information pattern is covered with the second solder resist.

  A method of manufacturing a semiconductor device according to an invention of the present application includes: (a) preparing a wiring substrate having an upper surface, a plurality of semiconductor chip mounting regions provided on the upper surface, and a lower surface opposite to the upper surface; (B) After the step (a), a step of mounting a plurality of semiconductor chips on the plurality of semiconductor chip mounting regions, respectively, (c) After the step (b), of the plurality of semiconductor chips The wiring board is placed in a first mold such that a plurality of first semiconductor chips are located in a first cavity, and a plurality of second semiconductor chips of the plurality of semiconductor chips are located in a second cavity. Between the first mold and the second mold, and by supplying resin to each of the first and second cavities, the plurality of semiconductor chips are sealed with resin, and the plurality of first semiconductor chips are sealed. First resin blow to stop And a step of forming a second resin block that seals click and a plurality of second semiconductor chips.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Warping of the wiring board due to shrinkage of a resin for sealing a plurality of semiconductor chips can be suppressed.

1 is a partially enlarged plan view of a matrix substrate (upper surface) used for manufacturing a resin-encapsulated semiconductor device according to a first embodiment of the present invention. 1 is a partially enlarged plan view of a matrix substrate (lower surface) used for manufacturing a resin-encapsulated semiconductor device according to a first embodiment of the present invention. (A) is an enlarged plan view of a matrix substrate (upper surface) showing an area for one resin-encapsulated semiconductor device, and (b) is an enlarged plan view of the lower surface. 1 is a partially enlarged plan view of a matrix substrate (lower surface) used for manufacturing a resin-encapsulated semiconductor device according to a first embodiment of the present invention. 1 is a partial enlarged cross-sectional view of a matrix substrate used for manufacturing a resin-encapsulated semiconductor device according to a first embodiment of the present invention. It is a top view of the matrix board | substrate (upper surface) which shows the manufacturing method of the resin-sealed semiconductor device which is Embodiment 1 of this invention. It is a top view of the matrix substrate (lower surface) which shows the manufacturing method of the resin-encapsulated semiconductor device which is Embodiment 1 of this invention. It is the top view and schematic sectional drawing of a matrix substrate which show the manufacturing method of the resin sealing type semiconductor device which is Embodiment 1 of this invention. It is the top view and schematic sectional drawing of a matrix substrate which show the manufacturing method of the resin sealing type semiconductor device which is Embodiment 1 of this invention. It is the top view and schematic sectional drawing of a matrix substrate which show the manufacturing method of the resin sealing type semiconductor device which is Embodiment 1 of this invention. It is a schematic sectional drawing of the mold die which shows the manufacturing method of the resin sealing type semiconductor device which is Embodiment 1 of this invention. It is a top view of the matrix board | substrate (upper surface) which shows the manufacturing method of the resin sealing type semiconductor device which is Embodiment 1 of this invention. It is the top view and schematic sectional drawing of a matrix substrate which show the manufacturing method of the resin sealing type semiconductor device which is Embodiment 1 of this invention. It is a schematic sectional drawing of the matrix substrate which shows the manufacturing method of the resin sealing type semiconductor device which is Embodiment 1 of this invention. It is a top view of the matrix substrate (lower surface) which shows the manufacturing method of the resin-encapsulated semiconductor device which is Embodiment 1 of this invention. (A) is a top view of a resin-sealed semiconductor device, and (b) is a schematic sectional view. It is a flowchart which shows the manufacturing method of the resin sealing type semiconductor device which is Embodiment 1 of this invention. It is a functional block diagram which shows an example of the electronic device incorporating the resin-encapsulated semiconductor device of this invention. It is a partially expanded plan view of the matrix substrate (lower surface) used for manufacturing the resin-encapsulated semiconductor device according to the second embodiment of the present invention. It is the top view and schematic sectional drawing of a matrix substrate which show the manufacturing method of the resin sealing type semiconductor device which is Embodiment 2 of this invention. (A) is a top view of a resin-sealed semiconductor device, and (b) is a schematic sectional view. It is a flowchart which shows the manufacturing method of the resin sealing type semiconductor device which is Embodiment 2 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 and 2 are enlarged views showing a part of a matrix substrate used for manufacturing the resin-encapsulated semiconductor device of this embodiment. FIG. 1 shows a chip mounting surface (upper surface), and FIG. Each surface (lower surface) is shown.

  The matrix substrate 1A is made of, for example, a thin resin wiring substrate having a length × width = 500 mm × 500 mm and a thickness of about 0.22 mm to 0.6 mm, and a plurality of semiconductor chips are vertically formed on the upper surface thereof by a pelletizing process described later. It is mounted in a matrix along the direction and the horizontal direction. This matrix substrate 1A is made of a well-known wiring board material, for example, glass / epoxy resin, BT resin, polyimide resin, etc., and in particular, by being made of an inexpensive wiring board material such as glass / epoxy resin, The manufacturing cost of the sealed semiconductor device can be reduced. The matrix substrate 1A can also be configured by a flexible wiring substrate such as a flexible substrate (FPC).

  As shown in FIG. 1, a plurality of pads 2 are provided on the upper surface of a matrix substrate 1A, an alignment target 3 serving as a positioning guide when a semiconductor chip is mounted on the matrix substrate 1A in a pelletizing process described later, and the pads 2 and the electrical Wiring (not shown) connected to is formed.

  As shown in FIG. 2, on the lower surface of the matrix substrate 1A, a plurality of pads 4 to which solder bumps are connected and a wiring 5 formed integrally therewith, and the solder bumps are connected to the pads 4 in a ball attaching process described later. An alignment target 6 serving as a positioning guide, an index pattern 7 indicating a direction when the resin-encapsulated semiconductor device is mounted on the mounting substrate, an address information pattern 8 indicating address information of the resin-encapsulated semiconductor device, and the like are formed. Yes.

  FIG. 3A is an enlarged view of the upper surface of the matrix substrate 1A showing a rectangular region surrounded by a one-dot chain line in FIG. 1, that is, a region corresponding to one resin-encapsulated semiconductor device. Horizontal = 6.4 to 6.6 mm × 6.4 to about 6.6 mm. The pad 2, alignment target 3 and wiring (not shown) on the upper surface of the matrix substrate 1A are formed by etching an electrolytic copper foil (or rolled copper foil) having a thickness of about 20 μm attached to the upper surface of the matrix substrate 1A. The pad 2 and the alignment target 3 have a configuration in which the pattern shown in FIG. 3A is a unit, and this unit pattern is repeatedly arranged along the vertical and horizontal directions of the matrix substrate 1A. Also, the wiring (not shown) has the same configuration.

  FIG. 3B is an enlarged view of the lower surface of the matrix substrate 1A showing a region for one resin-encapsulated semiconductor device. The pad 4, wiring 5, alignment target 6, index pattern 7 and address information pattern 8 on the lower surface of the matrix substrate 1A are made of electrolytic copper foil (or rolled copper foil) having a thickness of about 20 μm attached to the lower surface of the matrix substrate 1A. It is formed by etching. Of these patterns, the pattern excluding the address information pattern 8 has the pattern shown in FIG. 3B as one unit, and this unit pattern is repeatedly arranged along the vertical and horizontal directions of the matrix substrate 1A. ing. The pads 4 and the wirings 5 are electrically connected to the pads 2 through through holes (not shown) formed in the matrix substrate 1A.

  The number of pads 4 formed in the region corresponding to one resin-encapsulated semiconductor device is, for example, a total of 48 pads of length × width = 6 × 8. Moreover, the vertical and horizontal pitches of these pads 4 are each 0.75 mm, for example. The alignment target 6 and the index pattern 7 shown in the figure are configured by a cross shape and a triangular pattern, respectively, but are not limited to these shapes.

  The address information pattern 8 includes information indicating the position of the resin-encapsulated semiconductor device obtained using the matrix substrate 1A in the matrix substrate 1A. For example, A11, It is comprised by different patterns, such as A12 ..., A21, A22 .... The figure shows an example in which the alignment target 6, the index pattern 7, and the address information pattern 8 are arranged at different positions, but it is also possible to arrange them in one place to share the function. For example, FIG. 4 shows an example in which the index pattern 7 and the address information pattern 8 are integrally formed to share functions. Also in this case, the portion functioning as the index pattern 7 (triangular pattern) is the same pattern in each of the regions (regions corresponding to one resin-encapsulated semiconductor device), and the portion functioning as the address information pattern 8 (characters) The pattern) is different for each of the above regions.

  The figure shows an example in which the address information pattern 8 is composed of a three-digit character pattern such as A11, A12,..., A21, A22, etc., but the present invention is not limited to this. Any pattern can be used as long as it has a different pattern in each region. In addition, the address information pattern 8 may include information other than the position information, for example, various information indicating a manufacturing lot of the matrix substrate 1A and a model number of a mold used in a molding process described later.

  FIG. 5 is a cross-sectional view showing a part of the matrix substrate 1A. As shown in the figure, a known solder resist 9 made of, for example, a thin epoxy resin having a film thickness of about several tens of μm is coated on both surfaces of the matrix substrate 1A to prevent a short circuit between the wirings 5 and 5 due to solder. It has come to be. Of the various patterns described above, for example, the solder resist 8 is removed from the surfaces of the pad 2, the pad 4 and the index pattern 7, and Au plating or the like is applied as necessary. Further, the surface of the address information pattern 8 is covered with a solder resist 9 or removed according to means for recognizing the pattern 8 (camera, microscope, etc.).

  Next, a method for manufacturing a resin-encapsulated semiconductor device using the matrix substrate 1A will be described in the order of steps with reference to FIGS.

  First, the matrix substrate 1A as shown in FIGS. 6 and 7 is obtained by cutting the matrix substrate 1A and dividing it into a plurality of small pieces. The dimension of this matrix substrate 1B is, for example, about vertical × horizontal = 30 mm to 70 mm × 150 mm to 230 mm. The matrix substrate 1B for molding is defined by the size of the mold used in the molding process to be described later. Therefore, when the matrix substrate 1A is manufactured according to the size of the mold from the beginning, it is cut. The dividing step is not necessary. For the cutting of the matrix substrate 1A, a known dicing apparatus (dicer) used for cutting a resin wiring substrate is used. In addition, guide holes 11 used for positioning when the matrix substrate 1B is loaded onto the mold in the molding process are provided at the four corners of the matrix substrate 1B.

  Next, as shown in FIG. 8, a plurality of semiconductor chips (hereinafter simply referred to as chips) 12 are mounted on the upper surface of the matrix substrate 1B. The chip 12 has, for example, a memory LSI such as SRAM (Static Random Access Memory) formed on its main surface, and a plurality of bonding pads BP formed on two opposite sides. Vertical × Horizontal = 4.5 mm to 5.0 mm × It consists of single crystal silicon of about 5.5 mm to 6.0 mm. When the chip 12 is mounted on the matrix substrate 1B, alignment is performed by recognizing the position of the alignment target 3 with a camera or the like. For joining the chip 12 and the matrix substrate 1B, a known acrylic / epoxy resin adhesive, Ag paste, or the like is used.

  Next, as shown in FIG. 9, the pads 2 of the matrix substrate 1 </ b> B and the bonding pads BP of the chip 12 are electrically connected by wires 13. For example, a gold (Au) wire is used as the wire 13. For connection using the wire 13, for example, a well-known wire bonding apparatus using both thermocompression bonding and ultrasonic vibration is used.

  Next, as shown in FIG. 10, all the chips 12 on the matrix substrate 1 </ b> B are sealed with a resin 14. In order to seal the chip 12 with the resin 14, as shown in FIG. 11, the matrix substrate 1B is loaded onto the mold 15 of the molding apparatus and, for example, guide holes 11 (FIG. 6, FIG. 6) provided at the four corners of the matrix substrate 1B. After positioning the pins (not shown) of the mold 15 in the mold 15 (see FIG. 7), the resin is supplied to the gap (cavity) between the upper mold 15a and the lower mold 15b, whereby the matrix substrate 1B is supplied. All the mounted chips 12 are sealed with resin. As the sealing resin 14, for example, a well-known epoxy resin containing silica is used. As the molding apparatus, for example, a well-known molding apparatus used for manufacturing a QFP (Quad Flat Package) or a wafer level CSP (Chip Size Package) is used.

  Since the dimension of the matrix substrate 1B is larger than that of a normal resin-encapsulated semiconductor device (for example, QFP), when all the chips 12 mounted on the matrix substrate 1B are encapsulated in a resin, The warpage of the matrix substrate 1B may occur due to the shrinkage of the resin 14 and the connection between the pads 4 and the solder bumps may not be achieved in a ball attaching process described later. If there is such a possibility, as shown in FIG. 12, the resin 14 is divided into a plurality of blocks using a mold having a plurality of cavities, or slits 16 are formed in the matrix substrate 1B. It is desirable to suppress warping of the matrix substrate 1B.

  Next, as shown in FIG. 13, solder bumps 17 are connected to the pads 4 formed on the lower surface of the matrix substrate 1B. The solder bump 17 is made of, for example, a well-known Sn / Pb eutectic alloy solder. For the connection between the pads 4 and the solder bumps 17, for example, a plurality of solder balls are mounted on a well-known ball attachment jig used in the manufacture of BGA (Ball Grid Array) or the like, and all the pads formed on the matrix substrate 1B are connected. After these solder balls are connected to the pad 4 in a lump, the solder balls are reflowed in a heating furnace. When the solder ball is connected to the pad 4, the alignment is performed by recognizing the position of the alignment target 6 with a camera or the like.

  Next, as shown in FIG. 14, the BGA type resin-encapsulated semiconductor device 20 is obtained by cutting the matrix substrate 1B and the resin 14 in units of chips and dividing them into a plurality of small pieces. In order to cut the matrix substrate 1A and the resin 14, for example, a well-known dicing apparatus (dicer) used for cutting a resin wiring board is used in which a dicing blade having a width of about 200 μm is attached. At this time, as shown in FIG. 15, by forming an alignment target 18 for dicing on the lower surface of the matrix substrate 1B, cutting with high dimensional accuracy can be performed. This alignment target 18 is made of, for example, a wiring material (copper) and may be formed simultaneously with the other alignment targets 3 and 6.

  The plurality of resin-encapsulated semiconductor devices 20 obtained by cutting the matrix substrate 1B are subjected to a sorting test using a tester, and thereafter, as shown in FIG. A mark 19 (including the surface index mark) is printed. The mark 19 is printed by well-known laser processing or ink marking.

  Thereafter, the resin-encapsulated semiconductor device 20 is subjected to a sorting test and an appearance inspection using a tester, and only non-defective products are packaged and shipped to a requesting maker and the like, and then mounted on a substrate of various electronic devices. . When the resin-encapsulated semiconductor device 20 is mounted on a substrate, alignment is performed by recognizing the index pattern 7 formed on the mounting surface with a camera or the like.

  FIG. 17 is a flow of the manufacturing process described above. FIG. 18 is a functional block diagram of an electronic device (for example, a mobile phone) in which the resin-encapsulated semiconductor device 20 is incorporated.

  According to the manufacturing method of the present embodiment described above, each resin-encapsulated semiconductor device 20 that is a finished product is obtained by recognizing the address information pattern 8 formed on the matrix substrate 1A with a camera, a microscope, or visually. Since the position of the original matrix substrate 1A can be easily identified even after the division of the matrix substrate 1B, it is possible to quickly analyze the defect of the product due to the manufacturing process and specify the location where the defect has occurred.

(Embodiment 2)
In the first embodiment, the address information pattern 8 is formed on the mounting surface of the matrix substrate 1A using the wiring material. However, the present invention is not limited to this. For example, the address information pattern 8 is formed by the following method. You can also

  First, a matrix substrate 1A as shown in FIG. 19 is prepared. The matrix substrate 1A has the same configuration as the matrix substrate 1A of the first embodiment except that the address information pattern 8 is not formed.

  Next, according to the steps shown in FIGS. 6 to 11 of the first embodiment, formation of the mold matrix substrate 1B, mounting of the chip 12, bonding of the wire 13, and batch sealing of the chip 12 with the resin 14 were performed. Thereafter, as shown in FIG. 20, a mark 19 such as a product name or a manufacturing lot is printed on the surface of the resin 14. In the present embodiment, at the same time, the address information pattern 8 is printed on the surface of the resin 14. The marks 19 and the address information pattern 8 are printed by well-known laser processing or ink marking. The mark 19 has the same pattern in each region corresponding to one resin-encapsulated semiconductor device, and the address information pattern 8 has a different pattern in each of the above regions.

  Next, the resin-encapsulated semiconductor device 20 as shown in FIG. 21 is obtained by connecting the solder bumps 17 and cutting the matrix substrate 1B according to the steps shown in FIGS. can get. Note that the marks 19 and the address information pattern 8 may be printed on the surface of the resin 14 after the solder bumps 17 are connected. Thereafter, the resin-encapsulated semiconductor device 20 is subjected to a sorting test and an appearance inspection using a tester, and only good products are packaged and shipped, and then mounted on substrates of various electronic devices. FIG. 22 is a flow of the manufacturing process described above.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is not limited to the BGA type resin-encapsulated semiconductor device, but can be applied to various resin-encapsulated semiconductor devices having external connection terminals other than solder bumps, such as TSOJ, LGA, and mini cards. it can. Further, the chip is not limited to the SRAM, and for example, a chip on which various memory LSIs such as a DRAM and a flash memory are formed can be used.

  The present invention can be applied to the manufacture of a resin-encapsulated semiconductor device.

1A, 1B matrix substrate (wiring substrate)
2 Pad 3 Alignment target 4 Pad 5 Wiring 6 Alignment target 7 Index pattern 8 Address information pattern 9 Solder resist 11 Guide hole 12 Semiconductor chip 13 Wire 14 Resin 15 Mold 15a Upper mold 15b Lower mold 16 Slit 17 Solder bump 18 Alignment target 19 Mark 20 Resin-sealed semiconductor device BP Bonding pad

Claims (9)

Upper surface, a plurality of first pads formed on the upper surface, a first solder resist formed on the upper surface, a lower surface opposite to the upper surface, a plurality of second pads formed on the lower surface, formed on the lower surface An index pattern, an address information pattern formed on the lower surface, a second solder resist formed on the lower surface, and a wiring board having a side surface between the upper surface and the lower surface,
A main surface, a plurality of bonding pads formed on the main surface, and a back surface opposite to the main surface; a semiconductor chip mounted on the upper surface of the wiring board;
A resin having a main surface and side surfaces, and sealing the semiconductor chip;
Including
Each of the upper surface of the wiring board and the main surface of the resin is a quadrangle,
Each side of the resin is flush with each side of the wiring board,
Said plurality of first pad is exposed from the first solder resist,
Wherein the plurality of second pad and the index pattern, is exposed from the second solder resist,
The resin-encapsulated semiconductor device, wherein the address information pattern is covered with the second solder resist.   2. The resin-encapsulated semiconductor device according to claim 1, wherein each of the side surface of the resin and the side surface of the wiring board is a cut surface formed by the same cutting process.   3. The resin-encapsulated semiconductor device according to claim 1, wherein a plurality of solder bumps are connected to the plurality of second pads, respectively. 3. The resin-encapsulated semiconductor device according to claim 1, wherein a plurality of external connection terminals are respectively formed on the plurality of second pads.   5. The index pattern is arranged on a peripheral edge side of the lower surface of the wiring board with respect to the plurality of second pads on the lower surface of the wiring board. The resin-encapsulated semiconductor device described. The index pattern is a pattern indicating the direction of the resin-encapsulated semiconductor device,
2. The resin-encapsulated semiconductor device according to claim 1, wherein the address information pattern is a pattern indicating address information of the resin-encapsulated semiconductor device.   The resin-encapsulated semiconductor device according to claim 1, wherein a mark is formed on the main surface of the resin.   8. The resin-encapsulated semiconductor device according to claim 7, wherein the mark is a product name or a production lot.   2. The resin-encapsulated semiconductor device according to claim 1, wherein each of the plurality of first pads, the plurality of second pads, the index pattern, and the address information pattern is made of copper foil.

Images