JP5318915B2 - Optical module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a high frequency property even in an optical module which employs a can type package. <P>SOLUTION: A LD element 5 is mounted on a stem mount 1c of a stem 1 connected to a ground, and a high frequency electric signal is supplied to the LD element 5 via lead terminals 2a, 2b. Lower surfaces of chip capacitors 10a, 10b are connected to the stem mount 1c. The lead terminal 2a is connected to a cathode of the LD element 5 via the chip capacitor 10a, and the lead terminal 2b is connected to an anode of the LD element 5 via the chip capacitor 10b. The characteristic impedance of transmission lines 13a, 13b decreases by connecting chip capacitors 10a, 10b, thereby reflections at interfaces of transmission lines 12a, 12b to 13a, 13b are prevented to improve the high frequency characteristic. <P>COPYRIGHT: (C)2013,JPO&amp;INPIT

Description

  The present invention relates to an optical module in general, and more particularly to an optical semiconductor element module having excellent high frequency characteristics.

  In recent years, with the widespread use of optical access lines, there has been a demand for cost reduction of optical modules (LD modules) equipped with laser diodes (LD) as optical signal sources. In addition, in order to cope with traffic increase due to increased distribution of video content and the like in an optical access network, an LD module capable of supporting a transmission speed of 10 Gbit / s class is required.

  In order to reduce the cost of the LD module, it is advantageous to use an inexpensive can package (for example, see Patent Documents 1 and 2) such as an LD package for DVD and an LD package for low speed (1 Gbit / s or less) optical communication. The LD package for DVD and low-speed optical communication is assumed to be used at a low transmission speed of 10 Mbit / s to 1 Gbit / s, so the lead protruding from the top surface of the stem is as long as about 1 mm. It is difficult to ensure high-frequency characteristics due to the effect of inductance, and driving at 10 Gbit / s class causes large distortion in the optical signal waveform output by the LD module. It is not realistic to apply it as it is.

  On the other hand, the above problem can be avoided by shortening the lead and introducing a technique for replacing the wire for electrically connecting the lead and the LD element with a wiring board, but it is completely different from the DVD LD package. Because of the mounting form, there was a problem that the benefits of low cost due to mass production effects could not be enjoyed.

Details of the prior art will be described with reference to FIG.
7A and 7B show a side view and a top view of a conventional can-type LD package, respectively. Although not shown, the LD package is usually sealed with a cap provided with a window for taking out LD light or a lens. That is, each member disposed on the stem upper surface 1a and the stem upper surface 1a side of the stem 1 (such as the LD element 5, the monitor PD 7, the stem mount 1c, and the portions protruding from the stem upper surface 1a of the lead terminals 2a, 2b, 2c). Is sealed with a cap.

  As shown in FIGS. 7A and 7B, the stem 1 made of a conductive material (metal material) includes through holes 3a, 3b, 3c, and the through holes 3a, 3b, 3c are lead terminals 2a, 2b. , 2c. Here, the lead terminals 2a, 2b, 2c are fixed through an insulator (dielectric) 3d such as a glass material provided in the through holes 3a, 3b, 3c and penetrate the stem 1, so that the lead terminals 2a, 2b, 2c and the stem 1 are electrically insulated. The lead terminals 2a and 2b are provided to supply drive electric signals to the cathode and anode of the LD element 5 mounted on the stem mount 1c, which is a part of the stem 1, respectively. On the other hand, since the lead terminal 2d does not penetrate the stem 1 and is connected to the stem lower surface 1b by brazing or the like, it is electrically connected to the stem 1 and serves as a ground pin. Therefore, when the lead terminal 2d is connected to the ground, the stem 1 and the stem mount 1c as a part thereof are connected to the ground.

  The LD element 5 uses a dielectric having a high thermal conductivity and a thermal expansion coefficient close to that of the material of the LD element 5 (for example, AlN in the case of an LD element made of an InP-based material) as the heat sink 6a. Yes. The heat sink 6a is fixed to the stem mount 1c with solder or the like, and a wiring pattern 6b for wire wiring is provided on the upper surface of the heat sink 6a. A cathode (not shown) provided on the lower surface of the LD element 5 is fixed with a wiring pattern 6b and solder or the like.

  Most of the LD signals emitted from the LD element 5 are emitted in the direction opposite to the stem upper surface direction (+ z-axis direction). On the other hand, the light output intensity of the LD element 5 can be monitored by receiving the slightly emitted signal light in the stem upper surface direction (−z-axis direction) with the monitor PD 7. Such a monitor PD 7 generally has an APC (Auto Power Control) function that can obtain a constant light output intensity by controlling the drive current value of the LD element 5 so that the light receiving current of the monitor PD 7 is constant. Introduced to realize. The monitor PD 7 is mounted on the PD carrier 8 disposed in the stem recess 1d. The cathode of the monitor PD 7 is electrically connected to one end on the upper side of the stem of the lead terminal 2c via a wire 9a. Further, since the anode is electrically connected to the upper surface 1a of the stem via the wire 9b, it becomes a ground equivalent to the stem 1.

  Next, details of the transmission line of the LD drive electric signal, that is, the power supply system to the LD element 5 will be described. On the cathode side, a high-speed driving electric signal from the outside of the LD package reaches one end on the stem upper surface side from one end on the stem lower surface side of the lead terminal 2a, and passes through the wiring pattern 6b of the wire 4a and the heat sink 6a to the LD element. Power is supplied to the cathode provided on the lower surface (not shown) of 5. On the anode side, a high-speed driving electric signal from the outside of the LD package reaches one end on the stem upper surface side from one end on the stem lower surface side of the lead terminal 2b, and reaches the anode on the upper surface of the LD element 5 via the wire 4b. Is supplied with power.

  Here, the electric signal line on the cathode side is divided into transmission lines 11a, 12a, and 13a. The transmission line 11a extends from one end on the stem lower surface side of the lead terminal 2a to the stem lower surface 1b, the transmission line 12a passes through the stem 1 of the lead terminal 2a, and the transmission line 13a extends from the stem upper surface 1a to the stem upper surface side of the lead terminal 2a. To one end. Similarly, on the anode side, the transmission line 11b extends from one end on the stem lower surface side of the lead terminal 2b to the stem lower surface 1b, the transmission line 12b penetrates the stem 1 of the lead terminal 2b, and the transmission line 13b represents the stem upper surface 1a. To one end on the stem upper surface side of the lead terminal 2b.

  Next, the characteristic impedance in the vicinity of 10 GHz of the transmission lines 12a (12b) and 13a (13b) is estimated. The length of the transmission line 12a (12b) is 1.2 mm, the diameter of the through holes 3a, 3b is about 1 mm, and the dielectric constant of the glass material (insulating material 3d as a dielectric) provided in the through holes 3a, 3b. Is 4 to 7, the characteristic impedance of the transmission line 12a (12b) in the vicinity of 10 GHz is about 15 to 30Ω. On the other hand, the transmission line 13a (13b) is different from the transmission line 12a (12b) because there is no dielectric such as glass around the lead terminal 2a (2b), and the length is about 1 mm and the inductance component is long. The characteristic impedance in the vicinity of 10 GHz of the transmission line 13a (13b) becomes larger than the value (15 to 30Ω) of the transmission line 12a (12b). Therefore, the electrical signal input from the transmission line 11a (11b) passes through the transmission line 12a (12b), and then is reflected at the interface between the transmission line 12a (12b) and the transmission line 13a (13b), and is transmitted to the transmission line 12a. In the S11 characteristic 10 GHz of ˜13a (12b-13b), the high frequency characteristic becomes very bad at about −3 dB (FIG. 2, FIG. 4 and FIG. 6 show the high frequency characteristic of the conventional example).

JP 2008-170636 A JP 2004-363242 A

  As described above, in the prior art, the input high-frequency electric signal is reflected at the interface between the transmission line 12a (12b) and the transmission line 13a (13b) after passing through the transmission line 12a (12b). There was a problem that the high frequency characteristics of 12a to 13a (12b to 13b) deteriorated.

  An object of the present invention is to provide an optical module excellent in high frequency characteristics that can be driven by a 10 Gbit / s class high-speed signal even if a conventional inexpensive can package is used.

The configuration of the present invention for solving the above problems is as follows.
A stem made of a conductive material and connected to the ground;
A first lead terminal that is attached to the stem through the stem and electrically insulated from the stem by interposing an insulating material in a portion that penetrates the stem;
A second lead terminal which is attached to the stem through the stem and electrically insulated from the stem by interposing an insulating material in a portion penetrating the stem;
In an optical module having a laser diode mounted on a stem mount that is part of the stem ,
The stem mount includes a first chip capacitor and a second chip capacitor,
The first chip capacitor has one end electrically connected to the stem mount and the other end connected to the first lead terminal and the cathode or anode of the laser diode via a wire,
The second chip capacitor has one end electrically connected to the stem mount and the other end connected to the second lead terminal and the anode or cathode of the laser diode via a wire,
The first lead terminal, the second lead terminal, and the first lead terminal in a state in which the surface of the stem mount on which the first chip capacitor and the second chip capacitor are provided is viewed from the front. The chip capacitor and the second chip capacitor are not in overlapping positions,
The differential drive electrical signal passes through the first lead terminal and the first chip capacitor, and passes through the second lead terminal and the second chip capacitor, and then the laser diode. It is characterized by being supplied to .

The configuration of the present invention is as follows.
A first dielectric substrate is provided between the laser diode and the stem mount,
And, the lower surface of the first dielectric substrate is formed with metallization on the entire surface, and is electrically connected to the stem mount,
The top surface of the first dielectric substrate has a second wiring pattern for electrically connecting the first lead terminal or the second lead terminal and the laser diode,
And the cathode or anode of the laser diode is electrically connected to the second wiring pattern,
The first chip capacitor has one end electrically connected to the stem mount, the other end connected to the first lead terminal via a wire, and via a wire and a second wiring pattern. Connected to the cathode or anode of the laser diode;
One end of the second chip capacitor is electrically connected to the stem mount, the other end is connected to the second lead terminal via a wire, and the anode of the laser diode or the It is connected to the cathode .

The configuration of the present invention is as follows.
Furthermore, one or more third chip capacitors and one or more fourth chip capacitors are provided.
The third chip capacitor has one end electrically connected to the stem mount and the other end connected to the first chip capacitor of the first lead terminal via a wire. Are connected to each other, and are arranged so that the lengths of the respective wires connecting the first lead terminal and the other ends of the first chip capacitor and the third chip capacitor are equal to each other,
The fourth chip capacitor has one end electrically connected to the stem mount and the other end connected to the second chip capacitor of the second lead terminal via a wire; Are connected to each other, and are arranged so that the lengths of the respective wires connecting the second lead terminal and the other ends of the second chip capacitor and the fourth chip capacitor are equal to each other,
The first chip capacitor and the third chip capacitor all have the same capacitance value,
And each connection point which connects the 1st chip capacitor and the 3rd chip capacitor, and the 1st lead terminal is equidistant,
And the second chip capacitor and the fourth chip capacitor all have the same capacitance value,
And each connection point which connects the 2nd chip capacitor and the 4th chip capacitor, and the 2nd lead terminal is equidistant,
A pseudo distributed constant circuit is formed by the first and second lead terminals, the first to fourth chip capacitors, and the wires .

The configuration of the present invention is as follows.
Said laser diode, said chip capacitor, said laser diode and portion where the chip capacitor is projected to the side that is located out of the lead terminals, the laser diode and the chip capacitor of the surface of the stem is located The side surface is sealed with a cap.

  According to the present invention, it is possible to provide an inexpensive optical module that has good high-frequency characteristics capable of high-speed signal transmission of 10 Gbit / s class and is configured by an existing package.

It is a block diagram which shows the optical module of 1st Embodiment of this invention, Comprising: (a) is a side view, (b) is a top view. It is a characteristic view which shows the characteristic of the optical module of 1st Embodiment with a conventional characteristic. It is a block diagram which shows the optical module of the reference example of this invention, Comprising : (a) is a side view, (b) is a top view. It is a characteristic view which shows the characteristic of the optical module of a reference example with a conventional characteristic. It is a block diagram which shows the optical module of 2nd Embodiment of this invention, (a) is a side view, (b) is a top view. It is a characteristic view which shows the characteristic of the optical module of 2nd Embodiment with a conventional characteristic. It is a block diagram which shows the conventional optical module, Comprising: (a) is a side view, (b) is a top view.

  Hereinafter, embodiments of the present invention will be described in detail based on examples.

(Optical module using chip capacitors)
Hereinafter, the optical module according to the first embodiment of the present invention will be described in detail with reference to FIG. 1A and 1B are a side view and a top view, respectively, of the optical module of the first embodiment. 1, the configuration is the same as that of the conventional optical module shown in FIG. 7 except that chip capacitors 10a and 10b and wires 4a-1, 4a-2, 4b-1, and 4b-2 are introduced. (In FIG. 7 and FIG. 1, the same member is numbered in common in FIG. 7 and FIG. 1). Therefore, only the addition of the chip capacitors 10a and 10b and the arrangement of the wires are changed, and the package used is the same as a conventional inexpensive can-type LD package.

Further, the characteristic configuration of the first embodiment will be described. The chip capacitors 10a and 10b have electrodes for electrical connection on the upper and lower surfaces, respectively, and one end (lower surface) of the chip capacitors 10a and 10b is made of a conductive material. The stem 1 is electrically connected to the stem mount 1c and connected to the ground.
The wire 4a-1 electrically connects the other end (upper surface) of the chip capacitor 10a and the lead terminal 2a. The wire 4a-2 electrically connects the other end (upper surface) of the chip capacitor 10a and a wiring pattern 6b for wire wiring formed on the upper surface of the heat sink 6a. The wiring pattern 6b is electrically connected to the cathode formed on the lower surface of the LD element 5. After all, the other end (upper surface) of the chip capacitor 10 a is electrically connected to the lead terminal 2 a and the cathode on the lower surface of the LD element 5.
The wire 4b-1 electrically connects the other end (upper surface) of the chip capacitor 10b and the lead terminal 2b. The wire 4 b-2 is electrically connected to the other end (upper surface) of the chip capacitor 10 b and the anode formed on the upper surface of the LD element 5. Eventually, the other end (upper surface) of the chip capacitor 10 b is electrically connected to the lead terminal 2 b and the anode on the upper surface of the LD element 5.

  The optical module shown in FIG. 1 is a module for an optical communication system for transmitting a 10 Gbit / s class high-speed optical signal, and an LD element 5 is mounted as an optical semiconductor element. As the LD element 5, a distributed feedback LD (DFB-LD) having an active layer having a multiple quantum well (MQW) structure containing InGaAlAs having excellent temperature characteristics is suitable.

  In the optical module of the first embodiment shown in FIG. 1, among the 10 Gbit / s class differential drive electric signals (N signal, P signal) from the outside of the stem, the N signal passes through the transmission lines 11a, 12a, and 13a. Then, the wire 4a-1, the chip capacitor 10a, the wire 4a-2, and the wiring pattern 6b formed on the upper surface of the heat sink 6a are supplied to the cathode side formed on the lower surface (not shown) of the LD element 5. . Similarly, the P signal is supplied to the anode side of the LD element 5 through the transmission lines 11b, 12b, and 13b, through the wire 4b-1, the chip capacitor 10b, and the wire 4b-2.

Here, paying attention to the N signal, the introduction of the chip capacitor 10a, which is a shunt capacitor component, reduces the characteristic impedance of the transmission line 13a, and as a result, the characteristic impedance difference between the transmission lines 12a-13a is reduced. It becomes possible to suppress the reflection of the N signal between −13a. Similarly, in the P signal, the introduction of the chip capacitor 10b, which is a shunt capacitor component, reduces the characteristic impedance of the transmission line 13b. As a result, the characteristic impedance difference between the transmission lines 12b-13b is reduced. It becomes possible to suppress the reflection of the P signal between 13b.
As described above, since reflection of the drive electric signal (N signal, P signal) can be suppressed, high frequency characteristics can be improved.

  FIG. 2 shows the high frequency characteristics of a can type LD package in which a chip capacitor is actually introduced. The measurement was performed on the N signal side. As shown in FIG. 2, in the conventional method without introducing a chip capacitor, S21 (transmission characteristics) = − 3 dB and S11 (reflection characteristics) = − 3 dB were very deteriorated at a frequency of 10 GHz. On the other hand, when a chip capacitor was introduced and the capacitance was 0.2 pF, S21 = −2 dB and S11 = −5 dB were improved. Further, by increasing the capacitances to 0.4 pF and 0.6 pF, S21 = about −1 dB and S11 = −7 to −10 dB were further improved.

  Therefore, even if an inexpensive can-type package with poor high-frequency characteristics is used, this embodiment in which only a very inexpensive chip capacitor is added can provide good high-frequency characteristics even when driven with a 10 Gbit / s class high-speed signal. It is done. The chip capacitors 10a and 10b each desirably have a capacitance of about 0.1 pF to 1 pF, and the range of 0.2 to 0.6 pF is most effective.

Reference example

(Module for optical semiconductor elements using MIM capacitors)
Hereinafter, an optical module which is a reference example of the present invention will be described in detail with reference to FIG. 3A and 3B are a side view and a top view, respectively, of an optical module of a reference example . 3 except that MIM (metal-insulator-metal) capacitors 10c, 10d, wires 4a, 4b-1, 4b-2, and wiring patterns 6b, 6c, 6d of the heat sink 6a are introduced in FIG. The configuration is the same as the conventional optical module shown (the same members in FIGS. 7 and 3 are given the same numbers in FIGS. 7 and 3). Therefore, only the addition of the MIM capacitors 10c and 10d and the change of the wiring pattern (wiring patterns 6b, 6c and 6d) of the heat sink 6a are performed, and the package used is the same as the conventional inexpensive can-type LD package. It is.

  The MIM capacitors 10c and 10d can be easily formed on the substrate by adopting a configuration in which the dielectric thin film is sandwiched between two metal films, and 100 μm by controlling the dielectric constant and thickness of the dielectric thin film. It is characterized in that a capacitance of about 0.1 to 1 pF can be realized even with a small corner size. Further, since it can be formed on a heat sink material for LD such as AlN, one of the upper and lower electrodes of the MIM capacitors 10c and 10d is electrically connected to the wiring pattern on the heat sink 6a without wire connection. Can do. For this reason, the wire 4a-2 in the first embodiment shown in FIG. 1 is not necessary, so that parasitic inductance is generated in the wire connection portion of the element having capacitance (chip capacitor, MIM capacitor, photodiode, etc.) and the LD heat sink. This is advantageous in that it can be prevented.

Further, the characteristic configuration of the reference example will be described. Wiring patterns 6b, 6c and 6d for wiring are formed on the heat sink 6a. The wiring patterns 6b and 6c are formed on the surface of the heat sink 6a. The wiring pattern 6d is formed (conductive) from the surface of the heat sink 6a to the lower surface of the heat sink 6a through the side surface, and is connected to the ground by being connected to the stem mount 1c (stem 1) on the lower surface side.

The lower surface of the MIM capacitor 10c is connected to the wiring pattern 6d. For this reason, the lower surface of the MIM capacitor 10c is connected to the ground via the wiring pattern 6d. The upper surface of the MIM capacitor 10c is connected to the lead terminal 2a through the wire 4a, and is connected to the wiring pattern 6b through the capacitor upper electrode (air bridge) 10c-1. Such air bridge wiring can be realized by an integrated process with the MIM capacitor manufacturing technology, but may be connected by a wire or the like instead of the air bridge. A cathode (lower surface) of the LD element 5 is connected to the wiring pattern 6b. After all, the upper surface of the MIM capacitor 10 c is electrically connected to the lead terminal 2 a and the cathode (lower surface) of the LD element 5.
The capacitor upper electrode (air bridge) 10c-1 extends from the upper surface of the MIM capacitor 10c in the direction of the wiring pattern 6b and extends from the upper side to the lower side of the wiring pattern 6b and is connected to the wiring pattern 6b.

The lower surface of the MIM capacitor 10d is connected to the wiring pattern 6d. For this reason, the lower surface of the MIM capacitor 10d is connected to the ground via the wiring pattern 6d. The upper surface of the MIM capacitor 10d is connected to the lead terminal 2b through the wire 4b-1, and is connected to the wiring pattern 6c through the capacitor upper electrode (air bridge) 10d-1. The wiring pattern 6c is connected to the anode (upper surface) of the LD element 5 through the wire 4b-2. After all, the upper surface of the MIM capacitor 10 d is electrically connected to the lead terminal 2 b and the anode (upper surface) of the LD element 5.
The capacitor upper electrode (air bridge) 10d-1 extends from the upper surface of the MIM capacitor 10d in the direction of the wiring pattern 6c, and extends downward from the upper side of the wiring pattern 6c to be connected to the wiring pattern 6c.

  The optical module shown in FIG. 3 is a module for an optical communication system for transmitting a 10 Gbit / s class high-speed optical signal, and an LD element 5 is mounted as an optical semiconductor element. As the LD element 5, a distributed feedback LD (DFB-LD) having an active layer having a multiple quantum well (MQW) structure containing InGaAlAs having excellent temperature characteristics is suitable.

In the optical module of the reference example shown in FIG. 3, among the 10 Gbit / s class differential drive electrical signals (N signal, P signal) from the outside of the stem, the N signal passes through the transmission lines 11a, 12a, 13a, It is supplied to the cathode side formed on the lower surface (not shown) of the LD element 5 through the wire 4a, the upper surface of the MIM capacitor 10c, the air bridge 10c-1, and the wiring pattern 6b of the heat sink 6a.

  Similarly, the P signal also passes through the transmission lines 11b, 12b, and 13b, and passes through the wire 4b-1, the upper surface of the MIM capacitor 10d, the air bridge 10d-1, the wiring pattern 6c of the heat sink 6a, and the LD element through the wire 4b-2. 5 is supplied to the anode side.

Here, focusing on the N signal, the introduction of the MIM capacitor 10c, which is a shunt capacitor component, reduces the characteristic impedance of the transmission line 13a, and as a result, the characteristic impedance difference between the transmission lines 12a-13a is reduced. It becomes possible to suppress the reflection of the N signal between −13a. Similarly, in the P signal, the introduction of the MIM capacitor 10d, which is a shunt capacitor component, reduces the characteristic impedance of the transmission line 13b. As a result, the characteristic impedance difference between the transmission lines 12b-13b is reduced. It becomes possible to suppress the reflection of the P signal between 13b.
As described above, since reflection of the drive electric signal (N signal, P signal) can be suppressed, high frequency characteristics can be improved.

  FIG. 4 shows the high frequency characteristics of the can type LD package in which the MIM capacitor is actually introduced. The measurement was performed on the N signal side. As shown in FIG. 4, in the conventional method in which the MIM capacitor is not introduced, at a frequency of 10 GHz, S21 (transmission characteristics) = − 3 dB and S11 (reflection characteristics) = − 3 dB were extremely deteriorated. On the other hand, when a MIM capacitor was introduced and the capacitance was 0.4 pF, the S21 was reduced to −1 dB and S11 was improved to −7.5 dB.

Therefore, even if an inexpensive can-type package with poor high-frequency characteristics is used, even if it is driven by a 10 Gbit / s class high-speed signal, this high-cost reference example is very inexpensive by merely forming a MIM capacitor on the heat sink. Is obtained. Each of the MIM capacitors 10c and 10d desirably has a capacitance of about 0.1 pF to 1 pF, and the range of 0.2 to 0.6 pF is most effective.

(Optical module using multiple chip capacitors)
Hereinafter, the optical module according to the second embodiment of the present invention will be described in detail with reference to FIG.
FIGS. 5A and 5B are a side view and a top view of the optical module of the second embodiment, respectively. In FIG. 5, chip capacitors 10a-1, 10a-2, 10a-3, 10b-1, 10b-2, 10b-3 and wires 4a-1, 4a-2, 4a-3, 4a-4, 4b- Except for the introduction of 1, 4b-2, 4b-3, and 4b-4, the configuration is the same as that of the conventional optical module shown in FIG. 7 (the same members in FIG. 7 and FIG. 7 and FIG. 5 are numbered in common). Therefore, only the addition of the chip capacitors 10a-1, 10a-2, 10a-3, 10b-1, 10b-2, and 10b-3 and the arrangement of the wires are changed, and the package used is less expensive than the conventional one. It is the same as the can type LD package.

Further, the characteristic configuration of the second embodiment will be described. The chip capacitors 10a-2 and 10a-3 are arranged in a row adjacent to the chip capacitor 10a-1, and the chip capacitor is adjacent to the chip capacitor 10b-1. 10b-2 and 10b-3 are arranged in a line, and the chip capacitors 10a-1, 10a-2, 10a-3, 10b-1, 10b-2 and 10b-3 have the same capacitance values, The connection points between the chip capacitors and the lead terminals are arranged at equal intervals. Furthermore, the lengths of the wires connecting the chip capacitors and the lead terminals are also connected to be equal. With such an arrangement, the transmission lines 13a and 13b can be a pseudo distributed constant circuit suitable as a high-frequency transmission circuit.
The capacitances and intervals of the chip capacitors 10a-1, 10a-2, 10a-3, 10b-1, 10b-2, and 10b-3 are preferably 0.1 pF to 1.0 pF and 50 μm to 500 μm, respectively. However, it is not limited to this.

  One ends (lower surfaces) of the chip capacitors 10a-1, 10a-2, 10a-3, 10b-1, 10b-2, and 10b-3 are electrically connected to the stem mount 1c of the stem 1 made of a conductive material, and are grounded. It is connected to the.

  The other ends (upper surfaces) of the chip capacitors 10a-1, 10a-2, and 10a-3 and the lead terminals 2a are connected by wires 4a-1, 4a-2, and 4a-3, respectively. Furthermore, the other end (upper surface) of the chip capacitor 10a-1 and the wiring pattern 6b are connected by a wire 4a-4. The wiring pattern 6b is electrically connected to the cathode formed on the lower surface of the LD element 5. For this reason, the other end (upper surface) of the chip capacitor 10 a-1 is electrically connected to the lead terminal 2 a and the cathode on the lower surface of the LD element 5.

  The other ends (upper surfaces) of the chip capacitors 10b-1, 10b-2, and 10b-3 and the lead terminals 2b are connected by wires 4b-1, 4b-2, and 4b-3, respectively. Further, the other end (upper surface) of the chip capacitor 10b-1 is electrically connected to an anode formed on the lower surface of the LD element 5 by a wire 4b-4. For this reason, the other end (upper surface) of the chip capacitor 10 b-1 is electrically connected to the lead terminal 2 b and the anode on the upper surface of the LD element 5.

  The optical module shown in FIG. 5 is a module for an optical communication system for transmitting a 10 Gbit / s class high-speed optical signal, and an LD element 5 is mounted as an optical semiconductor element. As the LD element 5, a distributed feedback LD (DFB-LD) having an active layer having a multiple quantum well (MQW) structure containing InGaAlAs having excellent temperature characteristics is suitable.

In the optical module of the second embodiment shown in FIG. 5, among the 10 Gbit / s class differential drive electrical signals (N signal, P signal) from the outside of the stem, the N signal passes through the transmission lines 11a, 12a, 13a. To do. In the transmission line 13a, the upper surfaces of the chip capacitors 10a-1, 10a-2, and 10a-3 and the lead terminals 2a are connected by wires 4a-1, 4a-2, and 4a-3, respectively. Since the lower surfaces of the chip capacitors 10a-1, 10a-2, and 10a-3 are connected to the stem (ground) 1, they are grounded. Therefore, the transmission line 13a in the present embodiment is a quasi-distributed constant line having an LC three-stage configuration including a lead terminal 2a suitable for high-frequency transmission and three chip capacitors. Note that the wires 4a-1, 4a-2, and 4a-3 in the present embodiment are arranged at 300 μm intervals along the z-axis direction. The N signal that has passed through the transmission line 13a passes through the wire 4a-1, the chip capacitor 10a-1, the wire 4a-4, and the wiring pattern 6b formed on the upper surface of the heat sink 6a, and the lower surface of the LD element 5 (not shown). Are supplied to the cathode side.

  In the transmission line 13b, the upper surfaces of the chip capacitors 10b-1, 10b-2, and 10b-3 and the lead terminals 2b are connected by wires 4b-1, 4b-2, and 4b-3, respectively. Since the lower surfaces of the chip capacitors 10b-1, 10b-2, and 10b-3 are connected to the stem (ground) 1, they are grounded. Therefore, the transmission line 13b in the present embodiment is a quasi-distributed constant line having an LC three-stage configuration composed of a lead terminal 2b suitable for high-frequency transmission and three chip capacitors, like the transmission line 13a. Note that the wires 4b-1, 4b-2, and 4b-3 in the present embodiment are arranged at 300 μm intervals along the z-axis direction. The P signal that has passed through the transmission line 13b is supplied to the anode side of the LD element 5 through the wire 4b-1, the chip capacitor 10b-1, and the wire 4b-4.

Here, paying attention to the N signal, the introduction of the chip capacitors 10a-1, 10a-2, and 10a-3, which are shunt capacitor components, reduces the characteristic impedance of the transmission line 13a substantially uniformly to the high frequency region, and as a result. Since the characteristic impedance difference between the transmission lines 12a-13a can be reduced, reflection of the N signal between the transmission lines 12a-13a can be significantly suppressed. Similarly, in the P signal, by introducing the chip capacitors 10b-1, 10b-2, and 10b-3, which are shunt capacitor components, the characteristic impedance of the transmission line 13b is reduced almost uniformly to the high frequency region, and as a result, transmission is performed. Since the characteristic impedance difference between the lines 12b-13b can be reduced, reflection of the P signal between the transmission lines 12b-13b can be significantly suppressed.
As described above, since reflection of the drive electric signal (N signal, P signal) can be suppressed, high frequency characteristics can be improved.

  FIG. 6 shows the high-frequency characteristics of the can-type LD package in which a plurality of chip capacitors (three on each of the N side and the P side) are actually introduced. The measurement was performed on the N signal side. As shown in FIG. 6, in the conventional method in which a plurality of chip capacitors are not introduced, S21 (transmission characteristics) = − 3 dB and S11 (reflection characteristics) = − 3 dB are very deteriorated at a frequency of 10 GHz. On the other hand, when a plurality of chip capacitors are introduced and the capacitance of each chip capacitor is 0.2 pF, the improvement is greatly improved to S21 = −1 dB and S11 = −11 dB.

  Therefore, even if an inexpensive can-type package with poor high-frequency characteristics is used, this embodiment in which only a very inexpensive chip capacitor is added can provide good high-frequency characteristics even when driven with a 10 Gbit / s class high-speed signal. It is done. The chip capacitors 10a-1, 10a-2, 10a-3, 10b-1, 10b-2, and 10b-3 preferably have equal capacitance values in the range of about 0.1 pF to 1 pF. A range of 1 to 0.5 pF is most effective.

  In this embodiment, three capacitors are used for each of the N signal side and the P signal side. However, in order to obtain the pseudo-distributed constant line effect, the number is not limited to this, and each number is 2 or 4 or more. You may use. In order to maximize the quasi-distributed constant line effect, the connection points between the capacitors and the lead terminals should be arranged at equal intervals, and the lengths of the wires connecting the capacitors and the lead terminals should be equal. Although it is preferable, it is not necessarily limited to this because it has a certain effect even if it is not equally spaced or equal in length. It is clear that the same effect can be obtained even if a part or all of the chip capacitor is replaced by a plurality of MIM capacitors formed on the heat sink 6a.

DESCRIPTION OF SYMBOLS 1 Stem 1a Stem upper surface 1b Stem lower surface 1c Stem mount 1d Stem recessed part 2a-2d Lead terminal 3a-3c Through-hole 3d Insulator 4a, 4b, 4a-1, 4a-2, 4a-3, 4b-1, 4b-2 4b-3 Wire 5 LD element 6a Heat sink 6b, 6c, 6d Wiring pattern 7 Monitor PD
8 PD carrier 9a, 9b Wire 10a, 10b, 10a-1 to 10a-3, 10b-1 to 10b-3 Chip capacitor 10c, 10d MIM capacitor 10c-1, 10d-1 Capacitor upper electrode (air bridge)
11a-13a, 11b-13b Transmission line

Claims (4)

A stem made of a conductive material and connected to the ground;
A first lead terminal that is attached to the stem through the stem and electrically insulated from the stem by interposing an insulating material in a portion that penetrates the stem;
A second lead terminal which is attached to the stem through the stem and electrically insulated from the stem by interposing an insulating material in a portion penetrating the stem;
In an optical module having a laser diode mounted on a stem mount that is part of the stem ,
The stem mount includes a first chip capacitor and a second chip capacitor ,
The first chip capacitor has one end electrically connected to the stem mount and the other end connected to the first lead terminal and the cathode or anode of the laser diode via a wire,
The second chip capacitor has one end electrically connected to the stem mount and the other end connected to the second lead terminal and the anode or cathode of the laser diode via a wire,
The first lead terminal, the second lead terminal, and the first lead terminal in a state in which the surface of the stem mount on which the first chip capacitor and the second chip capacitor are provided is viewed from the front. The chip capacitor and the second chip capacitor are not in overlapping positions,
The differential drive electrical signal passes through the first lead terminal and the first chip capacitor, and passes through the second lead terminal and the second chip capacitor, and then the laser diode. An optical module characterized by being supplied to . The optical module according to claim 1 ,
A first dielectric substrate is provided between the laser diode and the stem mount ,
And, the lower surface of the first dielectric substrate is formed with metallization on the entire surface, and is electrically connected to the stem mount ,
The top surface of the first dielectric substrate has a second wiring pattern for electrically connecting the first lead terminal or the second lead terminal and the laser diode,
And the cathode or anode of the laser diode is electrically connected to the second wiring pattern,
Said first switch-up capacitor, with its one end electrically connected to said stem mounting, the other end connected to the first lead terminal through the wire and through the wire and the second wire pattern Connected to the cathode or anode of the laser diode;
Said second switch-up capacitor, with its one end electrically connected to the stem mount, the other end is connected via a wire to the second lead terminal and the anode of the laser diode through a wire or An optical module connected to a cathode. The optical module according to claim 1 or 2 ,
Further comprising one or more third Chi-up capacitor and one or more fourth Chi-up capacitor,
The third chip capacitor has one end electrically connected to the stem mount and the other end connected to the first chip capacitor of the first lead terminal via a wire. Are connected to each other, and are arranged so that the lengths of the respective wires connecting the first lead terminal and the other ends of the first chip capacitor and the third chip capacitor are equal to each other,
The fourth chip capacitor has one end electrically connected to the stem mount and the other end connected to the second chip capacitor of the second lead terminal via a wire; Are connected to each other, and are arranged so that the lengths of the respective wires connecting the second lead terminal and the other ends of the second chip capacitor and the fourth chip capacitor are equal to each other ,
The first chip capacitor and the third chip capacitor all have the same capacitance value,
And each connection point which connects the 1st chip capacitor and the 3rd chip capacitor, and the 1st lead terminal is equidistant,
And the second chip capacitor and the fourth chip capacitor all have the same capacitance value,
And each connection point which connects the 2nd chip capacitor and the 4th chip capacitor, and the 2nd lead terminal is equidistant,
An optical module , wherein a pseudo distributed constant circuit is formed by the first and second lead terminals, the first to fourth chip capacitors, and the wires . The optical module according to any one of claims 1 to 3 ,
Said laser diode, said chip capacitor, said laser diode and portion where the chip capacitor is projected to the side that is located out of the lead terminals, the laser diode and the chip capacitor of the surface of the stem is located An optical module, wherein the side surface is sealed with a cap.

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