JP4212845B2 - Optical semiconductor element module - Google Patents

Description

【００７６】
図１０（ａ）に示すように、例えば、信号ピンの半径ｒａが０．１５ｍｍの場合に特性インピーダンスを３０オームとするには、半径ｒｂが０．４ｍｍの誘電体（ガラス）を用いてフィードスルーを構成する必要がある。このフィードスルーをステムに２個並列に並べ、さらに、２つのフィードスルーの間に０．５ｍｍの間隔Ｓ１を確保すると、それらが信号ピンの径方向に占める長さは２．１ｍｍとなる。このような構成では、一般的なキャンパッケージの直径が５．４ｍｍ（または３．５ｍｍ）であるのに対して、フィードスルーが半分もの（または半分以上の）比率を占めてしまう。
【００７７】
また、誘電体６０２の半径（誘電体６０２の充填されるステム６０３の穴径）の変化に伴う特性インピーダンスの変化が大きく、加工する際に穴径やピンの取付け位置がずれた時、特性インピーダンスが大きくばらついてしまうという問題があった。また、このフィードスルーの出口から回路基板、またはストリップ線路などに接続する部分は、急激に特性インピーダンスが大きくなり、電気的な反射を起こしやすいため、特性インピーダンスのばらつきは整合回路の設計や製造を難しくしていた。
【００７８】
一方、図９（ｂ）は、この発明の実施の形態１によるキャンパッケージ１に設けた高周波信号ピン４１ａ、４１ｂを有するフィードスルーの断面を、模式的に示したものである。図において、高周波信号ピン４１ａ、４１ｂの半径をＲａ、高周波信号ピン４１ａ、４１ｂの中心間隔をＳ２とし、高周波信号ピン４１ａ、４１ｂの外周に半径Ｒｂの誘電体（ガラス）６１０（図５の誘電体７７に相当する）を設け、その外側にステム１０が配置されている。図では、説明を簡単にするために誘電体６１０を円形にしている。また、ステム１０は接地してある。
【００７９】
この場合の特性インピーダンスは、下式（２）で表せる。なお、式（１）及び式（２）は、小西義弘著のマイクロ波回路の基礎とその応用（第１版）の第１６ページ（総合電子出版社１９９０年８月２０日）の記載に基づくものである。図１０（ｂ）は高周波信号ピン４１ａ、４１ｂの半径Ｒａを０．１５ｍｍ、その中心間隔Ｓ２を０．６ｍｍから０．９ｍｍ（０．６ｍｍ、０．７ｍｍ、０．８ｍｍ、０．９ｍｍ）とし、誘電体（ガラス）の比誘電率εs=4.1、比透磁率μs=1として、差動線路のフィードスルーの特性インピーダンスを示したものである。例えば、高周波信号ピン４１ａ、４１ｂの半径Ｒａが０．１５ｍｍの場合、その中心間隔Ｓ２が０．７ｍｍから０．９ｍｍにばらつき、更に誘電体（ガラス）６１０の半径が０．６５ｍｍから１．１ｍｍの範囲でばらついても、特性インピーダンスは６０〜６５オームの範囲であって、その変動が少なくなる。
【００８０】
【数２】

単位Ω、但し、Ｒｂ＞ＲａとＳ２＞２Ｒａの条件で簡略化した。
【００８１】
このように、フィードスルーに差動線路を用いることで、高周波信号ピン４１ａ、４１ｂ間の電界結合により特性インピーダンスのバラツキが少なくなる。したがって、高周波信号ピン４１ａ、４１ｂのガラス融着固定工程におけるピンの位置のバラツキや、ステム加工時の穴径のバラツキを適宜に許容することができ、品質が安定し、安価なフィードスルーを得ることができる。また、誘電体６１０の半径を０．８ｍｍとすることができ、さらには誘電体を長円形、楕円形、繭型とする（図１８で誘電体の形状例を示す）ことで、単相のフィードスルーを横に並べた場合と比べてより小型なキャンパッケージを得ることが可能である。
【００８２】
さらに、キャンパッケージ１の内部（マイクロストリップ差動線路基板４６側）に突出するフィードスルーの出力端とマイクロストリップ差動線路基板４６を接続する部分や、キャンパッケージ１の外部（グランデッドコプレナ差動線路７０側）に突出するフィードスルーの出力端とマイクロストリップ差動線路基板４６を接続する部分では、線路間の電界結合が適宜に維持され、特性インピーダンスの変化を抑えることができる。このため、スタブ５４ａ，５４ｂのような整合回路の設計が容易となる。
【００８３】
図１０（ｃ）は高周波信号ピン４１ａ、４１ｂの半径Ｒａを０．０５ｍｍから０．２５ｍｍ（０．０５ｍｍ、０．１ｍｍ、０．１５ｍｍ、０，２０ｍｍ、０．２５ｍｍ）、ピンの中心間隔Ｓ２を０．８ｍｍとした時の特性インピーダンスを示すものであり、ピンの半径Ｒａを変えることで、特性インピーダンスを所望の大きさに合わせることができる。図からわかるように、ピンの半径Ｒａを適宜選択しても、誘電体Ｒｂの半径の変化に伴なう特性インピーダンスの変化が少なく、前述と同様の効果がある。
【００８４】
なお、好ましくは、高周波信号ピン４１ａ、４１ｂの中心間隔Ｓ２を０．７〜０．９ｍｍ、誘電体６１０の半径Ｒｂを０．６５〜１．１ｍｍとするのが良く、また、高周波信号ピン４１ａ、４１ｂの半径を０．０５ｍｍから０．５ｍｍとするのが好適である。
【００８５】
本実施の形態１においては、ＬＤ駆動回路１００の差動トランジスタ１０３，１０４の出力からＬＤ４０までのインピーダンスマッチングをとるためこれらの間を全て差動線路で構成してＬＤ４０を駆動するようにしており、ステム１０を貫通するピンも、長円形状の誘電体７７に一対の高周波信号ピン４１ａ，４１ｂを貫通させることで、差動線路を構成する差動ピンとしている。このため、両信号ピン間の電気的結合が高くなり、電界を封じ込めることができ、漏洩による損失を低減することができる。したがって、特に寸法バラツキが生じやすい高周波信号ピン４１ａ，４１ｂにおけるステム１０からＬＤ駆動回路１００側に露出されている部分（以下、ドライバ側ピン露出領域という）の電界の不連続を従来に比べ抑えることができる。さらに、このドライバ側ピン露出領域には、グランドピン４２ａ，４２ｂが高周波信号ピン４１ａ，４１ｂに並走するように配されているので、この部分のインピーダンスを低くして反射を抑えることができる。
【００８６】
また、例えば、単相駆動の場合には、ＬＤを駆動した大電流が接地を経由して駆動回路に帰還するので、接地電位が変動するため、近接して設置された微弱電流を検出する光受信系の電子回路に悪影響がでることがあるが、本実施の形態では、差動線路を用いて、ＬＤをプッシュプル動作しているので、大電流は差動線路を流れ、接地電位の変動が少なくなり、周辺回路への影響がでにくいという利点もある。
【００８７】
このように、ドライバ側ピン露出領域を差動線路構成としかつその外側にグランドピン４２ａ，４２ｂを配して、この部分のインピーダンスを従来に比べ低くするようにしたので、この部分とステム内側とのインピーダンス差が従来に比べ小さくなり、また電界の不連続も少なくしたので、通過特性および反射特性を改善することができる。
【００８８】
高周波信号ピン４１ａ，４１ｂの周りに配置される誘電体７７として、ガラスを使用しているので、ステム１０の内側部分（高周波信号ピン４１ａ，４１ｂが誘電体７７で囲まれているフィードスルー部分、以下ピン非露出領域ともいう）では、インピーダンスが下がりすぎる傾向がある。このピン非露出領域のインピーダンスを上げるためには、高周波信号ピンの周りに配置される誘電体７７の断面積（長円の面積）を大きくすればよいが、これでは小型化、省スペース化の要求を満足させることができない。
【００８９】
そこで、２本の高周波信号ピン４１ａ，４１ｂは、誘電体７７の外側にでると、即座にマイクロストリップ差動線路基板４６の差動信号線５２ａ，５２ｂに乗り移れるように、ＬＤ４０側への突出長を短くするとともに、マイクロストリップ差動線路基板４６のストリップ差動信号線５２ａ，５２ｂのうち、高周波信号ピン４１ａ，４１ｂに接続される、ステム１０に近い部分５２ｄ（図６参照）の間隔を、例えば、差動線路基板４７に近い部分の線路間隔よりも大きくしたり、ピン４１ａ、４１ｂの間隔よりも若干広く設定する等、比較的大きく設定することで、この部分の電気的結合を弱くして、この部分５２ｄを高インピーダンスに設定している。例えば、高周波信号ピン４１ａ，４１ｂのフィードスルー部分が６０Ω、ストリップ差動信号線５２ａ，５２ｂにおける間隔の広い５２ｄの部分が１５０Ω、ストリップ差動信号線５２ａ，５２ｂにおける差動線路基板４７に近い間隔の狭い部分が１００Ωとなるようにしている。
【００９０】
このように、ステム１０を出た直後の差動線路部分の線路間隔を大きくして、高インピーダンス部分を故意に作成しており、この高インピーダンス部分とステム内側（ピン非露出領域）の低インピーダンス部分とでインピーダンスを相殺させ、全体的に見てインピーダンスを整合させるようにしている。すなわち、ピン非露出領域（フィードスルー部分）は低インピーダンスであるので、その後にハイインピーダンスを少し作って、全体としてのインピーダンスマッチングをとるようにしている。
【００９１】
また、ストリップ差動信号線５２ａ，５２ｂの途中には、インピーダンス整合用の一対のスタブ５４ａ，５４ｂを形成しており、これら一対のスタブ５４ａ，５４ｂによりインピーダンスを下げてストリップ差動信号線５６ａ、５６ｂとのミスマッチングが発生しないようにしている。すなわち、これら一対のスタブ５４ａ，５４ｂにより、ドライバ側ピン露出領域のリアクタンス成分と、ピン非露出領域（フィードスルー部分）のリアクタンス成分を補償して、通過特性および反射特性を改善している。
【００９２】
また、この場合、一対のスタブ５４ａ，５４ｂは、外側にではなく、内側に（互いの信号線に接近するように）突出されているので、マイクロストリップ差動線路基板４６の小型化に寄与する。なお、小型化が必要ない場合は、図１１に示すように、差動線路５２ａ，５２ｂの外側に突出するようにしてもよい。
【００９３】
つぎに、台座１１上への４つの基板（マイクロストリップ差動線路基板４６，４７と、ＬＤ用チップキャリア４８と、バイアス回路用基板４９）と、ＰＤ用チップキャリア４５のレイアウトについて説明する。
【００９４】
キャンパッケージ１においては、高周波信号ピン４１ａ，４１ｂとＬＤ４０との間を接続する差動線路基板と、ＬＤ４０を搭載する基板と、ＬＤ４０に直流バイアス電流を供給するためのバイアス回路基板と、モニタＰＤ５０とを配置する必要がある。
【００９５】
図１２は、差動線路構成の場合の他の台座１１上のレイアウトを示すものである。ステム１０の中央には、高周波信号ピン４１ａ，４１ｂが貫通配置され、高周波信号ピン４１ａ，４１ｂを挟むようにグランドピン４２ａ、４２ｂが配置される。また、高周波信号ピン４１ａ，４１ｂ、およびグランドピン４２ａ、４２ｂを挟むように、バイアス給電ピン４４ａ、４４ｂが貫通配置されている。台座１１の中央部に、高周波信号ピン４１ａ，４１ｂとＬＤ４０間を接続する差動線路基板９０ａと、ＬＤ４０を搭載する基板９０ｂと、整合抵抗３１ａ、３１ｂを搭載する基板９０ｅとが配置される。また、台座１１のＬＤ４０の両側に、ソレノイドを有するバイアス回路基板９０ｃ，９０ｄが配置され、バイアス基板９０ｃ、９０ｄに設けられたソレノイドは、それぞれバイアス給電ピン４４ａ、４４ｂにワイヤボンドで接続されている。
【００９６】
このようなレイアウトの場合、レーザ光はＬＤ４０の前後にしか出射されないので、モニタＰＤ５０を高周波信号ピン４１ａ，４１ｂの上下に配置する必要があり、スペース的に配置が困難である。また、差動線路基板９０ａと、ＬＤ４０を搭載する基板９０ｂ、および整合抵抗３１ａ、３１ｂを搭載する基板９０ｅとが、レーザ光出射方向に直線上に配置されるので、台座１１のレーザ光出射方向に沿った長さが長くなり、パッケージの大型化を招来する。また、バイアス回路と接続するワイヤボンド３５ａ、３５ｂのインダクタンスを小さくするためには、基板を２分割しなくてはいけないので、コスト高になる。さらに、このレイアウトの場合は、高周波信号ピン４１ａ，４１ｂを封止固定するための透明の誘電体７７がＬＤ４０の真後ろに位置するので、ＬＤ４０からのモニタ光が透明な誘電体７７を介してキャンパッケージ１の外部に直接出射されることになり、ＬＤ４０を駆動しながらの作業を行う際に、作業者の目に入る可能性が高いという懸念もある。
【００９７】
このような状況を鑑み、実施の形態１においては、図５〜図７などに示すように、マイクロストリップ差動線路基板４６，４７と、バイアス回路用基板４９とで、ＬＤ用チップキャリア４８を挟むようにＬＤ用チップキャリア４８の両側に配置するようにしている。別言すれば、ＬＤ４０を真ん中にしてマイクロストリップ差動線路基板４６，４７の各ストリップ差動信号線５２ａ，５２ｂ，５６ａ，５６ｂと、一対のインダクタンス回路を含む配線パターン６２ａ，６２ｂと、ＬＤ４０とを略Ｕ字状に配置している。
【００９８】
このため、台座１１のレーザ光軸方向の長さは、マイクロストリップ差動線路基板４６，４７分の長さで済むようになり、図１２に示したレイアウトより小型化が実現できる。
【００９９】
また、マイクロストリップ差動線路基板４６，４７が、ＬＤ用チップキャリア４８からサイドにずれた位置に配設されるので、高周波信号ピン４１ａ，４１ｂを封止固定するための透明の誘電体７７の配置位置も、必然的に、ＬＤ用チップキャリア４８からサイドにずれた位置に配設されることになる。レーザ光は、ガウス分布的に光軸からずれるほど強度が弱くなるので、透明の誘電体７７には強度の弱い光しか入らなくなり、これにより作業時の安全性を向上させることができる。
【０１００】
なお、ＬＤ４０を搭載する基板と、高周波信号ピン４１ａ，４１ｂおよびＬＤ４０間を接続する差動線路基板とを、同一の基板で構成する手法もあるが、この場合は、熱源としてのＬＤ４０からの熱を放熱するため単位面積あたり高価な放熱性の良い窒化アルミ基板（ＡｌＮ）などの基板材料を広い面積で使用しなくてはならず、コストアップの原因となる。
【０１０１】
そこで、この実施の形態１においては、図５および図６に示すように、熱源としてのＬＤ４０を搭載するＬＤ用チップキャリア４８を、他の基板から分離して単独基板としている。このため、ＬＤ用チップキャリア４８にのみ高価な放熱性の良い窒化アルミ基板（ＡｌＮ）などのセラミック基板材料を使用すればよくなり、他の基板（マイクロストリップ差動線路基板４６，４７と、バイアス回路用基板４９）は、安価なＡｌ₂Ｏ₃などのセラミック基板材料を使用すればよくなり、低コスト化が可能となる。
【０１０２】
また、本実施の形態１のレイアウトによれば、インピーダンス整合用のマイクロストリップ差動線路基板４６と、整合抵抗３１ａ，３１ｂを配置するためのマイクロストリップ差動線路基板４７とを、別基板としたので、無駄のないセラミック基板の裁断が可能となって低コスト化に寄与する。また、インピーダンス整合用のマイクロストリップ差動線路基板４６は、ステム１０の製造時に一緒に製造して、ステム１０とマイクロストリップ差動線路基板４６とがロウ付け、または半田付けにより接続固定されたユニットを作成して、その後他の構成部品と組み立てるなどの自由度の高い製造作業を行うことが可能となり、作業性が向上する。なお、ステム１０の直径として、例えばφ５．６ｍｍの大きさを実現することが十分に可能である。
【０１０３】
また、バイアス回路用基板４９には、バイアス給電ピン４４ａ，４４ｂに接続される空芯ソレノイド３３ａおよび共振防止抵抗３４ａの並列回路と、空芯ソレノイド３３ｂおよび共振防止抵抗３４ｂの並列回路とを、同一基板上に配置して、バイアス回路基板の小面積化を図っているので、低コスト化および小型化に寄与する。
【０１０４】
また、バイアス回路用基板４９上の空芯ソレノイド３３ａ，３３ｂは、互いの磁界が干渉しないように、交差するように、好ましく直交するように、配置されているので、一方のソレノイドに発生する磁界が他方のソレノイドに影響を与えることがなくなるとともに、空芯ソレノイド３３ａ，３３ｂの配置位置をＬＤ４０のアノード、カソードにより近づけることが可能となる。
【０１０５】
つぎに、ＰＤ５０の配置について説明する。ＰＤ５０を搭載するＰＤ用チップキャリア４５は、ＬＤ４０の真後ろに配するのではなく、レーザ光軸に対し上下側および左右に少しずれた位置に配置することにより、スペースの有効活用を図り、ステム１０に配するバイアス給電ピン４４ａ，４４ｂ、モニタ信号ピン４３などの自由度の高いレイアウトを可能にしている。
【０１０６】
また、ＰＤ５０をＬＤ４０の上下のどちらにずらせるかを選択する際には、ＬＤ４０を構成する半導体基板９９と活性層９３との位置関係、並びにモニタ光の遠視野像の強度分布に応じて決定する。図１３は、ＬＤ４０の構造を概略的に示すものである。
【０１０７】
ＬＤ４０は、カソード（ｎ電極）９１と、アノード（ｐ電極）９２と、ｐ型の半導体基板９９と、発光領域をなす活性層９３と、反射防止膜（ＡＲコート）を施した端面１１０からの反射戻り光を低減するための窓構造９４と、活性層９３を挟むクラッド層５０１などを備えている。なお、窓構造９４とは、共振器端面（へき開面）５０２近傍に不純物を注入又は拡散させて無秩序化することにより、端面近傍におけるバンドギャップを増大させて、端面近傍における光吸収などを抑制し、端面破壊を防止するなどの効果を持つ構造である。
【０１０８】
活性層９３は、半導体基板９９と逆方向側に片寄った位置に配設されており、このため、出射されるレーザ光は次のような強度分布を持つようになる。
【０１０９】
活性層９３から出射されたレーザ光の一部は窓構造９４の上側にある反射率の高い金属で構成されるカソード９１で反射される。この反射光が、活性層９３から窓構造９４を介して直接出射される他のレーザ光と干渉するので、ＰＤ５０が配置される程度の距離を離した位置でのモニタ光の強度分布は、図１４に示すようになる。図１４に示す強度分布においては、正の角度領域（半導体基板９９側）では、上記干渉によるリップルが発生している。したがって、このようなリップル発生側に、ＰＤ５０を配置すると、若干の組立誤差などによって受光感度が急変するので、モニタ光を高精度に検出することができなくなるという問題がある。
【０１１０】
一方、図１４に示すように、負の角度領域（半導体基板９９と反対側）では、光線がアノード９１に蹴られる位置まで滑らかに変化する通常のガウス分布波形に近い形状が得られる。
【０１１１】
したがって、ＰＤ５０を光軸に対して半導体基板９９と反対の方向に片寄った側に配置すれば、上述した干渉による遠視野像のリップルの影響を受けることがなくなり、モニタ光を高精度に検出することができるようになる。
【０１１２】
図１５は、先の図５〜図７に示した実施の形態１のキャンパッケージ１におけるＬＤ４０とＰＤ５０との配置関係を示す図である。図１５に示すように、ＰＤ５０は、ＬＤ４０の上側に、すなわち光軸に対して半導体基板と反対の方向に片寄った側に配置するようにしており、上述した干渉による遠視野像のリップルの影響を受けることがなくなり、モニタ光を高精度に検出することができる。また、この場合は、ＰＤ５０は、ＬＤ４０に対し左右方向にもずれた位置に配置され、小型化している。なお、ＰＤ用チップキャリア４５の下面は、台座１１の上面から若干離間している。
【０１１３】
つぎに、図１６を用いてステム１０に挿入すべき長円形状の誘電体（ガラス）７７の厚みに関して説明する。誘電体７７の厚みを、ステム１０に形成した孔７４の深さすなわちステム１０の幅と同じ長さに設定すると、電気炉での加熱時にガラスの縁が盛り上がって、ステム１０の壁面に凹凸部が形成されてしまう。このようなステム１０壁面での凹凸は、各種の部品配置の際の邪魔になる。
【０１１４】
そこで、誘電体７７の厚みをステム１０に形成した孔７４の深さすなわちステム１０の幅よりも短く設定し、電気炉での加熱前には、図１６に示すように、ステム１０にはＬＤ側の開口部をすり鉢状に形成した孔９５が形成されるようにする。このようにすれば、電気炉での加熱時にガラスの縁が盛り上がっても、ガラスは、ステム１０の壁面まで到達することが無くなり、この誘電体７７の領域に重なるように任意の部品を配置できるようになる。先の図５〜図７に示した実施の形態１においては、図１６にも示すように、ＰＤ５０を配置するためのＰＤ用チップキャリア４５の一部を誘電体７７に重なるように配置している。すなわち、ＰＤ用チップキャリア４５が、孔９５のすり鉢状の開口部に重なるように配置されている。また、図５および図１５などに示すように、台座１１のステム１０への当接面の一部も、上記孔９５のすり鉢状の開口部に重なるように配置されている。なお、他のバイアス給電ピン４４ａ，４４ｂ、モニタ信号ピン４３を封止固定するための誘電体７９ａ，７９ｂ，７８も、同様にして、それらの厚みをステム１０の幅よりも短く設定している。また、この場合、孔９５を、ステム１０の台座１１が固定される方の壁面に形成するようにしたが、逆側の面にも部品を配置する場合は、ステム１０の逆側の壁面に、同様の孔を形成するようにしてもよい。
【０１１５】
なお、上記実施の形態１において、マイクロストリップ差動線路基板４６，４７の代わりに図１７に示すようなグランデッドコプレナ差動線路４６ｂを用いるようにしてもよい。グランデッドコプレナ差動線路４６ｂは、前述したように、基板上に形成された一対の差動信号線と、この一対の差動信号線を挟むように差動信号線の外側に配置されるグランドと、裏面に配置されるベタグランドとから構成されている。
【０１１６】
また、実施の形態１では、高周波信号ピン４１ａ，４１ｂの外側にグランドピン４２ａ，４２ｂを配設するようにしたが、図１８に示すように、グランドピン４２ａ，４２ｂを省略した実施形態も可能である。
【０１１７】
実施の形態２．
つぎに、図１９を用いてこの発明の実施の形態２について説明する。図１９（ａ）〜（ｃ）は、高周波信号ピン４１ａ，４１ｂを封止するための誘電体７７の他の形状を示すものである。
【０１１８】
図１９（ａ）は、誘電体７７の形状として、２７０°／３６０°程度の２つの円を直線（あるいは緩やかな曲線）で接続した繭型形状を採用している。１つのピン４１ａ（または４１ｂ）から誘電体７７の周縁、すなわちグランド部材としてのステム１０までの距離について着目すると、繭型形状の場合は、２７０°／３６０°が等距離ｒにあり、残りの部分は距離ｒよりも長くなる。一方、実施の形態１で用いた長円形状の誘電体の場合、１８０°／３６０°が等距離ｒにあり、残りの部分は距離ｒよりも長くなる。ピンとグランドまでの距離が長いほどインピーダンスが高くなるので、同じ面積の繭型形状と長円形状を比較した場合、長円形状のほうがインピーダンスを高く設定することができる。前述したように、ピン非露出領域（フィードスルー領域）では、インピーダンスが下がりすぎる傾向があるので、インピーダンスを上げるという点では、長円形状のほうが有利である。勿論、繭型形状を採用する場合は、その面積を調整して、長円形状の場合と同程度のインピーダンスが得られるようにすればよい。
【０１１９】
図１９（ｂ）では、誘電体７７として、２つの円を直接的に連結した形状を採用しており、図１９（ｃ）では、楕円形状を採用している。
【０１２０】
実施の形態３．
つぎに、図２０を用いてこの発明の実施の形態４について説明する。この実施の形態３においては、キャンパッケージ１の放熱特性をより向上させるようにしている。したがって、この実施の形態４は、コバールなどで台座１１およびステム１０が一体成形された、放熱性の悪いパッケージのときに適用すれば、好適である。
【０１２１】
図２０（ａ）に示すように、台座１１およびステム１０に、熱伝導の良いＣｕなどの線材（ヒートパイプ）８１を内挿するための線材挿入孔８２を形成する。線材挿入孔８２の径は、線材８１の径よりも大きくする。線材挿入孔８２の底部には、圧入穴８２ａを形成し、この圧入穴８２ａに線材８１の一端を圧入固定する。圧入穴８２ａの穴長は、線材８１を固定できる範囲でできるだけ短くする。これは、線材８１と台座１１との熱膨張係数差による歪の発生を防止する為である。ＬＤ４０からの放熱を考慮した場合、線材８１の一端を固定するための圧入穴８２ａは、ＬＤ４０あるいはＬＤ用チップキャリア４８の直下に配置した方が好ましい。
【０１２２】
なお、線材８１が孔８２の底部に至るまでの間は、線材８１が線材挿入孔８２の内周面に接触しないようにすることが好ましいが、線材８１と線材挿入孔８２との間の摩擦あるいは表面間の干渉によって、線材８１と台座１１との熱膨張係数差による歪の発生を防止できるならば、多少接触していても構わない。ただし、線材（ヒートパイプ）８１が、線材挿入孔８２の内周面で半田等によって接合されることは避けなければならない。
【０１２３】
また、図２０（ａ）をＫ方向から見た図２０（ｂ）に示すように、線材８１の他端は螺旋状に曲げられる。螺旋状に曲げられた線材８１の他端は、その螺旋中心にねじ５００が挿入され、グランデッドコプレナ差動線路７０の裏面側に位置する、ヒートシンク２０００に設けられたねじ穴と締結される。これによって、線材８１の他端がヒートシンク２０００に固定される。このとき、線材８１の他端はばね性を有して固定されるため、熱膨張係数差によって線材８１と台座１１との間に熱変位差が生じても、その熱変位差を吸収でき、台座１１の歪の発生を防止することができる。キャンパッケージ１に電気接続される外部基板と、ＬＤモジュール３とは、ともに図示しないケースに収納される。ヒートシンク２０００は、このケースの壁面に設けられている。
【０１２４】
ＬＤ４０で発生した熱は、ＬＤ用チップキャリア４８から台座１１を介して、線材８１の一端に放熱される。線材８１に伝えられた熱は、線材８１の他端からヒートシンク２０００に伝わり、ヒートシンク２０００に設けられたフィンから外気に放熱される。
【０１２５】
このように、この実施の形態３においては、台座１１およびステム１０の内部に、壁面と接触しないように放熱のための線材８１を設けるようにしているので、ＬＤ４０、ドライバＩＣ、トランスインピーダンスアンプなどの熱源から発生される熱を効率良く放熱することができるとともに、線材８１と台座１１との熱膨張係数差による歪の発生を防止することができる。
【０１２６】
ところで、上述の実施の形態においては、差動信号を入力するためのステム構成をＬＤ４０が搭載されたＬＤモジュールに適用するようにしたが、上記ステム構成を、電界吸収型光変調器（ＥＡ変調器、Electro-absorption Modulator）が搭載されたＥＡモジュールに適用するようにしてもよい。勿論、ＬＤの温度調整用のペルチェ素子を用いたものであっても良いことは云うまでもない。
【０１２７】
【発明の効果】
以上説明したように、この発明によれば、差動信号線路基板とバイアス回路基板が発光素子用チップキャリアを挟むように発光素子用チップキャリアの両側に配置しているので、光半導体素子モジュールの小型化、スペースの有効活用、さらにはコストダウンを実現することができる。
【図面の簡単な説明】
【図１】 この発明にかかる光半導体パッケージの外観構成を示す斜視図である。
【図２】 この発明にかかる光半導体パッケージとレセプタクルが接続されたＬＤモジュールの外観構成を示す斜視図である。
【図３】 ＬＤモジュールの水平及び垂直断面図である。
【図４】 キャンパッケージ内の構成要素およびＬＤ駆動回路の等価回路図である。
【図５】 実施の形態１のキャンパッケージの内部構成を示す斜視図である。
【図６】 実施の形態１のキャンパッケージの内部構成を示す平面図である。
【図７】 ステムとピンと台座の配置関係などを示すための図である。
【図８】 誘電体内に発生する泡を示すための図である。
【図９】 従来と実施の形態１のフィードスルーの断面を、模式的に示した図である。
【図１０】 従来と実施の形態１のフィードスルーにおけるガラス半径と特性インピーダンスとの関係を示す図である。
【図１１】 スタブの配置の変形態様を示す図である。
【図１２】 各種構成要素の一般的なレイアウトを示すための図である。
【図１３】 ＬＤとＰＤとの配置条件を説明するための図である。
【図１４】 ＬＤからの出射光の光強度分布を示す図である。
【図１５】 ＬＤとＰＤとの配置状態を説明するための図である。
【図１６】 ステムに配される長円形状の誘電体の近傍の拡大図である。
【図１７】 実施の形態１の変形態様を示す図であり、グランデッドコプレナ差動線路を示す図である。
【図１８】 実施の形態１の変形態様を示す図である。
【図１９】 この発明の実施の形態２を説明するための図であり、誘電体の他の形状を示す図である。
【図２０】 この発明の実施の形態３を説明するための図である。
【符号の説明】
１ キャンパッケージ、２ レセプタクル、３ 光半導体素子モジュール（ＬＤモジュール）、５ 泡、１０ ステム、１０ｚ ステム外壁面、１１ 台座、１２ 集光レンズ、１３ キャップ、１３ａ 第１キャップ部材、１３ｂ 第２キャップ部材、１４ 孔、１５ 内部空間、１６ ウィンドウ、１７ 孔、１８ダミーフェルール、１８ａ 光ファイバ、１９ フェルール挿入孔、２０ 光ファイバ、２１ フェルール、３０ 分布定数回路、３１ａ，３１ｂ 整合抵抗、３３ａ，３３ｂ ソレノイド（空芯ソレノイド）、３４ａ，３４ｂ 共振防止抵抗、３５ａ，３５ｂ ワイヤボンド、３６ バイアス定電流源、４０ 半導体レーザダイオード（ＬＤ）、４１ａ，４１ｂ 高周波信号ピン、４２ａ，４２ｂグランドピン、４３ モニタ信号ピン、４４ａ，４４ｂ バイアス給電ピン、４５ ＰＤ用チップキャリア、４６，４７ マイクロストリップ差動線路基板、４６ｂ グランデッドコプレナ差動線路、４８ ＬＤ用チップキャリア、４９ バイアス回路用基板、５０ フォトダイオード（ＰＤ）、５２ａ，５２ｂ ストリップ差動信号線、５３ａ，５３ｂ パッド、５４ａ，５４ｂ スタブ、５６ａ，５６ｂ ストリップ差動信号線、５７ａ，５７ｂ ワイヤボンド、５９ａ，５９ｂ ストリップ差動信号線、６０ ワイヤボンド、６１ａ，６１ｂ ワイヤボンド、６２ａ，６２ｂ 配線パターン、６３ａ，６３ｂ ワイヤボンド、７０ グランデッドコプレナ差動線路、７１ａ，７１ｂ 差動信号線、７２ａ，７２ｂグランド（グランド線）、７７，７８，７９ａ，７９ｂ 誘電体、８０ａ，８０ｂ ピン挿入孔、８１ 線材、８２ 孔（線材挿入孔）、８２ａ 圧入穴、９１ カソード、９２ アノード、９３ 活性層、９４ 窓構造、９５ 孔、９９半導体基板、１００ ＬＤ駆動回路、１０１ 外部基板、１０２ 入力バッファ、１０３，１０４ トランジスタ（差動トランジスタ）、１０５ トランジスタ（バイアス定電流源）、５００ ねじ、５０１ クラッド層、５０２ 共振端面、６０１ 信号ピン、６０２，６１０ 誘電体（ガラス）、６０３ ステム、２０００ ヒートシンク。[0001]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor package in which an optical semiconductor element such as a semiconductor laser is incorporated, and more specifically, a coaxial module with an optical fiber and an optical semiconductor element module with a receptacle adapter for connecting an optical fiber It is about.
[0002]
[Prior art]
In recent years, in optical communication systems that transmit optical signals via optical fibers, in order to respond to the increase in communication traffic accompanying the spread of the Internet, the transmission speed of optical signals has been remarkably increased. The transmission rate is shifting from 2.5 Gb / s to 10 Gb / s, and research and development are currently under way to achieve a transmission rate of 40 Gb / s. Along with this, the transmission speed of signals handled by the optical transceiver is also required to be increased.
[0003]
The optical transceiver converts a data signal to be transmitted from an electrical signal to an optical signal, transmits the optical signal through the transmission optical fiber, and receives and receives the optical signal through the reception optical fiber. The optical signal is reproduced as an electric signal.
[0004]
As prior art relating to an optical semiconductor element module used in this type of optical transceiver, there are those disclosed in Japanese Patent Laid-Open Nos. 6-314857 and 11-233876.
[0005]
Japanese Unexamined Patent Publication No. 6-314857 discloses a single-phase power feeding type optical semiconductor element module having a glass-sealed through lead pin. Japanese Patent Laid-Open No. 11-233976 discloses a metal stem provided with a pair of spaced signal pins sealed with separate dielectrics, and outputs one output of a differential driver through one signal pin. There is a technology in which the laser diode is driven by connecting to one electrode of the diode and connecting the other output of the differential driver to the other electrode of the laser diode via a dummy load and further via a virtual ground line. It is shown.
[0006]
Since the single-phase can package as described in the above publications is a single-phase system, when transmitting a modulation signal of 10 Gb / s or more, a feedthrough (a portion where the pin is covered with a dielectric) is used. Before and after (the part where the pin is exposed from the dielectric to the air layer), impedance is likely to be mismatched, and there is a problem that high-frequency transmission characteristics deteriorate, and it is used only for signal transmission of about 2.5 Gb / s.
[0007]
Japanese Patent Application Laid-Open No. 11-233976 is not only intended to achieve the stability at high speed operation by making each load impedance for the differential driver the same, but also the signal pin and the line from the signal pin to the laser diode are different. A transmission line configuration is not used, and a dummy resistor is arranged outside, and transmission of a modulation signal of 10 Gb / s or more deteriorates the signal quality. Further, this prior art is not driven differentially by applying differential signals of normal and negative phases to the anode and the cathode, respectively, for the laser diode.
[0008]
Therefore, in order to cope with 10 Gb / s, Japanese Unexamined Patent Publication Nos. 2000-164970 and 2000-19473 disclose an optical semiconductor element module having a ceramic substrate feedthrough provided with input / output terminals for electrical signals. It is disclosed. However, both of these increase the size of the package due to the structure in which the feedthrough of the ceramic substrate is provided on the side wall of the box-shaped (hexahedral) package. In the box-type package, there is a space for accommodating the mount on which the optical semiconductor element is mounted and the lens. On the side wall of the box-type package, the optical fiber is held on the wall surface where no feedthrough is provided. It is necessary to attach a member. In addition, the ceramic substrate itself is expensive per unit area, it becomes a multilayer ceramic when trying to construct a feedthrough, and a process such as brazing is required in terms of joining the multilayer ceramic and the lead, which is troublesome. Therefore, it was expensive.
[0009]
[Problems to be solved by the invention]
In the field of this type of optical transceiver, optical transmission of 10 Gb / s or more is small in size and low cost in order to spread optical communication not only to trunk line systems but also to access systems such as offices and homes. There is a strong demand for an optical semiconductor element module capable of realizing the above.
[0010]
However, in the package used in the conventional optical semiconductor element module as described in JP-A-6-314857 and JP-A-11-233976, impedance is likely to be mismatched before and after feedthrough, and high frequency transmission characteristics are obtained. There was a problem of deterioration. Therefore, it cannot withstand the signal transmission at the bit rate of 10 Gb / s or more.
[0011]
Moreover, in a box-shaped package used in a conventional optical semiconductor element module provided with external terminals formed of ceramic, as described in JP 2000-164970 A, JP 2000-19473 A, and the like, The ceramic substrate itself is expensive per unit area, it becomes a multilayer ceramic when trying to construct a feedthrough, and a process such as brazing is required in order to join the multilayer ceramic and the lead, which is troublesome. Or, there is a problem that the package becomes expensive and becomes large.
[0012]
The present invention has been made in view of the above, and in an optical semiconductor element module capable of performing a modulation operation at a bit rate of 10 Gb / s or more, the high-frequency transmission characteristics are good, the size is reduced, and the mounting space for housing components is reduced. An object of the present invention is to obtain an optical semiconductor element module that realizes a package structure that can be effectively used. It is another object of the present invention to obtain an optical semiconductor element module that can realize a low-cost mounting structure.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, an optical semiconductor element module according to the present invention includes a semiconductor light emitting element driven differentially, a chip carrier for a light emitting element on which the semiconductor light emitting element is mounted, and a differential signal to the semiconductor light emitting element. An optical semiconductor element module comprising a differential signal line substrate having a differential line to be supplied and a bias circuit substrate having at least a pair of inductance circuits and supplying a bias current to the semiconductor light emitting element on a base. The differential signal line substrate and the bias circuit substrate are arranged on both sides of the light emitting element chip carrier so as to sandwich the light emitting element chip carrier.
[0014]
The light-receiving element further receives a monitor light emitted backward from the semiconductor light-emitting element, and the light-receiving element has a line segment connecting the semiconductor light-emitting element and the light-receiving element in plan view. And the bias circuit board.
[0015]
Further, the light receiving element may be arranged on the side of the semiconductor light emitting element that is offset in the direction opposite to the semiconductor substrate with the optical axis of the semiconductor light emitting element as the center.
[0016]
The bias circuit board may be formed by mounting a parallel circuit of a pair of air-core solenoids and resistors on a single ceramic board.
[0017]
The pair of air-core solenoids may be spaced apart so that the extension lines of their central axes intersect.
[0018]
A stem having a hole; a dielectric having a pair of pin insertion holes; and a through hole fixed to the pair of pin insertion holes of the dielectric; A pair of high-frequency signal pins electrically connected to the differential line may be further provided, and the pedestal may be disposed substantially perpendicular to the stem.
[0019]
The differential line substrate is connected to the pair of high frequency signal pins and has a differential line for impedance matching with the high frequency signal pins, and a differential line on which a matching resistor is disposed. It may be divided into a second substrate having
[0020]
The dielectric may be transparent or translucent, and may be disposed at a position shifted from the optical axis of the semiconductor light emitting element.
[0021]
A stem having a hole; a dielectric having a pair of pin insertion holes; and a through hole fixed to the pair of pin insertion holes of the dielectric; A pair of high-frequency signal pins that are electrically connected to the differential line; and a carrier of a light receiving element that mounts the light receiving element on the stem, the opening of the hole in the stem is formed in a mortar shape, and the pedestal or A part of the carrier of the light receiving element may overlap the mortar-shaped opening.
[0022]
The pedestal has a hollow hole into which a thermally conductive linear member is inserted, and one end of the linear member is the bottom of the hollow hole and the chip carrier mounting surface of the pedestal. While being connected directly below, the part other than the connection part with the bottom part in the linear member may be non-joined with the inner peripheral surface of the hollow hole.
[0023]
An optical semiconductor element module according to the next invention includes a semiconductor light emitting element that is differentially driven, a differential signal line that supplies a differential signal to the semiconductor light emitting element, and at least a pair of inductance circuits, An optical semiconductor element module having a bias circuit for supplying a bias current to a semiconductor light emitting element mounted on a pedestal and incorporating the pedestal in a package, wherein the differential signal line, the bias circuit, and the semiconductor light emitting element are substantially U The semiconductor light emitting device is arranged in a letter shape, and is arranged in a substantially U-shaped folded portion.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of an optical semiconductor element module according to the present invention will be explained below in detail with reference to the accompanying drawings. The optical semiconductor element module according to this embodiment is applied to a local area network such as a connection between servers installed in a building and a connection between servers installed in different buildings.
[0026]
Embodiment 1 FIG.
An optical semiconductor element module according to Embodiment 1 of the present invention will be described with reference to FIGS. The optical semiconductor element module according to the first embodiment employs an inexpensive can package type module, and a laser diode (hereinafter referred to as LD) is incorporated as an optical semiconductor element in the package. Further, in this specification, the optical semiconductor element module is a generic name including a module without a sealing cap (lid).
[0027]
FIG. 1 shows an external configuration of an optical semiconductor package (hereinafter referred to as a can package) that constitutes an optical semiconductor element module, and FIG. 2 shows an optical semiconductor element module (hereinafter referred to as this embodiment) including a can package 1 and a receptacle 2. In this embodiment, an example in which an LD is mainly mounted is shown, so that the external configuration of the LD module 3 is shown. FIGS. 3A and 3B are horizontal to the LD module 3 (parallel to the x-axis in FIG. 2). 1) shows a cross-sectional view, and a vertical (direction parallel to the y-axis in FIG. 2) cross-sectional view.
[0028]
As shown in FIGS. 1 to 3, the can package 1 includes a disc-shaped stem 10 on which a bias feeding pin, a high-frequency signal pin, and the like are mounted, and a trapezoidal columnar pedestal 11 (pedestal) on which a plurality of ceramic substrates are mounted. Block), a condensing lens 12 for condensing the laser light generated from the LD 40, and a cylindrical cap 13 for sealing the pedestal 11 and the like from the outside.
[0029]
As shown in FIG. 3, the cap 13 includes a first cap member 13a fixed to the stem 10 by projection welding or the like, and a first cap member externally fitted to the distal end side of the first cap member 13a by YAG welding or the like. It has a two-stage cylindrical shape composed of a second cap member 13b fixed to 13a. Specifically, the first cap member 13a has a stepped outer cylinder, and a thin outer diameter cylinder is provided at the tip of the outer diameter outer cylinder. The inner cylinder on one end side of the second cap member 13b is fitted to the outer periphery of the thin outer cylinder, and the first cap member 13a and the second cap member 13b are fixed by through YAG welding.
[0030]
A lens insertion hole 14 is formed on the distal end side of the first cap member 13 a, and the condenser lens 12 is inserted into the hole 14. The condenser lens 12 is fixed to the first cap member 13a with a screw, an adhesive, or the like. The internal space 15 of the first cap member 13a is defined from the outside by a glass window 16, so that the internal space 15 in which the base 11 is accommodated is kept airtight. Note that the window 16 may be omitted when the internal space 15 can be kept airtight by bonding and fixing the condenser lens 12 to the hole 14 of the cap 13.
[0031]
A hole 17 for allowing laser light to pass through is formed in a portion (the other end side) of the second cap member 13b that faces the condenser lens 12. The second cap member 13b is slid with respect to the first cap member 13a, positioned and adjusted in the laser optical axis direction, and fixed to the first cap member 13a by YAG welding, so that the condensing lens 12 and the receptacle 2 Alignment with the dummy ferrule 18 in the laser optical axis direction is performed.
[0032]
The receptacle 2 has a ferrule insertion hole 19 into which a ferrule 21 (see FIG. 2) to which the optical fiber 20 is connected is inserted. A dummy ferrule 18 having an optical fiber 18a disposed therein is press-fitted and fixed to the can package 1 side in the ferrule insertion hole 19. One end face of the receptacle 2 on the side where the dummy ferrule 18 is fixed is fixed to the end face on the other end side of the second cap member 13b of the can package 1 by butt welding by YAG welding or the like. When the receptacle 2 is fixed to the second cap member 13b, positioning adjustment in two directions perpendicular to the laser optical axis direction is performed with the joint surfaces in contact with each other, whereby the condenser lens 12 and the receptacle 2 are adjusted. Positioning with respect to two directions perpendicular to the laser optical axis with the dummy ferrule 18 is performed.
[0033]
The ferrule 21 connected to the optical fiber 20 presses the ferrule 21 toward the dummy ferrule 18 and locks the ferrule 21 to the receptacle 2 when the ferrule 21 is inserted into the ferrule insertion hole 19 of the receptacle 2. For this purpose, an appropriate mechanism (not shown) is provided. Therefore, when the ferrule 21 is inserted into the ferrule insertion hole 19 of the receptacle 2, the optical fiber 18a of the dummy ferrule 18 and the end faces of the optical fiber 20 in the ferrule 21 come into contact with each other, thereby connecting the fibers (optical coupling). Is done.
[0034]
Next, the configuration within the can package 1 will be described. Before describing the configuration in the can package 1, an equivalent circuit of each component in the can package 1 will be described with reference to FIG.
[0035]
FIG. 4 shows an example of the circuit configuration of each component in the can package 1 and the circuit configuration of the LD drive circuit 100 that drives the LD 40 in the can package 1. The LD drive circuit 100 is mounted on an external substrate that is electrically connected to the can package 1. A grounded coplanar differential line 70 (see FIGS. 5 and 6) is provided on the external substrate.
[0036]
The LD driving circuit 100 includes an input buffer 102 having a differential input configuration, a pair of transistors 103 and 104 having a differential configuration for outputting a positive phase signal and a negative phase signal, and a transistor 105 as a bias constant current source. And resistors 106 and 107 for impedance matching.
[0037]
The input buffer 102 shapes the waveforms of the input normal phase signal and negative phase signal, and outputs the shaped normal phase signal and negative phase signal to the bases of the transistors 103 and 104.
[0038]
A pair of transistors 103 and 104 having a differential configuration forms a differential amplifier. The collector sides of the transistors 103 and 104 are connected to resistors 106 and 107, respectively. The other side of the resistors 106 and 107 is connected to the ground terminal. The emitters of the transistors 103 and 104 are connected to the collector of the transistor 105, which is a constant current source. The base of the transistor 103 is connected to the negative phase signal output terminal of the input buffer 102, and the base of the transistor 104 is connected to the positive phase signal output terminal of the input buffer 102. That is, the positive phase input transistor 104 is connected to the positive phase signal I. ₂ , The transistor 103 to which the negative phase is input is connected to the negative phase signal I. ₁ Is converted into a current value determined by the transistor 105 and output. The emitter side of the transistor 105 is connected to the negative power source Vee1.
[0039]
The output terminals on the emitter side of the transistors 103 and 104 are connected to the LD 40 via a distributed constant circuit 30 including a microstrip differential line, a grounded coplanar differential line, a high-frequency signal pin described later, and matching resistors 31a and 31b. Are connected to a pair of electrodes (cathode, anode).
[0040]
The can package 1 side has a distributed constant circuit 30, impedance matching resistors 31a and 31b of about 20Ω, a condenser lens 12, an LD 40 having a high frequency impedance of about 5Ω, and an air core as an inductance element having a high frequency impedance. Solenoids 33a and 33b, anti-resonance resistors 34a and 34b connected in parallel to the air core solenoids 33a and 33b, and wire bonds 35a and 35b for connecting the LD 40 and the air core solenoids 33a and 33b are provided.
[0041]
The cathode side of the LD 40 is connected to one end of a bias constant current source 36 through a parallel circuit of a wire bond 35a, an air-core solenoid 33a connected in series to the wire bond 35a, and a resonance preventing resistor 34a. The other end of the bias constant current source 36 is connected to the negative power source Vee2. The anode side of the LD 40 is grounded via a parallel circuit of a wire bond 35b, an air-core solenoid 33b connected in series to the wire bond 35b, and a resonance preventing resistor 34b. The air core solenoids 33a and 33b are both electrically connected to the pair of electrodes of the LD 40 on the side closer to the LD 40 than the matching resistors 31a and 31b. The negative power source Vee1 and the negative power source Vee2 are preferably the same power source, but may be different power sources.
[0042]
According to the driving configuration of the LD 40, the cathode and anode of the LD 40 are connected to a bias power source (the bias constant current source 36 and the ground terminal in FIG. 4) via solenoids 33 a and 33 b, and a pair of differential transistors A high frequency modulation signal is differentially input to the cathode and anode of the LD 40 by 103 and 104.
[0043]
In other words, when the transistor 104 of the LD drive circuit 100 is turned from OFF to ON (the transistor 103 is turned from ON to OFF), a current flows through the LD 40, and the laser light output from the LD 40 is turned from OFF to ON. Further, when the transistor 104 is turned from ON to OFF (the transistor 103 is turned from OFF to ON), the current flowing through the LD 40 is reduced, and the laser light output from the LD 40 is turned from ON to OFF.
[0044]
As described above, the modulated electric signal output from the differential transistors 103 and 104 of the LD driving circuit 100 is transmitted to the LD 40 through the distributed constant circuit 30 or the like, and the modulated electric signal is converted into an optical modulation signal in the LD 40. The light modulation signal generated from the LD 40 is condensed on the optical fiber 18a by the condenser lens 12 and output through the optical fiber 18a.
[0045]
Next, each component of the can package 1 will be described with reference to FIGS. FIG. 5 is a perspective view showing the can package 1 with the cap 13 removed, and FIG. 6 is a plan view thereof. FIG. 7 is a diagram for illustrating an arrangement relationship of the stem, the pin, and the pedestal. 6 is slightly different from FIGS. 3, 5, and 7 in the arrangement positions of the bias power supply pins 44a and 44b and the monitor signal pin 43 for convenience of explanation.
[0046]
As shown in FIGS. 5 to 7, the can package 1 includes a disc-shaped stem 10 on which a plurality of pins are mounted, and a trapezoidal columnar base that is fixed to the inner wall surface of the stem 10 by Ag brazing or the like. 11.
[0047]
The stem 10 constituting the ground has a pair of high-frequency signal pins 41a and 41b to which a differential modulation electric signal (hereinafter also referred to as a differential high-frequency signal) is transmitted from the LD driving circuit 100, and the high-frequency signal pins 41a and 41b. Two ground pins 42a and 42b arranged on both sides of 41b, one monitor signal pin 43 for signal transmission of a light receiving element for monitoring (for example, a photodiode, hereinafter referred to as PD) 50, and LD 40 A pair of bias power supply pins 44a and 44b for supplying a bias current from an external DC bias current source and a PD chip carrier 45 for mounting a monitoring PD 50 are mounted. For example, the positive-phase current signal I shown in FIG. ₂ Is pulled out and the current signal I shown in FIG. ₂ And a current signal I of opposite phase ₁ Is given.
[0048]
Among these signal pins, the high-frequency signal pins 41a and 41b constitute a feed-through that allows an electrical signal to pass through the stem 10 while maintaining airtightness. As will be described in detail later, each of these pins is fixed in a hermetically sealed state to the stem 10 via a dielectric made of a material such as glass. The ground pins 42a and 42b are fixed to the outer wall surface of the stem 10 constituting the ground by pressure bonding and welding. The PD 50 mounted on the PD chip carrier 45 is for monitoring monitor light emitted backward from the LD 40. The PD 50 is arranged so that the line segment connecting the LD 40 and the PD 50 is between the microstrip differential signal line substrates 46 and 47 and the bias circuit substrate 49 in the plan view shown in FIG. .
[0049]
A pedestal 11 is disposed substantially perpendicular to the stem 10. On the upper surface of the pedestal 11, microstrip differential line substrates 46 and 47, an LD chip carrier 48, and a bias circuit substrate 49 are mounted. The pedestal 11 and the stem 10 have conductive plating on the entire surface. A planar conductor plate (hereinafter referred to as a solid ground) formed on the back surface of the microstrip differential line substrates 46 and 47 and the LD chip carrier 48 and soldered to the upper surface of the base 11 is electrically connected. ing. The pedestal 11 is a heat dissipation path for heat generated from the LD 40 or the like.
[0050]
The micro differential line substrates 46 and 47 and the bias circuit substrate 49 are arranged on both sides of the LD chip carrier 48 so as to sandwich the LD chip carrier 48. That is, the micro differential line substrates 46 and 47, the LD chip carrier 48, and the bias circuit substrate 49 are arranged in a substantially U shape, and the LD chip carrier 48 is arranged in a substantially U-shaped folded portion. Has been.
[0051]
The microstrip differential line substrate 46 includes a ceramic substrate 51, a pair of strip differential signal lines 52a and 52b formed on the top surface of the ceramic substrate 51, and a solid ground (not shown) formed on the back surface of the ceramic substrate 51. ). Pads 53a and 53b for making contact with the high-frequency signal pins 41a and 41b protruding from the stem 10 are formed on one end side of the strip differential signal lines 52a and 52b. In the middle of the strip differential signal lines 52a and 52b, stubs 54a and 54b that function as capacitors and that have a low characteristic impedance and protrude so as to approach the signal lines are formed. The strip differential signal lines 52a and 52b have a large distance between the signal lines so as to increase the characteristic impedance in the input side portion 52d (FIG. 6) close to the stem 10 for impedance matching with the high frequency signal pins 41a and 41b. Is set. Further, the strip differential signal lines 52a and 52b have a portion where the signal line interval gradually approaches and an output side portion which is arranged in parallel with the interval approaching. As shown in FIG. 7, the ends of the high-frequency signal pins 41a and 41b mounted on the stem 10 are connected and fixed to the pads 53a and 53b of the microstrip differential line substrate 46 by brazing or soldering.
[0052]
The microstrip differential line substrate 47 includes a ceramic substrate 55, a pair of strip differential signal lines 56a and 56b formed on the upper surface of the ceramic substrate 55, and a solid ground (not shown) formed on the back surface of the ceramic substrate 55. ). The strip differential signal lines 56a and 56b have corner curve portions for bending the signal line direction by approximately 90 degrees. In the middle of the strip differential signal lines 56a and 56b, impedance matching resistors 31a and 31b (see FIG. 4) are formed, respectively. The strip differential signal lines 52a and 52b and the strip differential signal lines 56a and 56b are connected by wire bonds 57a and 57b, respectively.
[0053]
The LD chip carrier 48 includes a ceramic substrate 58, a pair of strip differential signal lines 59a and 59b formed on the upper surface of the ceramic substrate 58, and a solid ground (not shown) formed on the back surface of the ceramic substrate 58. The LD 40 is mounted so that the anode, which is one electrode of the LD 40, is in direct contact with one of the strip differential signal lines 59b. The cathode as the other electrode of the LD 40 is connected to the other strip differential signal line 59 a by a wire bond 60. The strip differential signal lines 56a and 56b and the strip differential signal lines 59a and 59b are connected by wire bonds 61a and 61b, respectively. The ceramic substrate 58 is made of a material such as aluminum nitride (AlN) or silicon carbide (SiC) having good thermal conductivity. As the LD 40, for example, a distributed feedback type laser diode element capable of 10 Gb / s modulation is used.
[0054]
On the bias circuit (ceramic) substrate 49, two wiring patterns 62a and 62b and a pair of inductance circuits (a parallel circuit of a solenoid and an anti-resonance resistor) are formed. In one wiring pattern 62a, an anti-resonance resistor 34a for preventing resonance between the line capacitance and the inductance of the air core solenoid 33a and the air core solenoid 33b is arranged so as to be electrically connected in parallel, and the other wiring pattern. Similarly, the air core solenoid 33b and the resonance prevention resistor 34b are arranged in 62b so as to be electrically connected in parallel. The air-core solenoid 33a and the air-core solenoid 33b are spaced apart so that the central axes (extensions thereof) of the solenoids 33a and 33b intersect each other so as to prevent mutual mutual magnetic fields from interfering with each other. . One end of each of the two wiring patterns 62a and 62b is connected to the strip differential signal lines 56a and 56b of the LD chip carrier 48 via the wire bonds 35a and 35b. The other end is connected to bias feed pins 44a and 44b provided on the stem 10 via wire bonds 63a and 63b.
[0055]
Next, the characteristic configuration of each part of the can package 1 will be described in more detail. First, the configuration of the stem 10 will be described in detail.
[0056]
The differential high-frequency signals output from the differential transistors 103 and 104 of the LD drive circuit 100 shown in FIG. 4 are output from the can package 1 via the grounded coplanar differential line 70 as shown in FIGS. Is input. The grounded coplanar differential line 70 includes a pair of differential signal lines 71a and 71b formed on the substrate 73 and the differential signal lines 71a and 71b so as to sandwich the pair of differential signal lines 71a and 71b. It is composed of grounds 72a and 72b disposed on the outside and a solid ground (not shown) disposed on the back surface and connected to the grounds 72a and 72b.
[0057]
The differential signal lines 71 a and 71 b of the grounded coplanar differential line 70 are connected and fixed to high-frequency signal pins 41 a and 41 b provided on the stem 10. The ground lines 72 a and 72 b of the grounded coplanar differential line 70 are connected and fixed to ground pins 42 a and 42 b provided on the stem 10.
[0058]
The stem 10 is made of a metal such as Kovar (Fe—Ni alloy), soft iron, or CuW (copper tungsten), and is usually plated with Ni or gold on the upper layer for soldering. For example, the stem 10 made of Kovar or soft iron can be made by punching a metal plate with a metal mold, and the stem 10 made of CuW can be made with a metal injection mold, which is easy to manufacture, so the cost is low. A plurality of holes 74, 75, 76a, 76b are formed in the stem 10 in a dispersed manner, and dielectrics 77, 78, 79a, 79b are inserted into these holes 74, 75, 76a, 76b.
[0059]
A pair of pin insertion holes 80a and 80b are formed in the dielectric 77, and the high frequency signal pins 41a and 41b are inserted and fixed in these pin insertion holes 80a and 80b. Similarly, holes (not shown) are formed in the dielectrics 78, 79a, and 79b, and the monitor signal pin 43 and the bias feed pins 44a and 44b are inserted and fixed in these holes. In this case, the shape of the dielectric 77 into which the pair of high frequency signal pins 41a and 41b is inserted has an oval shape. Correspondingly, the hole 74 into which the dielectric 77 is inserted also has an oval shape. The other dielectrics 78, 79a, 79b have a circular shape. The ground pins 42a and 42b do not penetrate through the stem 10, and are fixed to the outer wall surface 10z (FIGS. 6 and 7) of the stem 10 by pressure bonding and welding as described above.
[0060]
Here, in consideration of the high frequency characteristics, the two high frequency signal pins 41a and 41b have a length (a protruding length toward the LD 40) of a portion protruding outside at least one of the dielectrics 77 as the monitor signal pin 43. And the bias feeding pins 44a and 44b are set to be shorter than the protruding length, and when the signal transmitted through the high frequency signal pins 41a and 41b appears outside the dielectric 77, the microstrip differential line substrate 46 is instantly used. The differential signal lines 52a and 52b can be transferred. Since the monitor signal pin 43 and the bias power supply pins 44a and 44b are not severely restricted by high frequency characteristics, a certain protrusion length is secured to facilitate wire bonding connection work and the like.
[0061]
As the dielectrics 77, 78, 79a, and 79b, for example, Kovar glass is preferably used, and borosilicate glass or the like may be used. Here, Kovar glass has a dielectric constant εr = 4-5. Further, as the high frequency signal pins 41a and 41b, the monitor signal pin 43, the bias power supply pins 44a and 44b, and the ground pins 42a and 42b, for example, a metal such as Kovar or 50% Ni—Fe alloy is used.
[0062]
When the high frequency signal pins 41a and 41b, the monitor signal pin 43, the bias power supply pins 44a and 44b, and the dielectrics 77, 78, 79a, and 79b are inserted and fixed to the stem 10, the dielectric insertion holes 74 and 75 are inserted. , 76a, 76b, the dielectrics 77, 78, 79a, 79b are placed in the holes 74, 75, 76a, 79b by applying vibration in a state where the dielectrics 77, 78, 79a, 79b are placed on the stem 10. In the same manner, the pins 41a, 41b, 43, 44a, and 44b are dropped into holes 80a and 80b formed in the dielectrics 77, 78, 79a, and 79b. In this state, the plurality of stems 10 are inserted into a carbon jig (not shown), and then the dielectric is temporarily melted by applying heat in an electric furnace at a stretch, and the dielectric and pins are fixed to the stem 10. To do.
[0063]
When the stem 10 and the pedestal 11 are manufactured separately, the pedestal 11 is connected and fixed to the stem 10 by Ag brazing or the like. Of course, you may make it manufacture the stem 10 and the base 11 as an integral thing.
[0064]
Incidentally, when the two metal pins are not fixed by the ellipse-shaped dielectric (glass) 77 as described above, the metal pins are fixed by melting glass beads to constitute a feed line. As seen in the example of the coaxial connector for high frequency, if it is manufactured under sufficient manufacturing control, performance can be obtained, but since the glass beads are melted and solidified, the glass sealed in the pin through-holes is solidified. The impedance is likely to be mismatched because the shape varies, the pin falls down, or the connection position with the feeder line in the module becomes non-uniform. As a result, jitter is likely to occur in the signal waveform input to the LD 40, and problems such as degradation of the optical output waveform are likely to occur.
[0065]
Next, the material of the stem 10, signal pins 41a, 41b,..., Dielectrics 77, 78,. When selecting these materials, the materials vary depending on what characteristics are optimized.
[0066]
(1) Prevent cracks generated in the dielectric (glass).
In order to obtain impedance matching and ensure the reliability of the airtight structure, the dielectric 77 of the high-frequency signal pins 41a and 41b needs to have a thickness, and as a material, glass such as Kovar glass or borosilicate glass is used. Since it is used, the pins and stems 10 arranged on the inside and outside of the glass so as not to be cracked with respect to the temperature fluctuation of −40 ° C. to 85 ° C. required as the environmental temperature of the communication device. The thermal expansion coefficient is set to the same level as that of glass. For this reason, Kovar is used as the material of the pin, and Kovar or CuW is used as the material of the stem 10.
[0067]
(2) Optimizing heat dissipation.
In order to optimize the heat dissipation of the heat generated from the LD 40 or the like, it is optimal to integrate the stem 10 and the base 11 with CuW. If the metal injection molding technique is used, a complicated shape such as an integral structure of the stem 10 and the pedestal 11 can be made relatively inexpensively. Kovar glass, borosilicate glass or the like is used for the dielectric, and Kovar is used for the pin.
[0068]
(3) Reduce costs.
What integrated the stem 10 and the base 11 with Kovar is optimal. However, since Kovar has poor heat dissipation, it can be used only for packages for optical semiconductor elements that generate little heat. As in the present embodiment, in the case of an LD module, the LD heat generation is about 0.2 W, so that Kovar can be used. On the other hand, in the case of a PD module with a transimpedance amplifier, the amplifier heat generation is 0. Since there is about 5W, the temperature rise is large and it is difficult to use Kovar.
[0069]
(4) Eclectic plan
The pedestal 11 supporting the heat source may be made of inexpensive Kovar for the stem 10 using CuW having good heat dissipation. These joints are brazed. The pedestal 11 may be made of inexpensive iron, and the stem 10 made of Kovar may be joined thereto by brazing.
[0070]
The distributed constant circuit 30 includes the grounded coplanar differential line 70, the high frequency signal pins 41a and 41b, the ground pins 42a and 42b, the stem 10, the wire bonds 57a and 57b, the microstrip differential line substrate 46, and the like. Is done.
[0071]
Next, a transparent or translucent glass material is used for the ellipsoidal dielectric 77 through which the high-frequency signal pins 41a and 41b are penetrated, thereby deteriorating the reflection characteristics of the high-frequency signal. Bubbles 5 (see FIG. 8) generated in the material can be easily visually inspected. Incidentally, as a glass used for this kind of dielectric material, a black glass has been conventionally used, and visual inspection of bubbles 5 generated in the glass has been difficult. Of course, it goes without saying that black glass may be used for the monitor signal pin 43 and the bias feed pins 44a and 44b other than the high-frequency signal pins 41a and 41b.
[0072]
Next, a configuration for impedance matching in the differential signal line will be described.
[0073]
A conventional can package using a single-phase line is low in cost, but has a problem that high frequency characteristics are not good enough. FIG. 9A is a diagram schematically showing a cross-section of a feed-through portion of a conventional can package using a single-phase line signal pin described in Japanese Patent Application Laid-Open No. 11-233876. In FIG. 9A, the outer periphery of a metal signal pin 601 having a radius ra is filled with a dielectric (glass) 602 having a radius rb, and the outer periphery of the dielectric 602 is surrounded by a metal stem 603 for feedthrough. Is configured. The stem 603 is grounded.
[0074]
Such characteristic impedance of the signal pin 601 can be expressed by the following equation (1). FIG. 10A shows the signal pin of the signal pin 601 in the case of the single-phase feedthrough signal pin shown in FIG. 9A with the relative permittivity εs = 4.1 and relative permeability μs = 1 of the dielectric (glass). The characteristic impedance of the feedthrough when the radius ra is 0.1 mm, 0.15 mm, 0.2 mm, and 0.25 mm is shown.
[0075]
[Expression 1]

[0076]
As shown in FIG. 10A, for example, when the signal pin radius ra is 0.15 mm and the characteristic impedance is 30 ohms, a dielectric (glass) having a radius rb of 0.4 mm is used. A thru must be configured. If two of these feedthroughs are arranged in parallel on the stem and a space S1 of 0.5 mm is secured between the two feedthroughs, the length of the signal pins in the radial direction is 2.1 mm. In such a configuration, the diameter of a typical can package is 5.4 mm (or 3.5 mm), whereas the feedthrough accounts for half (or more than half).
[0077]
In addition, the characteristic impedance changes greatly due to the change in the radius of the dielectric 602 (the hole diameter of the stem 603 filled with the dielectric 602), and the characteristic impedance changes when the hole diameter or the pin mounting position shifts during processing. There was a problem that would vary greatly. In addition, since the characteristic impedance of the part connected from the feedthrough outlet to the circuit board or strip line, etc., suddenly increases and is likely to cause electrical reflection, variations in characteristic impedance can cause the matching circuit to be designed and manufactured. It was difficult.
[0078]
On the other hand, FIG. 9B schematically shows a cross-section of a feedthrough having high-frequency signal pins 41a and 41b provided in the can package 1 according to the first embodiment of the present invention. In the figure, the radius of the high-frequency signal pins 41a and 41b is Ra, the center distance between the high-frequency signal pins 41a and 41b is S2, and a dielectric (glass) 610 having a radius Rb is formed on the outer periphery of the high-frequency signal pins 41a and 41b (the dielectric of FIG. 5). Corresponding to the body 77), and the stem 10 is disposed on the outside thereof. In the figure, the dielectric 610 is circular in order to simplify the description. The stem 10 is grounded.
[0079]
The characteristic impedance in this case can be expressed by the following equation (2). In addition, Formula (1) and Formula (2) are based on the description of the 16th page (general electronic publishing company August 20, 1990) of the fundamentals of the microwave circuit of the author, and its application (1st edition) by Yoshihiro Konishi. Is. In FIG. 10B, the radius Ra of the high frequency signal pins 41a and 41b is 0.15 mm, and the center interval S2 is 0.6 mm to 0.9 mm (0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm). The characteristic impedance of the feedthrough of the differential line is shown with the relative permittivity εs = 4.1 and the relative permeability μs = 1 of the dielectric (glass). For example, when the radius Ra of the high frequency signal pins 41a and 41b is 0.15 mm, the center distance S2 varies from 0.7 mm to 0.9 mm, and the radius of the dielectric (glass) 610 is 0.65 mm to 1.1 mm. The characteristic impedance is in the range of 60 to 65 ohms, and the fluctuation is small.
[0080]
[Expression 2]

The unit is Ω, but simplified under the conditions of Rb> Ra and S2> 2Ra.
[0081]
Thus, by using a differential line for the feedthrough, variation in characteristic impedance is reduced due to electric field coupling between the high frequency signal pins 41a and 41b. Therefore, it is possible to appropriately allow variations in pin positions in the glass fusion fixing process of the high-frequency signal pins 41a and 41b, and variations in hole diameters during stem processing, and the quality is stable and an inexpensive feedthrough is obtained. be able to. Further, the radius of the dielectric 610 can be set to 0.8 mm, and further, the dielectric can be formed into an oval, an ellipse, or a bowl (an example of the shape of the dielectric is shown in FIG. 18). It is possible to obtain a smaller can package as compared with the case where the feedthroughs are arranged side by side.
[0082]
Further, a portion connecting the output end of the feedthrough projecting inside the can package 1 (microstrip differential line substrate 46 side) and the microstrip differential line substrate 46, or the outside of the can package 1 (difference in grounded coplanar) In the portion connecting the output end of the feedthrough projecting to the movement line 70 side and the microstrip differential line substrate 46, the electric field coupling between the lines is appropriately maintained, and the change in characteristic impedance can be suppressed. This facilitates the design of matching circuits such as the stubs 54a and 54b.
[0083]
FIG. 10C shows the radius Ra of the high frequency signal pins 41a and 41b from 0.05 mm to 0.25 mm (0.05 mm, 0.1 mm, 0.15 mm, 0, 20 mm, 0.25 mm), and the center distance S2 between the pins. Is a characteristic impedance when the radius is 0.8 mm, and the characteristic impedance can be adjusted to a desired size by changing the radius Ra of the pin. As can be seen from the figure, even if the pin radius Ra is appropriately selected, there is little change in the characteristic impedance accompanying the change in the radius of the dielectric Rb, and the same effect as described above can be obtained.
[0084]
Preferably, the center interval S2 between the high-frequency signal pins 41a and 41b is 0.7 to 0.9 mm, the radius Rb of the dielectric 610 is 0.65 to 1.1 mm, and the high-frequency signal pin 41a. The radius of 41b is preferably 0.05 mm to 0.5 mm.
[0085]
In the first embodiment, in order to perform impedance matching from the outputs of the differential transistors 103 and 104 of the LD driving circuit 100 to the LD 40, the LD 40 is driven by configuring all of them as differential lines. The pins that penetrate the stem 10 are also differential pins constituting a differential line by passing a pair of high-frequency signal pins 41a and 41b through an elliptical dielectric 77. For this reason, the electrical coupling between both signal pins is increased, the electric field can be contained, and loss due to leakage can be reduced. Therefore, the discontinuity of the electric field of the portion exposed to the LD drive circuit 100 side from the stem 10 (hereinafter referred to as the driver side pin exposed region) in the high-frequency signal pins 41a and 41b that are particularly likely to vary in size is suppressed as compared with the conventional case. Can do. Furthermore, since the ground pins 42a and 42b are arranged so as to run in parallel with the high-frequency signal pins 41a and 41b in the driver-side pin exposed region, it is possible to suppress reflection by reducing the impedance of this portion.
[0086]
Also, for example, in the case of single-phase driving, since the large current that drives the LD returns to the drive circuit via the ground, the ground potential fluctuates, so the light that detects the weak current installed nearby Although the receiving electronic circuit may be adversely affected, in this embodiment, the differential line is used to push-pull the LD, so that a large current flows through the differential line and the ground potential varies. There is also an advantage that the influence on peripheral circuits is less likely to occur.
[0087]
In this way, the driver side pin exposed region has a differential line configuration, and the ground pins 42a and 42b are arranged on the outside thereof so that the impedance of this portion is lower than in the prior art. The impedance difference is smaller than that of the prior art and the discontinuity of the electric field is reduced, so that the transmission characteristics and reflection characteristics can be improved.
[0088]
Since glass is used as the dielectric 77 disposed around the high-frequency signal pins 41 a and 41 b, an inner portion of the stem 10 (a feedthrough portion in which the high-frequency signal pins 41 a and 41 b are surrounded by the dielectric 77, In the following description, the impedance tends to be too low. In order to increase the impedance of the non-exposed region of the pin, the cross-sectional area (the area of the ellipse) of the dielectric 77 disposed around the high frequency signal pin may be increased. However, this reduces the size and space. The request cannot be satisfied.
[0089]
Therefore, the two high-frequency signal pins 41a and 41b protrude to the LD 40 side so as to be immediately transferred to the differential signal lines 52a and 52b of the microstrip differential line substrate 46 when they are outside the dielectric 77. While shortening the length, among the strip differential signal lines 52a and 52b of the microstrip differential line substrate 46, the interval between the portions 52d (see FIG. 6) close to the stem 10 connected to the high frequency signal pins 41a and 41b is set. For example, the electrical coupling of this part is weakened by setting it comparatively large, such as making it larger than the line interval of the part near the differential line board | substrate 47, or setting a little wider than the space | interval of pin 41a, 41b. Thus, this portion 52d is set to a high impedance. For example, the feedthrough portions of the high-frequency signal pins 41a and 41b are 60Ω, the wide 52d portion of the strip differential signal lines 52a and 52b is 150Ω, and the strip differential signal lines 52a and 52b are close to the differential line substrate 47. The narrow part is set to 100Ω.
[0090]
Thus, the high-impedance portion is intentionally created by increasing the line spacing of the differential line portion immediately after exiting the stem 10, and the low-impedance portion between the high-impedance portion and the stem inside (the pin non-exposed region). The impedance is canceled with the portion, and the impedance is matched as a whole. That is, since the pin non-exposed region (feedthrough portion) has a low impedance, a high impedance is made a little thereafter so that impedance matching as a whole is taken.
[0091]
A pair of stubs 54a and 54b for impedance matching are formed in the middle of the strip differential signal lines 52a and 52b, and the impedance is lowered by the pair of stubs 54a and 54b to reduce the strip differential signal line 56a, This prevents mismatching with 56b. That is, with the pair of stubs 54a and 54b, the reactance component in the driver side pin exposed region and the reactance component in the pin non-exposed region (feed through portion) are compensated to improve the pass characteristic and the reflection characteristic.
[0092]
Further, in this case, the pair of stubs 54a and 54b protrude not to the outside but to the inside (so as to approach each other's signal lines), thereby contributing to the miniaturization of the microstrip differential line substrate 46. . In the case where miniaturization is not necessary, as shown in FIG. 11, the differential lines 52a and 52b may be protruded outside.
[0093]
Next, the layout of the four substrates (the microstrip differential line substrates 46 and 47, the LD chip carrier 48, and the bias circuit substrate 49) on the base 11 and the PD chip carrier 45 will be described.
[0094]
In the can package 1, a differential line substrate for connecting the high frequency signal pins 41a, 41b and the LD 40, a substrate on which the LD 40 is mounted, a bias circuit substrate for supplying a DC bias current to the LD 40, and a monitor PD50 And need to be placed.
[0095]
FIG. 12 shows another layout on the base 11 in the case of the differential line configuration. In the center of the stem 10, high frequency signal pins 41a and 41b are disposed so as to penetrate, and ground pins 42a and 42b are disposed so as to sandwich the high frequency signal pins 41a and 41b. In addition, bias power supply pins 44a and 44b are disposed so as to sandwich the high-frequency signal pins 41a and 41b and the ground pins 42a and 42b. A differential line substrate 90a for connecting the high frequency signal pins 41a and 41b and the LD 40, a substrate 90b for mounting the LD 40, and a substrate 90e for mounting the matching resistors 31a and 31b are disposed in the center of the base 11. Also, bias circuit boards 90c and 90d having solenoids are arranged on both sides of the LD 40 of the base 11, and the solenoids provided on the bias boards 90c and 90d are connected to the bias power supply pins 44a and 44b by wire bonds, respectively. .
[0096]
In such a layout, since the laser light is emitted only before and after the LD 40, it is necessary to dispose the monitor PD 50 above and below the high-frequency signal pins 41a and 41b, and it is difficult to dispose in space. In addition, since the differential line substrate 90a, the substrate 90b on which the LD 40 is mounted, and the substrate 90e on which the matching resistors 31a and 31b are mounted are arranged linearly in the laser beam emission direction, the laser beam emission direction of the base 11 The length along the line becomes longer, leading to an increase in the size of the package. Further, in order to reduce the inductance of the wire bonds 35a and 35b connected to the bias circuit, the substrate has to be divided into two, which increases the cost. Further, in this layout, since the transparent dielectric 77 for sealing and fixing the high-frequency signal pins 41 a and 41 b is located immediately behind the LD 40, the monitor light from the LD 40 can be canceled via the transparent dielectric 77. The light is emitted directly to the outside of the package 1, and there is a concern that there is a high possibility of entering the eyes of the operator when performing work while driving the LD 40.
[0097]
In view of such a situation, in the first embodiment, as shown in FIGS. 5 to 7 and the like, the LD chip carrier 48 is composed of the microstrip differential line substrates 46 and 47 and the bias circuit substrate 49. It is arranged on both sides of the LD chip carrier 48 so as to sandwich it. In other words, the strip differential signal lines 52a, 52b, 56a, and 56b of the microstrip differential line substrates 46 and 47, the wiring patterns 62a and 62b including a pair of inductance circuits, and the LD 40 with the LD 40 in the middle. Are arranged in a substantially U-shape.
[0098]
For this reason, the length of the pedestal 11 in the direction of the laser optical axis can be a length corresponding to the microstrip differential line substrates 46 and 47, and can be made smaller than the layout shown in FIG.
[0099]
Further, since the microstrip differential line substrates 46 and 47 are disposed at positions shifted to the side from the LD chip carrier 48, the transparent dielectric 77 for sealing and fixing the high frequency signal pins 41a and 41b is formed. The arrangement position is inevitably arranged at a position shifted to the side from the LD chip carrier 48. Since the intensity of the laser light becomes weaker as it is shifted from the optical axis in a Gaussian distribution, only light having a low intensity enters the transparent dielectric 77, thereby improving safety during operation.
[0100]
There is a method in which the substrate on which the LD 40 is mounted and the differential line substrate that connects the high-frequency signal pins 41a and 41b and the LD 40 are formed of the same substrate, but in this case, heat from the LD 40 as a heat source is used. In order to dissipate heat, it is necessary to use a substrate material such as an aluminum nitride substrate (AlN), which is expensive per unit area and has good heat dissipation, over a wide area, which causes an increase in cost.
[0101]
Therefore, in the first embodiment, as shown in FIGS. 5 and 6, the LD chip carrier 48 on which the LD 40 as a heat source is mounted is separated from other substrates to be a single substrate. For this reason, it is only necessary to use an expensive ceramic substrate material such as an aluminum nitride substrate (AlN) with good heat dissipation for the LD chip carrier 48, and other substrates (microstrip differential line substrates 46 and 47, biases). Circuit board 49) is an inexpensive Al ₂ O _Three It is sufficient to use a ceramic substrate material such as the above, and the cost can be reduced.
[0102]
In addition, according to the layout of the first embodiment, the microstrip differential line substrate 46 for impedance matching and the microstrip differential line substrate 47 for arranging the matching resistors 31a and 31b are separate substrates. Therefore, it is possible to cut a ceramic substrate without waste, which contributes to a reduction in cost. The impedance matching microstrip differential line substrate 46 is manufactured at the time of manufacturing the stem 10, and the stem 10 and the microstrip differential line substrate 46 are connected and fixed by brazing or soldering. It is possible to perform manufacturing operations with a high degree of freedom such as assembling and then assembling with other component parts, thereby improving workability. As the diameter of the stem 10, for example, a size of φ5.6 mm can be realized sufficiently.
[0103]
Further, on the bias circuit substrate 49, the parallel circuit of the air-core solenoid 33a and the resonance prevention resistor 34a connected to the bias feed pins 44a and 44b and the parallel circuit of the air-core solenoid 33b and the resonance prevention resistor 34b are the same. Since the bias circuit substrate is arranged on the substrate to reduce the area, it contributes to cost reduction and miniaturization.
[0104]
Further, the air core solenoids 33a and 33b on the bias circuit substrate 49 are arranged so as to cross each other preferably so as not to interfere with each other, so that the magnetic field generated in one solenoid is the other. It is possible to make the arrangement position of the air-core solenoids 33a and 33b closer to the anode and cathode of the LD 40.
[0105]
Next, the arrangement of the PD 50 will be described. The PD chip carrier 45 on which the PD 50 is mounted is not disposed immediately behind the LD 40 but is disposed at a position slightly deviated vertically and laterally with respect to the laser optical axis, thereby effectively utilizing the space. The bias power supply pins 44a and 44b, the monitor signal pins 43, and the like arranged in FIG.
[0106]
Further, when selecting whether the PD 50 is shifted above or below the LD 40, it is determined according to the positional relationship between the semiconductor substrate 99 and the active layer 93 constituting the LD 40 and the intensity distribution of the far-field image of the monitor light. To do. FIG. 13 schematically shows the structure of the LD 40.
[0107]
The LD 40 includes a cathode (n electrode) 91, an anode (p electrode) 92, a p-type semiconductor substrate 99, an active layer 93 forming a light emitting region, and an end face 110 provided with an antireflection film (AR coating). A window structure 94 for reducing reflected return light, a clad layer 501 sandwiching the active layer 93, and the like are provided. Note that the window structure 94 increases the band gap in the vicinity of the end face by suppressing the absorption of light in the vicinity of the end face by injecting or diffusing impurities in the vicinity of the resonator end face (cleavage face) 502. It is a structure that has effects such as preventing end face destruction.
[0108]
The active layer 93 is disposed at a position offset in the direction opposite to the semiconductor substrate 99, and thus the emitted laser light has the following intensity distribution.
[0109]
Part of the laser light emitted from the active layer 93 is reflected by the cathode 91 made of a highly reflective metal on the upper side of the window structure 94. Since this reflected light interferes with other laser light directly emitted from the active layer 93 through the window structure 94, the intensity distribution of the monitor light at positions separated by a distance where the PD 50 is disposed is shown in FIG. As shown in FIG. In the intensity distribution shown in FIG. 14, ripples due to the interference are generated in the positive angle region (semiconductor substrate 99 side). Therefore, if the PD 50 is arranged on the ripple generation side, the light receiving sensitivity changes suddenly due to a slight assembly error, and thus there is a problem that the monitor light cannot be detected with high accuracy.
[0110]
On the other hand, as shown in FIG. 14, in the negative angle region (on the side opposite to the semiconductor substrate 99), a shape close to a normal Gaussian distribution waveform that smoothly changes to a position where the light beam is kicked by the anode 91 is obtained.
[0111]
Therefore, if the PD 50 is arranged on the side offset in the direction opposite to the semiconductor substrate 99 with respect to the optical axis, it is not affected by the ripple of the far-field image due to the interference described above, and the monitor light is detected with high accuracy. Will be able to.
[0112]
FIG. 15 is a diagram showing an arrangement relationship between the LD 40 and the PD 50 in the can package 1 of the first embodiment shown in FIGS. As shown in FIG. 15, the PD 50 is arranged on the upper side of the LD 40, that is, on the side that is offset in the direction opposite to the semiconductor substrate with respect to the optical axis, and the influence of the ripple of the far-field image due to the above-described interference. The monitor light can be detected with high accuracy. Further, in this case, the PD 50 is arranged at a position shifted in the left-right direction with respect to the LD 40 and is miniaturized. The lower surface of the PD chip carrier 45 is slightly separated from the upper surface of the base 11.
[0113]
Next, the thickness of the elliptical dielectric (glass) 77 to be inserted into the stem 10 will be described with reference to FIG. When the thickness of the dielectric 77 is set to the same depth as the depth of the hole 74 formed in the stem 10, that is, the width of the stem 10, the edge of the glass rises during heating in the electric furnace, and the uneven portion is formed on the wall surface of the stem 10. Will be formed. Such unevenness on the wall surface of the stem 10 interferes with various component arrangements.
[0114]
Therefore, the thickness of the dielectric 77 is set shorter than the depth of the hole 74 formed in the stem 10, that is, the width of the stem 10, and before heating in the electric furnace, as shown in FIG. A hole 95 in which the opening on the side is formed in a mortar shape is formed. In this way, even if the edge of the glass rises during heating in the electric furnace, the glass does not reach the wall surface of the stem 10, and arbitrary parts can be arranged so as to overlap the region of the dielectric 77. It becomes like this. In the first embodiment shown in FIGS. 5 to 7, a part of the PD chip carrier 45 for arranging the PD 50 is arranged so as to overlap the dielectric 77 as shown in FIG. Yes. That is, the PD chip carrier 45 is arranged so as to overlap the mortar-shaped opening of the hole 95. Further, as shown in FIGS. 5 and 15, etc., a part of the contact surface of the base 11 with the stem 10 is also arranged so as to overlap the mortar-shaped opening of the hole 95. The dielectrics 79a, 79b, 78 for sealing and fixing the other bias power supply pins 44a, 44b and the monitor signal pin 43 are similarly set to have a thickness shorter than the width of the stem 10. . Further, in this case, the hole 95 is formed on the wall surface to which the base 11 of the stem 10 is fixed. However, when components are arranged on the opposite surface, the hole 10 is formed on the opposite wall surface of the stem 10. A similar hole may be formed.
[0115]
In the first embodiment, a grounded coplanar differential line 46b as shown in FIG. 17 may be used instead of the microstrip differential line substrates 46 and 47. As described above, the grounded coplanar differential line 46b is disposed outside the differential signal line so as to sandwich the pair of differential signal lines formed on the substrate and the pair of differential signal lines. It is composed of a ground and a solid ground arranged on the back surface.
[0116]
In the first embodiment, the ground pins 42a and 42b are disposed outside the high-frequency signal pins 41a and 41b. However, as shown in FIG. 18, an embodiment in which the ground pins 42a and 42b are omitted is also possible. It is.
[0117]
Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described with reference to FIG. 19A to 19C show other shapes of the dielectric 77 for sealing the high-frequency signal pins 41a and 41b.
[0118]
FIG. 19A employs a saddle shape in which two circles of about 270 ° / 360 ° are connected by a straight line (or a gentle curve) as the shape of the dielectric 77. Focusing on the distance from one pin 41a (or 41b) to the periphery of the dielectric 77, that is, the stem 10 as the ground member, in the case of a saddle shape, 270 ° / 360 ° is at an equal distance r, and the rest The part becomes longer than the distance r. On the other hand, in the case of the elliptical dielectric used in the first embodiment, 180 ° / 360 ° is equidistant r, and the remaining portion is longer than the distance r. The longer the distance from the pin to the ground, the higher the impedance. Therefore, when comparing the saddle shape and the oval shape of the same area, the oval shape can set the impedance higher. As described above, in the pin non-exposed region (feed-through region), the impedance tends to decrease too much, so that the oval shape is more advantageous in terms of increasing the impedance. Of course, when the saddle shape is adopted, the area may be adjusted so that the impedance equivalent to that of the oval shape can be obtained.
[0119]
In FIG. 19B, a shape in which two circles are directly connected is adopted as the dielectric 77, and in FIG. 19C, an elliptical shape is adopted.
[0120]
Embodiment 3 FIG.
Next, a fourth embodiment of the present invention will be described with reference to FIG. In the third embodiment, the heat dissipation characteristics of the can package 1 are further improved. Therefore, the fourth embodiment is suitable when applied to a package with poor heat dissipation, in which the base 11 and the stem 10 are integrally formed with Kovar or the like.
[0121]
As shown in FIG. 20A, a wire insertion hole 82 for inserting a wire (heat pipe) 81 such as Cu having good heat conductivity is formed in the base 11 and the stem 10. The diameter of the wire rod insertion hole 82 is made larger than the diameter of the wire rod 81. A press-fit hole 82a is formed at the bottom of the wire-insertion hole 82, and one end of the wire 81 is press-fitted and fixed into the press-fit hole 82a. The length of the press-fitting hole 82a is made as short as possible within a range where the wire 81 can be fixed. This is to prevent the occurrence of distortion due to the difference in thermal expansion coefficient between the wire 81 and the base 11. When heat dissipation from the LD 40 is taken into consideration, it is preferable that the press-fitting hole 82 a for fixing one end of the wire 81 is disposed immediately below the LD 40 or the LD chip carrier 48.
[0122]
It is preferable that the wire 81 does not come into contact with the inner peripheral surface of the wire insertion hole 82 until the wire 81 reaches the bottom of the hole 82, but the friction between the wire 81 and the wire insertion hole 82 is preferable. Alternatively, as long as the occurrence of distortion due to the difference in thermal expansion coefficient between the wire 81 and the pedestal 11 can be prevented by interference between the surfaces, they may be in contact with each other. However, it is necessary to avoid that the wire (heat pipe) 81 is joined to the inner peripheral surface of the wire insertion hole 82 by solder or the like.
[0123]
Moreover, as shown in FIG. 20B when FIG. 20A is viewed from the K direction, the other end of the wire 81 is bent in a spiral shape. The other end of the wire 81 bent in a spiral shape is screwed into the center of the spiral, and is fastened to a screw hole provided in the heat sink 2000 located on the back side of the grounded coplanar differential line 70. . As a result, the other end of the wire 81 is fixed to the heat sink 2000. At this time, since the other end of the wire 81 is fixed with springiness, even if a thermal displacement difference occurs between the wire 81 and the pedestal 11 due to a difference in thermal expansion coefficient, the thermal displacement difference can be absorbed. Generation | occurrence | production of the distortion of the base 11 can be prevented. Both the external substrate electrically connected to the can package 1 and the LD module 3 are accommodated in a case (not shown). The heat sink 2000 is provided on the wall surface of this case.
[0124]
The heat generated in the LD 40 is dissipated from the LD chip carrier 48 to the one end of the wire 81 through the base 11. The heat transferred to the wire 81 is transferred from the other end of the wire 81 to the heat sink 2000 and is radiated from the fins provided on the heat sink 2000 to the outside air.
[0125]
Thus, in the third embodiment, since the wire 81 for heat dissipation is provided inside the base 11 and the stem 10 so as not to contact the wall surface, the LD 40, the driver IC, the transimpedance amplifier, etc. It is possible to efficiently dissipate the heat generated from the heat source, and to prevent the occurrence of distortion due to the difference in thermal expansion coefficient between the wire 81 and the base 11.
[0126]
By the way, in the above-described embodiment, the stem configuration for inputting the differential signal is applied to the LD module on which the LD 40 is mounted. However, the stem configuration is applied to the electroabsorption optical modulator (EA modulation). The present invention may be applied to an EA module on which an electro-absorption modulator is mounted. Needless to say, a Peltier element for adjusting the temperature of the LD may be used.
[0127]
【The invention's effect】
As described above, according to the present invention, since the differential signal line substrate and the bias circuit substrate are arranged on both sides of the light emitting element chip carrier so as to sandwich the light emitting element chip carrier, the optical semiconductor element module Downsizing, effective use of space, and cost reduction can be realized.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an external configuration of an optical semiconductor package according to the present invention.
FIG. 2 is a perspective view showing an external configuration of an LD module in which an optical semiconductor package and a receptacle according to the present invention are connected.
FIG. 3 is a horizontal and vertical sectional view of an LD module.
FIG. 4 is an equivalent circuit diagram of components in a can package and an LD drive circuit.
FIG. 5 is a perspective view showing an internal configuration of the can package according to the first embodiment.
FIG. 6 is a plan view showing an internal configuration of the can package according to the first embodiment.
FIG. 7 is a diagram for illustrating an arrangement relationship of a stem, a pin, and a pedestal.
FIG. 8 is a view for showing bubbles generated in a dielectric body.
FIG. 9 is a diagram schematically showing a cross section of a feedthrough according to the related art and the first embodiment.
10 is a diagram showing the relationship between the glass radius and the characteristic impedance in the feedthrough of the conventional example and Embodiment 1. FIG.
FIG. 11 is a diagram showing a modification of the arrangement of stubs.
FIG. 12 is a diagram for illustrating a general layout of various components.
FIG. 13 is a diagram for explaining an arrangement condition between an LD and a PD.
FIG. 14 is a diagram showing a light intensity distribution of light emitted from an LD.
FIG. 15 is a diagram for explaining an arrangement state of an LD and a PD.
FIG. 16 is an enlarged view of the vicinity of an elliptical dielectric disposed on the stem.
17 is a diagram showing a modification of the first embodiment, and is a diagram showing a grounded coplanar differential line. FIG.
FIG. 18 is a diagram showing a modification of the first embodiment.
FIG. 19 is a diagram for explaining the second embodiment of the present invention, and is a diagram showing another shape of a dielectric;
FIG. 20 is a diagram for explaining a third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Can package, 2 receptacle, 3 optical semiconductor element module (LD module), 5 foam, 10 stem, 10z stem outer wall surface, 11 base, 12 condensing lens, 13 cap, 13a 1st cap member, 13b 2nd cap member , 14 hole, 15 internal space, 16 window, 17 hole, 18 dummy ferrule, 18a optical fiber, 19 ferrule insertion hole, 20 optical fiber, 21 ferrule, 30 distributed constant circuit, 31a, 31b matching resistance, 33a, 33b solenoid ( Air core solenoid), 34a, 34b anti-resonance resistor, 35a, 35b wire bond, 36 bias constant current source, 40 semiconductor laser diode (LD), 41a, 41b high frequency signal pin, 42a, 42b ground pin, 43 monitor signal pin, 44a, 44b Bias Electrical pin, 45 PD chip carrier, 46, 47 Microstrip differential line substrate, 46b Grounded coplanar differential line, 48 LD chip carrier, 49 Bias circuit substrate, 50 Photodiode (PD), 52a, 52b Strip differential signal line, 53a, 53b pad, 54a, 54b stub, 56a, 56b Strip differential signal line, 57a, 57b wire bond, 59a, 59b Strip differential signal line, 60 wire bond, 61a, 61b wire bond, 62a, 62b wiring pattern, 63a, 63b wire bond, 70 grounded coplanar differential line, 71a, 71b differential signal line, 72a, 72b ground (ground line), 77, 78, 79a, 79b dielectric, 80a, 80b Pin insertion hole, 81 wire rod, 82 hole ( Material insertion hole), 82a press-fitting hole, 91 cathode, 92 anode, 93 active layer, 94 window structure, 95 holes, 99 semiconductor substrate, 100 LD drive circuit, 101 external substrate, 102 input buffer, 103, 104 transistor (differential Transistor), 105 transistor (bias constant current source), 500 screw, 501 cladding layer, 502 resonance end face, 601 signal pin, 602, 610 dielectric (glass), 603 stem, 2000 heat sink.

Claims (10)

A differentially driven semiconductor light emitting device; and
A chip carrier for a light emitting element on which the semiconductor light emitting element is mounted;
A differential signal line substrate having a differential line for supplying a differential signal to the semiconductor light emitting element;
A bias circuit board having at least a pair of inductance circuits and supplying a bias current to the semiconductor light emitting element;
A pedestal on which is mounted ,
A dielectric having a pair of pin insertion holes;
A pair of high-frequency signal pins which are fixedly penetrated in the pair of pin insertion holes of the dielectric and electrically connected to the differential lines of the differential signal line substrate;
A stem in which the dielectric is sealed in the formed hole and the pedestal is fixed;
With
An optical semiconductor element module, wherein the differential signal line substrate and the bias circuit board are arranged on both sides of the light emitting element chip carrier so as to sandwich the light emitting element chip carrier on the pedestal . A light receiving element for receiving monitor light emitted backward from the semiconductor light emitting element;
2. The light receiving element is arranged such that a line segment connecting the semiconductor light emitting element and the light receiving element is between the differential signal line substrate and the bias circuit substrate in a plan view. An optical semiconductor element module according to 1.   3. The optical semiconductor element module according to claim 2, wherein the light receiving element is arranged on a side of the semiconductor light emitting element that is offset in a direction opposite to the semiconductor substrate with the optical axis of the semiconductor light emitting element as a center.   The optical semiconductor element module according to any one of claims 1 to 3, wherein the bias circuit board is formed by mounting a parallel circuit of a pair of air-core solenoids and resistors on one ceramic board.   5. The optical semiconductor element module according to claim 4, wherein the pair of air-core solenoids are spaced apart so that extension lines of their central axes intersect. The differential line substrate includes a first substrate connected to the pair of high frequency signal pins and having a differential line for impedance matching with the high frequency signal pins, and a differential line on which a matching resistor is disposed. The optical semiconductor element module according to claim 1, wherein the optical semiconductor element module is divided into a second substrate. Wherein the dielectric is transparent or translucent, optical semiconductor according to any one of claims 1 to 6, characterized in that the is arranged at a position shifted with respect to the optical axis of the semiconductor light emitting element Element module. The pre-Symbol receiving element comprising a career of light receiving elements mounted on said stem,
3. The optical semiconductor element module according to claim 2 , wherein the opening of the hole of the stem is formed in a mortar shape, and a part of the carrier of the pedestal or the light receiving element overlaps the mortar-shaped opening. A differentially driven semiconductor light emitting device; and
A chip carrier for a light emitting element on which the semiconductor light emitting element is mounted;
A differential signal line substrate having a differential line for supplying a differential signal to the semiconductor light emitting element;
A bias circuit board having at least a pair of inductance circuits and supplying a bias current to the semiconductor light emitting element;
Is an optical semiconductor element module mounted on a pedestal,
The pedestal has a hollow hole into which a thermally conductive linear member is inserted, and one end of the linear member is at the bottom of the hollow hole and directly below the chip carrier mounting surface of the pedestal. The optical semiconductor element module is characterized in that a portion of the linear member excluding a connection portion with the bottom portion is not joined to the inner peripheral surface of the hollow hole. A differentially driven semiconductor light emitting device; and
A differential signal line for supplying a differential signal to the semiconductor light emitting element;
A bias circuit having at least a pair of inductance circuits and supplying a bias current to the semiconductor light emitting element;
A pedestal on which is mounted ,
A dielectric having a pair of pin insertion holes;
A pair of high-frequency signal pins which are fixedly penetrated in the pair of pin insertion holes of the dielectric and electrically connected to the differential lines of the differential signal line substrate;
A stem in which the dielectric is sealed in the formed hole and the pedestal is fixed;
The provided, an optical semiconductor element module which incorporates the base package,
An optical semiconductor element module, wherein the differential signal line, the bias circuit, and the semiconductor light emitting element are arranged in a substantially U shape, and the semiconductor light emitting element is arranged in a substantially U-shaped folded portion.

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