JP5301126B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5301126B2 JP5301126B2 JP2007215190A JP2007215190A JP5301126B2 JP 5301126 B2 JP5301126 B2 JP 5301126B2 JP 2007215190 A JP2007215190 A JP 2007215190A JP 2007215190 A JP2007215190 A JP 2007215190A JP 5301126 B2 JP5301126 B2 JP 5301126B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 216
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229920005989 resin Polymers 0.000 claims abstract description 134
- 239000011347 resin Substances 0.000 claims abstract description 134
- 239000000853 adhesive Substances 0.000 claims abstract description 64
- 230000001070 adhesive effect Effects 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims description 150
- 238000007789 sealing Methods 0.000 claims description 127
- 239000000463 material Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 16
- 238000012360 testing method Methods 0.000 claims description 13
- 238000003825 pressing Methods 0.000 claims description 3
- 238000000465 moulding Methods 0.000 abstract 5
- 229920002050 silicone resin Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000011800 void material Substances 0.000 description 4
- 239000004925 Acrylic resin Substances 0.000 description 3
- 229920000178 Acrylic resin Polymers 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
12 第1中継基板
14 第1封止樹脂
15 第1ダイ接着剤
18 第1基板電極
19 第1ワイヤ
20 第2半導体チップ
21 アンダーフィル材
22 第2中継基板
23 バンプ電極
27 試験電極
28 第2基板電極
30 接着剤
32 支持材
40 第2封止樹脂
42 第2ワイヤ
44 外部接続端子
50 第1半導体パッケージ
52 第2半導体パッケージ
100 半導体装置
Claims (11)
- 第1半導体チップと、
前記第1半導体チップが上面に実装された第1中継基板と、
前記第1中継基板の上面に設けられ、前記第1半導体チップを封止する第1封止樹脂と、
前記第1封止樹脂の上面に実装された第2半導体チップと、
前記第2半導体チップがフリップチップボンディングにより実装された第2中継基板と、
前記第1中継基板の上面に設けられ、前記第1封止樹脂、前記第2半導体チップ、及び前記第2中継基板を封止する第2封止樹脂と、
を具備し、
前記第2半導体チップは、前記第2中継基板に実装された面と反対側の面を下にして、前記第1封止樹脂の上面に接着剤を介して実装され、
前記第2中継基板には前記第2半導体チップが複数実装され、前記複数の第2半導体チップのうち少なくとも1つが、前記接着剤を介して前記第1封止樹脂の上面に実装されていることを特徴とする半導体装置。 - 前記第1封止樹脂及び前記第2中継基板の間の領域に、少なくとも前記第2半導体チップの側面を覆って設けられた支持材を具備することを特徴とする請求項1に記載の半導体装置。
- 前記支持材は、前記第1封止樹脂及び前記第2中継基板の間の領域全体に設けられていることを特徴とする請求項2に記載の半導体装置。
- 前記接着剤は、前記第1封止樹脂及び前記第2中継基板の間の領域に、少なくとも前記第2半導体チップの側面を覆って設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記接着剤は、前記第1封止樹脂及び前記第2中継基板の間の領域全体に設けられていることを特徴とする請求項4に記載の半導体装置。
- 前記第2中継基板における、前記第2半導体チップが実装された面に設けられた試験電極を具備することを特徴とする請求項1から5のうちいずれか1項に記載の半導体装置。
- 第1中継基板の上面に実装された第1半導体チップを封止する第1封止樹脂の上面に、第2中継基板にフリップチップボンディングにより実装された第2半導体チップを、前記第2中継基板に実装された面と反対側の面を下にして、接着剤を介して実装する工程と、
前記第1中継基板の上面に、前記第1封止樹脂、前記第2半導体チップ、及び前記第2中継基板を封止する第2封止樹脂を形成する工程と、
を具備し、
前記第2半導体チップを前記第1封止樹脂の上面に前記接着剤を介して実装する工程は、前記第2中継基板に実装された複数の前記第2半導体チップのうち少なくとも1つを、前記第2中継基板に実装された面と反対側の面を下にして、前記第1封止樹脂の上面に前記接着剤を介して実装することを特徴とする半導体装置の製造方法。 - 前記第2半導体チップを前記第1封止樹脂の上面に前記接着剤を介して実装する工程は、
前記第1封止樹脂の上面に前記接着剤を供給する工程と、
前記第2半導体チップを前記接着剤に接触させた後さらに押圧し、前記第1封止樹脂及び前記第2中継基板の間の領域に前記接着剤を充填する工程と、
を含むことを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記第1封止樹脂及び前記第2中継基板の間の領域に前記接着剤を充填する工程は、前記接着剤を前記第1封止樹脂及び前記第2中継基板の間の領域全体に充填することを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記第2半導体チップを前記第1封止樹脂の上面に前記接着剤を介して実装する工程の後、前記第1封止樹脂及び前記第2中継基板の間の領域に、少なくとも前記第2半導体チップの側面を覆って支持材を充填する工程を具備することを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記第1封止樹脂及び前記第2中継基板の間の領域に前記支持材を充填する工程は、前記支持材を前記第1封止樹脂及び前記第2中継基板の間の領域全体に充填することを特徴とする請求項10に記載の半導体装置の製造方法。
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JP2007215190A JP5301126B2 (ja) | 2007-08-21 | 2007-08-21 | 半導体装置及びその製造方法 |
US12/196,156 US8749039B2 (en) | 2007-08-21 | 2008-08-21 | Semiconductor device having chip mounted on an interposer |
US14/271,115 US9312252B2 (en) | 2007-08-21 | 2014-05-06 | Method of manufacturing a semiconductor device having a chip mounted on an interposer |
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JP2005123542A (ja) * | 2003-10-20 | 2005-05-12 | Genusion:Kk | 半導体装置のパッケージ構造およびパッケージ化方法 |
US9899794B2 (en) * | 2014-06-30 | 2018-02-20 | Texas Instruments Incorporated | Optoelectronic package |
US9929085B2 (en) | 2016-06-02 | 2018-03-27 | Globalfoundries Inc. | Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same |
US9892970B2 (en) | 2016-06-02 | 2018-02-13 | Globalfoundries Inc. | Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same |
US11024616B2 (en) * | 2019-05-16 | 2021-06-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
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US5786273A (en) | 1995-02-15 | 1998-07-28 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and associated fabrication method |
JP4075204B2 (ja) * | 1999-04-09 | 2008-04-16 | 松下電器産業株式会社 | 積層型半導体装置 |
KR100334577B1 (ko) | 1999-08-06 | 2002-05-03 | 윤종용 | 사진공정의 해상도를 능가하는 트렌치를 절연막내에 형성하는방법 |
JP2001320014A (ja) * | 2000-05-11 | 2001-11-16 | Seiko Epson Corp | 半導体装置及びその製造方法 |
KR100652370B1 (ko) | 2000-06-15 | 2006-11-30 | 삼성전자주식회사 | 플로팅 바디효과를 제거한 반도체 메모리소자 및 그제조방법 |
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JP3463038B2 (ja) | 2000-11-14 | 2003-11-05 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20030040152A1 (en) | 2001-08-22 | 2003-02-27 | Chen-Chin Liu | Method of fabricating a NROM cell to prevent charging |
US6940152B2 (en) | 2002-02-21 | 2005-09-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor storage device and its manufacturing method |
US7057269B2 (en) * | 2002-10-08 | 2006-06-06 | Chippac, Inc. | Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package |
KR100465632B1 (ko) | 2002-12-21 | 2005-01-13 | 주식회사 하이닉스반도체 | 반도체 소자의 비트라인 형성방법 |
JP4123027B2 (ja) * | 2003-03-31 | 2008-07-23 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2005209882A (ja) * | 2004-01-22 | 2005-08-04 | Renesas Technology Corp | 半導体パッケージ及び半導体装置 |
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WO2006106569A1 (ja) * | 2005-03-31 | 2006-10-12 | Spansion Llc | 積層型半導体装置及びその製造方法 |
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JP4871280B2 (ja) * | 2005-08-30 | 2012-02-08 | スパンション エルエルシー | 半導体装置およびその製造方法 |
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JP4435102B2 (ja) | 2006-03-13 | 2010-03-17 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
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US20090206462A1 (en) | 2009-08-20 |
JP2009049249A (ja) | 2009-03-05 |
US9312252B2 (en) | 2016-04-12 |
US20140256088A1 (en) | 2014-09-11 |
US8749039B2 (en) | 2014-06-10 |
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