JP5381632B2 - Method for fabricating group III nitride semiconductor light-emitting device, method for forming electrode for group III nitride semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a group III nitride semiconductor light emitting device, a method for forming an electrode for a group III nitride semiconductor device, and a group III nitride semiconductor device.

  Patent Document 1 describes a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes a polarity reversal layer formed immediately above the first semiconductor layer and a second semiconductor layer formed directly above the polarity reversal layer. The second semiconductor layer has a polarity to be etched by wet etching, and the first semiconductor layer has a polarity to be an etching stop layer for the wet etching of the second semiconductor.

  Patent Document 2 describes a group III nitride semiconductor device and a manufacturing method thereof. In this nitride semiconductor device, an amorphous layer for a current confinement layer is formed by low temperature deposition (for example, 400 degrees Celsius), and then an opening for a current path is formed in the amorphous layer. Thereafter, a p-type cladding layer is grown at a temperature higher than the deposition temperature of the amorphous layer (for example, 1000 degrees Celsius), and another layer is grown on the p-type cladding layer. During this growth, the amorphous layer is converted to a crystalline layer.

  Patent Document 3 describes a method for manufacturing a semiconductor device. According to this manufacturing method, the current confinement portion of the semiconductor device using the group III-V nitride semiconductor can be formed without damaging the exposed surface of the active region. A semiconductor device includes a first semiconductor layer made of an n-type group III-V nitride semiconductor, a second semiconductor layer made of a p-type group III-V nitride semiconductor, and a group III-V nitride provided therebetween. A light emitting layer made of a semiconductor is included. An oxidized region is formed by the oxidation of the second semiconductor layer. Oxide regions are formed on both sides of the second semiconductor layer for current confinement. A p-side electrode is formed on the entire surface of the second semiconductor layer and the oxidized region.

In Patent Document 4, a first film (SiO ₂ ) and a second film (ZrO ₂ ) made of an insulator are formed on a gallium nitride based semiconductor layer, and a gallium nitride based semiconductor is formed using these two layer films. A recess is formed in the layer. The etching rate of the second film (ZrO ₂ ) is smaller than the etching rate of the first film (SiO ₂ ) with respect to the etching with respect to the fluorine-containing etchant and the chlorine-containing etchant. Thereafter, a third film (ZrO ₂ ) whose etching rate for the fluorine-containing etchant is smaller than that of the first film (SiO ₂ ) is formed in the second film (ZrO ₂ ) and the recess.

International Publication WO2006-013698 JP 2003-078215 A JP 2003-283052 A Japanese Patent Laid-Open No. 2004-119772

  The invention in Patent Document 1 utilizes the fact that hexagonal gallium nitrides having polarities opposite to each other exhibit different etching rates in wet etching. However, it is not easy to stack hexagonal gallium nitride layers having opposite polarities.

  In the invention in Patent Document 2, the growth of the amorphous layer and the conversion of the amorphous layer into the crystalline layer are performed thereafter. The crystalline layer converted from the amorphous layer remains in the finished semiconductor composition.

  In the invention in Patent Document 3, a gallium nitride based semiconductor is oxidized in an oxygen atmosphere using a mask in order to form a structure for current confinement. The resulting insulator is limited to oxides of constituent elements of gallium nitride based semiconductors.

In the invention of Patent Document 4, the first film to be etched in the lift-off process for ridge formation is composed of SiO _2. The third film finally remaining on the device is limited to a material smaller than the etching rate of the first film in the etching using the fluorine-containing etchant. Since the first film etched during lift-off is made of SiO ₂ , silicon oxide cannot be used as the third film.

  The present invention has been made in view of such circumstances, and a group III nitride semiconductor light emitting device capable of forming an exposed area of a group III nitride with good position controllability with respect to an opening of an insulating film. It is an object of the present invention to provide a manufacturing method. Further, the present invention provides a group III nitride in which an exposed area of group III nitride can be formed with good position controllability with respect to the opening of the insulating film, and an electrode can be formed on the exposed area with good contact characteristics. An object is to provide a method of forming an electrode for a semiconductor device. Another object of the present invention is to provide a group III nitride semiconductor device having an electrode in which the exposed area of the group III nitride is aligned with good position controllability with respect to the opening of the insulating film.

  The invention according to one aspect of the present invention is a method of manufacturing a group III nitride semiconductor light emitting device. This method includes (a) a step of epitaxially growing a group III nitride semiconductor layer on a semiconductor stack including an active layer, and (b) a group III nitride lift-off layer on the group III nitride semiconductor layer. (C) forming a mask for forming a pattern for a ridge structure on the group III nitride lift-off layer on the group III nitride lift-off layer; d) transferring the pattern of the mask to the group III nitride lift-off layer and the group III nitride semiconductor layer to form a patterned group III nitride lift-off layer and a patterned group III nitride semiconductor region; And (e) growing an insulating film on the mask, the patterned group III nitride lift-off layer, and the patterned group III nitride semiconductor region, and (f) the pattern. The formed group III nitride lift-off layer is selectively removed from the insulating film using an etchant, and an insulating film patterned to have an opening is formed by a lift-off method and the pattern is formed. Exposing the group III nitride semiconductor region to the opening. The refractive index of the insulating film is smaller than the refractive index of the group III nitride semiconductor layer, the group III nitride lift-off layer contains aluminum as a group III constituent element, and the growth temperature of the group III nitride lift-off layer is: The etching temperature of the group III nitride semiconductor layer is lower than the growth temperature of the group III nitride semiconductor layer, and the etching rate of the group III nitride lift-off layer is higher than the etching rate of the insulating film in etching with the etchant.

  According to this method, after forming a patterned III-nitride lift-off layer and a patterned III-nitride semiconductor region, a mask, a patterned III-nitride lift-off layer, and a patterned III An insulating film is grown on the group nitride semiconductor region. Thereafter, the patterned group III nitride lift-off layer is selectively removed from the insulating film using an etchant by a lift-off method. When the growth temperature of the group III nitride lift-off layer is set lower than the growth temperature of the group III nitride semiconductor layer, and the etching with the etchant for lift-off is performed, the etching rate of the group III nitride lift-off layer is larger than the etching rate of the insulating film. it can. For this reason, the insulating film is patterned to have an opening by the lift process, and the group III nitride semiconductor region is exposed in this opening in a self-aligned manner (self-aligned).

  Also, in the formation of the substrate product, a lift-off layer made of a similar group III nitride is grown on the group III nitride semiconductor layer, so that the similar group III nitride semiconductor layer is exposed until it is exposed in the lift-off process. Covered by a group nitride lift-off layer. Therefore, good protection is provided to the exposed surface of the group III nitride semiconductor layer.

  Furthermore, since the group III nitride semiconductor region patterned for the ridge structure is exposed in the opening of the insulating film having a refractive index smaller than the refractive index of the group III nitride semiconductor layer, good current confinement and light A group III nitride semiconductor light emitting device having a confinement property can be manufactured.

  In the method according to one aspect of the present invention, the growth of the group III nitride semiconductor layer is preferably performed using a growth furnace, and the growth of the group III nitride lift-off layer is performed using the growth furnace. Is good. In the method, after the group III nitride lift-off layer is grown on the group III nitride semiconductor layer, the pattern is formed after the step of taking out the substrate product from the growth furnace and applying the lift-off method. Forming an electrode on the exposed surface of the group III nitride semiconductor region.

  According to this method, after the group III nitride semiconductor layer is grown using the growth furnace, the group III nitride lift-off layer can be grown on the group III nitride semiconductor layer using the growth furnace. Therefore, the group III nitride lift-off layer covers the entire surface of the group III nitride semiconductor region with which the electrode is in contact. When the substrate product is removed from the growth furnace, the exposed area in the patterned group III nitride semiconductor region is not exposed to the atmosphere.

  The invention according to another aspect of the present invention is a method of forming an electrode for a group III nitride semiconductor device. This method includes (a) a step of epitaxially growing a group III nitride semiconductor layer on a substrate, and (b) a group III nitride lift-off layer on the group III nitride semiconductor layer to grow a substrate product. (C) forming a mask for forming a pattern on the group III nitride lift-off layer on the group III nitride lift-off layer; (d) the group III nitride lift-off layer; and Transferring the pattern of the mask to a nitride semiconductor layer to form a patterned group III nitride lift-off layer and a patterned group III nitride semiconductor region; and (e) the mask and the pattern. A step of growing an insulating film on the formed group III nitride lift-off layer and the patterned group III nitride semiconductor region; and (f) forming the patterned group III nitride lift-off layer into the pattern III nitride lift-off layer. By selectively removing the edge film using an etchant, an insulating film patterned to have an opening is formed by a lift-off method, and an exposed surface of the patterned group III nitride semiconductor region is formed. And (g) forming an electrode on the exposed surface of the patterned group III nitride semiconductor region after application of the lift-off method. The group III nitride lift-off layer contains aluminum as a group III constituent element, and the growth temperature of the group III nitride lift-off layer is lower than the growth temperature of the group III nitride semiconductor layer. The etching rate of the group III nitride lift-off layer is larger than the etching rate of the insulating film.

  According to this method, after forming a patterned III-nitride lift-off layer and a patterned III-nitride semiconductor region, a mask, a patterned III-nitride lift-off layer, and a patterned III An insulating film is grown on the group nitride semiconductor region. Thereafter, the patterned group III nitride lift-off layer is selectively removed from the insulating film using an etchant by a lift-off method. When the growth temperature of the group III nitride lift-off layer is set lower than the growth temperature of the group III nitride semiconductor layer, and the etching with the etchant for lift-off is performed, the etching rate of the group III nitride lift-off layer is larger than the etching rate of the insulating film. it can. Therefore, the insulating film is patterned to have an opening by the lift-off process, and the group III nitride semiconductor region is exposed in this opening in a self-aligned manner (self-aligned).

  In addition, since the electrode is formed on the exposed surface defined in a self-aligned manner, the contact area can be defined with good controllability.

  Further, in forming the substrate product, a similar group III nitride lift-off layer is grown on the group III nitride semiconductor layer. Since the group III nitride semiconductor layer is covered with a similar group III nitride lift-off layer until it is exposed in the lift-off process, this method provides good protection to the exposed surface of the group III nitride semiconductor layer. Provided.

In the method according to the above aspect, a contact resistance between the exposed surface of the patterned group III nitride semiconductor region and the electrode may be less than 1 × 10 ⁻³ Ω · cm.

  According to this method, after the group III nitride semiconductor layer is grown using the growth furnace, the group III nitride lift-off layer can be grown on the group III nitride semiconductor layer using the growth furnace. Therefore, the group III nitride lift-off layer covers the entire surface of the group III nitride semiconductor region with which the electrode is in contact. When the substrate product is removed from the growth furnace, the exposed area in the patterned group III nitride semiconductor region is not exposed to the atmosphere. For this reason, the concentration of oxygen remaining on the exposed surface can be reduced. As a result, contact resistance variation can be reduced and contact resistance stability can be increased.

  In the method according to the above aspect, the group III nitride lift-off layer preferably includes at least one of AlN, AlGaN, AlInN, and InAlGaN.

  According to this method, when the group III nitride lift-off layer contains aluminum as a group III constituent element, a desired selectivity can be obtained using a predetermined etchant in etching for lift-off.

In the method according to the above aspect, the group III nitride lift-off layer includes In _X Al _Y Ga _1- XYN (0 ≦ X <1, 0 <Y ≦ 1, 0 <X + Y ≦ 1), The aluminum composition Y of the group III nitride lift-off layer is preferably 0.5 or more and 1.0 or less.

  According to this method, when the group III nitride lift-off layer has the above Al composition range, wet etching of the group III nitride lift-off layer is easy.

  In the method according to the above aspect, in the step of growing the group III nitride lift-off layer, the group III nitride lift-off layer preferably includes a non-single-crystal group III nitride.

  According to this method, the growth temperature of the group III nitride lift-off layer can be made lower than the growth temperature of the group III nitride semiconductor layer, and the group III nitride lift-off layer can be grown so as to include the non-single crystal group III nitride. . At this time, in the etching using the etchant for lift-off, the etching rate of the group III nitride lift-off layer can be made larger than the etching rate of the insulating film.

  In the method according to the above aspect, in the step of growing the group III nitride lift-off layer, the group III nitride lift-off layer includes at least a group III nitride microcrystal, a group III nitride polycrystal, and a group III nitride amorphous. It is preferable to include any of them. These growths can make the etching rate of the group III nitride lift-off layer larger than the etching rate of the insulating film in the etching with the etchant for lift-off.

  In the method according to the above aspect, the growth temperature of the group III nitride lift-off layer is preferably greater than 200 degrees Celsius and less than 600 degrees Celsius.

  According to this method, when the growth temperature of the group III nitride semiconductor layer is within the above temperature range, the group III nitride lift-off layer can be grown so as to include the non-single crystal group III nitride. At this time, in the etching using the etchant for lift-off, the etching rate of the group III nitride lift-off layer can be made larger than the etching rate of the insulating film.

  In the method according to the above aspect, the growth temperature of the III nitride lift-off layer is preferably greater than 300 degrees Celsius and less than 500 degrees Celsius.

  According to this method, when the growth temperature of the group III nitride semiconductor layer is within the above temperature range, the group III nitride lift-off layer can be grown so as to include the non-single crystal group III nitride. At this time, in the etching using the etchant for lift-off, the etching rate of the group III nitride lift-off layer can be made larger than the etching rate of the insulating film.

  In the method according to the above aspect, the insulating film preferably contains a silicon-based inorganic compound. A silicon-based inorganic compound is suitable for stabilizing the surface of the group III nitride. In the method according to the above aspect, the insulating film can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Self-aligned contacts can be formed using these silicon-based inorganic compounds.

  In the method according to the above aspect, the thickness of the group III nitride lift-off layer is greater than 0 nm. The group III nitride lift-off layer has a thickness of 1000 nm or less. More preferably, in the method according to the above aspect, the thickness of the group III nitride lift-off layer is greater than 50 nm. The thickness of the group III nitride lift-off layer is 400 nm or less.

  In the method according to the above aspect, the main surface of the group III nitride semiconductor layer may include a semipolar surface. According to this method, the semipolar surface can be exposed to self-alignment in the opening of the insulating film. In the method according to the above aspect, the main surface of the group III nitride semiconductor layer may include any nonpolar surface. According to this method, the nonpolar surface can be exposed to self-alignment in the opening of the insulating film.

  In the method according to the above aspect, the main surface of the group III nitride semiconductor layer may be 10 degrees or more and 80 degrees or less and 100 degrees or less with respect to a plane orthogonal to a reference axis extending in the c-axis direction of the group III nitride semiconductor layer. It can be inclined at an inclination angle in the range of not less than 170 degrees and not more than 170 degrees. If the angle is less than 10 degrees or more than 170 degrees, the property due to the polar surface becomes stronger on the exposed surface. Further, when the angle exceeds 80 degrees or less than 100 degrees, the property due to the asexual surface becomes stronger on the exposed surface.

  In the method according to the above aspect, the main surface of the group III nitride semiconductor layer is more than 80 degrees or less than 100 degrees with respect to a plane orthogonal to a reference axis extending in the c-axis direction of the group III nitride semiconductor layer. It can be inclined at an inclination angle in the range of. In the angle range of 80 degrees to less than 100 degrees, a property close to a nonpolar plane can be used.

  In the method according to the above aspect, the inclination angle of the main surface of the group III nitride semiconductor layer is preferably inclined with an inclination angle in the range of 63 degrees to 80 degrees and 100 degrees to 117 degrees.

  In the method according to the above aspect, the main surface of the group III nitride semiconductor layer may include a polar surface. According to this method, the polar surface can be exposed to self-alignment in the opening of the insulating film.

  In the method according to the above aspect, the main surface of the group III nitride semiconductor layer is less than 10 degrees or more than 170 degrees with respect to a plane orthogonal to a reference axis extending in the c-axis direction of the group III nitride semiconductor layer. It can be inclined at an inclination angle in the range of angles. At angles less than 10 degrees and greater than 170 degrees, properties close to the polar plane can be utilized.

  The invention according to still another aspect of the present invention is a group III nitride semiconductor device having a self-aligned contact. The group III nitride semiconductor device includes: (a) a first group III nitride semiconductor portion including first and second portions; a convex shape located on the second portion and having side surfaces and an upper surface. A group III nitride semiconductor layer including a second group III nitride semiconductor portion; and (b) the second group III provided on the first portion of the first group III nitride semiconductor portion. An insulating layer in contact with the side surface of the nitride semiconductor portion; and (c) a group III nitride semiconductor layer and a first electrode provided on the insulating layer. The first electrode is in contact with the upper surface of the second group III nitride semiconductor portion and is provided on the surface of the insulating layer, and the insulating layer includes a silicon-based inorganic compound.

According to this group III nitride semiconductor device, a self-aligned contact can be provided to the group III nitride semiconductor device. The opening of this self-aligned contact is defined by the opening of a silicon-based inorganic compound that can provide reliability. Further, the self-alignment contact can be produced by the method according to the above-described side surface. In this method, the contact resistance between the upper surface of the convex second group III nitride semiconductor portion and the electrode can be less than 1 × 10 ⁻³ Ω · cm.

  In the group III nitride semiconductor device according to still another aspect of the present invention, the first electrode may include a palladium electrode. According to this group III nitride semiconductor device, good contact resistance can be realized.

  A group III nitride semiconductor device according to still another aspect of the present invention includes a group III nitride substrate on which a group III nitride semiconductor layer is mounted, and a second group provided on the back surface of the group III nitride substrate. An electrode. The group III nitride substrate has conductivity. According to this group III nitride semiconductor device, a semiconductor device having a vertical structure is provided.

  In the group III nitride semiconductor device according to still another aspect of the present invention, the group III nitride semiconductor device is a laser diode, and the convex portion is a ridge of the semiconductor laser. The insulating film has a refractive index smaller than that of the group III nitride semiconductor layer. According to this group III nitride semiconductor device, both the ridge and the self-aligned contact to the upper surface of the ridge can be provided to the laser diode. Therefore, the laser diode has a good current confinement property and light confinement property.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, it is possible to provide a method for manufacturing a group III nitride semiconductor light-emitting device capable of forming an exposed area of group III nitride with good position controllability with respect to the opening of the insulating film. . Further, according to the present invention, the exposed area of the group III nitride can be formed with good position controllability with respect to the opening of the insulating film, and an electrode can be formed on the exposed area with good contact characteristics. A method of forming an electrode for a nitride semiconductor device can be provided. Furthermore, according to the present invention, it is possible to provide a group III nitride semiconductor device having an electrode in which the exposed area of group III nitride is aligned with good position controllability with respect to the opening of the insulating film.

FIG. 1 is a drawing showing a process flow in a method for producing a group III nitride semiconductor light emitting device and a substrate product and a method for forming an electrode according to the present embodiment. FIG. 2 is a drawing showing a process flow in a method for producing a group III nitride semiconductor light emitting device and a substrate product and a method for forming an electrode according to the present embodiment. FIG. 3 is a drawing showing major steps in a method for producing a group III nitride semiconductor light emitting device and a substrate product and a method for forming an electrode according to the present embodiment. FIG. 4 is a drawing showing major steps in a method for producing a group III nitride semiconductor light emitting device and a substrate product and a method for forming an electrode according to the present embodiment. FIG. 5 is a drawing showing main steps in a method for producing a group III nitride semiconductor light emitting device and a substrate product and a method for forming an electrode according to the present embodiment. FIG. 6 is a drawing showing main steps in a method for producing a group III nitride semiconductor light-emitting device and a substrate product and a method for forming an electrode according to the present embodiment. FIG. 7 is a drawing showing main steps in a method for producing a group III nitride semiconductor light emitting device and a substrate product and a method for forming an electrode according to the present embodiment. FIG. 8 is a drawing showing an example of a group III nitride semiconductor device in the example.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, with reference to the accompanying drawings, the Group III nitride semiconductor light-emitting device and the method of manufacturing the substrate product of the present invention, the method of forming an electrode for the Group III nitride semiconductor device, the substrate product and the Group III An embodiment relating to a nitride semiconductor device will be described. Where possible, the same parts are denoted by the same reference numerals.

  1 and 2 are drawings showing a process flow in a method for producing a group III nitride semiconductor light emitting device and a substrate product and a method for forming an electrode according to the present embodiment. 3 to 7 are drawings showing main steps in a method for producing a group III nitride semiconductor light emitting device and a substrate product and a method for forming an electrode according to the present embodiment.

  Referring to FIG. 1, a substrate is prepared in step S101. A good group III nitride semiconductor layer is grown on this substrate. For this purpose, the substrate has a main surface made of a group III nitride, and the group III nitride can be, for example, GaN, AlN, InGaN, AlGaN, InAlGaN, or the like. The plane orientation of the group III nitride main surface can be any of a polar plane, a semipolar plane, and a nonpolar plane.

  In step S102, a group III nitride layer is grown on the substrate in the growth furnace 10a. The growth of the group III nitride can be performed by, for example, a metal organic chemical vapor deposition method, but is not limited thereto. First, in step S103, an epitaxial region made of a group III nitride semiconductor is grown on the substrate.

  Specifically, in step S104, the substrate 11 is placed in the growth furnace 10a as shown in FIG. In step 105, as shown in FIG. 3A, the semiconductor stack 13 is epitaxially grown on the substrate using the growth furnace 10a. The semiconductor stack 13 includes one or more group III nitride semiconductor layers. When the group III nitride semiconductor device is, for example, a light emitting device, a first conductivity type cladding layer (for example, n-type InAlGaN layer) 15 and a first light guide layer 17 (for example, undoped GaN layer) are formed to form the semiconductor stack 13. ), An active layer 19, a carrier block layer (eg, an AlGaN electron block layer) 21, a second light guide layer (eg, an undoped GaN layer) 23, and a p-type cladding layer (eg, a p-type InAlGaN layer) 25 are grown. The active layer 19 can include, for example, a GaN barrier layer and an InGaN well layer.

  In step S106, as shown in FIG. 3A, the group III nitride semiconductor layer 27 is grown on the semiconductor stack 13 using the growth furnace 10a to form an epitaxial region 29. When the group III nitride semiconductor device is, for example, a light emitting device, the group III nitride semiconductor layer 27 is, for example, a contact layer (for example, a p-type GaN layer). Through these steps, the epitaxial substrate EP is manufactured. Epitaxial substrate EP includes substrate 11 and epitaxial region 29 provided on substrate 11. In the production of the epitaxial substrate EP, the growth temperature of the epitaxial layers 15, 17, 19, 21, 23, 25, and 27 made of a group III nitride semiconductor can be 700 degrees Celsius or higher and 1100 degrees Celsius or lower. Can be.

  After growing the group III nitride semiconductor layer 27, the substrate temperature of the epitaxial substrate EP is lowered in step S107. In step S108, the group III nitride lift-off layer 31 is grown on the epitaxial substrate EP using the growth furnace 10a. The growth of the group III nitride lift-off layer 31 is not epitaxial growth because it is performed at a low temperature. Through these steps, the substrate product SP is produced. The substrate product SP includes a substrate 11 and a group III nitride region 33. Group III nitride region 33 includes an epitaxial substrate EP and a group III nitride lift-off layer 31 provided thereon.

  After producing the group III nitride lift-off layer 31, the substrate product SP is taken out from the growth furnace 10a in step S109. Thereafter, in step S110, a lift-off process is performed. In the lift-off process, pattern formation is performed on the group III nitride lift-off layer 31 and selective etching of the patterned group III nitride lift-off layer is performed. In order to perform this etching with a desired quality, the production of the group III nitride lift-off layer 31 is performed as described later.

  The lift-off process 110 will be described. In step S111, as shown in FIG. 4A, a mask film 35 is grown on the substrate product SP using the growth furnace 10b to form another substrate product SP1. The mask film 35 can be, for example, a silicon-based inorganic insulating film (specifically, silicon oxide, silicon nitride, silicon oxynitride) or the like. The mask film 35 is formed by, for example, a plasma CVD method.

  In step S112, as shown in FIG. 4B, a resist mask 37 having a pattern defining an opening is formed. In step S113, as shown in FIG. 4B, the mask film 35 is dry-etched by the processing apparatus 10c using the resist mask 37 to form a mask (patterned mask film) 35a. The pattern of the resist mask 37 is transferred to the mask film 35. This etching is performed by, for example, a dry etching method. After this etching, the resist mask 37 is removed.

  In step S114, as shown in FIG. 5A, the group III nitride lift-off layer 31 is dry-etched using the mask 35a to form a patterned group III nitride lift-off layer 31a. An etching apparatus 10d is used for the dry etching. The pattern of the mask 35 a is transferred to the group III nitride lift-off layer 31. This etching is performed by, for example, a dry etching method. By this step, the group III nitride region 33a is formed.

  In step S115, as shown in FIG. 5B and FIG. 6A, the epitaxial region 29 is dry-etched by the processing apparatus 10e using the mask 35a to form a patterned group III nitride semiconductor region ( Epitaxial region). The pattern of the mask 35 a is transferred to the group III nitride semiconductor region 29. This etching is performed with, for example, tetramethylammonium. In the present embodiment, by this processing, as shown in FIG. 5B, the contact layer 27 is etched to form a patterned contact layer 27a. By this step, the group III nitride region 33b and the epitaxial region 29a are formed. Next, as shown in FIG. 6A, the clad layer 25 is etched to form a patterned clad layer 25a. By this step, the group III nitride region 33c and the epitaxial region 29b are formed. If necessary, the epitaxial region can be further processed.

  In step S116, as shown in FIG. 6B, the insulating film 39 is grown using the film forming apparatus 11f. The insulating film 39 is grown on the mask 35a, the patterned group III nitride lift-off layer 31a, and the patterned group III nitride semiconductor region 33c. The refractive index of the insulating film 39 is smaller than that of the group III nitride semiconductor layers 27, 25, 23, 21, 19, 17, 15. The insulating film 39 is formed to a thickness such that the side surface of the patterned group III nitride lift-off layer 31a is exposed, for example. Therefore, the insulating film 39 includes a first portion 39a formed on the mask 35a and a second portion 39b formed on the patterned group III nitride semiconductor region 33c. The first portion 39a is separated from the second portion 39b, or the side surface of the group III nitride lift-off layer 31a patterned by the opening of the insulating film 39 is exposed. With this form of the insulating film 39, lift-off can be applied.

  The insulating film 39 preferably contains a silicon-based inorganic compound. A silicon-based inorganic compound is suitable for stabilizing the surface of the group III nitride. In the method according to the above aspect, the insulating film 39 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Self-aligned contacts can be formed using these silicon-based inorganic compounds.

  In step S117, as shown in FIG. 7A, etching for lift-off is performed. The patterned group III nitride lift-off layer 31a is selectively etched using an etchant with respect to the insulating film 39 to form an insulating film 39b having an opening 39c by a lift-off method. In this etching, the etching rate of the group III nitride lift-off layer 31 a is higher than the etching rate of the insulating film 39. Therefore, the upper surface 29d of the patterned group III nitride semiconductor region 29b is exposed to the opening 39c. An insulating film 39b covers the side surface 29e and the side surface 29f of the patterned epitaxial region 29b.

  In the etching described above, the etching rate of the group III nitride semiconductor layer 27 is lower than the etching rate of the group III nitride lift-off layer 31a. Therefore, the group III nitride lift-off layer 31a can be surely removed by sufficient etching.

  According to this method, after forming the patterned group III nitride lift-off layer 31a and the patterned group III nitride semiconductor region 29b, the mask 35a, the patterned group III nitride lift-off layer 31a and the pattern are formed. An insulating film 39 is grown on the formed group III nitride semiconductor region 29a. Thereafter, the patterned group III nitride lift-off layer 31a is selectively removed from the insulating film 39 using an etchant by a lift-off method. The growth temperature of the group III nitride lift-off layer 31a is set lower than the growth temperature of the group III nitride semiconductor epitaxial layers 27, 25, 23, 21, 19, 17, 15 and the group III nitride lift-off is performed in the etching for lift-off. The etching rate of the layer 31 can be made larger than the etching rate of the insulating film 39. Therefore, the insulating film 39 is patterned so as to have the opening 39c by the lift-off process, and the group III nitride semiconductor region 29b is exposed in the opening 27c in a self-aligned (self-aligned) manner.

  Further, in the formation of the substrate product SP, a similar group III nitride lift-off layer 31 is grown on the group III nitride semiconductor layer 27, so that the group III nitride semiconductor layer 27 is similar until it is exposed in the lift-off process. In this method, good protection is provided to the upper surface 27b of the group III nitride semiconductor layer 27 (a part of the upper surface becomes an exposed surface). .

  Further, the group III nitride semiconductor region 29b patterned for the ridge structure is exposed in the opening 39c of the insulating film 39 having a refractive index smaller than that of the group III nitride semiconductor layer 27. When the material semiconductor element is a light emitting element, a group III nitride semiconductor light emitting element having good current confinement and light confinement can be produced.

The group III nitride lift-off layer 31 preferably includes at least one of AlN, AlGaN, AlInN, and InAlGaN. When the group III nitride lift-off layer 31 contains aluminum as a group III constituent element, a desired selectivity can be obtained by using a predetermined etchant in the etching for lift-off. In addition, the group III nitride lift-off layer 31 includes In _X Al _Y Ga _1- XYN (0 ≦ X <1, 0 <Y ≦ 1, 0 <X + Y ≦ 1), and the group III nitride lift-off layer The aluminum composition Y of 31 is preferably 0.5 or more and 1.0 or less. When group III nitride lift-off layer 31 has the above Al composition range, wet etching of group III nitride lift-off layer 31 is easy. In the step of growing group III nitride lift-off layer 31, group III nitride lift-off layer 31 preferably contains non-single-crystal group III nitride. The growth temperature of the group III nitride lift-off layer 31 can be made lower than the growth temperature of the group III nitride semiconductor layer 31, and the group III nitride lift-off layer 31 can be grown so as to include the non-single crystal group III nitride. At this time, in the etching with the etchant for lift-off, the etching rate of the group III nitride lift-off layer 31 can be made larger than the etching rate of the insulating film.

  In the step of growing the group III nitride lift-off layer 31, the group III nitride lift-off layer 31 preferably includes at least one of group III nitride microcrystal, group III nitride polycrystal, and group III nitride amorphous. . These growths can make the etching rate of the group III nitride lift-off layer 31 higher than the etching rate of the insulating film 39 in the etching with the etchant for lift-off.

  The growth temperature of the group III nitride lift-off layer 31 is preferably larger than 200 degrees Celsius and smaller than 600 degrees Celsius. When the growth temperature of the group III nitride semiconductor layers 27, 25, 23, 21, 19, 17, and 15 is within the above temperature range, the group III nitride lift-off layer 31 is formed so as to include the non-single crystal group III nitride. Can grow. At this time, in the etching using the etchant for lift-off, the etching rate of the group III nitride lift-off layer 31 can be made larger than the etching rate of the insulating film 39.

  The growth temperature of the group III nitride lift-off layer 31 is preferably larger than 300 degrees Celsius and smaller than 500 degrees Celsius. When the growth temperature of the group III nitride lift-off layer 31 is within the above temperature range, the group III nitride lift-off layer 31 can be grown so as to include the non-single crystal group III nitride. At this time, in the etching with the etchant for lift-off, the etching rate of the group III nitride lift-off layer 31 can be made larger than the etching rate of the insulating film.

  The thickness of the group III nitride lift-off layer 31 is greater than 0 nm, and the thickness of the group III nitride lift-off layer 31 is 1000 nm or less. More preferably, the thickness of the group III nitride lift-off layer 31 is greater than 50 nm. The thickness of the group III nitride lift-off layer 31 is 400 nm or less.

  In the method according to the present embodiment, if necessary, after the group III nitride lift-off layer 31 is grown on the group III nitride semiconductor layer 27, the substrate product is taken out from the growth furnace 10a and the lift-off method is applied. As shown in FIG. 7B, in step S118, the electrode 41 can be formed on the exposed surface 29d (27b) of the patterned group III nitride semiconductor region.

  After the group III nitride semiconductor layer 27 is grown using the growth furnace 10a, the group III nitride lift-off layer 31 is grown using the growth furnace 10a without exposing the epitaxial substrate to the atmosphere. Therefore, the group III nitride lift-off layer 31 covers the entire surface of the group III nitride semiconductor region 29 with which the electrode 41 is in contact. For this reason, when the substrate product is taken out from the growth furnace 10a, the area that becomes the exposed surface 29d in the patterned group III nitride semiconductor region 29b is not exposed to the atmosphere.

  According to this method, after forming the patterned group III nitride lift-off layer 31a and the group III nitride semiconductor region 29b, the mask 35a and the patterned group III nitride lift-off layer 31a and the group III nitride semiconductor are formed. An insulating film 39 is grown on the region 29b. Thereafter, the patterned group III nitride lift-off layer 31a is selectively removed from the insulating film 39 using an etchant by a lift-off method. Therefore, the insulating film 39 is patterned to have the opening 39c by the lift-off process, and the group III nitride semiconductor region 29b is exposed in the opening 39c in a self-aligned manner (self-alignment).

  Further, when the electrode 39 is formed on the exposed surface 29d defined in a self-aligned manner, the contact area can be defined with good controllability.

  Furthermore, in the formation of the substrate product, a similar group III nitride lift-off layer 31 is grown on the group III nitride semiconductor layer 29, so that the group III nitride semiconductor layer 29 is similar until it is exposed in the lift-off process. Since it is covered with the group III nitride lift-off layer 31, good protection is provided to the exposed surface 27b (29d) of the group III nitride semiconductor layer 27a (29b).

  Further, according to this method, the group III nitride lift-off layer covers the entire surface of the group III nitride semiconductor region. Therefore, when the substrate product is taken out from the growth furnace, the exposed area in the patterned group III nitride semiconductor region is not exposed to the atmosphere. For this reason, the oxygen concentration remaining on the exposed surface can be reduced. As a result, contact resistance variation can be reduced and contact resistance stability can be increased.

(Example 1): Electrode formation process In the above manufacturing method, after processing the Mg-doped p-type GaN contact film and the p-type AlGaN clad film into a stripe shape (ridge shape), an opening is formed using an AlGaN lift-off layer. A silicon oxide film was formed. The following electrodes were formed on the p-type GaN self-aligned contact layer. On the p-type GaN layer and the silicon oxide film, a palladium layer (for example, a thickness of 50 nm) was grown by, for example, a vapor deposition method. After the palladium layer was processed into a stripe formation by lift-off to form a palladium electrode, a titanium layer (for example, 5 nm in thickness) and a gold layer (for example, 30 nm in thickness) were formed by vapor deposition to form a pad electrode. In place of the palladium electrode, a good electrode could be formed using gold, tungsten, platinum or the like.

The effects of surface oxide film and oxygen concentration on contact resistance were investigated. In the manufacturing method not using the AlGaN lift-off layer, the contact resistance was about 10 ⁻² Ω · cm. In this method, the p-type GaN contact layer is oxidized by a photolithography method or a cleaning process. The surface oxide film thickness was about 6 nm, for example. It is considered that a good ohmic electrode could not be formed due to the formation of this natural oxide film. In order to overcome the technical problem caused by the natural oxide film, the cleaning process has been devised, but a desired result could not be obtained. The technical problem has been solved by the method of the present embodiment. When the p-type GaN contact layer and the AlGaN lift-off layer are formed by a series of growths, the p-type GaN contact layer is not oxidized, and a very good ohmic electrode can be formed. The contact resistance in this case was less than 10 ⁻³ Ω · cm, and was reduced to a value on the order of 10 ⁻⁴ Ω · cm.

(Example 2)
On the LD structure grown on the n-type GaN substrate, AlGaN having a thickness of 200 nm was grown at a low temperature of 400 degrees Celsius to form an AlGaN lift-off layer. On the AlGaN lift-off layer, SiO ₂ having a thickness of 200 nm was deposited by plasma CVD. Thereafter, a stripe resist mask having a width of 2 micrometers was formed by photolithography. Next, SiO ₂ was removed by dry etching (etchant: CF ₄ gas) by reactive ion etching (RIE) to produce an insulating film mask. After removing the resist by organic cleaning, the GaN structure is formed by etching the AlGaN lift-off layer and the GaN-based epitaxial layer immediately below this by dry etching (etchant: Cl ₂ / N ₂ mixed gas) using an insulating film mask. Processing was done for. Furthermore, SiO ₂ having a thickness of 200 nm was deposited by electron beam evaporation. The AlGaN lift-off layer was selectively lifted off with respect to the GaN-based epitaxial layer directly below by an alkaline wet etchant (for example, positive developer: tetramethylammonium, etc.) to form an opening above the ridge. After forming an opening on the ridge, a p-side ohmic electrode was deposited on the ridge.

According to the experiments by the inventors, the range of the Al composition in the Al _X Ga _1-X N lift _- off layer may be 0 <X ≦ 1, and preferably 0.5 ≦ X ≦ 1. In this composition range, wet etching of AlGaN is further facilitated. The growth temperature T of the AlGaN lift-off layer may be in the range of, for example, greater than 200 degrees Celsius and less than 600 degrees Celsius, and preferably in the range of greater than 300 degrees Celsius and less than 500 degrees Celsius. In this film forming temperature range, AlGaN becomes polycrystalline that facilitates wet etching. The film thickness D of the AlGaN lift-off layer may be 0 <D <1000 nm, and preferably 50 nm ≦ D in order to facilitate wet etching. In order to obtain the accuracy of dry etching, the thickness D ≦ 400 nm is preferable.

In the present embodiment, a laser diode structure of a group III nitride semiconductor is processed. In gallium nitride laser diodes, the refractive index guided type (ridge type) is the mainstream. However, the desired reproducibility could not be obtained with the conventional processing methods. When this embodiment is applied to the manufacture of a laser diode, a simple ridge structure can be realized. According to experiments by the inventors, it has been found that AlGaN that can be removed by wet etching is effective as a mask material when an epitaxial substrate for a GaN-based laser diode is processed into a ridge type. The ridge processing method, after forming the AlGaN liftoff layer at a low temperature epitaxial substrate for the GaN-based laser diode, is deposited as a SiO ₂ film, a SiO ₂ film patterning for laser stripe by using a resist mask went. Using this SiO ₂ mask, AlGaN / GaN was removed by dry etching. Thereafter, an insulating film for passivation was formed on the entire surface of the substrate product. The AlGaN lift-off layer was lifted off by wet etching, and the ridge structure was opened at the top of the laser diode structure.

  When using the zirconium oxide used in the prior art, after the formation of the Zr / GaN interface, ZrO at this interface could not be easily removed, and a processing residue was generated. In this embodiment, no processing residue is generated. A self-aligned structure can be easily fabricated in a semiconductor device.

  Thus, the processing of the group III nitride semiconductor is facilitated. In manufacturing a ridge structure laser diode manufactured as an example, there are fewer processing residues than in the prior art. Therefore, the reliability of the semiconductor device is high, and excellent reproducibility is exhibited in the formation of the ridge shape and the contact resistance. The laser diode has a low threshold current.

  In this embodiment, not only the epitaxial region grown on the c-plane GaN substrate but also semipolarity such as (10-1-1) plane, (10-1-3) plane, (11-22) plane, etc. It is also applicable to epitaxial regions grown on non-polar planes such as planes and m-planes and a-planes. The present embodiment provides a method for processing a group III nitride semiconductor. In the above example, the epitaxial multilayer structure for the laser diode was processed into a ridge shape. The present invention can be applied not only to laser diodes but also to light emitting devices such as light emitting diodes, and also to electronic devices such as transistors, Schottky diodes, and pn junction diodes.

The main surface 27b of the group III nitride semiconductor layer 27a may include a semipolar surface. The semipolar surface can be exposed to the self-alignment in the opening 39c of the insulating film 39. The main surface 27b of the group III nitride semiconductor layer 27a can include any of nonpolar surfaces. A nonpolar surface can be exposed in the opening 39c of the insulating film 39 in a self-aligned manner. The main surface 27b of the group III nitride semiconductor layer 27a is, for example, any one of {20-21} plane, {10-11} plane, {20-2-1} plane, and {10-1-1} plane. Can be a face.

  The main surface 27b of the group III nitride semiconductor layer 27a is 10 degrees or more and 80 degrees or less and 100 degrees or more and 170 degrees or less with respect to a plane orthogonal to the reference axis extending in the c-axis direction of the group III nitride semiconductor layer 27a. Can be tilted at a range of tilt angles. If the angle is less than 10 degrees or more than 170 degrees, the property due to the polar surface becomes stronger on the exposed surface. In addition, when the angle exceeds 80 degrees or less than 100 degrees, the property due to the asexual surface becomes stronger on the exposed surface 29d.

  The main surface 27b of the group III nitride semiconductor layer 27a has an inclination angle in the range of more than 80 degrees or less than 100 degrees with respect to a plane orthogonal to the reference axis extending in the c-axis direction of the group III nitride semiconductor layer 27a. Can be inclined. In the angle range of 80 degrees to less than 100 degrees, a property close to a nonpolar surface can be used in the exposed surface 29d.

  The inclination angle of main surface 27b of group III nitride semiconductor layers 27 and 27a is preferably inclined at an inclination angle in the range of 63 degrees to 80 degrees and 100 degrees to 117 degrees. When the inclination angle is 63 degrees or more, it is easy to grow a crystal with high flatness. When the tilt angle is 80 degrees or less, the doping efficiency using the tilt can be improved. When the inclination angle is 100 degrees or more, the right-left symmetry of the ridge shape is good. When the tilt angle is 117 degrees or less, it is easy to grow a good active layer.

  The main surface 27b of the group III nitride semiconductor layer 27a may include a polar surface. The polar surface can be exposed to self-alignment in the opening 39c of the insulating film 39.

  The main surface 27b of the group III nitride semiconductor layer 27a has an angle range of less than 10 degrees or more than 170 degrees with respect to a plane orthogonal to the reference axis extending in the c-axis direction of the group III nitride semiconductor layers 27, 27a. It can be inclined at an inclination angle. At angles less than 10 degrees and greater than 170 degrees, properties close to the polar plane can be utilized.

  FIG. 8 is a drawing showing an example of a group III nitride semiconductor device in the example. In the laser diode LD having a self-aligned contact, a group III nitride semiconductor (epitaxial semiconductor) region 63 is formed on a conductive group III nitride substrate, for example, on the main surface 61 a of the GaN support base 61. The epitaxial semiconductor region 63 has an LD structure. The epitaxial semiconductor region 63 includes an n-type AlGaN cladding layer 65, an n-type GaN light guide layer 67a, an undoped InGaN light guide layer 67b, an active layer 69, an undoped InGaN light guide layer 71b, a p-type GaN light guide layer 71a, and a p-type AlGaN. A cladding layer 73 and a p-type GaN contact layer 75 are included. These semiconductor layers (LD structure) are arranged in the direction of the normal axis Bx of the main surface 61 a of the support base 61. The ridge structure 77 includes a p-type GaN light guide layer 71a, a p-type AlGaN cladding layer 73, and a p-type GaN contact layer 75. The anode electrode 79 a is bonded to the p-type GaN contact layer 75, and the cathode electrode 79 b is bonded to the back surface 61 b of the GaN support base 61. In order to confine the current in the laser diode LD that provides laser oscillation with a wavelength of 500 nm or more, the ridge structure shown in FIG. 8 is formed. The surface 77 c of the ridge structure 77 is covered with an insulating film 81 except for the top surface 77 d of the ridge structure 77. In order to form the ridge structure 77, a striped mask is formed on the epitaxial substrate by photolithography. After this mask was formed, at least a portion of the p-type contact layer, p-type cladding layer, and light guide layer of the epitaxial substrate was removed by dry etching to form a ridge structure 77. The ridge structure 77 includes a ridge portion 77a and first and second side portions 77b. The ridge portion 77a extends in the direction of a predetermined axis, and the first and second side portions 77b are adjacent to the ridge portion 77a on the first and second sides of the ridge portion 77a, respectively, in the direction of the predetermined axis Ax. Extend to. The ridge portion 77a is located between the first and second side portions 77b. The ridge portion 77a includes a top surface 77d and side surfaces 77e and 77f. Each of the side surfaces 77e and 77f is inclined with respect to the top surface 77d and is inclined with respect to the main surface of the side portion 77b. After the formation of the ridge portion, a confinement portion including the insulating film 81 is formed on the ridge portion 77a and the surface 77c of the first and second side portions 77b. Although the confinement part is formed so as to embed the ridge part, it is not limited to this form. As a material of the insulating film 81, for example, silicon oxide is used. In this embodiment, thereafter, the mask is removed by a lift-off method, and an opening is formed in the insulating film 81. Thereby, an opening for the electrode is formed in a self-aligned manner with respect to the ridge portion 77a. A top surface 77d is exposed in the opening. The formation of the opening is not limited to the lift-off method. Thereafter, a p-type electrode and an n-type electrode were formed by vapor deposition.

  When the ridge structure 77 was formed, laser diodes having various thicknesses were produced with respect to the upper guide layer 71a. For example, in a laser diode in which the thickness of the side portion 77c of the ridge structure 77 is adjusted so as to leave the upper guide layer 71a thicker than half of its total thickness (for example, the thickness of the side portion is 400 nm), the ridge structure 77 is The oscillation threshold current was hardly reduced as compared with the laser diode not having it, and was 800 mA. On the other hand, in the laser diode in which the upper guide layer 71a is etched to be less than half of the total thickness, the oscillation threshold current is remarkably reduced to 200 mA. Considering the relationship between the remaining thickness of the upper guide layer 71a and the oscillation threshold, the thickness DC of the upper guide layer is preferably 50 nm or more and 250 nm or less, and more preferably 50 nm or more and 150 nm or less.

  Although an insulator such as silicon oxide is used as the material of the insulating film 81, at least one of silicon nitride and aluminum nitride can be used instead. These materials can also provide the same optical confinement effect as silicon oxide. The insulating film 81 can contain a silicon-based inorganic compound. The insulating film 81 has a refractive index smaller than that of the light guide layer 71a.

  In this laser diode LD, the group III nitride semiconductor region 63 includes a first group III nitride semiconductor portion 76 and a second group III nitride semiconductor portion (ridge structure) 77. The first group III nitride semiconductor portion 76 includes a first portion 63a and a second portion 63b. Second group III nitride semiconductor portion 77 has a convex shape, is located on second portion 63b, and has side surface 77c and upper surface 77d.

  The insulating layer 81 is provided on the second portion 63 b of the first group III nitride semiconductor portion 76 and is in contact with the side surface 77 c of the second group III nitride semiconductor portion 77. The electrode 79 a is provided on the contact layer (group III nitride semiconductor layer) 75 and the insulating film 81. The electrode 79 a is in contact with the entire upper surface 77 d of the second group III nitride semiconductor portion 77 and is provided on the surface 81 a of the insulating film 81. The insulating film 81 covers the entire side surface 77 c of the second group III nitride semiconductor portion 77.

According to this structure, a self-aligned contact can be provided to the laser diode LD. The opening of the self-aligned contact is defined by an insulating film 81 made of a silicon-based inorganic compound that can provide reliability. The electrode 79a may include a palladium electrode, a gold electrode, a tungsten electrode, and / or a platinum electrode. In this self-aligned contact, the contact resistance between the upper surface 77d of the convex group III nitride semiconductor portion (ridge structure) 77 and the electrode 79a can be less than 1 × 10 ⁻³ Ω · cm.

  In the laser diode LD, the electrode 79b is provided on the back surface 61b of the GaN support base 61 on which the group III nitride semiconductor region 63 is mounted. According to this laser diode LD, a vertical semiconductor device is provided. In addition, the self-aligned contact to the upper surface 77d of the ridge structure 77 can be provided to the laser diode LD by using the convex ridge structure 77 and the insulating film 81 smaller than the refractive index of the group III nitride semiconductor region. Therefore, the laser diode LD has a good current confinement property and light confinement property.

  In order to provide the main surface 27b of the group III nitride semiconductor layers 27 and 27a with a polar surface, a semipolar surface, or a nonpolar surface, the main surface 61a of the GaN support base 61 has a polar surface, a semipolar surface, and a nonpolar surface, respectively. Has a sexual aspect.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

DESCRIPTION OF SYMBOLS 10a ... Growth furnace, 10b ... Growth furnace, 10c ... Processing apparatus, 10d ... Etching apparatus, 10e ... Processing apparatus, 11 ... Substrate, 13 ... Semiconductor lamination | stacking, 15 ... 1st conductivity type clad layer, 17 ... 1st light guide Layer, 19 ... active layer, 21 ... carrier block layer, 23 ... second light guide layer, 25, 25a ... p-type cladding layer, 27, 27a ... group III nitride semiconductor layer, 27b ... group III nitride semiconductor layer Upper surface, 29, 29a, 29b ... epitaxial region, 29e ... epitaxial region side surface, 29f ... epitaxial region side surface, EP ... epitaxial substrate, 31, 31a ... III nitride lift-off layer, SP ... substrate product, 33a, 33b, 33c ... Group III nitride region, 35 ... Mask film, 35a ... Mask, 37 ... Resist mask, 39, 39a, 39b ... Insulating film, 39c ... Opening of insulating film , 41 ... Electrode, 61 ... GaN support base, 63 ... Epitaxial semiconductor region, 65 ... n-type AlGaN cladding layer, 67a ... n-type GaN light guide layer, 67b ... undoped InGaN light guide layer, 69 ... active layer, 71b ... undoped InGaN light guide layer, 71a ... p-type GaN light guide layer, 73 ... p-type AlGaN cladding layer, 75 ... p-type GaN contact layer, 77 ... ridge structure, 79a ... anode electrode, 79b ... cathode electrode, 81 ... confinement part.

Claims (20)

A method of fabricating a group III nitride semiconductor light emitting device,
Epitaxially growing a group III nitride semiconductor layer on the semiconductor stack including the active layer;
Growing a group III nitride lift-off layer on the group III nitride semiconductor layer to form a substrate product;
Forming a mask for forming a pattern for a ridge structure on the III-nitride lift-off layer on the III-nitride lift-off layer;
The pattern of the mask is transferred to the group III nitride lift-off layer and the group III nitride semiconductor layer to form a patterned group III nitride lift-off layer and a patterned group III nitride semiconductor region. Process,
Growing an insulating film on the mask, the patterned III-nitride lift-off layer, and the patterned III-nitride semiconductor region;
The patterned group III nitride lift-off layer is selectively removed from the insulating film using an etchant to form an insulating film patterned to have an opening by a lift-off method and the pattern. Exposing the formed group III nitride semiconductor region to the opening ;
With
The refractive index of the insulating film is smaller than the refractive index of the group III nitride semiconductor layer,
The group III nitride lift-off layer contains aluminum as a group III constituent element,
The growth temperature of the group III nitride lift-off layer is lower than the growth temperature of the group III nitride semiconductor layer, and the etching rate of the group III nitride lift-off layer is higher than the etching rate of the insulating film in etching with the etchant. A method characterized by that.   The method of claim 1, wherein the III-nitride lift-off layer comprises at least one of AlN, AlGaN, AlInN, and InAlGaN. The group III nitride lift-off layer includes In _X Al _Y Ga _1- XYN (0 ≦ X <1, 0 <Y ≦ 1, 0 <X + Y ≦ 1),
3. The method according to claim 1, wherein an aluminum composition Y of the group III nitride lift-off layer is 0.5 or more and 1.0 or less.   4. The method according to claim 1, wherein in the step of growing a group III nitride lift-off layer, the group III nitride lift-off layer includes a non-single crystal group III nitride. 5. Way.   In the step of growing a group III nitride lift-off layer, the group III nitride lift-off layer includes at least one of polycrystalline group III nitride and amorphous group III nitride. Item 5. The method according to any one of Items 4.   6. The method according to claim 1, wherein a growth temperature of the group III nitride lift-off layer is larger than 200 degrees Celsius and smaller than 600 degrees Celsius.   7. The method according to claim 1, wherein a growth temperature of the group III nitride lift-off layer is greater than 300 degrees Celsius and less than 500 degrees Celsius.   The method according to claim 1, wherein the insulating film contains a silicon-based inorganic compound.   The method according to claim 1, wherein the insulating film includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.   The method according to any one of claims 1 to 9, wherein the thickness of the group III nitride lift-off layer is 1000 nm or less.   11. The method according to claim 1, wherein the thickness of the group III nitride lift-off layer is greater than 50 nm and equal to or less than 400 nm. The growth of the group III nitride semiconductor layer is performed using a growth furnace,
The growth of the III nitride lift-off layer is performed using the growth furnace,
The method includes the step of removing the substrate product from the growth furnace after growing the group III nitride lift-off layer on the group III nitride semiconductor layer;
Forming an electrode on an exposed surface of the patterned group III nitride semiconductor region after application of the lift-off method ;
The method according to claim 1, further comprising: The method of claim 12, wherein a contact resistance between the exposed surface of the patterned group III nitride semiconductor region and the electrode is less than 1 × 10 ⁻³ Ω · cm.   The main surface of the said group III nitride semiconductor layer contains either a semipolar surface or a nonpolar surface, The method as described in any one of Claims 1-13 characterized by the above-mentioned.   The main surface of the group III nitride semiconductor layer has a range of 10 degrees or more and 80 degrees or less and 100 degrees or more and 170 degrees or less with respect to a plane orthogonal to a reference axis extending in the c-axis direction of the group III nitride semiconductor layer. The method according to claim 1, wherein the method is inclined at an inclination angle of 1 to 14. 16. The main surface of the group III nitride semiconductor layer is inclined at an inclination angle in a range of 63 degrees to 80 degrees and 100 degrees to 117 degrees. The method described in any one of the paragraphs.   The method according to claim 1, wherein a main surface of the group III nitride semiconductor layer includes a polar surface. A method of forming an electrode for a group III nitride semiconductor device comprising:
Epitaxially growing a group III nitride semiconductor layer on the substrate;
Growing a group III nitride lift-off layer on the group III nitride semiconductor layer to form a substrate product;
Forming a mask on the III-nitride lift-off layer for forming a pattern on the III-nitride lift-off layer;
Transferring the pattern of the mask to the group III nitride lift-off layer and the nitride semiconductor layer to form a patterned group III nitride lift-off layer and a patterned group III nitride semiconductor region; ,
Growing an insulating film on the mask, the patterned III-nitride lift-off layer, and the patterned III-nitride semiconductor region;
The patterned group III nitride lift-off layer is selectively removed using an etchant with respect to the insulating film by a lift-off method to form an insulating film patterned to have an opening and to form the pattern Exposing the exposed surface of the group III nitride semiconductor region formed in the opening;
Forming an electrode on the exposed surface of the patterned group III nitride semiconductor region after application of the lift-off method ;
With
The group III nitride lift-off layer contains aluminum as a group III constituent element,
The growth temperature of the group III nitride lift-off layer is lower than the growth temperature of the group III nitride semiconductor layer, and the etching rate of the group III nitride lift-off layer is higher than the etching rate of the insulating film in etching with the etchant. A method characterized by that. The insulating film includes a silicon-based inorganic compound,
19. The method of claim 18 , wherein in the step of growing a group III nitride lift-off layer, the group III nitride lift-off layer comprises an amorphous group III nitride. The growth of the group III nitride semiconductor layer is performed using a growth furnace,
The growth of the III nitride lift-off layer is performed using the growth furnace,
The method, after the growth of the III nitride semiconductor layer and the III nitride liftoff layer, claim 18 or claim further comprising a growth reactor the step of taking out the substrate product, it is characterized by The method described in 19 .

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