JP5217412B2 - Power supply circuit, display driver, electro-optical device, and electronic device - Google Patents

Description

  The present invention relates to a power supply circuit, a display driver, an electro-optical device, an electronic apparatus, and the like.

  Portable electronic devices are required to further reduce power consumption. A liquid crystal display device is often used as a display device mounted on such an electronic device. In order to drive the liquid crystal display device, a plurality of power sources such as a high voltage and a negative voltage are required. In this case, it is desirable from the viewpoint of cost that the liquid crystal driving device that drives the liquid crystal display device incorporates a power supply circuit that generates a plurality of power supplies.

Such a power supply circuit includes a booster circuit. As this booster circuit, for example, a charge pump circuit that generates a boosted voltage by a charge pump operation as described in Patent Document 1, for example, is often employed. The charge pump circuit connects one end of a capacitor that stores electric charge to various voltages by a switch element (for example, a metal oxide semiconductor (MOS) transistor), thereby converting the electric charge stored in the capacitor. The corresponding voltage is boosted. By using such a charge pump circuit, consumption can be reduced.
JP-A-9-312095

  From the viewpoint of the power efficiency of the booster circuit, it is desirable to make the output load of the booster circuit as small as possible. Therefore, for example, as in Patent Document 1, the output of the booster circuit is directly connected to the circuit to which the output voltage of the booster circuit is supplied.

  A regulator is used to adjust the output potential of the booster circuit. At this time, it is desirable to operate the regulator with the lowest possible operating voltage for the purpose of reducing power consumption. Therefore, the voltage boosted by the booster circuit is not adjusted by the regulator, but the adjusted voltage is input to the booster circuit after the voltage is adjusted by the regulator.

  However, when the potential is adjusted by the regulator, the maximum value of the output voltage of the regulator is, for example, a low potential voltage from the high-potential side power supply voltage of the regulator by at least the threshold voltage ΔVthp of the transistor. Similarly, the minimum value of the output voltage of the regulator also becomes a high potential voltage by at least the threshold voltage ΔVthn of the transistor from the power supply voltage on the low potential side of the regulator. That is, the output voltage of the regulator is in a narrower range than the voltage between the power supply voltage on the low potential side and the power supply voltage on the high potential side. When the output voltage of such a regulator is boosted by S (S is a number greater than 1) times, only a voltage having a potential lower by, for example, S × ΔVthn can be obtained than the voltage obtained by boosting the power supply voltage on the high potential side of the regulator. This means that the power supply voltage range of the circuit to which the voltage obtained by boosting the output voltage of the regulator is supplied becomes narrow, and the power supply margin is reduced.

  When the voltage of the booster circuit that boosts the voltage adjusted by the regulator exceeds the target voltage, the system ground power supply is discharged to reduce the excess voltage. For example, when the voltage of 3.3 V is boosted twice, the electric charge is reduced so that the potential is lowered by 0.6 V (= 3.3 × 2−6) so that the absolute maximum rating of the integrated circuit device is 6 V or less. Is discharged. Therefore, if the charge / discharge amount for adjusting the excess voltage can be reduced, the power consumption of the power supply circuit can be reduced.

  Further, the output load of the power supply circuit that supplies power to the liquid crystal display device differs depending on the display image and the display mode of the liquid crystal display device, and the boosting efficiency of the power supply circuit may deteriorate when the output load is small.

  According to some aspects of the present invention, it is possible to provide a power supply circuit, a display driver, an electro-optical device, and an electronic apparatus that can supply a boosted voltage with low power consumption without reducing boosting efficiency.

  According to another aspect of the present invention, it is possible to provide a power supply circuit, a display driver, an electro-optical device, and an electronic apparatus that can sufficiently secure a power supply margin.

In order to solve the above problems, the present invention
A power supply circuit for outputting a boosted voltage,
A booster circuit that generates a boosted voltage obtained by boosting the second voltage with reference to the first voltage;
A limiter circuit for limiting the potential of the boosted voltage,
The limiter circuit is
The present invention relates to a power supply circuit that discharges charges to a power supply line to which the second voltage is supplied or charges charges from the power supply line so that the boosted voltage becomes a given target voltage.

  According to the present invention, even when the boosted voltage exceeds the target voltage, the electric charge is discharged to the power supply line to which the boosting source power is supplied. The power consumption can be significantly reduced compared with the case where electric charges are discharged to the wire.

In the power supply circuit according to the present invention,
Including a regulator that regulates the potential of a given input voltage;
When the driving voltage of the electro-optical device is generated based on the boosted voltage,
When the electro-optical device is driven in a high load display mode, a voltage obtained by limiting the potential of the boosted voltage with the limiter circuit is output as the boosted voltage,
When the electro-optical device is driven in the low load display mode, a voltage obtained by boosting the output voltage of the regulator by the booster circuit can be output as it is without being limited by the limiter circuit.

In the power supply circuit according to the present invention,
Including display mode setting register,
When the high load display mode is designated by the control data set in the display mode setting register, a voltage obtained by limiting the potential of the boosted voltage by the limiter circuit is output as the boosted voltage,
When the low load display mode is designated by the control data set in the display mode setting register, a voltage obtained by boosting the output voltage of the regulator by the boosting circuit can be output as the boosted voltage.

  According to any one of the above-described inventions, when the output load of the power supply circuit is large, a boosted voltage can be generated with a high boosting capability. The boosted voltage can be supplied stably without significantly reducing the efficiency.

In the power supply circuit according to the present invention,
The booster circuit is
A first charge pump circuit for generating the boosted voltage by boosting the output voltage of the regulator with reference to the first voltage by a charge pump operation using a first flying capacitor;
For generating the boosted voltage by boosting the second voltage with reference to the first voltage by a charge pump operation using a second flying capacitor having a larger capacitance value than the first flying capacitor. A second charge pump circuit;
When the electro-optical device is driven in the high load display mode, the boosted voltage generated by the first and second charge pump circuits or the boosted voltage generated by the second charge pump circuit is output. ,
When the electro-optical device is driven in the low load display mode, the boosted voltage generated by the first charge pump circuit can be output.

  According to the present invention, the boosting capability of the power supply circuit can be changed with a simple configuration and control.

In the power supply circuit according to the present invention,
When the electro-optical device is driven in the high load display mode, control is performed to change the boosting capability of the booster circuit according to the output load of the power supply circuit,
When the electro-optical device is driven in the low-load display mode, control for changing the boosting capability of the booster circuit according to the output load of the power supply circuit can be omitted.

  According to the present invention, since the boosting capability can be changed in accordance with the display image that is a factor that changes the output load of the power supply circuit in the high load display mode, it is possible to reliably suppress a decrease in boosting efficiency.

In the power supply circuit according to the present invention,
When the high load display mode is specified,
When it is determined that the boost capability is high with respect to the output load of the power supply circuit, the boost capability is changed so that the boost capability becomes lower,
When it is determined that the boosting capability is low with respect to the output load, the boosting capability can be changed so that the boosting capability becomes higher.

  According to the present invention, since the boosting capability can be maintained at an appropriate level according to the output load, it is possible to stabilize the voltage obtained by the boosting capability and prevent the boosting efficiency from decreasing with respect to the output load. become.

In the power supply circuit according to the present invention,
When the high load display mode is specified,
The booster circuit is
The boosting capability can be changed based on the output load of the power supply circuit and limiter operation information indicating whether or not the limiter circuit has limited the potential of the boosted voltage.

In the power supply circuit according to the present invention,
When the high load display mode is specified,
The booster circuit is
The boosting capability can be changed according to a comparison result between a threshold value updated based on the limiter information and an output load of the power supply circuit.

In the power supply circuit according to the present invention,
The threshold is
It may be updated based on a comparison result between a given threshold voltage and the boosted voltage.

In the power supply circuit according to the present invention,
A comparator for comparing the given threshold voltage with the boost voltage;
A counter that counts pulses that are output results of the comparator,
The threshold is
It may be updated based on the count number of the counter.

  According to any one of the above-described inventions, since the boosting capability can be changed based on the operation information of the limiter circuit, the power supply circuit capable of low power consumption operation with the optimum boosting capability for various output loads Can provide.

In the power supply circuit according to the present invention,
When a driving voltage corresponding to gradation data of each source line of the plurality of source lines of the electro-optical device is generated based on the boosted voltage,
The output load is
The evaluation may be based on the sum of gradation data for one scanning line of the plurality of source lines.

  According to the present invention, the output load can be evaluated with a simple configuration.

The present invention also provides
A display driver for driving an electro-optical device,
Any one of the power supply circuits described above;
A drive unit for driving the electro-optical device,
The present invention relates to a display driver that generates a driving voltage of the driving unit based on the boosted voltage.

In the display driver according to the present invention,
The drive unit is
A plurality of source lines of the electro-optical device can be driven by a driving voltage corresponding to the gradation data generated using the boosted voltage.

  According to any one of the above-described inventions, it is possible to provide a display driver to which a power supply circuit capable of supplying a boosted voltage with low power consumption without reducing the boosting efficiency.

The present invention also provides
Multiple gate lines,
Multiple source lines,
A gate driver that scans the plurality of gate lines;
A source driver for driving the plurality of source lines;
Including any of the power supply circuits described above,
At least one of the scanning voltage of the gate driver and the driving voltage of the source driver is related to the electro-optical device generated based on the boosted voltage.

The present invention also provides
Multiple gate lines,
Multiple source lines,
A gate driver that scans the plurality of gate lines;
The present invention relates to an electro-optical device including the display driver described above that drives the plurality of source lines.

  According to any one of the above inventions, it is possible to provide an electro-optical device to which a power supply circuit capable of supplying a boosted voltage with low power consumption without reducing the boosting efficiency is applied.

The present invention also provides
The present invention relates to an electronic device including any one of the power supply circuits described above.

The present invention also provides
The present invention relates to an electronic device including the display driver described above.

The present invention also provides
The present invention relates to an electronic apparatus including the electro-optical device described above.

  According to any one of the above-described inventions, it is possible to provide an electronic device to which a power supply circuit that can supply a boosted voltage with low power consumption without reducing the boosting efficiency is applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Display Device FIG. 1 shows an example of a block diagram of a liquid crystal display device of this embodiment.

  The liquid crystal display device 10 (liquid crystal device; electro-optical device in a broad sense) includes a display panel 12 (a liquid crystal panel in a narrow sense, an LCD (Liquid Crystal Display) panel, an electro-optical panel in a broad sense), and a source driver 20 (in a broad sense). Data line driving circuit), gate driver 30 (scanning line driving circuit in a broad sense), display controller 40, and power supply circuit 50. It is not necessary to include all these circuit blocks in the liquid crystal display device 10, and a part of the circuit blocks may be omitted. The electro-optical device can include a device using a light emitting element such as an organic EL (Electro Luminescence) or an inorganic EL element.

  Here, the display panel 12 (electro-optical device) includes a plurality of gate lines (scanning lines in a broad sense), a plurality of source lines (data lines in a broad sense), and pixel electrodes specified by the gate lines and the source lines. Including. In this case, an active matrix liquid crystal display device can be configured by connecting a thin film transistor TFT (Thin Film Transistor, switching element in a broad sense) to a source line and connecting a pixel electrode to the TFT.

More specifically, the display panel 12 is an amorphous silicon liquid crystal panel in which an amorphous silicon thin film is formed on an active matrix substrate (for example, a glass substrate). In the active matrix substrate, a plurality of gate lines G _{1 to} G _M (M is a natural number of 2 or more) arranged in the Y direction and extending in the X direction, and a plurality of source lines arranged in the X direction and extending in the Y direction, respectively. S _{1 to} S _N (N is a natural number of 2 or more) are arranged. The thin film transistor TFT _KL (switching in a broad sense) is provided at a position corresponding to the intersection of the gate line G _K (1 ≦ K ≦ M, K is a natural number) and the source line S _L (1 ≦ L ≦ N, L is a natural number). Element).

The gate electrode of the thin film transistor TFT _KL is connected with the gate line _{G K,} a source electrode of the _{thin film transistor TFT KL} is connected with the source line _{S L,} the drain electrode of the _{thin film transistor TFT KL} is connected with a pixel electrode _{PE KL.} Between the pixel electrode PE _KL and the counter electrode CE (common electrode, common electrode) facing the pixel electrode PE _KL with a liquid crystal (electro-optical material in a broad sense) interposed therebetween, a liquid crystal capacitance CL _KL which is an element capacitance (Liquid crystal element) and auxiliary capacitor CS _KL are formed. Then, liquid crystal is formed between the active matrix substrate on which the TFT _KL , the pixel electrode PE _{KL, and the} like are formed and the counter substrate on which the counter electrode CE is formed, and the pixel electrode PE _KL , the counter electrode CE, The transmittance of the pixel is changed in accordance with the applied voltage between. The element capacitance can include a liquid crystal capacitance formed in a liquid crystal element and a capacitance formed in an EL element such as an inorganic EL element.

  Note that the voltage level (high potential side voltage VCOMH, low potential side voltage VCOML) of the counter electrode voltage VCOM applied to the counter electrode CE is generated by a counter electrode voltage generation circuit included in the power supply circuit 50. For example, the counter electrode CE is formed on one surface on the counter substrate.

The source driver 20 drives the source lines S _{1 to} S _N of the display panel 12 based on the gradation data. The gate driver 30 scans the gate lines _G 1 ~G _M of the display panel 12 (sequential drive).

  The display controller 40 controls the source driver 20, the gate driver 30, and the power supply circuit 50 in accordance with the contents set by a host such as a central processing unit (CPU) (not shown). More specifically, the display controller 40 sets, for example, an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the source driver 20 and the gate driver 30, and supplies to the power supply circuit 50. Thus, the polarity inversion timing of the voltage level of the common electrode voltage VCOM applied to the common electrode CE is controlled.

  The power supply circuit 50 boosts the system power supply voltage supplied from the outside, and various voltage levels (grayscale voltages) necessary for driving the display panel 12 and the voltage level of the common electrode voltage VCOM of the common electrode CE. Is generated. The power supply circuit 50 in the present embodiment can generate a boosted voltage obtained by boosting the system power supply voltage VDD. The power supply circuit 50 can change the boosting capability when generating the boosted voltage. Here, the boosting ability can be said to be an ability to change the output voltage with respect to the change of the output load current.

  When the source driver 20 and the gate driver 30 are drive units for driving the display panel 12, the drive voltage of the drive unit can be generated based on the voltage boosted by the power supply circuit 50.

  In the liquid crystal display device 10 having such a configuration, the source driver 20, the gate driver 30, and the power supply circuit 50 cooperate with each other based on the gradation data supplied from the outside under the control of the display controller 40. To drive.

  In FIG. 1, the liquid crystal display device 10 includes the display controller 40, but the display controller 40 may be provided outside the liquid crystal display device 10. Alternatively, the host may be included in the liquid crystal display device 10 together with the display controller 40. Further, part or all of the source driver 20, the gate driver 30, the display controller 40, and the power supply circuit 50 may be formed on the display panel 12.

  In FIG. 1, the source driver 20, the gate driver 30, and the power supply circuit 50 may be integrated to constitute the display driver 60 as a semiconductor device (integrated circuit, IC).

  FIG. 2 is a block diagram showing another configuration example of the liquid crystal display device according to this embodiment.

  In FIG. 2, a display driver 60 including a source driver 20, a gate driver 30, and a power supply circuit 50 is formed on the display panel 12 (panel substrate). As described above, the display panel 12 includes a plurality of gate lines, a plurality of source lines, a plurality of pixels (pixel electrodes) connected to the gate lines of the plurality of gate lines and the source lines of the plurality of source lines. A source driver that drives a plurality of source lines and a gate driver that scans a plurality of gate lines can be included. A plurality of pixels are formed in the pixel formation region 44 of the display panel 12. Each pixel can include a TFT having a source connected to the source and a gate line connected to the gate, and a pixel electrode connected to the drain of the TFT.

  In FIG. 2, at least one of the gate driver 30 and the power supply circuit 50 on the display panel 12 may be omitted.

  In FIG. 1 or FIG. 2, the display driver 60 may incorporate the display controller 40. 1 or 2, the display driver 60 may be a semiconductor device in which one of the source driver 20 and the gate driver 30 and the power supply circuit 50 are integrated.

1.1 Gate Driver FIG. 3 shows a configuration example of the gate driver 30 shown in FIG.

  The gate driver 30 includes a shift register 32, a level shifter 34, and an output buffer 36.

  The shift register 32 includes a plurality of flip-flops provided corresponding to the gate lines and sequentially connected. When the shift register 32 holds the enable input / output signal EIO in the flip-flop in synchronization with the clock signal CLK, the shift register 32 sequentially shifts the enable input / output signal EIO to the adjacent flip-flop in synchronization with the clock signal CLK. The enable input / output signal EIO input here is a vertical synchronization signal supplied from the display controller 40.

  The level shifter 34 shifts the voltage level from the shift register 32 to a voltage level corresponding to the liquid crystal element of the display panel 12 and the transistor capability of the TFT. Since this voltage level requires a high voltage level, a high breakdown voltage process different from other logic circuit units is used.

  The output buffer 36 buffers the scanning voltage shifted by the level shifter 34 and outputs it to the gate line to drive the gate line.

1.2 Source Driver FIG. 4 is a block diagram showing a configuration example of the source driver 20 shown in FIG.

  The source driver 20 includes a shift register 22, line latches 24 and 26, a DAC 28 (Digital-to-Analog Converter) (data voltage generation circuit in a broad sense), and a source line drive circuit 29.

  The shift register 22 includes a plurality of flip-flops provided corresponding to each source line and sequentially connected. When the shift register 22 holds the enable input / output signal EIO in synchronization with the clock signal CLK, the shift register 22 sequentially shifts the enable input / output signal EIO to the adjacent flip-flops in synchronization with the clock signal CLK.

  Gradation data (DIO) is input to the line latch 24 from the display controller 40 in units of 18 bits (6 bits (gradation data) × 3 (each RGB color)), for example. The line latch 24 latches the gradation data (DIO) in synchronization with the enable input / output signal EIO sequentially shifted by each flip-flop of the shift register 22.

  The line latch 26 latches the grayscale data for one horizontal scan latched by the line latch 24 in synchronization with the horizontal synchronization signal LP supplied from the display controller 40.

The reference voltage generation circuit 27 generates 64 (= 2 ⁶ ) types of reference voltages. The 64 types of reference voltages generated by the reference voltage generation circuit 27 are supplied to the DAC 28.

  A DAC (data voltage generation circuit) 28 generates an analog data voltage to be supplied to each source line. Specifically, the DAC 28 selects one of the reference voltages from the reference voltage generation circuit 27 based on the digital gradation data from the line latch 26, and outputs an analog data voltage corresponding to the digital gradation data. Output.

  The source line drive circuit 29 buffers the data voltage from the DAC 28 and outputs it to the source line to drive the source line. Specifically, the source line driving circuit 29 includes a voltage follower connection operational amplifier OPC (impedance conversion circuit in a broad sense) provided for each source line, and each of these operational amplifiers OPC receives data from the DAC 28. The voltage is impedance-converted and output to each source line.

  In FIG. 4, the digital gradation data is converted from digital to analog and output to the source line via the source line driving circuit 29. However, the analog video signal is sampled and held. A configuration of outputting to the source line via the source line driving circuit 29 can also be adopted.

  FIG. 5 shows a configuration example of the reference voltage generation circuit 27, the DAC 28, and the source line driving circuit 29 in FIG. In FIG. 5, the gradation data is 6-bit data D0 to D5, and the inverted data of the data of each bit is indicated as XD0 to XD5. In FIG. 5, the same parts as those in FIG.

The reference voltage generation circuit 27 generates 64 types of reference voltages by resistance-dividing the voltages VDDH and VSSH at both ends. Here, the voltage VDDH can be the boosted voltage VOUT obtained by the power supply circuit 50. Each reference voltage corresponds to each gradation value represented by 6-bit gradation data. Each reference voltage is commonly supplied to the source lines S _{1 to} S _N.

  The DAC 28 includes a decoder provided for each source line, and each decoder outputs a reference voltage corresponding to the gradation data to the operational amplifier OPC.

1.3 Power Supply Circuit FIG. 6 shows a configuration example of the power supply circuit 50 shown in FIG.

  The power supply circuit 50 includes a booster circuit 52, a limiter circuit 53, a scanning voltage generation circuit 54, and a counter electrode voltage generation circuit 56. The power supply circuit 50 is supplied with a system ground power supply voltage VSS (first voltage) and a system power supply voltage VDD (second voltage).

  The booster circuit 52 is supplied with the system ground power supply voltage VSS and the system power supply voltage VDD. Then, the booster circuit 52 generates a power supply voltage VOUT (boost voltage) obtained by boosting the input voltage (for example, the system power supply voltage VDD), for example, twice in the positive direction with reference to the system ground power supply voltage VSS. That is, the booster circuit 52 boosts the voltage difference between the system ground power supply voltage VSS and the input voltage (system power supply voltage VDD) by a factor of two. Such a booster circuit 52 can be constituted by a charge pump circuit. The power supply voltage VOUT is supplied to the source driver 20, the scanning voltage generation circuit 54, and the counter electrode voltage generation circuit 56. The source driver 20 generates a gradation voltage corresponding to the gradation data based on the power supply voltage VOUT. The gate driver 30 can include a scanning voltage generation circuit 54. In this case, it can be said that the scanning voltage is generated based on the power supply voltage VOUT.

  The limiter circuit 53 is a power supply to which the input voltage or the system power supply voltage VDD (second voltage) is supplied so that the power supply voltage VOUT (boosted voltage) generated by the booster circuit 52 becomes a given target voltage. The line is discharged or charged from the power line. In the present embodiment, since the booster circuit 52 boosts the voltage in the positive direction with respect to the system ground power supply voltage VSS, positive charge is discharged to the power supply line to which the input voltage or the voltage VOUT is supplied (from the power supply line). Charge negative charge). As a result, the electric charge can be reused rather than discharging the electric power to the power supply line to which the system ground power supply voltage VSS (first voltage) is supplied, so that the power consumption can be reduced. Furthermore, in this embodiment, the booster circuit 52 can change the boosting capability.

  The scan voltage generation circuit 54 is supplied with the system ground power supply voltage VSS and the power supply voltage VOUT. The scan voltage generation circuit 54 generates a scan voltage. The scanning voltage is a voltage applied to the gate line driven by the gate driver 30. The high potential side voltage of this scanning voltage is VDDHG, and the low potential side voltage is VEE.

  The counter electrode voltage generation circuit 56 generates a counter electrode voltage VCOM. The common electrode voltage generation circuit 56 outputs the high potential side voltage VCOMH or the low potential side voltage VCOML as the common electrode voltage VCOM based on the polarity inversion signal POL. The polarity inversion signal POL is generated by the display controller 40 in accordance with the polarity inversion timing.

  FIG. 7 shows an example of the drive waveform of the display panel 12 shown in FIG.

  A gradation voltage DLV corresponding to the gradation value of the gradation data is applied to the source line. In FIG. 7, a gradation voltage DLV having an amplitude of 5 V is applied with respect to the system ground power supply voltage VSS (= 0 V).

  A low potential side voltage VEE (= −10 V) is applied to the gate line as a non-selection voltage when not selected, and a scanning voltage GLV of a high potential side voltage VDDHG (= 15 V) is applied as a selection voltage when selected.

  The counter electrode CE is applied with the counter electrode voltage VCOM of the high potential side voltage VCOMH (= 3 V) and the low potential side voltage VCOML (= −2 V). The polarity of the voltage level of the counter electrode voltage VCOM with respect to a given voltage is inverted in accordance with the polarity inversion timing. FIG. 7 shows the waveform of the counter electrode voltage VCOM during so-called scanning line inversion driving. In accordance with the polarity inversion timing, the polarity of the grayscale voltage DLV of the source line is also inverted with reference to a given voltage.

  By the way, the liquid crystal element has a property that it deteriorates when a DC voltage is applied for a long time. For this reason, a driving method is required in which the polarity of the voltage applied to the liquid crystal element is inverted every predetermined period. Such driving methods include frame inversion driving, scanning (gate) line inversion driving, data (source) line inversion driving, dot inversion driving, and the like.

  Among these, the frame inversion drive has a disadvantage that the image quality is not so good although the power consumption is low. Data line inversion driving and dot inversion driving have good image quality, but have the disadvantage that a high voltage is required to drive the display panel.

  In this embodiment, scanning line inversion driving is employed. In this scanning line inversion drive, the polarity of the voltage applied to the liquid crystal element is inverted every scanning period (every scanning line). For example, a positive voltage is applied to the liquid crystal element in the first scanning period (scanning line), a negative voltage is applied in the second scanning period, and a positive voltage is applied in the third scanning period. The On the other hand, in the next frame, a negative voltage is applied to the liquid crystal element in the first scanning period, a positive voltage is applied in the second scanning period, and a negative voltage is applied in the third scanning period. Voltage is applied.

  In this scan line inversion drive, the voltage level of the counter electrode voltage VCOM of the counter electrode CE is inverted every scan period.

  More specifically, as shown in FIG. 8, the voltage level of the common electrode voltage VCOM becomes the low potential side voltage VCOML in the positive period T1 (first period), and in the negative period T2 (second period). The high potential side voltage VCOMH is obtained. The polarity of the gradation voltage applied to the source line in accordance with this timing is also reversed. The low potential side voltage VCOML is a voltage level obtained by inverting the polarity of the high potential side voltage VCOMH with reference to a given voltage level.

  Here, the positive period T1 is a period in which the voltage level of the pixel electrode to which the grayscale voltage of the source line is supplied is higher than the voltage level of the counter electrode CE. In this period T1, a positive voltage is applied to the liquid crystal element. On the other hand, the negative period T2 is a period in which the voltage level of the pixel electrode to which the grayscale voltage of the source line is supplied is lower than the voltage level of the counter electrode CE. In this period T2, a negative voltage is applied to the liquid crystal element.

  Thus, by reversing the polarity of the counter electrode voltage VCOM, the voltage necessary for driving the display panel can be lowered. As a result, the withstand voltage of the drive circuit can be lowered, and the manufacturing process of the drive circuit can be simplified and the cost can be reduced.

  The display driver 60 including the source driver 20, the gate driver 30, and the power supply circuit 50 can drive the display panel 12 in various display modes. Therefore, the display driver 60 includes a control register unit (not shown).

  FIG. 9 is an explanatory diagram of the control register unit built in the display driver 60.

  The display driver 60 can include a control register unit 80 shown in FIG. The control register unit 80 includes a display mode setting register 82. The host or display controller 40 can access the control register unit 80 of the display driver 60. Then, the host or the display controller 40 sets the control data in the display mode setting register 82 of the control register unit 80, so that the normal display mode as the high load display mode or the partial display mode as the low load display mode is set. It can be specified.

  That is, the control signal MODE corresponding to the control data set in the display mode setting register 82 is output from the control register unit 80. This control signal MODE is supplied to each part of the display driver 60 so that each part can be controlled according to the display mode.

  10A and 10B are explanatory diagrams of the partial display mode.

  The X direction and the Y direction in FIGS. 10A and 10B correspond to the X direction and the Y direction in FIG. That is, in FIGS. 10A and 10B, a plurality of gate lines arranged in the Y direction extend in the X direction, and a plurality of source lines arranged in the X direction extend in the Y direction. In the partial display mode shown in FIG. 10A, a display region and a non-display region are formed in the vertical scanning direction by not selecting a part of the plurality of gate lines in one vertical scanning period. In this way, it is not necessary to apply a selection voltage for the gate line in the non-display area, so that power consumption can be reduced. In the partial display mode shown in FIG. 10B, a given non-display voltage is supplied to some of the plurality of source lines in one horizontal scanning period, so that a display region and a non-display region are arranged in the horizontal scanning direction. Is formed. By doing so, it is possible to reduce power consumption accompanying driving of the source line in the non-display area.

2. By the way, when adjusting the potential of the boosted voltage by the power supply circuit, there are a method of boosting the potential after adjusting the potential with a regulator and a method of limiting the potential of the boosted voltage with a limiter circuit. In the method of boosting after adjusting the potential with the regulator, the regulator can be operated at a lower voltage, so that the power consumption can be reduced, but the voltage range of the boosted voltage is narrowed. Further, in the method of limiting the potential of the boosted voltage with the limiter circuit, the voltage range of the boosted voltage is not narrowed, but power is consumed because the limiter circuit always operates. For this reason, the output load current of the power supply circuit varies depending on the display image and display mode that define the output load of the power supply circuit.

  FIG. 11 schematically shows the relationship between the output load and the output load current of the power supply circuit.

FIG. 11 shows the relationship between the output load of the power supply circuit and the output load current when the display panel 12 is a normally white panel, and the output load increases from the left side to the right side . That is, the output load of the power supply circuit when driving the display panel 12 in the partial display mode is smaller than the output load of the power supply circuit when driving the display panel 12 in the normal display mode.

  Even when the display panel 12 is driven in the normal display mode, the output load of the power supply circuit varies depending on the display image. In the normally white display panel 12, as shown in FIG. 11, the output load of the power supply circuit increases in the order of white display in the entire display area, natural image display, and black display in the entire display area.

  Depending on the method of adjusting the potential of the boosted voltage in the power supply circuit 50, the way of increasing the output load current corresponding to the output load of the power supply circuit 50 is different. For example, in the method of boosting after adjusting the potential with a regulator, the output load current is small when the output load is small, and the output load current is large when the output load is large (R1 in FIG. 11). This is presumably because when the output load increases, the booster circuit cannot sufficiently exhibit the ability to supply electric charges to the load. Therefore, the boosting efficiency decreases as the output load increases.

  On the other hand, for example, in the method of limiting the potential of the boosted voltage with a limiter circuit, the limiter circuit constantly consumes current, so the output load current increases from when the output load is small, but the output load increases. However, the output load current does not increase so much (R2 in FIG. 11). This is presumably because the load can be sufficiently driven even if the output load increases due to, for example, the charge supply capability of the operational amplifier incorporated in the limiter circuit. Therefore, even if the output load increases, the boosting efficiency does not decrease so much.

  Therefore, paying attention to the relationship of FIG. 11, in the partial display mode, the boosting efficiency of the power supply circuit is better in the method of boosting after adjusting the potential with the regulator. In the normal display mode, the method of limiting the potential of the boosted voltage with a limiter circuit in most display images has better boosting efficiency of the power supply circuit.

  For this reason, if the charge supply capability of the power supply circuit is built on the basis of the normal display mode, for example, by the method of limiting the potential of the boosted voltage with a limiter circuit with good boosting efficiency, the boosting efficiency of the power supply circuit in the partial display mode There was a problem of worsening.

  Therefore, in this embodiment, the boosting method of the power supply circuit can be changed according to the display mode. By doing so, the boosted voltage can be generated by a boosting method with good boosting efficiency in each display mode, so that the boosted voltage can be supplied without reducing the boosting efficiency.

  Below, the principal part of the power supply circuit 50 in this embodiment is demonstrated.

2.1 First Configuration Example FIG. 12 shows a configuration example of the booster circuit 52 and the limiter circuit 53 of the power supply circuit 50 in the first configuration example of the present embodiment.

  The booster circuit 52 includes a plurality of charge pump circuits having different boosting capabilities, and the boosting capability can be changed by enabling the operation of these charge pump circuits with control signals ENB1 and ENB2.

For example, the booster circuit 52 includes a regulator REG1 and first and second charge pump circuits 100 ₁ and 100 ₂ as shown in FIG. The first flying capacitor FC1 used for the charge pump operation of the _first charge pump circuit 1001 is connected to the external connection terminals TC1 and TC2 of the booster circuit 52 (power supply circuit 50). The second flying capacitor FC2 used for the charge pump operation of the _second charge pump circuit 1002 is connected to the external connection terminals TC3 and TC4 of the booster circuit 52 (power supply circuit 50).

The capacitance value of the second flying capacitor FC2 is larger than the capacitance value of the first flying capacitor FC1. The size of the transistors constituting the first charge pump circuit 100 ₁ is smaller than the size of the transistors constituting the second charge pump circuit 100 ₂ (channel length × channel width), the first charge pump circuit 100 ₁ The current driving capability of the transistors constituting the second charge pump circuit 1002 is smaller than the current driving capability of the transistors constituting the _second charge pump circuit 1002. In this way, the first charge pump circuit 100 ₁ of the step-up capability, can be made smaller than the second charge pump circuit 100 ₂ boosting capability.

The operation of the regulator REG1 is enabled by the control signal REG1en. The high potential side power supply voltage of the regulator REG1 is the system power supply voltage VDD, and the low potential side power supply voltage is the system ground power supply voltage VSS. The regulator REG1 is an operational amplifier connected in a voltage follower, and a given input voltage VIN0 is input to a non-inverting input terminal of the operational amplifier. The output voltage VREG of the regulator REG1 is supplied to the _first charge pump circuit 1001.

The first charge pump circuit 100 ₁ set in the enable state by the control signal ENB1 is voltage, for example, 2-fold with respect to the system ground power supply voltage VSS between the output voltage VREG of the system ground power supply voltage VSS and the regulator REG1 A power supply voltage VOUT that has been boosted to a low level is generated.

Control signal second charge pump circuit 100 _2, which is enabled state by the ENB2 is up the voltage between the system ground power supply voltage VSS and a system power supply voltage VDD, doubled for example by a system ground power supply voltage VSS The generated power supply voltage VOUT is generated.

FIG. 13 is a circuit diagram showing a configuration example of the _first charge pump circuit 1001 shown in FIG.

In Figure 13, it will be described first configuration example of the charge pump circuit 100 _1, except that the system power supply voltage VDD is employed instead of the output voltage VREG of the second charge pump circuit 100 _2, the regulator REG1 It is the same.

The first charge pump circuit 100 ₁ includes a transistor is a switch element for generating a boosted voltage using the charge accumulated by the charge pump operation in the first flying capacitor FC1. More specifically, a first charge pump circuit 100 _1, the P-type (broad to be inserted in series between the power supply line to the output power supply line and the voltage VREG of the boosted voltage is output is supplied first 1-conductivity type) MOS transistors (hereinafter simply referred to as transistors) PT1 and PT2. The first charge pump circuit 100 _1, P-type MOS transistor PT3, N-type to be inserted in series between the power supply line to which a power supply line and the system ground power supply voltage VSS to the voltage VREG is supplied is supplied ( In a broad sense, it includes a second conductivity type) MOS transistor (hereinafter simply referred to as transistor) NT1.

  The charge clock CK1P is supplied to the gate of the transistor PT1. The charge clock CK2P is supplied to the gate of the transistor PT2. The charge clock CK3P is supplied to the gate of the transistor PT3. The charge clock CK1N is supplied to the gate of the transistor NT1.

  A power supply line for outputting a boosted voltage is connected to the source of the transistor PT1. One end of the first flying capacitor FC1 is connected to the connection node of the transistors PT1 and PT2 via the terminal TC1. The other end of the first flying capacitor FC1 is connected to the connection node of the transistors PT3 and NT1 via the terminal TC2.

  FIG. 14 schematically shows the timing of the charge clocks CK1P, CK2P, CK3P, and CK1N in FIG.

  When the charge clock CK1P is at the L level, the charge clock CK2P is at the H level, and the charge clocks CK3P and CK1N are at the L level (period PH1). When the charge clock CK1P is at the H level, the charge clock CK2P is at the H level, and the charge clocks CK3P and CK1N are at the H level (period PH2).

  In the period PH1, the transistor PT1 is turned on, the transistor PT2 is turned off, and the voltage at one end of the first flying capacitor FC1 connected via the terminal TC1 is output to the output power supply line. At this time, the transistor PT3 is turned on, the transistor NT1 is turned off, and the voltage VREG is supplied to the other end of the first flying capacitor FC1 connected via the external connection terminal TC2.

  In the period PH2, the transistor PT1 is turned off and the transistor PT2 is turned on, and the voltage VREG is supplied to one end of the first flying capacitor FC1 connected through the terminal TC1. At this time, since the transistor PT3 is turned off and the transistor NT1 is turned on, the system ground power supply voltage VSS is supplied to the other end of the first flying capacitor FC1 connected via the external connection terminal TC2. Therefore, in the period PH2, the first flying capacitor FC1 accumulates charges corresponding to the voltage between the voltage VREG and the system ground power supply voltage VSS.

  In the period PH1, again, the voltage at one end of the first flying capacitor FC1 is output to the output power line as described above. At this time, since the voltage at the other end of the first flying capacitor FC1 connected to the external connection terminal TC2 becomes the voltage VREG, the voltage of the output power supply line is the voltage between the voltage VREG and the system ground power supply voltage VSS. The voltage is doubled.

  It is desirable to change the charge clocks CK1P and CK2P so that the transistors PT1 and PT2 are not turned on at the same time. Further, it is desirable to change the charge clocks CK2P and CK3P so that the transistors PT2 and PT3 are not turned on at the same time. Furthermore, it is desirable to change the charge clocks CK3P and CK1N so that the transistors PT3 and NT1 are not turned on at the same time.

  Returning to FIG. 12, the description will be continued.

  The limiter circuit 53 of FIG. 12 includes a comparator CMP1 and a voltage limiting circuit 150.

  The comparator CMP1 receives an input voltage Vin obtained by resistance-dividing the voltage between the voltage VOUT and the system ground power supply voltage VSS and a given reference voltage VREF. Then, the comparator CMP1 outputs the comparison result between the input voltage Vin and the reference voltage VREF as a comparison result pulse. The operation of the comparator CMP1 is enabled by the control signal LMTe, and the operation of the limiter circuit 53 is also enabled by the control signal LMTe.

  The voltage limiting circuit 150 is configured by a P-type MOS transistor TRO. The comparison result pulse from the comparator CMP1 is input to the gate of the P-type MOS transistor TRO. A power supply line to which the voltage VOUT is supplied is connected to the source of the P-type MOS transistor TRO. The drain of the P-type MOS transistor TRO is connected to a power supply line to which the system power supply voltage VDD is supplied.

  FIG. 15 shows a circuit diagram of a configuration example of the comparator CMP1 and the voltage limiting circuit 150 of FIG.

  The comparator CMP1 includes a differential amplifier DIF1 and an output circuit DRV1. The differential amplifier DIF1 includes a differential transistor pair to which a source is connected, a current source transistor that supplies a current to the source of the differential transistor pair, and a current mirror circuit that supplies a current to each transistor constituting the differential transistor pair. Including. Among the transistors constituting the differential transistor pair, the reference voltage VREF is supplied to the gate of the transistor serving as the non-inverting input terminal, and the input voltage Vin is supplied to the gate of the transistor serving as the inverting input terminal. Output circuit DRV1 includes a P-type MOS transistor PDRV1 and an N-type MOS transistor NDRV1 connected in series. The gate of the N-type MOS transistor NDRV1 is supplied with the same voltage as the gate voltage of the current source transistor of the differential amplifier DIF1, and drives the drain of the P-type MOS transistor PDRV1. The output voltage of the differential amplifier DIF1 is supplied to the gate of the P-type MOS transistor PDRV1.

  The voltage of the drain of the P-type MOS transistor PDRV1 of the output circuit DRV1 is supplied to the gate of the P-type MOS transistor TRO constituting the voltage limiting circuit 150.

  When the disabled state is set by the control signal LMTen, the voltage at the output node of the differential amplifier DIF1 is fixed at, for example, the system power supply voltage VDD. Further, when the control signal LMTen is set to a disabled state, the current source transistor is set to a non-conductive state. Further, when the disabled state is set by the control signal LMTen, the gate voltage of the P-type MOS transistor TRO is fixed to the source voltage of the P-type MOS transistor TRO.

  When the enable state is set by the control signal LMTen and the input voltage Vin is higher than the reference voltage VREF, the potential of the output voltage of the differential amplifier DIF1 increases, and the impedance of the P-type MOS transistor PDRV1 increases. As a result, the potential of the comparison result pulse, which is the output of the comparator CMP1, changes in the direction of decreasing. At this time, the impedance of the P-type MOS transistor TRO changes in a decreasing direction, and the amount of charge discharged to the power supply line to which the system power supply voltage VDD is supplied increases.

  On the other hand, when the enable state is set by the control signal LMTen and the input voltage Vin is lower than the reference voltage VREF, the potential of the output voltage of the differential amplifier DIF1 is lowered and the impedance of the P-type MOS transistor PDRV1 is lowered. As a result, the potential of the comparison result pulse, which is the output of the comparator CMP1, changes in the increasing direction. At this time, the impedance of the P-type MOS transistor TRO changes in the increasing direction, and the amount of charge discharged to the power supply line to which the system power supply voltage VDD is supplied decreases.

  Such a power supply circuit 50 has a power supply circuit control unit (not shown), and generates control signals for the respective units in the power supply circuit.

  FIG. 16 shows an outline of the configuration of the power supply circuit control unit 58 of the power supply circuit 50.

  The power supply circuit control unit 58 generates control signals REG1en, ENB1, ENB2, and LMTen based on the control signal MODE from the display mode setting register 82. Such a power supply circuit control unit 58 is configured by a known combinational circuit.

  FIG. 17 shows an operation explanatory diagram of the power supply circuit control unit 58 of FIG.

In the first configuration example, when the normal display mode (high load display mode) is specified by the control signal MODE, the regulator REG1 is disabled by the control signal REG1en, and the first charge pump circuit is set by the control signal ENB1. 100 ₁ is set to the enable state or disable state, by the control signal ENB2 second charge pump circuit 100 ₂ is set in the enabled state, the limiter circuit 53 is set to the enable state by the control signal LMTen.

The control signal when the partial display mode (low load display mode) is designated by the MODE control signal REG1en regulator REG1 is set to an enable state by, the first charge pump circuit 100 ₁ is enabled by the control signal ENB1 is set by the control signal ENB2 second charge pump circuit 100 ₂ is set to the disable state, the limiter circuit 53 is set to the disable state by the control signal LMTen.

  That is, when the drive voltage of the display panel 12 is generated based on the boosted voltage VOUT generated by the power supply circuit 50, when the display panel 12 is driven in the normal display mode, the power supply circuit 50 Is output as the boosted voltage. When the display panel 12 is driven in the partial display mode (low load display mode), the power supply circuit 50 does not limit the voltage obtained by boosting the output voltage VREG of the regulator REG1 by the booster circuit 52 by the limiter circuit 53. The boosted voltage is output as it is. By doing so, the boosted voltage can be generated by a boosting method with good boosting efficiency in each display mode, so that the boosted voltage can be supplied without reducing the boosting efficiency.

More specifically, when the display panel 12 is driven in the normal display mode, the power supply circuit 50 generates the boosted voltage generated by the first and second charge pump circuits 100 ₁ and 100 ₂ or the second charge. and outputs the boosted voltage generated by the pump circuit 100 _2. Further, when the display panel 12 is driven in the partial display mode, the boosted voltage generated by the _first charge pump circuit 1001 is output. As a result, when the output load of the power supply circuit 50 is large, a boosted voltage can be generated with a high boosting capability, and when the output load of the power supply circuit 50 is small, a boosted voltage can be generated with a low boosting capability, thereby significantly reducing the boosting efficiency. The boosted voltage can be supplied stably without any problems.

2.2 Second Configuration Example In the first configuration example, in the normal display mode, the boost voltage is generated without changing the boost capability according to the output load of the power supply circuit 50, so the output load changes. Even when the output load becomes high, there is a possibility that the boosting capability becomes insufficient and the boosting efficiency is lowered. In contrast, in the second configuration example, when the display panel 12 is driven in the normal display mode, control is performed to change the boosting capability of the booster circuit in accordance with the output load of the power supply circuit 50, and in the partial display mode. When the display panel 12 is driven, the control for changing the boosting capability of the booster circuit according to the output load of the power supply circuit 50 is omitted. Thus, even when the output load of the power supply circuit 50 is high, it is possible to prevent the boosting efficiency from being lowered with respect to the output load without reducing the boosting capability.

  FIG. 18 shows a main configuration part of the liquid crystal display device according to the second configuration example of the present embodiment. In FIG. 18, the same parts as those in FIG. 1 or FIG. Further, illustration and description of other blocks of the liquid crystal display device are omitted.

  In the second configuration example, the drive voltage of the source line of the display panel 12 is generated based on the boosted voltage VOUT, and the power supply circuit 50 uses the total data GSUM, which is an evaluation value for evaluating the output load, as a given threshold value. It is possible to determine whether or not to change the boosting capability. The total data GSUM is obtained by the gradation data total calculation unit 25 of the source driver 20. The power supply circuit 50 changes the boost capability based on the sum data GSUM and supplies the boost voltage to the source driver 20.

  More specifically, when it is determined that the boosting capability is high with respect to the output load of the power supply circuit 50, the power supply circuit 50 changes the boosting capability so that the boosting capability becomes lower, and When it is determined that the boosting capability is low, the boosting capability is changed so that the boosting capability becomes higher.

  Hereinafter, only the difference between the second configuration example and the first configuration example will be described, and description of the same part will be appropriately omitted.

  FIG. 19 shows a block diagram of a configuration example of the source driver in the second configuration example of FIG. In FIG. 19, the same parts as those in FIG.

  The source driver in the second configuration example is different from the source driver in the first configuration example in that the source driver in the second configuration example includes the gradation data summation calculation unit 25.

  The gradation data sum calculation unit 25 calculates an evaluation value for evaluating the output load of the power supply circuit 50 based on the gradation data. This evaluation value is supplied to the power supply circuit 50 as total data GSUM. More specifically, the gradation data summation calculation unit 25 can obtain the evaluation value by adding gradation data for one scanning line. For example, the gradation data summation calculation unit 25 adds the gradation data fetched into the line latch 26 for each source output, obtains summation data, and uses it as an evaluation value. Based on the total data as such evaluation values, the magnitude of the gradation voltage used for driving the display panel 12 can be roughly evaluated, and can be used for evaluating the output load of the power supply circuit 50.

  FIG. 20 shows a configuration example of the booster circuit 52 and the limiter circuit 53 of the power supply circuit 50 in the second configuration example.

  The booster circuit 52 in the second configuration example is different from the booster circuit 52 in the first configuration example in that the switching control unit 110 is included in the second configuration example.

The switching control unit 110 performs enable control of the first and second charge pump circuits 100 ₁ and 100 ₂ . More specifically, the switching control unit 110 sets one of the first and second charge pump circuits 100 ₁ , 100 ₂ to an enabled state, or the first and second charge pump circuits 100 _1. It may or enabled state both 100 _2. By doing so, the switching control unit 110 can select and control the boosting capability of the booster circuit 52 from any of the three types. The switching control unit 110 performs control to change the boosting capability of the booster circuit 52 according to the output load of the power supply circuit 50.

  FIG. 21 is an operation explanatory diagram of the power circuit controller 58 of the power circuit in the second configuration example.

In the second configuration example, when the normal display mode (high load display mode) is designated by the control signal MODE, the regulator REG1 is disabled by the control signal REG1en, and the limiter circuit 53 is enabled by the control signal LMTen. Set to The enable control of the first and second charge pump circuits 100 ₁ and 100 ₂ is performed according to the output load of the power supply circuit 50. More specifically, when the normal display mode is designated, the booster circuit 52 of the power supply circuit 50 indicates whether or not the output load of the power supply circuit 50 and the limiter circuit 53 limit the potential of the boosted voltage. Based on the information, the boosting capability is changed.

The control signal when the partial display mode (low load display mode) is designated by the MODE control signal REG1en regulator REG1 is set to an enable state by, the first charge pump circuit 100 ₁ is enabled by the control signal ENB1 is set by the control signal ENB2 second charge pump circuit 100 ₂ is set to the disable state, the limiter circuit 53 is set to the disable state by the control signal LMTen. As a result, even when the output load of the power supply circuit 50 is high, it is possible to prevent the boosting efficiency from decreasing with respect to the output load without decreasing the boosting capability.

  The power supply circuit 50 in the second configuration example further includes a comparator CMP2, a level shifter 180, a counter 182, a determination logic unit 184, and a threshold update unit 186.

  The comparator CMP2 can detect the operation information of the limiter circuit 53 by determining the period during which the voltage limiting circuit 150 of the limiter circuit 53 has adjusted the voltage based on the comparison result pulse from the comparator CMP1.

  FIG. 22 is an explanatory diagram of comparison result pulses of the comparator CMP1.

  The comparison result pulse becomes a pulse signal as shown in FIG. When the input voltage Vin is higher than the reference voltage VREF, the comparison result pulse is at the L level, which is a period for discharging charges to the power supply line to which the system power supply voltage VDD is supplied as described above. Further, when the input voltage Vin is lower than the reference voltage VREF, the comparison result pulse is at the H level, and it is a period during which no charge is discharged to the power supply line.

  Thus, in the limiter circuit 53, when the input voltage Vin becomes higher than the reference voltage VREF, the P-type MOS transistor TRO is turned on, and the charge of the power supply line to which the voltage VOUT is supplied is changed to the system power supply voltage VDD. Is controlled to discharge to the power supply line to which is supplied.

  As described above, the power supply circuit 50 in the second configuration example compares the summation data GSUM, which is an evaluation value for evaluating the output load, with a given threshold value to determine whether or not to change the boosting capability. It is possible to judge. Further, this threshold value is updated based on limiter operation information indicating whether or not the limiter circuit 53 has limited the potential of the voltage VOUT that is the boosted voltage. Therefore, the power supply circuit 50 can change the boosting capability of the booster circuit 52 based on the output load of the power supply circuit 50 and the limiter operation information.

  Therefore, in FIG. 20, the comparison result pulse from the limiter circuit 53 and a given threshold voltage VTH are input to the comparator CMP2. When the power supply on the high potential side of the comparator CMP2 is the voltage VOUT and the power supply on the low potential side is the system ground power supply voltage VSS, the threshold voltage VTH can be expressed by the following equation.

VTH = VOUT−Vthp−α (1)
Here, Vthp is a threshold voltage of the P-type MOS transistor TRO constituting the voltage limiting circuit 150, and α is a positive constant value of about 0.1V to 0.2V. The output signal of the comparator CMP2 is a signal corresponding to the H level and L level of the comparison result pulse in FIG. 22, and is a signal for monitoring the length of time for discharging the charge to the power supply line.

  The level shifter 180 shifts the voltage level of the output signal of the comparator CMP2 to a signal having a given voltage level. The counter 182 counts the pulse width or number of pulses of the pulse signal that is the output signal of the level shifter 180. The count value in the predetermined period of the counter 182 can be considered as a signal indicating limiter operation information. That is, when the boosting capability is large, the period during which the limiter circuit 53 is operating becomes long. Therefore, the limiter operation information of the limiter circuit 53 can be digitized by counting the pulse width or the number of pulses of the pulse signal. When counting the number of pulses of the pulse signal, for example, the number of pulses corresponding to the period during which the limiter circuit 53 is operated in a certain period (one or more horizontal scanning periods, one or more vertical scanning periods) is set to a dot clock (pixel clock). ) Etc. may be counted using a given clock signal.

The determination logic unit 184 controls the switching control unit 110 of the booster circuit 52 by comparing the sum data GSUM with a given threshold value. In the present embodiment, based on the determination result from the determination logic unit 184, the switching control unit 110 performs control so that at least one of the first and second charge pump circuits 100 ₁ and 100 ₂ is enabled. . As a result, the switching control unit 110, after changing the boosting capability of the booster circuit 52, a first boosted voltage generated by the charge pump circuit 100 _1, second boosted voltage generated by the charge pump circuit 100 _2, or The boosted voltage generated by the first and second charge pump circuits 100 ₁ and 100 ₂ is output.

  Further, the determination logic unit 184 determines whether or not the threshold value should be updated based on the count value of the counter 182. For example, the determination logic unit 184 compares a given update determination threshold value with a count value. When the determination logic unit 184 determines that the threshold should be updated, the threshold update unit 186 updates the threshold by incrementing or decrementing the current threshold, and supplies the threshold to the determination logic unit 184. Then, the determination logic unit 184 controls the switching control unit 110 by comparing the threshold value with the total data GSUM. Thus, by determining whether the operation period of the limiter circuit 53 is long or short based on the count value, the threshold value is updated based on the comparison result between the given threshold voltage and the voltage VOUT (boosted voltage). The

  FIG. 23 illustrates an example of the operation of the determination logic unit 184 in FIG.

In the second configuration example, the boosting capability of the booster circuit 52 is changed with respect to the maximum value of the sum total data GSUM in accordance with the sum total data GSUM of the scan lines to be calculated. Therefore, the determination logic unit 184 has two threshold values THA and THB. Threshold THA is a state in which the second charge pump circuit 100 ₂ is set to an enable state, a threshold value for the first charge pump circuit 100 ₁ determines whether the enabled state. The threshold value THB is a threshold value for determining whether or not one of the first and second charge pump circuits 100 ₁ and 100 ₂ is set to an enable state.

Therefore, when the sum data GSUM is larger than the threshold value THA, control is performed to set the first and second charge pump circuits 100 ₁ and 100 ₂ to the enable state. A sum data GSUM is below the threshold value THA, and when the threshold THB greater than the first charge pump circuit 100 ₁ is set to the disable state, the control for setting the second charge pump circuit 100 ₂ in the enabled state Do. Furthermore, when the total data GSUM the following threshold THB, the first charge pump circuit 100 ₁ is set to the enable state, the control for setting the second charge pump circuit 100 ₂ disabled state.

  FIG. 24 shows a circuit diagram of a main part of a configuration example of the determination logic unit 184 of FIG.

  The determination logic unit 184 includes comparators CMP10, CMP11, CMP12, and CMP13, and minimum value / maximum value determination units MM1 and MM2. Note that the determination logic unit 184 includes a plurality of flip-flops DFF1 to DFF6, and each flip-flop is initialized by an initialization signal (not shown).

  24 receives the horizontal synchronization signal LP, the sum data GSUM, threshold values THA, THB, and pulse data PLSET, PCNT1, and PCNT2, and outputs control signals ENB1, ENB2, INCA, DECA, INCB, and DECB. To do.

Here, the pulse data PLSET is threshold data. For example, the comparator CMP 12 compares the voltage VOUT with a given threshold voltage (VTH = VTH = 5.9 V) based on the comparison result pulse, indicating that the voltage VOUT has become a given threshold voltage (VTH = 5.9 V) or less. 6.12 V) or higher, a comparison result signal can be output indicating that Then, the width of the comparison result signal (maintaining a given level), the pulse width, or the comparison result signal indicating that the voltage VOUT is equal to or lower than the given threshold voltage (VTH = 5.9) A result obtained by testing a period for maintaining the level using a given clock (for example, a dot clock or a pixel clock) is input as pulse data PCNT1. The width of the comparison result signal indicating that the voltage VOUT is equal to or higher than a given threshold voltage (VTH = 6.12 V) (maintaining a given level), the pulse width, or the comparison result signal is a given level. The result of testing the period for maintaining the value using a given clock (for example, dot clock or pixel clock) is input as pulse data PCNT2. The pulse data PLSET is compared with each pulse data of the pulse data PCNT1 and PCNT2.

  Since the limiter circuit 53 operates when the boosting capability is too high, when it is determined that the pulse data PCNT1 is larger than the pulse data PLSET, the threshold THB corresponding to the threshold voltage (VTH = 5.9V) is incremented. . Similarly, when it is determined that the pulse data PCNT2 is larger than the pulse data PLSET, control is performed to increment the threshold value THA corresponding to the threshold voltage (VTH = 6.12V).

Since the limiter circuit 53 does not operate when the boosting capability is too low, when it is determined that the pulse data PCNT1 is smaller than the pulse data PLSET, control is performed to decrement the threshold value THB corresponding to the threshold voltage (VTH = 5.9V). Similarly, when it is determined that the pulse data PCNT2 is smaller than the pulse data PLSET, control is performed to decrement the threshold value THA corresponding to the threshold voltage (VTH = 6.12V).

  The control signal INCA is a control signal for incrementing the threshold value THA. The control signal INCB is a control signal for incrementing the threshold value THB. The control signal DECA is a control signal for decrementing the threshold value THA. The control signal DECB is a control signal for decrementing the threshold value THB.

The control signal ENB1 is a control signal for setting the _first charge pump circuit 1001 to an enable state. The control signal ENB2 is a control signal for setting the _second charge pump circuit 1002 to an enable state.

  In FIG. 24, when the sum data GSUM is larger than the threshold value THA, the output signal of the comparator CMP10 becomes H level. When the sum data GSUM is larger than the threshold value THBA, the output signal of the comparator CMP11 becomes H level. When the pulse data PCNT2 is larger than the pulse data PLSET, the output signal of the comparator CMP12 becomes H level. When the pulse data PCNT1 is larger than the pulse data PLSET, the output signal of the comparator CMP13 becomes H level.

  The minimum value / maximum value determination unit MM1 outputs a control signal for prohibiting the increment control when each bit of the threshold value THA is “1”. The minimum value / maximum value determination unit MM1 outputs a control signal for prohibiting decrement control when each bit of the threshold value THA is “0”.

  The minimum / maximum value determination unit MM2 outputs a control signal for prohibiting the increment control when each bit of the threshold value THB is “1”. The minimum / maximum value determination unit MM2 outputs a control signal for prohibiting decrement control when each bit of the threshold value THB is “0”.

As described above, the determination logic unit 184 can perform control for setting the first and second charge pump circuits 100 ₁ and 100 ₂ to the enable state based on the total data GSUM and the threshold values THA and THB. Further, the determination logic unit 184 can determine a period during which the limiter circuit 53 has been operated based on the comparison result pulse, and can perform control to increment or decrement the thresholds THA and THB according to the determination result.

  As described above, according to the present embodiment, even when the boosted voltage exceeds the target voltage, the electric charge is discharged to the power supply line to which the boosting source power is supplied. The power consumption can be significantly reduced as compared with the case where electric charges are discharged to the power supply line to which the power supply voltage VSS is supplied. Furthermore, according to the first configuration example, when the output load of the power supply circuit 50 is large, the boosted voltage can be generated with a high boosting capability, and when the output load of the power supply circuit 50 is small, the boosted voltage can be generated with a low boosting capability. Thus, the boosted voltage can be stably supplied without significantly reducing the boosting efficiency. Furthermore, according to the second configuration example, since the boosting capability of the booster circuit can be changed according to the output load, even when the output load is high, the boosting capability is not decreased and the output load is reduced. It becomes possible to prevent the boosting efficiency from being lowered.

3. Electronic Device FIG. 25 shows a block diagram of a configuration example of an electronic device to which the power supply circuit of the present embodiment is applied. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera, and supplies image data captured by the CCD camera to the display controller 540 in the YUV format. The display controller 540 has the function of the display controller 40 of FIG. 1 or FIG.

  The mobile phone 900 includes a display panel 512. The display panel 512 is driven by the source driver 520 and the gate driver 530. The display panel 512 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels. The display panel 512 has the function of the display panel 12 shown in FIG.

  The display controller 540 is connected to the source driver 520 and the gate driver 530 and supplies gradation data in RGB format to the source driver 520.

  The power supply circuit 542 is connected to the source driver 520 and the gate driver 530, and supplies a driving power supply voltage to each driver. The power supply circuit 542 has the function of the power supply circuit 50 in FIG. 1 or FIG. The display driver 544 includes a source driver 520, a gate driver 530, and a power supply circuit 542, and the display driver 544 can drive the display panel 512.

  The host 940 is connected to the display controller 540. The host 940 controls the display controller 540. In addition, the host 940 can demodulate the gradation data received via the antenna 960 by the modem 950 and then supply it to the display controller 540. The display controller 540 causes the display panel 512 to display the source driver 520 and the gate driver 530 based on the gradation data. The source driver 520 has the function of any of the source drivers in the first to third embodiments. The gate driver 530 has the function of the gate driver 30 shown in FIG.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the display panel 512 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices. Furthermore, the present invention is not limited to driving a display panel, and can be applied to a device that supplies power to various circuits.

  Furthermore, the liquid crystal display device of the above-described embodiment includes a mobile phone, a portable information device (PDA, etc.), a digital camera, a projector, a portable audio player, a mass storage device, a video camera, an electronic notebook, or a GPS (Global Positioning System). It can be incorporated in various electronic devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

FIG. 3 is a diagram illustrating an example of a block diagram of a liquid crystal display device of the present embodiment. The block diagram of the other structural example of the liquid crystal display device in this embodiment. FIG. 3 is a block diagram of a configuration example of the gate driver in FIG. 1 or FIG. 2. FIG. 3 is a block diagram of a configuration example of the source driver in FIG. 1 or FIG. 2. FIG. 5 is a diagram illustrating a configuration example of a reference voltage generation circuit, a DAC, and a source line driver circuit in FIG. 4. The figure which shows the structural example of the power supply circuit of FIG. 1 or FIG. FIG. 3 is a diagram showing an example of a drive waveform of the display panel of FIG. 1 or FIG. 2. Explanatory drawing of the polarity inversion drive of this embodiment. Explanatory drawing of the control register part which the display driver of this embodiment incorporates. 10A and 10B are explanatory diagrams of the partial display mode. The figure which shows typically the relationship between the output load of an electric power circuit, and output load current. The figure which shows the structural example of the booster circuit and limiter circuit of the power supply circuit of the 1st structural example of this embodiment. FIG. 13 is a circuit diagram of a configuration example of a first charge pump circuit in FIG. 12. FIG. 14 is a diagram schematically showing the timing of the charge clock in FIG. 13. The circuit diagram of the structural example of the comparator of FIG. 12, and a voltage limiting circuit. The figure which shows the outline | summary of a structure of the power supply circuit control part of the power supply circuit of a 1st structural example. FIG. 17 is an operation explanatory diagram of the power supply circuit control unit of FIG. 16. The figure which shows the principal part of the liquid crystal display device in the 2nd structural example of this embodiment. The block diagram of the structural example of the source driver in a 2nd structural example. The figure which shows the structural example of the booster circuit of the power supply circuit in a 2nd structural example, and a limiter circuit. The operation explanatory view of the power circuit control part of the power circuit in the 2nd example of composition. Explanatory drawing of the comparison result pulse of a comparator. FIG. 21 is an explanatory diagram illustrating an example of the operation of the determination logic unit in FIG. 20. The circuit diagram of the principal part of the structural example of the determination logic part of FIG. 1 is a block diagram of a configuration example of an electronic device to which a power supply circuit according to an embodiment is applied.

Explanation of symbols

10 liquid crystal display device, 12 display panel, 20 source driver,
22, 32 shift register, 24, 26 line latch,
25 gradation data sum calculation unit, 27 reference voltage generation circuit, 28 DAC,
29 source line drive circuit, 30 gate driver, 34, 180 level shifter,
36 output buffer, 40 display controller, 50 power supply circuit,
52 booster circuit, 53 limiter circuit, 54 scan voltage generation circuit,
56 counter electrode voltage generation circuit, 60 display driver,
80 control register section, 82 display mode setting register,
100 ₁ 1st charge pump circuit, 100 ₂ 2nd charge pump circuit,
110 switching control unit, 150 voltage limiting circuit, 182 counter,
184 decision logic unit, 186 threshold update unit,
CMP1, CMP2 comparator, FC1 first flying capacitor,
FC2 second flying capacitors, _G 1 _~G M, _{G K} gate lines,
GSUM sum data, REG1 regulator, _S 1 _~S N, _{S L} source line,
TC1 to TC4 external connection terminal, VTH threshold voltage, VREF reference voltage,
VDD System power supply voltage, VSS System ground power supply voltage

Claims (17)

A power supply circuit for outputting a boosted voltage,
A booster circuit that generates a boosted voltage obtained by boosting the second voltage with reference to the first voltage;
A limiter circuit for limiting the potential of the boosted voltage ;
A regulator that regulates the potential of a given input voltage,
The limiter circuit is
Discharging the charge to the power supply line to which the second voltage is supplied so that the boosted voltage becomes a given target voltage, or charging the charge from the power supply line ,
When the driving voltage of the electro-optical device is generated based on the boosted voltage,
When the electro-optical device is driven in a high load display mode, a voltage obtained by limiting the potential of the boosted voltage with the limiter circuit is output as the boosted voltage,
When the electro-optical device is driven in a low load display mode, a voltage obtained by boosting the output voltage of the regulator by the booster circuit is output as the boosted voltage without being limited by the limiter circuit. Power supply circuit. In claim 1 ,
Including display mode setting register,
When the high load display mode is designated by the control data set in the display mode setting register, a voltage obtained by limiting the potential of the boosted voltage by the limiter circuit is output as the boosted voltage,
When the low load display mode is designated by the control data set in the display mode setting register, a power supply circuit that outputs a voltage obtained by boosting the output voltage of the regulator by the booster circuit as the boosted voltage . In claim 1 or 2 ,
The booster circuit is
A first charge pump circuit for generating the boosted voltage by boosting the output voltage of the regulator with reference to the first voltage by a charge pump operation using a first flying capacitor;
For generating the boosted voltage by boosting the second voltage with reference to the first voltage by a charge pump operation using a second flying capacitor having a larger capacitance value than the first flying capacitor. A second charge pump circuit;
When the electro-optical device is driven in the high load display mode, the boosted voltage generated by the first and second charge pump circuits or the boosted voltage generated by the second charge pump circuit is output. ,
A power supply circuit that outputs a boosted voltage generated by the first charge pump circuit when the electro-optical device is driven in the low-load display mode. In any one of Claims 1 thru | or 3 ,
When the electro-optical device is driven in the high load display mode, control is performed to change the boosting capability that is the current driving capability of the booster circuit according to the output load of the power supply circuit,
Wherein when said low-load display mode electro-optical device is driven, the power supply circuit, characterized by omitting the control for changing the boosting capability of the booster circuit in accordance with the output load of the power supply circuit. In claim 4 ,
When the high load display mode is specified,
When it is determined that the boost capability is high with respect to the output load of the power supply circuit, the boost capability is changed so that the boost capability becomes lower,
When it is determined that the boost capability is low with respect to the output load, the boost capability is changed so that the boost capability becomes higher. In claim 4 or 5 ,
When the high load display mode is specified,
The booster circuit is
The power supply circuit, wherein the boosting capability is changed based on an output load of the power supply circuit and limiter operation information indicating whether or not the limiter circuit limits the potential of the boosted voltage. In claim 6 ,
When the high load display mode is specified,
The booster circuit is
A power supply circuit, wherein the boosting capability is changed according to a comparison result between a threshold value updated based on the limiter operation information and an output load of the power supply circuit. In claim 7 ,
The threshold is
A power supply circuit that is updated based on a comparison result between a given threshold voltage and the boosted voltage. In claim 8 ,
A comparator for comparing the given threshold voltage with the boost voltage;
A counter that counts pulses that are output results of the comparator,
The threshold is
The power supply circuit is updated based on a count number of the counter. In any one of Claims 4 thru | or 9 .
When a driving voltage corresponding to gradation data of each source line of the plurality of source lines of the electro-optical device is generated based on the boosted voltage,
The output load is
The power supply circuit is evaluated based on a sum of gradation data for one scanning line of the plurality of source lines. A display driver for driving an electro-optical device,
A power supply circuit according to any one of claims 1 to 10 ,
A drive unit for driving the electro-optical device,
A display driver that generates a drive voltage of the drive unit based on the boosted voltage. In claim 11 ,
The drive unit is
A display driver, wherein a plurality of source lines of the electro-optical device are driven by a driving voltage corresponding to gradation data generated using the boosted voltage. Multiple gate lines,
Multiple source lines,
A gate driver that scans the plurality of gate lines;
A source driver for driving the plurality of source lines;
A power supply circuit according to any one of claims 1 to 10 ,
An electro-optical device, wherein at least one of a scanning voltage of the gate driver and a driving voltage of the source driver is generated based on the boosted voltage. Multiple gate lines,
Multiple source lines,
A gate driver that scans the plurality of gate lines;
13. An electro-optical device comprising: the display driver according to claim 12 which drives the plurality of source lines. An electronic apparatus comprising a power supply circuit according to any one of claims 1 to 10. An electronic apparatus comprising the display driver according to claim 11 . An electronic apparatus comprising the electro-optical device according to claim 13 .

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