JP5271886B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5271886B2 JP5271886B2 JP2009278214A JP2009278214A JP5271886B2 JP 5271886 B2 JP5271886 B2 JP 5271886B2 JP 2009278214 A JP2009278214 A JP 2009278214A JP 2009278214 A JP2009278214 A JP 2009278214A JP 5271886 B2 JP5271886 B2 JP 5271886B2
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- semiconductor device
- wiring board
- main surface
- convex portion
- heat sink
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Description
本発明の一実施の形態の半導体装置およびその製造方法(製造工程)を図面を参照して説明する。
図1および図2は、本発明の一実施の形態である半導体装置1の断面図(側面断面図)であり、図3および図4は、半導体装置1の要部断面図(部分拡大断面図)であり、図5は、半導体装置1の上面図(平面図)であり、図6は、半導体装置1の下面図(底面図、裏面図、平面図)である。図7は、封止部7を透視したときの半導体装置1の上面側の平面透視図(上面図)であり、図8は、封止部8を透視したときの半導体装置1の下面側の平面透視図(下面図)である。図9は、図8において、更にボンディングワイヤBWを外した(透視した)状態の半導体装置1の平面透視図(下面図)である。図10は、図9において、更に半導体チップ5を外した(透視した)状態の半導体装置1の平面透視図(下面図)である。なお、図5〜図10のA1−A1線の断面が図1にほぼ対応し、図5〜図10のA2−A2線の断面が図2にほぼ対応する。また、図3は、図1において、円で囲まれた領域RG1の部分拡大図に対応し、図4は、図2において、円で囲まれた領域RG2の部分拡大図に対応する。図11は、本実施の形態の半導体装置1に使用されている配線基板2の上面図(平面図)であり、図12は、本実施の形態の半導体装置1に使用されている配線基板2の下面図(平面図)である。図13は、本実施の形態の半導体装置1に使用されている放熱板4の上面図(平面図)であり、図14は、本実施の形態の半導体装置1に使用されている放熱板4の下面図(平面図)であり、図15は、本実施の形態の半導体装置1に使用されている放熱板4の側面図であり、図16および図17は、本実施の形態の半導体装置1に使用されている放熱板4の断面図(側面断面図)である。なお、図13および図14のB1−B1線の断面が図16にほぼ対応し、図13および図14のB2−B2線の断面が図17にほぼ対応するが、図13および図14のB1−B1線の位置は、上記図5〜図10のA1−A1線の位置に対応しており、図13および図14のB2−B2線の位置は、上記図5〜図10のA2−A2線の位置に対応している。従って、図16は図1と同じ断面が示され、図17は図2と同じ断面が示されていることになる。また、理解を簡単にするために、図7において、封止部7を透視しても放熱板4で隠れて見えない貫通孔3の位置を点線で示してあり、また、図8において、透視した封止部8の外形位置を点線で示してある。
半導体装置1の実装について説明する。
次に、本実施の形態の半導体装置1の製造方法を、図面を参照して説明する。図22は、本実施の形態の半導体装置1の製造工程を示す工程フロー図である。図23〜図46は、本実施の形態の半導体装置1の製造工程中の平面図または断面図である。
上記ステップS5,S6の放熱板4の配置工程および固定(かしめ)工程について、より詳細に説明する。
上記ステップS8のモールド工程について、より詳細に説明する。
本実施の形態では、放熱板4を用いたことにより、半導体装置の放熱特性を向上させることができる。半導体装置を製造する際には、この放熱板4を配線基板31に固定しないと、ワイヤボンディング工程やモールド工程、あるいは工程間の搬送などで、放熱板4が配線基板31から外れてしまう可能性がある。このため、半導体装置を製造する際には、放熱板4を配線基板31に固定する必要がある。
上記実施の形態1で説明した製造工程では、放熱板4の凸部12上に半導体チップ5を搭載してから、半導体チップ5が搭載された放熱板4を配線基板31の貫通孔3内に配置していた。本実施の形態では、放熱板4の凸部12に半導体チップ5を搭載する前に、放熱板4を配線基板31の貫通孔3内に配置し、その後、配線基板31の貫通孔3内に配置された放熱板4の凸部12に半導体チップ5を搭載する。この場合を、図68〜図74を参照して説明する。
図75および図76は、本実施の形態の半導体装置1aの断面図(側面断面図)であり、上記実施の形態1の上記図1および図2にそれぞれ対応するものである。
図77および図78は、本実施の形態の半導体装置1bの断面図(側面断面図)であり、上記実施の形態1の上記図1および図2にそれぞれ対応するものである。図79は、本実施の形態の半導体装置1bの上面図であり、上記実施の形態1の上記図5に対応するものであり、図80は、本実施の形態の半導体装置1bの下面図であり、上記実施の形態1の上記図6に対応するものである。図81は、封止部8を透視したときの半導体装置1bの下面側の平面透視図(下面図)であり、上記実施の形態1の上記図8に対応するものである。図82は、図81において、更にボンディングワイヤBWおよび半導体チップ5を外した(透視した)状態の半導体装置1の平面透視図(下面図)であり、上記実施の形態1の上記図10に対応するものである。なお、図79〜図82のA1−A1線の断面が図77にほぼ対応し、図79〜図82のA2−A2線の断面が図78にほぼ対応する。また、理解を簡単にするために、図81において、透視した封止部8の外形位置を点線で示してある。
本実施の形態は、上記実施の形態1の変形例に対応する。
2 配線基板
2a 上面
2b 下面
3 貫通孔
4 放熱板
5 半導体チップ
5a 表面
5b 裏面
7 封止部
7a 上面
7c 封止部
8 封止部
8a 主面
9 半田ボール
11 基材部
11a 主面
11b 裏面
11c 側面
12 凸部
12a 主面
12b 側面
13 支持部
13a 支持面
14 接合材
14a 半田
14b 銀ペースト
15,15a,15b 隙間部
16 溝
17 四隅
18,19 隙間
21 実装基板
22,22a,22b,22c 基板側端子
23 導電性シート
24 筐体
25a,25b,25c 半田
26 チップ部品
27 半導体装置
28 アウタリード部
31 配線基板
31a 上面
31b 下面
32 半導体装置領域
41 フレーム
42 フレーム枠
43,44 連結部
45 キャリア
46 治具
47 先端部
51,52 金型
53 シート
54,55 ローラ
56 レジンゲート
57 エアベント
61,62 金型
71 領域
BL ボンディングリード
BW ボンディングワイヤ
CAV1,CAV2,CAV3 キャビティ
LA バンプランド
MR 樹脂材料
PD 電極パッド
RG1,RG2,RG3,RG4,RG5,RG6,RG7,RG8 領域
Claims (20)
- (a)第1主面と、前記第1主面とは反対側の第1裏面と、前記第1主面から前記第1裏面に到達する貫通孔と、前記第1裏面において前記貫通孔の周囲に形成された複数のボンディングリードと、前記第1裏面に形成されかつ前記複数のボンディングリードとそれぞれ電気的に接続された複数のバンプランドとを有する配線基板を準備する工程、
(b)第2主面および前記第2主面とは反対側の第2裏面を有する基材部と、前記基材部の前記第2主面における中央部に位置し、かつ前記基材部から突出する凸部と、前記基材部の前記第2主面に形成されかつ前記凸部よりも低い支持部とを有する放熱板を準備する工程、
(c)複数の電極パッドが形成された第3主面を有する半導体チップを、前記放熱板の前記凸部に搭載する工程、
(d)前記第2主面が前記配線基板の前記第1主面と対向し、かつ前記凸部が前記貫通孔内に位置し、かつ前記支持部が前記配線基板の前記第1主面に接触するように、前記配線基板の前記第1主面側に前記放熱板を配置する工程、
(e)前記(d)工程後、前記放熱板を前記配線基板に固定する工程、
(f)前記(e)工程後、前記半導体チップの前記複数の電極パッドと前記配線基板の前記複数のボンディングリードとを複数の導電性接続部材を介して電気的に接続する工程、
(g)前記(f)工程後、前記半導体チップおよび前記複数の導電性接続部材を樹脂封止する工程、
を含み、
前記(b)工程で準備された前記放熱板の前記凸部は、溝が形成された第4主面と、前記第4主面と前記基材部の前記第2主面との間に位置する側面とを有しており、
前記(c)工程では、前記凸部の前記第4主面に前記半導体チップを搭載し、
前記(d)工程では、前記貫通孔内に配置された前記凸部の前記側面が前記貫通孔の内壁と対向するように、前記放熱板を前記配線基板の前記第1主面に配置し、
前記(e)工程では、前記凸部の前記第4主面の前記溝を押し広げることで前記凸部の前記側面の一部を前記貫通孔の内壁と接触させて、前記放熱板を前記配線基板に固定することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(e)工程では、治具により、前記凸部の前記第4主面の前記溝を押し広げることを特徴とする半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記放熱板の前記凸部では、前記第4主面の周辺部に前記溝が形成されていることを特徴とする半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記(c)工程では、前記凸部の前記第4主面において、前記溝が形成されている領域よりも中央側に前記半導体チップが搭載されることを特徴とする半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記(g)工程後、
(h)前記配線基板の前記複数のバンプランド上に複数の外部端子をそれぞれ形成する工程、
を更に有することを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
前記(e)工程後、前記凸部の前記側面と前記貫通孔の内壁との間における少なくとも1箇所に、前記凸部の前記側面と前記貫通孔の内壁とが離間しかつ前記配線基板の前記第1主面から前記第1裏面まで繋がる第1隙間部があり、
前記(g)工程では、前記配線基板の前記第1主面側に供給した樹脂材料を、前記第1隙間部を通じて前記配線基板の前記第1裏面側にも供給することを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(g)工程では、前記配線基板の前記第1裏面側に第1封止部が、前記第1主面側に第2封止部が、それぞれ前記樹脂材料によって形成され、
前記半導体チップおよび前記複数の導電性接続部材は前記第1封止部で封止されることを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記(e)工程後、前記凸部の前記側面と前記貫通孔の内壁との間における複数箇所に前記第1隙間部があることを特徴とする半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記(e)工程後、前記支持部が前記配線基板の前記第1主面に接し、前記基材部の前記第2主面と前記配線基板の前記第1主面との間に隙間が形成されており、
前記(g)工程では、前記配線基板の前記第1主面側に供給した前記樹脂材料を、前記隙間および前記第1隙間部を通じて、前記配線基板の前記第1裏面側に供給することを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記(g)工程では、前記隙間および前記第1隙間部にも前記樹脂材料が充填されることを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記第2封止部から前記放熱板の前記基材部の前記第2裏面が露出することを特徴とする半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記(g)工程では、前記凸部の前記側面のうちの前記貫通孔の内壁と直接接していない部分と前記貫通孔の内壁との間にも前記樹脂材料が充填されることを特徴とする半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記(a)工程で準備された前記配線基板の前記貫通孔の平面形状と前記(b)工程で準備された前記放熱板の前記凸部の平面形状とは、それぞれ矩形状であり、
前記第1隙間部は、前記矩形状の四隅の位置にそれぞれ形成されることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(e)工程で前記配線基板に固定された前記放熱板の前記凸部の前記第4主面は、前記配線基板の前記第1主面と前記第1裏面との間の高さ位置にあることを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(e)工程で前記配線基板に固定された前記放熱板の前記凸部の前記第4主面は、前記配線基板の前記第1主面とほぼ同じ高さ位置にあることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程の後に、前記(d)工程が行われ、
前記(d)工程では、前記半導体チップが搭載された前記凸部が前記貫通孔内に位置するように、前記配線基板の前記第1主面側に前記放熱板を配置することを特徴とする半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記(c)工程では、前記半導体チップが前記放熱板の前記凸部の前記第4主面に半田を介して搭載されて接合されることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程の前に、前記(d)工程が行われることを特徴とする半導体装置の製造方法。 - 請求項18記載の半導体装置の製造方法において、
前記(c)工程では、前記半導体チップが前記放熱板の前記凸部の前記第4主面に銀ペーストを介して搭載されて接合されることを特徴とする半導体装置の製造方法。 - 第1主面および前記第1主面とは反対側の第1裏面を有する配線基板であって、前記第1主面から前記第1裏面に到達する貫通孔と、前記第1裏面において前記貫通孔の周囲に形成された複数のボンディングリードと、前記第1裏面に形成されかつ前記複数のボンディングリードとそれぞれ電気的に接続された複数のバンプランドとを有する前記配線基板と、
前記配線基板の前記第1主面と対向する第2主面を有する基材部と、前記基材部の前記第2主面における中央部に位置しかつ前記基材部から突出する凸部と、前記基材部の前記第2主面に形成されかつ前記配線基板の前記第1主面と接触する支持部とを有する放熱板であって、前記凸部が前記配線基板の前記貫通孔内に位置するように前記配線基板の前記第1主面に配置された前記放熱板と、
第3主面と、前記第3主面に形成された複数の電極パッドと、前記第3主面と反対側の第3裏面とを有し、前記放熱板の前記凸部に搭載された半導体チップと、
前記配線基板の前記第1裏面側に形成され、前記半導体チップを封止する第1封止部と、
前記配線基板の前記第1主面側に形成され、前記基材部の一部を封止する第2封止部と、
を含み、
前記放熱板の前記凸部は、溝が形成された第4主面と、前記第4主面と前記基材部の前記第2主面との間に位置する側面とを有しており、
前記放熱板の前記凸部の前記側面の一部は、前記凸部の前記第4主面に形成された前記溝が押し広げられたことで前記貫通孔の内壁と直接的に接触しており、
前記凸部の前記側面と前記貫通孔の内壁との間における少なくとも1箇所に、前記凸部の前記側面と前記貫通孔の内壁とが離間しかつ前記配線基板の前記第1主面から前記第1裏面まで繋がる第1隙間部があり、
前記第1封止部と前記第2封止部とは、前記第1隙間部内に充填された樹脂を介して一体的に繋がっていることを特徴とする半導体装置。
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