JP5013446B2 - Memory control device and display device using the same - Google Patents

Description

  The present invention relates to data write / read control of a memory, and more particularly to a memory control device suitable for a frame buffer circuit of a display device and a display device using the same.

  In a display device that inputs and displays image signals, the input image signals are temporarily stored. This is because the input image signal has various resolutions and standards while the speed for use in display is almost constant. For this reason, the input image signal is once stored in the storage means and read at a speed used for display.

  There is a method of using memory elements called multi-port and dual-port which can simultaneously read and write as image signal storage means such as a display device for a frame memory. In this method, since the memory element itself can perform writing and reading simultaneously at a dedicated port, control is easy, and it has been used for a display device, a graphic card used for image output of a computer, and the like. However, this type of storage element is unique to each company, and the parts cost is also expensive.

  On the other hand, in order to realize cost reduction and high-speed operation, there is a method of using a storage element such as SRAM or SDRAM for a frame memory. In particular, SDRAM is good at low cost. SDRAM, SRAM, and the like have only one port for both reading and writing, and are referred to as a single port memory with respect to the previous storage element. When reading and writing are performed alternately using two single-port memories of this type, a so-called overtaking problem occurs.

  In Patent Document 1, in a method of performing reading and writing using two single-port memories that are advantageous in terms of cost, it is prohibited to use one of the means for detecting the position of reading and writing to overtake the other. Therefore, image disturbance that occurs when overtaking occurs is prevented. Specifically, when overtaking occurs in an image for one frame, different memory read / write controls are performed so as not to be overtaken. However, in this method, even if the overtaking detection method is improved, the contents of the memory on the same side are repeatedly displayed a plurality of times, so that the image quality deteriorates every time reading is performed twice.

Japanese Patent Laid-Open No. 2003-264753

  When writing and reading are alternately performed by using two storage units and the respective operations are controlled independently, there is a concern about interference such as one overtaking the other during the operation. Particularly in the display device, the disturbance of the image caused by the overtaking directly deteriorates the display quality. In contrast to this problem, in the method of monitoring so as not to overtake as in Patent Document 1, there is a problem such as missing updated images due to continuous display of the same image in a state where control is performed so that overtaking does not occur. is there.

  An object of the present invention is to realize a memory control device with few missing images and a high-quality display device using the memory control device.

The memory control device of the present invention includes first and second storage means capable of storing at least one frame of image, write control means for controlling writing to the first or second storage means, and first or second storage means. Output from the read control means for controlling reading from the two storage means, switching means for switching the first and second storage means to be written and read by the write control means and the read control means, and the write control means First address detection means for detecting the completion of the write operation for one frame by inputting the address of the write operation, and the read operation address output from the read control means for inputting the read operation for one frame A second address detecting means for detecting completion of data and a priority for setting a priority for one of the write or read operation to the first or second storage means And a constant means.

  Each time the switching means detects the completion of the writing or reading operation for one frame, the first or second address detecting means of the writing or reading operation to which the priority is set detects the completion of the first or second operation. The storage means is switched. In addition, the write control means or the read control means in the write or read operation for which priority is not set so as to write or read to continuous addresses before and after the switching of the first or second storage means. To do. In one embodiment, the first or second address detection means for the write or read operation for which priority is not set is the address input immediately before the switching between the first and second storage means, The write control means or the read control means for the write or read operation for which priority is not set is output to the write control means or the read control means based on the address from the first or second address detection means. An address for performing the next writing or reading operation is generated, and writing or reading to a continuous address is performed before and after switching between the first and second storage means.

  In the memory control device of the present invention, any one of the reading and writing operations is surely performed for each frame, while the operation for switching the target storage means in the middle of one frame is continuous even if the storage means are different. By performing the read / write operation on the address, image loss is reduced.

  The memory control device of the present invention further includes resolution detection means for detecting resolution information of the number of scanning lines of one frame and the number of data in the scanning lines for the input image signal. The first and second address detection means compare the input address with the resolution information and detect the completion of the writing or reading operation for one frame. As a result, images with various resolutions can be handled.

  In the memory control device of the present invention, the priority setting means has means for setting the priority for the write or read operation by comparing the write speed and the read speed. For example, when the writing speed is faster than the reading speed, the priority is set for the reading operation, and when the writing speed is vice versa, the priority is set for the writing operation. As a result, information that has been discarded without being read because the read / write operation has not been completed can be read, and display that reflects the contents that could not be reflected before can be performed, thereby improving image quality. Improve.

  Further, the memory control device of the present invention has means for setting a priority for a write or read operation by an external signal, and the setting result is determined by comparing the write speed and the read speed. Give priority. Thereby, the user can forcibly give priority to writing to or reading from the storage means as required, and the image quality can be adjusted according to the user's desire.

  In the memory control device of the present invention, the first and second storage means are constituted by a single port memory. Thereby, reduction of the component cost of a memory | storage means is implement | achieved.

  The present invention also provides a display device using such a memory control device as a frame buffer circuit for an input image. Thereby, a display device with improved image quality is realized.

  According to the memory control device of the present invention, with respect to the operation for which priority is set, the operation with priority is performed without omission by switching the storage means for each operation of one frame, and for the operation without priority, Each time the storage unit is switched, the operation is performed on consecutive addresses before and after the switching of the storage unit based on the address detected by the address detection unit, thereby reducing image loss and improving image quality.

  Further, according to the display device of the present invention, as a frame buffer of the display device, a storage unit that performs only one of writing and reading is used to write or read a continuous image, thereby reducing component costs. In addition, good image quality can be realized by writing or reading continuous images.

  FIG. 1 is a block diagram showing a configuration example of a memory control device according to the present invention. In the figure, thick lines indicate image signals, and thin lines indicate various control signals.

  The input image signal for one frame is written to either one of the storage means 10-1 and 10-2 capable of storing at least one input image frame by the writing control means 50. During the writing period, reading is performed from the other by the reading control means 60. By alternately switching this operation by the switching means 70 and 80, even when a single port memory is used for the storage means 10-1 and 10-2, the input image signal can be written and read in parallel. it can. However, writing and reading are performed by different clock signals, so that the writing period and the reading period are different. For this reason, an access collision (overtaking) on the frame memory occurs due to the difference between the writing speed and the reading speed, and the image is disturbed.

  The present invention controls at least one of the operations (write or read operation with priority set) by controlling the switching means 70 and 80 by the priority setting unit 90 for setting priority to either read or write operation. Performs the switching operation of the storage means 10-1 and 10-2 for every operation of one frame, and the operation without priority is continuously performed before and after the switching of the storage means 10-1 and 10-2. By performing the operation on the address, the disturbance of the image is reduced. The present invention is described in detail below.

  The resolution detection means 20 detects the number of pixels on the scanning line of the frame (number of data) and the number of scanning lines of one frame for one frame image, and outputs it to the address detection means 30 and 40 as resolution information. The resolution information can be detected by counting the number of scanning lines in one frame and counting the number of clocks in one scanning line. Usually, for these detections, a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal used for controlling one frame image are used. In FIG. 1, an image of one frame is shown as a control signal together with an image signal that is pixel information, a horizontal synchronization signal, a vertical synchronization signal, a clock signal, and the like.

  The writing control means 50 generates a control signal for writing an image of one frame into the storage means 10-1 or 10-2 via the switching means (1) 70. The generated control signals include an address indicating a place to be written, a clock synchronized with the data to be written, and a control signal necessary for writing to the storage means to be used. For example, with regard to the address, the write control means 50 includes an address generation circuit, and generates an address for performing the write operation at time t + 1 based on the address written at time t. Among the control signals, the address signal is simultaneously output to the address detection means (1) 30. This address signal includes a scanning line address (corresponding to the number of scanning lines of resolution) indicating the position of the scanning line currently written, and a scanning line address (resolution resolution) indicating the data position of writing on one scanning line. Equivalent to the number of data in the scanning line).

  In the address detecting means (1) 30, the resolution information (the number of data in the scanning line, the number of scanning lines in one frame) previously detected by the resolution detecting means 20 and the address from the writing control means 50 (the address in the scanning line being written) And the scanning line address), the end of the writing operation for one frame is detected and output to the priority setting means 90. Further, the address detecting means 1 (30) always temporarily stores the input address (the address within the scanning line being written, the scanning line address) that is currently being written, and the storage means 10 during the writing operation. -1 and 10-2 are switched, the temporarily stored address is returned to the write control unit 50 by the notification from the priority setting unit 90, and the write control unit 50 continues to the switched storage unit. Allow write operation to continue with address. That is, the address detection means (1) 30 always stores the address at which the writing was completed immediately before the writing control means 50 performs the writing control, so that the writing operation is not set to the priority right. Images can be continuously written to consecutive addresses before and after switching of the storage means 10-1 and 10-2.

  Similarly for reading, the reading control means 60 controls a control signal (address, clock, and other reading means for reading out images from the storage means 10-1 or 10-2 that performs the reading operation). Control signal). The address signal (scan line address being read, scan line address) is simultaneously output to the address detection means (2) 40. In the address detecting means (2) 40, the priority setting means can also be used to detect the end of the reading operation for one frame by reading the resolution information previously detected by the resolution detecting means 20 and comparing the address with the address from the control means 60. Output to 90. Further, the address detection means (2) 40 always temporarily stores the address (the address within the scanning line being read, the scanning line address) currently being read out, and the storage means 10-1 in the middle of the reading operation. When 10-2 is switched, the temporarily stored address is returned to the read control means 60 by the notification from the priority setting means 90, and the read control means 60 reads the address continuously in the switched storage means. Allow the operation to continue.

  The priority setting means 90 sets a priority for one of the write operation and the read operation with respect to the other. The operation set with the priority is performed every time the address detection means 30 or 40 of the operation set with the priority detects the completion of the operation for one frame, regardless of the operation status of the other. A switching signal is output to 80 to switch the writing and reading operations of the storage means 10-1 and 10-2. At the same time, the priority setting unit 90 notifies the switching to the address detection unit that does not set the priority, and the address detection unit writes the previously temporarily stored address in accordance with this notification. Or it returns to the read control means 60.

  FIG. 2 shows a block diagram of an embodiment of the address detection means (1) 30 on the write operation side. The number-of-scanning-line data within one frame and the number-of-data data within one scanning line of resolution information detected by the resolution detecting means 20 are temporarily stored in the registers 310 and 320, respectively. This value is updated when the resolution of one frame is changed. The write control means 50 also receives, as address information for the current write operation, a scan line address that indicates the number of scan lines that are currently written, and a scan line that indicates the data position where writing is performed on one scan line. The internal address is input and sequentially stored in the registers 370 and 380, respectively. The values of register (1) 310 and register (3) 370 are compared by comparator (1) 330, and the values of register (2) 320 and register (4) 380 are compared by comparator (2) 340, respectively. The values of the registers 370 and 380 are supplied to the comparators 330 and 340 through the output controllers 350 and 360, respectively.

  When priority is set for writing, the comparison result of the comparators 330 and 340 shows that the number of scanning lines (scanning line address) being written matches the number of one frame (comparator (1) output = H ) When the number of data in the scanning line (address in the scanning line) during writing coincides with the number of data in one scanning line (comparator (2) output = H), the AND circuit 390 makes these two comparators. By taking the logical product of 330 and 340, it is detected that writing of one frame has been completed. Upon receiving this detection, the priority setting means 90 outputs a switching signal to the switching means 70 and 80. The switching means 70 and 80 specify the connection destinations of the write control means 50 and the read control means 60, respectively, as storage means (1 ) From 10-1 to storage means (2) 10-2 or from storage means (2) 10-2 to storage means (1) 10-1. As a result, in the new connection destination storage means of the write control means 50, writing for the next one frame starts from the head address.

  On the other hand, when the priority is set to read, even if it is detected that the address detection means (1) 30 shown in FIG. No switching signal is output to 70 and 80. Therefore, the storage means 10-1 and 10-2 are not switched.

  Instead, when the address detection means (2) 40 detects the completion of reading for one frame, the priority setting means 90 outputs a switching signal to the switching means 70 and 80, and the storage means 10-1, 10 -2 write / read operation is switched.

  At the same time, the priority setting unit 90 notifies the address detection unit (1) 30 of the switching. When the address detection means (1) 30 receives the switching notification from the priority setting means 90, the output control sections 350 and 360 output the outputs of the registers 370 and 380 to the original write control means (1) 50 only at that time. To do. Other than this, it outputs to the comparators 330 and 340 as before.

  The write control means 50 uses consecutive addresses for generating addresses for performing write operations. In this case, it is possible to easily control the address to be written by generating the address to be written sequentially based on the address written immediately before (add a constant to the address written immediately before). By doing so, the address to be written next can be calculated). As a result, the addresses output from the output control units 350 and 360 of the address detection means (1) 30 to the write control means 50 are set to the addresses written immediately before this, so that the storage means 10-1 and 10 Even if -2 is switched, continuous writing can be continued.

  The configuration and operation of the address detection unit (1) 30 on the write side have been described above, but the configuration and operation of the address detection unit (2) 40 on the read side are exactly the same.

  According to this embodiment, one of the writing and reading to the storage means can be operated by switching the storage means for each frame by setting the priority, and the operation in which the priority is not set is address detection. By using the means, even if the storage means is switched during the operation, the operation can be performed on consecutive addresses before and after the switching.

  Note that the priority setting unit 90 may directly output the storage unit switching notification to the write control unit 50 or the read control unit 60 on the side where the priority is not set. The write control means 50 or the read control means 50 that has received the switching notification generates the next address based on the address that was written or read immediately before, and continues writing or reading to the switched storage means. . This makes it possible to operate on consecutive addresses before and after switching without acquiring addresses from the address detection means 30 or 40, eliminating the need for output control units for the address detection means 30 and 40. The configuration of the address detection means 30 and 40 is simplified.

Next, a method for setting priority is described. First, an embodiment will be described in which priority is automatically set according to the size of the writing speed and the reading speed. When the write speed is V1 and the read speed is V2, the priority combinations are read priority when V1> V2, write priority when V1> V2, read priority when V1 <V2, and write priority when V1 <V2. There are four possible ways. Hereinafter, the write and read operations in each case will be described with reference to FIG.
(A) V1> V2 Read priority (Fig. 3 (a))
Since writing is faster than reading, writing (writing 0, 1, 2, 3, 4) by a plurality of frames is performed in one frame reading period (reading 0 period in FIG. 3A). However, since it is written in the same storage means during this period, overwriting is performed, and the content actually read out by the read 1 is the latter half of the write 3 and the first half of the write 4 in FIG. This is an image corresponding to one hatched frame. The display corresponding to one frame is displayed for each substantially constant frame corresponding to the ratio of the writing / reading speed, and the frame that is not displayed is overwritten and erased as described above.
(B) V1> V2 Write priority (FIG. 3B)
Each time the writing earlier than the reading is completed for one frame, the storage means is switched. For this reason, reading is a combination of a plurality of frames. Read 0 in FIG. 3A is an image obtained by reading only a part from one frame written before the storage means is switched (hatched portion in FIG. 3B). Each time the storage means is switched, only a part of one frame is read, and that one frame becomes one newly written (updated) frame each time the storage means is switched. Is partially reflected in the read result.
(C) V1 <V2 Read priority (Fig. 3 (c))
Since reading is prioritized, the storage means is switched every time one frame is read. In FIG. 3C, it is assumed that writing is performed by writing one frame over the time of about four frames for reading. At this time, only the portion indicated by hatching in FIG. 3C can be updated by writing for one frame of reading. The rest is the contents of the previous writing. Reading is performed by sequentially updating only a part of the storage means having a capacity of one frame.
(D) V1 <V2 Write priority ((d) in FIG. 3)
Data for which writing for one frame is completed is read a plurality of times at a reading speed faster than writing. There is a possibility that the mixed contents of two frames may be obtained at the portion where the storage means is switched. The same frame is simply displayed except for the part to be switched.

  When V1 = V2, writing and reading are operating at the same speed. In this case, priority setting is not necessary. When both writing and reading are performed from the same address, one output frame consisting of one input frame is output on a one-to-one basis. When the address is shifted, it is displayed as a mixture of two frames regardless of whether writing or reading is prioritized.

  In this way, different images can be formed and displayed depending on the combination of the writing / reading speed and the priority setting. For example, when the writing speed is faster than the reading speed, display using a part of each frame can be performed by giving priority to writing (FIG. 3B). This effectively uses a portion that has been erased by overwriting. When the reading speed is faster than the writing speed, priority can be given to reading, so that a display that is always switched for each part can be performed (FIG. 3C). Conventionally, it is possible to obtain an image in which the same display is performed for a plurality of frames, and the display is always updated with a new frame for the display whose contents are switched in one frame.

  FIG. 4 shows a specific circuit configuration of the priority setting means 90 of this embodiment. Assuming that writing and reading are performed with the same data bus width, the writing speed and the reading speed can be realized by detecting the frequency of the clock used for each operation. The speed comparison can be performed by counting the number of clocks for a certain period and comparing the numbers.

  In FIG. 4, the clock on the writing side is counted by the counting unit (1) 910, and the clock on the reading side is counted by the counting unit (1) 920. The counting units 910 and 920 can be realized by using a counter. The counters 910 and 920 are reset at the same time, and the count result is simultaneously taken into the comparator 930 after a certain period to determine whether it is large or small. In the comparator 930, for example, as shown in FIG.

  The priority setting unit 940 inputs the determination result of the comparator 930, for example, when the writing speed is slower than the reading speed, the writing priority is given. When the writing speed is faster than the reading speed, the reading priority is given. When the speed is slower than the reading speed, the reading priority is set. When the writing speed is higher than the reading speed, the writing priority is set. Also, when the writing speed and the reading speed are equal, the priority is not set. Whether to give priority to writing or reading depending on the magnitude of the writing speed and the reading speed is determined in advance, for example. For this, for example, a loop-up table (LUT) can be used. Further, for example, a flag (latch) can be used for setting the priority.

  In the case of writing priority, the priority setting unit 940 outputs a switching signal to the switching means 70 and 80 upon receiving a write operation completion signal for one frame from the address detection means (1) 30 on the writing side. At the same time, the switching is notified to the address detecting means (2) 40 on the reading side. In the case of read priority, when an operation completion signal for one frame is received from the address detection means (2) 40 on the read side, a switching signal is output to the switching means 70 and 80. At the same time, the switching is notified to the address detecting means (1) 30 on the writing side. As described above, the notification of switching may be directly notified to the write control means 50 or the read control means 60 on the side where the priority is not set.

  FIG. 6 shows another circuit configuration of the priority setting means 90. A method based on the difference in writing / reading speed can be used as one criterion for setting the priority of writing / reading. FIG. 6 shows this. The comparator 930 makes a judgment on the magnitude of the count results of the counting units 910 and 920 shown in FIG. 4 and the quotient of the large count result and the small count result is taken by the divider 950. Thus, the speed ratio is obtained. The rest is basically the same as FIG. In general, division is considered to take time even in the calculation. However, here, there is no problem even if the division is performed because the calculation result may be obtained in a plurality of frames.

  Next, an embodiment in which the user sets the priority setting from the outside will be described. Here, priority is given to writing or reading according to the setting of the user by switching the result of automatically setting the priority of writing and reading shown in FIG. 4 and FIG. 6 from the result of setting from the outside. An example that can be set is shown.

  Specifically, in normal use, the priority is set by the automatic setting on the device side, and the priority determined to switch the changeover switch when the user operates the switch with the intention to set as necessary. By inputting, the user can easily set priority.

  FIG. 7 shows a specific circuit configuration of this embodiment. A signal for determining the priority based on the judgment in the apparatus (priority setting unit) is input to the INUT in FIG. For example, INPUT is set to High for write priority and Low for read priority. A signal indicating the final priority according to this internal determination or user setting is output from OUT. For example, OUT is High for write priority and Low for read priority.

  A switch that outputs the operation result and the operation result by the user is installed outside the device. As a specific example, by touching the switch or holding your hand near the switch, changes in capacitance, minute current, light, etc. are detected, and the user's operation preparation or operation is detected. Install switches that output the specified results by specifying the operation to set the priority. In FIG. 7, the switch for setting the priority is SW2, and the switch for detecting that the user tried to operate is SW1. It is assumed that the ON / OFF state of SW1 maintains the ON / OFF state and performs a toggle operation every time it is detected that the user has attempted to operate. SW1 indicates GND (Low) when ON, and VCC (High) when OFF. Similarly, SW2 is a toggle switch that is alternately held ON and OFF each time it is pressed.

  When the user is not touching SW2 or has not put his hand close to the vicinity, SW1 is OFF and indicates High, and input 2 of AND circuit U1 always inputs High, so output 3 of AND circuit U1. Is determined by input 1 (INPUT). On the other hand, since the output of the inverter circuit U4 is Low, the input 2 of the AND circuit U2 is always Low, and the output 3 of the AND circuit U2 is always Low regardless of the state of SW2. By taking the logical sum of the AND circuits U1 and U2 in the off circuit U3, when this SW1 is OFF, the INPUT signal is output from OUT.

  On the other hand, when the user attempts to operate SW2, SW1 is turned on (in this example, a switch for detecting a change in capacitance), and SW1 causes input 2 of AND circuit U1 to be Low, and the output of AND circuit U1 is always Low. Become. On the other hand, since the output of the inverter circuit U4 becomes High, the AND circuit U2 inputs High to the input 2 and outputs the state of SW2 to OUT via the AND circuit U3 as it is. For example, the user turns off SW2 when writing is prioritized, and turns on SW2 when reading is prioritized.

  According to the present embodiment, a display method that allows the user to freely change the setting and obtain a better image quality is selected from the display methods according to the priority determined by the determination in the device until now. It becomes possible to do. The present embodiment is not limited to the configuration shown in FIG. For example, a mechanical toggle switch having a function of holding one state of both SW1 and SW2 may be used.

  FIG. 8 is a diagram showing a configuration example of a display device using the memory control device of the present invention and a frame buffer circuit for an input image. Although FIG. 8 shows a three-plate reflective liquid crystal (LCOS) projector as a specific example of the display device, the application of the memory control device of the present invention is not limited to moss.

  In FIG. 8, a non-polarized light beam emitted from a light source 1001 such as an ultra-high pressure mercury lamp becomes substantially parallel light in a reflector 1002 and enters an optical integrator 1003. The optical integrator 1003 is for uniformizing the amount of light on the light modulation elements 1010, 1014, and 1016, and generally includes a pair of fly-eye lenses 1003-1 and 1003-2. The light beam exiting the optical integrator 1003 enters the polarization conversion element 1004, and the non-polarized light beam is converted into a light beam having a predetermined polarization direction. The light beam emitted from the polarization conversion element 1004 passes through the condenser lens 1005, is reflected by the reflection mirror 1006, and is then separated into blue, green, and red color components by the blue reflection dichroic mirror 1007 and the green reflection dichroic mirror 1007. . The blue component separated by the blue reflecting dichroic mirror 1007 passes through the relay lens 1009, is reflected by the reflecting mirror 1010, is reflected by the blue polarization beam splitter 1011, and enters the blue light modulation element 1012. Similarly, the green component separated by the green reflection dichroic mirror 1008 is reflected by the green polarization beam splitter 1013 and incident on the green light modulation element 1014, and the red component transmitted through the green reflection dichroic mirror 1008 is for red. The light is reflected by the polarization beam splitter 1015 and is incident on the red light modulation element 1016.

  The light modulation elements 1012, 1014, and 1016 perform light modulation by rotating the polarization direction of light incident by an electric signal. In FIG. 8, it is assumed that reflection type liquid crystal (LCOS) is used for the light modulation elements 1012, 1014, and 1016. The blue, green, and red light beams that are respectively light-modulated and reflected by the light modulation elements 1012, 1014, and 1016 are transmitted through the polarization beam splitters 1011, 1013, and 1015 for the respective colors, and are combined by the dichroic prism 1017 to be a projection lens. 1018 is projected onto the screen 1019.

  On the other hand, the frame buffer circuit 1020 receives a control signal and an image signal from the outside, and alternately switches between the two storage means (frame memories) 10-1 and 10-2 to simultaneously perform the image signal writing and reading operations. The image signal is output sequentially.

  The frame buffer circuit 1020 uses the memory control device shown in FIG. As described above, the write / read operations of the storage means 10-1 and 10-2 are independently controlled by the write control means 50 and the read control means 60, but the priority is set by the priority setting means 90. For writing or reading, the storage means 10-1 and 10-2 are switched for each operation of one frame to perform writing or reading operation with priority without omission, and for the operation without priority, the storage means 10 -1 and 10-2 each time switching is performed, writing or reading operation is performed to consecutive addresses before and after switching of the storage means based on the addresses detected by the address detection means 30 and 40, thereby reducing image loss. Good image quality can be realized.

  In the frame buffer circuit 1020, for example, SDRAM is used for the storage means 10-1 and 10-2. SDRAM can only perform one of the operations of writing and reading, but since it operates in synchronization with the clock, multi-port VRAM, FIFO, etc. that can perform writing and reading asynchronously from the memory structure at high speed Compared to low price. For this reason, by using SDRAM for the storage means 10-1 and 10-2, it is possible to realize a display device with high-speed operation and reduced component costs.

  Although omitted in FIG. 8, the image signal is composed of three colors of red, blue, and green, and the frame buffer circuit 1020 actually has three components of red, blue, and green. The image processing circuit 1030 performs image processing such as resolution conversion for each of the red, blue, and green image signals output from the three frame buffer circuits, and outputs the image processing to the LCOS control circuit for each color. The red LCOS control circuit 1040 generates a control signal for light modulation of the red light modulation element (LCOS) 1016, a gradation signal by each pixel constituting the LCOS, and the like, and generates a red light modulation element (LCOS). Control 1016 light modulation. Although omitted in FIG. 8, the same applies to the blue and green LCOS control circuits.

It is a block diagram which shows the structural example of the memory control apparatus of this invention. It is a block diagram which shows the structural example of the address detection means (1) of FIG. It is a figure which shows the relationship between the priority setting by writing / reading speed, and writing / reading operation. It is a figure which shows the structural example of the priority setting means of FIG. It is a figure which shows the example of the judgment result of the comparator of FIG. It is a figure which shows another structural example of the priority setting means of FIG. It is a figure which shows the structural example in the case of setting a priority from the outside. It is a figure which shows the Example of the display apparatus which uses the memory control apparatus of this invention for the frame buffer circuit.

Explanation of symbols

10-1, 10-2 Storage means 20 Resolution detection means 30, 40 Address detection means 50 Write control means 60 Read control means 70, 80 Switching means 90 Priority setting means 1001 Light source 1012, 1014, 1016 Light modulation element (LCOS)
1017 Dichroic prism 1018 Projection lens 1019 Screen 1020 Frame buffer circuit 1030 Image processing circuit 1040 LCOS control circuit

Claims (8)

First and second storage means capable of storing at least one frame of image;
Write control means for controlling writing to the first or second storage means;
Reading control means for controlling reading from the first or second storage means;
Switching means for switching between the first and second storage means to be written and read by the write control means and the read control means;
First address detecting means for inputting the address of the write operation output from the write control means and detecting completion of the write operation for one frame;
Second address detection means for inputting the address of the read operation output from the read control means and detecting completion of the read operation for one frame;
Priority setting means for setting a priority for one of the write or read operations to the first or second storage means;
Each time the switching means detects the completion of the writing or reading operation for one frame by the first or second address detecting means of the writing or reading operation for which the priority is set, Switching the second storage means;
The write control means or read control means for the write or read operation for which priority is not set performs writing or reading to consecutive addresses before and after switching of the first or second storage means. Memory control device. The memory control device according to claim 1.
When the first or second address detecting means of the write or read operation for which the priority is not set is switched between the first and second storage means, the address inputted immediately before is changed to the priority right. Is output to the write control means or read control means of the write or read operation not set,
The write control means or the read control means generates an address for performing the next write or read operation on the basis of the address from the first or second address detection means, and the first and second storages A memory control device for performing writing or reading to continuous addresses before and after switching means. The memory control device according to claim 1 or 2,
The input image signal further includes resolution detection means for detecting resolution information of the number of scanning lines in one frame and the number of data in the scanning lines,
The memory control device according to claim 1, wherein the first and second address detecting means detect the completion of writing or reading operation for one frame by comparing the input address with the resolution information. The memory control device according to any one of claims 1 to 3,
The memory control apparatus according to claim 1, wherein the priority setting means includes means for setting a priority for a write or read operation by comparing a write speed and a read speed. The memory control device according to any one of claims 1 to 3,
The memory control apparatus according to claim 1, wherein the priority setting means has means for setting priority for a write or read operation by an external signal. The memory control device according to any one of claims 1 to 3,
The priority setting means compares the write speed with the read speed, sets the priority for the write or read operation, and sets the priority for the write or read operation by an external signal. A memory control apparatus that prioritizes the setting result of the second means. The memory control device according to any one of claims 1 to 6,
The memory control device according to claim 1, wherein the first and second storage means are constituted by a single port memory.   A display device comprising the memory control device according to claim 1 as a frame buffer circuit for an input image.

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