JP2004184457A - Image processing apparatus and image display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To overcome the problem in which processing including even pixels which are vertically arrayed can not be adapted to at a high processing speed. <P>SOLUTION: A plurality of image processing parts 1 to 4 are provided which divide one frame of display image data into a plurality of subframes to generate display image data corresponding to the respective subframes and source image data of a plurality of lines are inputted to the plurality of image processing parts 1 to 4 at the same time and processed in parallel to generate display image data. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing device that performs at least resolution conversion processing of original image data, and an image display device having the image processing device.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the resolution of displayed images has been increasingly increased due to the dramatic increase in the processing capability of computers, and accordingly, demands for higher resolution have been increasing in image display devices such as projectors.
On the other hand, in an image display device, various processes are often performed on an original image for display. However, as the resolution increases, an ever higher processing speed is required. For example, QXGA (2048 horizontal pixels × 1536 vertical pixels) requires a clock frequency of about 300 MHz for processing, which is practically difficult to realize.
[0003]
Conventional techniques for solving such problems and realizing high-resolution image processing are described in Patent Documents 1 and 2.
The prior art described in Patent Document 1 is configured to input four-phase image data, provide four processing circuits corresponding to the four-phase input image data, and process the four-phase input image data in parallel. Clock frequency is reduced.
[0004]
The prior art described in Patent Literature 2 further increases the number of phases of input image data that has been converted into four phases to the number of phases necessary for enlarging / reducing processing using a delay unit, and selects four filter operations in the subsequent stage by a selection unit. The multi-phase input image data is selectively output corresponding to each of the sections, and the multi-phase input image data from the selection means is processed in parallel by four filter operation sections to lower the clock frequency.
[0005]
[Patent Document 1]
JP 2001-142451 A
[Patent Document 2]
JP 2001-143060 A
[0006]
[Problems to be solved by the invention]
In each of the above prior arts, a plurality of processing circuits are provided to process input image data in parallel, thereby lowering the clock frequency even for high-resolution images, enabling processing similar to that of conventional low-speed processing. It is something to try.
However, these conventional techniques are all used when the data of four pixels continuous in the horizontal direction is converted into four phases as input image data, and therefore, the four processing circuits are also used for the pixels continuous in the horizontal direction. It is limited to a configuration that performs processing.
[0007]
However, in general, when image processing is performed on original image data to generate display image data, processing is often performed including a plurality of pixels arranged not only in the horizontal direction but also in the vertical direction. Thereby, a higher quality display image can be obtained.
For example, general methods of resolution conversion include “linear interpolation” and “convolution interpolation (cubic convolution interpolation)”. Both of them generate a coordinate data of each pixel of the display image on the original image by inversely mapping each pixel of the display image on the coordinates of the original image.
[0008]
The linear interpolation method assigns, as display data, a weighted average of data of four adjacent (2 horizontal pixels × 2 vertical pixels) original pixels for each display pixel in accordance with coordinate data. Good display quality is obtained.
The convolution interpolation method refers to 16 (4 × 4) input pixels adjacent to each display pixel and assigns a value by weighting according to a cubic function approximation of a sync function. This method is excellent in the preservability of the edge portion of the text and the line drawing, and can obtain a better display quality.
[0009]
That is, since the above-described conventional technology is limited to processing only for pixels arranged in the horizontal direction as described above, it cannot be adapted to processing including such pixels arranged in the vertical direction. There are drawbacks. If it is attempted to cope, first, processing is performed only on pixels arranged in the horizontal direction, the result is stored in the memory, data is sequentially read out from the memory, and processing is performed on the pixels arranged in the vertical direction. In this case, more processing circuits and memories are required, the circuit becomes large-scale and expensive, and the number of times of processing is doubled, so that there is a problem that the effect on the processing speed is reduced. .
[0010]
The present invention solves the above-described disadvantages of the prior art, enables image processing including pixels arranged not only in the horizontal direction but also in the vertical direction, and enables high-speed and high-resolution image processing. It is an object of the present invention to provide an image processing apparatus that can realize high quality. It is another object of the present invention to provide an image processing apparatus capable of performing image processing even when original image data is not input at a time as much as necessary for processing.
[0011]
Another object of the present invention is to provide an image processing apparatus capable of appropriately responding to input of original image data having various resolutions.
Another object of the present invention is to provide an image processing apparatus capable of reducing the load on the coordinate data generating means when the coordinate data generating means also performs other various controls at the same time.
Another object of the present invention is to provide an image processing apparatus capable of speeding up image processing.
Still another object of the present invention is to provide a high-resolution and high-quality image display device.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 is an image processing apparatus that processes original image data to generate display image data, wherein one frame of the display image data is divided into a plurality of subframes, A plurality of image processing units for generating display image data corresponding to each sub-frame are provided, and the display image data is obtained by simultaneously inputting the original image data for a plurality of lines to the plurality of image processing units and performing parallel processing. To generate.
[0013]
According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the image processing unit has a resolution conversion processing unit that enlarges or reduces an original image.
[0014]
The invention according to claim 3 is the image processing device according to claim 1 or 2, further comprising a frame memory for storing the original image data, wherein the original image data is read from the frame memory and the plurality of image processing units are used. At the same time.
[0015]
According to a fourth aspect of the present invention, in the image processing apparatus according to any one of the first to third aspects, the image processing section holds original image data holding a part or all of the input original image data. It has a part.
[0016]
According to a fifth aspect of the present invention, in the image processing apparatus according to any one of the first to third aspects, the image processing section holds original image data holding a part or all of the input original image data. It has a part.
[0017]
According to a sixth aspect of the present invention, in the image processing apparatus according to the fifth aspect, there is provided an original image size detecting means for detecting a size of an original image from a synchronization signal inputted together with the original image data from the outside, and The generating means generates the coordinate data based on the original image size detected by the original image size detecting means.
[0018]
According to a seventh aspect of the present invention, in the image processing apparatus according to any one of the fourth to sixth aspects, the coordinate data includes, for each pixel of the display image, a plurality of original images adjacent on the coordinates of the original image. The image processing unit includes address information of a pixel, and the image processing unit selects and processes the corresponding original image data of the original image data holding unit based on the address information.
[0019]
According to an eighth aspect of the present invention, in the image processing apparatus according to any one of the fourth to seventh aspects, the coordinate data includes, for each pixel of the display image, a plurality of original images which are adjacent on the coordinates of the original image. The image processing unit includes a relative position information between a pixel and the display pixel, the image processing unit processes the original image data selected from the original image data holding unit based on the address information based on the relative position information, and displays the display pixel. Generate data.
[0020]
According to a ninth aspect of the present invention, in the image processing device according to any one of the fifth to eighth aspects, the image processing unit has a coordinate data storage unit that stores the coordinate data, and performs the image processing. This is performed based on the coordinate data read from the coordinate data storage unit.
[0021]
According to a tenth aspect of the present invention, in the image processing apparatus according to any one of the seventh to ninth aspects, the image processing unit stores the corresponding original image data from the original image data holding unit based on the address information. They are selected and processed at the same time.
[0022]
According to an eleventh aspect of the present invention, in the image processing device according to the tenth aspect, the original image data holding unit has a line buffer, and the image processing unit receives the original image data from the line buffer and receives the address. It has a selection means for simultaneously outputting the corresponding original image data according to the information.
[0023]
According to a twelfth aspect of the present invention, there is provided the image processing apparatus according to any one of the first to eleventh aspects, wherein display image data of a plurality of sub-frames generated in the plurality of image processing units are combined. One frame of display image data is generated, and an image of one frame is displayed based on the display image data.
[0024]
According to a thirteenth aspect of the present invention, there is provided the image processing apparatus according to any one of the first to eleventh aspects, wherein a display image data of a plurality of sub-frames generated by the plurality of image processing units is displayed on a display screen. In this case, an image for one frame is generated by displaying an image in a time-division manner.
[0025]
According to a fourteenth aspect of the present invention, in the image display device according to the thirteenth aspect, an image is displayed in a time-division manner at a plurality of different positions in a horizontal direction and a vertical direction on a display screen by the display image data of the plurality of sub-frames. Thus, an image for one frame is generated.
[0026]
According to a fifteenth aspect of the present invention, in the image display device according to the thirteenth aspect, a spatial light modulator in which a plurality of pixels capable of controlling light according to display image data are two-dimensionally arranged; An illumination device for illuminating light, an optical device for observing an image pattern displayed on the spatial light modulator, the image processing device according to any one of claims 1 to 11, and the image processing device Driving means for displaying an image on the spatial light modulator in a time-division manner with display image data of a plurality of sub-frames generated by the plurality of image processing units, and from each pixel of the spatial light modulator to the optical device. Optical path shift means for deflecting the optical path of the outgoing light, and displaying the image pattern in a state where the display position is shifted in accordance with the state of deflection of the optical path for each sub-frame, whereby the spatial light modulation is performed. It is for displaying by multiplying the number of pixels of the apparent child.
[0027]
According to a sixteenth aspect of the present invention, in the image display device according to the fifteenth aspect, the number of times of the optical path deflection by the optical path shifting means and the number of times of the time division are the same.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a first embodiment of the present invention. The first embodiment is an example of an image processing apparatus. In the first embodiment, a plurality of image processings for enlarging or reducing an original image by dividing one frame of display image data into four sub-frames and performing a resolution conversion process on each corresponding sub-frame by a linear interpolation method. It has parts 1 to 4. Here, one frame is divided into, for example, four subframes in the horizontal direction.
[0029]
In FIG. 1, Ri, Gi, and Bi are red, green, and blue analog image signals input to the first embodiment, respectively. Here, FIG. 1 shows only the portion relating to the red analog image signal Ri of the first embodiment, but also the portion relating to the analog image signals Gi and Bi of other colors of the first embodiment shown in FIG. The analog image signals Gi and Bi of other colors are processed in the same manner as the image signal Ri and have the same configuration. The signals HD and VD are a horizontal synchronizing signal and a vertical synchronizing signal input to the first embodiment corresponding to the input image signal, respectively.
[0030]
The video amplifier 5 amplifies the image signal Ri to an appropriate level. The synchronous clock reproducing circuit 6 reproduces a clock WCK synchronized with the input image signal Ri from the horizontal synchronous signal HD and outputs the clock. The image signal ARi from the video amplifier 5 is input to the A / D conversion circuit 7 and is converted by the A / D conversion circuit 7 into digital image data DRi based on the synchronization clock WCK.
[0031]
The original image size detecting means 8 detects the number of scanning lines by counting the number of pulses of the horizontal synchronizing signal HD within one frame period, and detects effective pixels within one horizontal period from the synchronizing clock WCK from the synchronizing clock reproducing circuit 6. By detecting the number, the size of the input original image is detected.
[0032]
The writing control circuit 9 generates and outputs a writing control signal WA for writing the image data Dri to the frame memory 10 from the original image size detection signal SIZE from the original image size detecting means 8. Here, the write control signal WA includes a write address, and the write address includes a horizontal address portion corresponding to the main scanning direction and a vertical address portion corresponding to the sub-scanning direction.
[0033]
The frame memory 10 sequentially writes the image data DRi from the A / D conversion circuit 7 in synchronization with the synchronization clock WCK from the synchronization clock reproduction circuit 6 according to the control signal WA from the writing control circuit 9. Note that the frame memory 10 is a memory having a dual port function capable of reading image data asynchronously with writing by a read address RA from a read control circuit 11 described later.
[0034]
The coordinate data generating means 12 internally creates a coordinate system of the original image based on the original image size detection signal SIZE from the original image size detecting means 8, and inversely maps each pixel of the display image on the coordinates of the original image. To generate coordinate data C1 to C4 of each display pixel on the original image. The coordinate data C1 to C4 correspond to the display pixels of each subframe generated by the image processing units 1 to 4, respectively, and are therefore input to the corresponding image processing units 1 to 4, respectively. As the coordinate data generating means 12, for example, a one-chip microcomputer can be used.
[0035]
FIG. 3 shows an example of the coordinate data C1 to C4. The coordinate data C1 to C4 include command bits, relative position information, and address information. The command bits of the coordinate data C1 to C4 control the processing operation in the image processing units 1 to 4. When the command bits are "1", the image processing units 1 to 4 execute the resolution conversion processing and convert the display pixel data. Generate. The address information of the coordinate data C1 to C4 is horizontal address data of a predetermined pixel among the original image pixels adjacent to the corresponding display pixel, and the relative position information of the coordinate data C1 to C4 is the same as that of the adjacent original image pixel. This shows the positional relationship with the display pixels.
[0036]
FIG. 2 schematically shows a relationship between the display pixel and an original image pixel adjacent thereto, where Sxy is a display pixel, and S11 to S22 are original image pixels adjacent to the display pixel Sxy. In FIG. 2, x1 and y1 are relative position information shown in FIG. The address information of the coordinate data C1 to C4 shown in FIG. 3 is the horizontal address data of the original image pixels S11 and S21 shown in FIG. When the control signal RE from the coordinate data generation means 12 is “1”, the read control circuit 11 generates a read address RA of image data based on the original image size detection signal SIZE from the original image size detection means 8.
[0037]
The frame memory 10 reads the original image data R in accordance with the read address RA from the read control circuit 11 and outputs the same to the image processing units 1 to 4 at the same time. The image processing units 1 to 4 respectively perform resolution conversion processing of the original image data R based on the coordinate data C1 to C4 from the frame memory 10 and output display image data Ro1 to Ro4 and address data A1 to A4. Then, when generating one piece of display pixel data, the image processing units 1 to 4 set the signals PC1 to PC4 to “1”. The coordinate data generating means 12 controls the read address control circuit 11 by outputting a control signal RE to the read address control circuit 11 based on the signals PC1 to PC4 from the image processing units 1 to 4.
[0038]
FIG. 4 schematically shows a configuration example of the image processing unit 1. FIG. 4 shows the image processing unit 1 in FIG. 1. However, the image processing units 2 to 4 are configured in exactly the same way as the image processing unit 1 and transfer image data of other colors in the same manner as the image processing unit 1. To process.
The original image data R read from the frame memory 10 is sequentially written to the shift register 13. When outputting the pixel data for one line, the read control circuit 11 sets the signal H to “1”. When the signal H from the read control circuit 11 becomes “1”, the line buffers 14 and 15 receive and output the data R1 to Rm from the shift register 13 and the data R21 to R2m from the line buffer 14, respectively.
[0039]
The selection unit 16 receives the original image data R11 to R1m for one line from the line buffer 15 and the original image data R21 to R2m for one line from the line buffer 14, and receives the coordinate data C1 from the coordinate data generation unit 12. , The corresponding four pixel data S11 to S22 are selected and output simultaneously.
[0040]
When the command bit of the coordinate data C1 from the coordinate data generating unit 12 is “1”, the resolution conversion processing unit 17 outputs the output image data S11 to S22 from the selecting unit 16 and the coordinate data C1 from the coordinate data generating unit 12. The following operation is performed on the relative position information x1 and y1 to output or display pixel data Ro1 (= Sxy), thereby enlarging or reducing the original image and outputting a one-pulse signal CNT.
[0041]
Sxy = S11 · (1-x1) · (1-y1) + S12 · x1 · (1-y1) + S21 · (1-x1) · y1 + S22 · x1 · y1
The output address generation unit 18 counts the pulse signal CNT from the resolution conversion processing unit 17 and outputs the count value as the address data A1 of the display pixel data Ro1.
[0042]
FIG. 5 schematically shows a configuration example of the selection means 16 in FIG. The selection means 16 is composed of four multiplexers (MUX) 19 to 22. The multiplexers 19 and 20 receive the pixel data R11 to R1 (m-1) and R12 to R1m of the preceding line written in the line buffer 15, respectively. Of pixel data R21 to R2 (m-1) and R22 to R2m.
[0043]
The multiplexer 19 and the multiplexer 20, and the multiplexer 21 and the multiplexer 22, to which the same input terminal receives the image data shifted by one pixel in the horizontal direction. Therefore, the multiplexers 19 to 22 simultaneously output the four adjacent pixels shown in FIG. 2 by selecting the data of the same input terminal according to the coordinate data C1 from the coordinate data generating means 12.
[0044]
FIG. 6 schematically shows another embodiment 2 of the present invention. Embodiment 2 is another embodiment of the image processing apparatus. In FIG. 6, the same components as those in FIG. 1 are not shown except for the frame memory 10.
The differences between the second embodiment and the first embodiment are as follows.
[0045]
The image processing units 23 to 26 read out the control signals RE1 to RE4, respectively, and output them to the control circuit 27.
The image processing units 23 to 26 receive the read address RA from the read control circuit 27.
The address information of the coordinate data from the coordinate data generating means 28 is the horizontal and vertical address data of the pixel S21 shown in FIG.
[0046]
When the original image size detection signal SIZE from the original image size detector 8 changes, the coordinate data generator 28 generates coordinate data C1 to C4 in response to the change, sets the command bit to “1”, and sets the command bit to “1”. To 26. After outputting the data for all the display pixels, the coordinate data generating means 28 does not perform the operation of generating and outputting the coordinate data until the original image size detection signal SIZE from the original image size detecting means 8 changes again.
[0047]
Each of the image processing units 23 to 26 has a coordinate data storage unit, and stores coordinate data C1 to C4 sequentially input from the coordinate data generation unit 28 in the coordinate data storage unit. Then, the image processing units 23 to 26 sequentially read out the coordinate data stored in the coordinate data storage unit and perform a resolution conversion process of the image data R from the frame memory 10.
[0048]
FIG. 7 shows a configuration example of the image processing unit 23. Although FIG. 7 shows the image processing unit 23 in FIG. 6, the image processing units 24 to 26 have the same configuration as the image processing unit 23. In FIG. 7, the same parts as those in FIG. 4 are denoted by the same reference numerals.
[0049]
When the command bit of the coordinate data from the coordinate data generation means 28 is "1", the write / read control circuit 29 sets the control signal W / R to the coordinate data storage unit 30 to the write mode and sets the control signal W / R to the write mode. Is written in the coordinate data storage unit 30. Here, the control signal W / R includes a write control signal and a write address. When the writing of all data to the coordinate data storage unit 30 is completed, the write / read control circuit 29 switches the control signal W / R to the read mode, and reads from the coordinate data corresponding to the first display pixel. Start. Here, the control signal W / R includes a read address.
[0050]
Each time the display pixel data is generated by the resolution conversion processing unit 17 and the signal PC1 from the resolution conversion processing unit 17 becomes “1”, the write / read control circuit 29 sequentially writes the next coordinate data MC1 to the coordinate data MC1. Read from the storage unit 30. The coordinate data MC1 read from the coordinate data storage unit 30 is input to the selection unit 16, the resolution conversion processing unit 17, and the output address generation unit 18 instead of the coordinate data C1, and is input to the comparison unit 31. You.
[0051]
When the signal H from the read control circuit 27 becomes “1”, the comparator 31 reads the image read address RA from the frame memory 10 at that time and the vertical direction of the address information in the coordinate data from the coordinate data storage 30. The addresses are compared. If the addresses do not match, it is determined that the processing for the image data written in the line buffer 15 has not been completed, and the control signal RE1 is set to “0” to set the image data from the frame memory 10. Stop reading. When the image read address RA matches the vertical address of the address information in the coordinate data, the comparison unit 31 sets the signal EN to the line buffers 14 and 15 to “1” and changes the contents of the line buffers 14 and 15. Update.
[0052]
According to the first and second embodiments, a plurality of image processing units 1 to 4, 23 to 26 that divide one frame of display image data into a plurality of subframes and generate display image data corresponding to each subframe. And display image data is generated by simultaneously inputting a plurality of lines of original image data to a plurality of image processing units 1 to 4 and 23 to 26 to generate display image data. , And any image processing becomes possible, and high-resolution image processing can be realized at high speed and with high quality.
[0053]
According to the first and second embodiments, the image processing units 1 to 4 and 23 to 26 have the resolution conversion processing unit 17 that enlarges or reduces the original image. High quality display can be realized.
[0054]
In general, when original image data is input from the outside, a synchronous clock of the image data is reproduced from a synchronous signal input simultaneously with the original image data. However, such a reproduction clock usually has a large amount of jitter and cannot be applied to image processing such as the above-described resolution conversion. Therefore, a memory using a FIFO or the like is provided, and once the input image data is written into the memory in synchronization with the reproduction clock, the image data is read out from the memory using another high-quality clock that does not include jitter and processed. It is common practice to do so.
[0055]
According to the first and second embodiments, the frame memory 10 for storing the original image data is provided, and the original image data is read from the frame memory 10 and input to the plurality of image processing units 1 to 4 and 23 to 26 simultaneously. In addition, high-quality image processing can be easily performed on original image data input from the outside.
[0056]
In the first and second embodiments, original image data may be sequentially input for each horizontal line. In such a case, in order for the image processing units 1 to 4 and 23 to 26 to perform the above-described processing such as the linear interpolation and the convolution interpolation, the original image data for a plurality of lines in at least a vertical direction necessary for the processing is held. You need a way to do that.
[0057]
Therefore, in the first and second embodiments, the image processing unit has the original image data holding units 13 to 15 that hold a part or all of the input original image data. The image processing can be performed even when the input is not performed at one time, so that the data transfer load can be reduced and the design can be simplified.
[0058]
In general, there are various resolutions of original image data, and the image display device has means for appropriately coping with them.
According to the first and second embodiments, since the coordinate data generating means 12 is provided, high-quality image processing can be realized for input of an original image of any resolution.
[0059]
According to the first and second embodiments, the coordinate data includes, for each pixel of the display image, address information of a plurality of adjacent original image pixels on the coordinates of the original image. 23 to 26 select and process the corresponding original image data in the original image data holding units 14 and 15 based on the address information, so that an image processing apparatus can be realized with a simple configuration.
[0060]
According to the first and second embodiments, the coordinate data includes, for each pixel of the display image, relative position information between a plurality of adjacent original image pixels on the coordinates of the original image and the display pixel. The processing units 1 to 4 and 23 to 26 generate display pixel data by processing the original image data selected from the original image data holding units 14 and 15 based on the address information based on the relative position information. An image processing apparatus can be realized with a simple configuration.
[0061]
Generally, a general-purpose arithmetic processing device such as a one-chip microcomputer is used as the coordinate data generating means 12, and this is not limited to the above-described image processing. Control such as light / dark adjustment of a display image is also performed at the same time. Therefore, it is necessary to prevent an unnecessary load from being applied to the arithmetic processing device to perform various controls.
[0062]
According to the second embodiment, the image processing units 23 to 26 have the coordinate data storage unit 30 that stores the coordinate data, and perform the image processing based on the coordinate data read from the coordinate data storage unit 30. Even when various controls are performed simultaneously using a general-purpose arithmetic processing device such as a one-chip microcomputer as the coordinate data generating means 12, the load of image processing can be reduced and more multifunctional functions can be achieved. An image processing device having a highly reliable operation performance can be realized.
[0063]
Further, according to the first and second embodiments, the image processing unit simultaneously selects and processes the corresponding original image data based on the address information of the coordinate data, so that even higher speed processing is possible. A simple image processing apparatus can be realized.
[0064]
FIG. 8 schematically shows Embodiment 3 of the present invention. Embodiment 3 is an embodiment of an image display device.
First, in the third embodiment, the image processing devices 32 to 34 are the image processing devices of the first or second embodiment, and correspond to the three primary color image data Ri, Gi, and Bi of red, green, and blue, respectively. The resolution conversion processing is performed on the three primary color image data Ri, Gi, and Bi to generate three primary color display image data Ro1 to Ro4, Go1 to Go4, and Bo1 to Bo4 of each subframe.
[0065]
The image synthesizing units 35 to 37 convert the image data Ro1 to Ro4, Go1 to Go4, and Bo1 to Bo4 of each subframe generated by the image processing devices 32 to 34 into a format suitable for the input specification of the liquid crystal display panel 38 at the subsequent stage. To generate one frame of display image data, and temporarily store the display image data in an internal buffer memory.
[0066]
The liquid crystal display panel (liquid crystal panel) drive control unit 39 generates a read address RA2 and outputs the read address RA2 to the image synthesizing units 35 to 37. The image synthesizing units 35 to 37 buffer based on the read address RA2 from the liquid crystal panel drive control unit 39. The R, G, and B image data Ro, Go, and Bo stored in the memory are sequentially read and input to the D / A converter 40. The liquid crystal panel drive control section 39 outputs a control signal LC for driving the liquid crystal display panel 38.
[0067]
The D / A converter 40 converts the image data Ro, Go, Bo from the image synthesizing means 35 to 37 into analog image signals ARo, Ago, Abo for driving the liquid crystal pixels of the liquid crystal display panel 38, and outputs them. The liquid crystal display panel 38 is an image obtained by subjecting an input original image to resolution conversion processing based on the control signal LC from the liquid crystal panel drive control section 39 and the analog image signals ARo, Ago, and ABo from the D / A converter 40 to enlarge or reduce the image. Is displayed.
[0068]
According to the third embodiment, the image processing apparatus according to the first or second embodiment is provided, and the display image data of a plurality of sub-frames generated by the plurality of image processing units 32 to 34 is combined to generate one frame. Since the display image data is generated and an image for one frame is displayed by the display image data, the image processing device processes the original image at high speed and high quality to generate high resolution display image data. And an image display device capable of displaying a high-resolution moving image with high quality can be realized.
[0069]
FIG. 9 schematically shows Embodiment 4 of the present invention. Embodiment 4 is another embodiment of the image display device. The differences between the fourth embodiment and the third embodiment are as follows.
The image combining means 35 to 37 of the third embodiment are replaced with image switching means 41 to 43, respectively.
[0070]
The liquid crystal panel drive control unit 44 generates a signal SEL and inputs the signal SEL to the image switching units 41 to 43.
The liquid crystal panel drive control unit 44 sequentially outputs the image data Ro1 to Ro4, Go1 to Go4, and Bo1 to Bo4 of each sub-frame input from the image processing devices 32 to 34 to the image switching units 1 to 3 in response to the signal SEL. And selectively output. The liquid crystal display panel 38 displays an image in a time-division manner for each subframe based on the control signal LC from the liquid crystal panel drive control unit 44 and the analog image signals ARo, Ago, and ABo from the D / A converter 40, thereby displaying one frame. Is formed and displayed.
[0071]
FIG. 10 shows a configuration example of the image switching means 41 to 43. Although FIG. 10 shows the image switching unit 41, the image switching units 42 and 43 have the same configuration as the image switching unit 41.
The subframe buffer memories 45 to 48 temporarily store the image data Ro1 to Ro4 of the respective subframes from the image processing devices 32 to 34, respectively. The sub-frame buffer memories 45 to 48 sequentially read the temporarily stored image data based on the read address RA2 from the liquid crystal panel drive control unit 44. The selection means 49 selects and outputs any one of the image data Rx1 to Rx4 of each subframe from the subframe buffer memories 45 to 48 based on the signal SEL from the liquid crystal panel drive control unit 44.
[0072]
According to the fourth embodiment, an image is displayed in a time-division manner on the display screen by the display image data of a plurality of sub-frames generated by the plurality of image processing units 32 to 34 in the first or second embodiment. Since an image for a frame is generated and displayed, a high-resolution and high-quality image display device can be provided.
[0073]
FIG. 11 schematically shows Embodiment 5 of the present invention. The fifth embodiment is an example of an image display device that displays a single-color image. In the fifth embodiment, the configuration for one color in the fourth embodiment is used, and the liquid crystal display panel 49 is used as a spatial light modulator in which a plurality of pixels capable of controlling light according to display image data are two-dimensionally arranged. 2 is a configuration example of a projector that has been installed.
[0074]
The integrator optical system 50 is composed of, for example, a fly-eye lens array, and makes the light from the light source 51 uniform. The condenser lens 52 is for condensing illumination light from the integrator optical system 50 to the spatial light modulator 49 via the polarizing beam splitter 53 for illumination. Here, the spatial light modulator 49 is a reflective liquid crystal display panel. The light source 51, the integrator optical system 50, and the condenser lens 52 constitute an illumination device that collects light and illuminates the spatial light modulator 49.
[0075]
The display control means 54 is a portion excluding the liquid crystal display panel 49 in the device shown in FIG. 9 and modulates the illumination light incident from the polarization beam splitter 53 on each pixel of the spatial light modulator 49 for each of a plurality of subframes. . The illumination light spatially modulated by the spatial light modulator 49 enters the optical path shift unit 55 via the polarizing beam splitter 53 as image light, and the image light is shifted in the pixel arrangement direction (horizontal direction in this case). Shifted by an amount. The drive unit 56 controls the optical path shift unit 55 using the control signal SEL from the liquid crystal panel drive control unit 44 shown in FIG. 9 as a synchronization signal, and performs the optical path shift in synchronization with the control signal SEL. Note that the polarization beam splitter 53 is for separating illumination light and image light. The light emitted from the optical path shifting means 55 is magnified by the projection lens 57 and projected on the screen 58, and an image pattern in a state where the display position is shifted according to the deflection state of the optical path for each sub-frame is displayed on the screen 58. Thus, the apparent number of pixels of the spatial light modulator 49 is multiplied and displayed.
[0076]
FIG. 12 shows a part of the sixth embodiment of the present invention. Embodiment 6 is an embodiment of a color image display device. In the sixth embodiment, spatial light modulators 49R, 49G, and 49B for three primary colors are provided in place of the spatial light modulator 49 for one color in the fifth embodiment, and the spatial light modulators 49R, 49G, A dichroic mirror 59 is provided between 49B and the polarization beam splitter 53.
[0077]
The red component of the illumination light from the polarization beam splitter 53 is reflected by the dichroic film 59a and the side wall 59c of the dichroic mirror 59 via the air gap 60, enters the spatial light modulation element 49R, and receives the illumination light from the polarization beam splitter 53. The blue component passes through the dichroic films 59 a and 59 b of the dichroic mirror 59 via the air gap 60 and enters the spatial light modulator 49. The green component of the illumination light from the polarizing beam splitter 53 passes through the dichroic film 59a of the dichroic mirror 59 through the air gap 60, is reflected by the dichroic films 59b and 59a of the dichroic mirror 59, and enters the spatial light modulator 49B. The spatial light modulators 49R, 49g, and 59B are driven and controlled by display control means (not shown) to modulate the incident light. These display control means are parts except for the liquid crystal display panel 49 in the apparatus shown in FIG.
[0078]
The illumination light spatially modulated by the spatial light modulators 49R, 49G, and 49B travels in the opposite direction through the dichroic mirror 59 as image light, passes through the polarization beam splitter 53, and is arranged by the optical path shift unit 55 in the pixel arrangement direction (here, horizontal). Direction) is shifted by the set shift amount. The driving unit that drives the optical path shift unit 55 controls the optical path shift unit 55 using the control signal SEL from the liquid crystal panel drive control unit 44 shown in FIG. 9 as a synchronization signal, and performs the optical path shift in synchronization with the control signal SEL. Let
[0079]
The light emitted from the optical path shifting means 55 is magnified by the projection lens 57 and projected on the screen 58, and an image pattern in a state where the display position is shifted according to the deflection state of the optical path for each sub-frame is displayed on the screen 58. Thus, the apparent number of pixels of the spatial light modulator 49 is multiplied and displayed.
[0080]
According to the fifth and sixth embodiments, the spatial light modulator 49 or 49R, 49G, or 49B in which a plurality of pixels capable of controlling the light in accordance with the display image data are two-dimensionally arranged, and the light is applied to the spatial light modulator. Illuminating devices 50 to 52, a screen 58 as an optical device for observing an image pattern displayed on the spatial light modulator 49, and a plurality of image processing units in the image processing device of the first or second embodiment. A driving unit (display control unit) for displaying an image on the spatial light modulator 49 or 49R, 49G, 49B in a time-division manner based on the display image data of a plurality of sub-frames generated in 1-4 or 23-26; An optical path shift means 55 for deflecting the optical path of light emitted from each pixel of the modulation element 49 or 49R, 49G, 49B to the optical device; By displaying an image pattern in which the display position is shifted in accordance with the deflection state of each optical path, the apparent number of pixels of the spatial light modulator 49 or 49R, 49G, 49B is multiplied and displayed. A high-resolution and high-quality image display device can be provided.
[0081]
In the fourth to sixth embodiments, an image for one frame is displayed on the display screen in a time-division manner only on the display screen based on the display image data of a plurality of sub-frames generated by the plurality of image processing units. Was generated and displayed, but by displaying the image in a time-division manner at a plurality of different positions in the horizontal and vertical directions on the display screen based on the display image data of the plurality of sub-frames generated by the plurality of image processing units. An image for one frame may be generated and displayed. For example, in the fifth and sixth embodiments, a plurality of image data displaced by a set amount in the horizontal and vertical directions from the image processing devices 32 to 34 in the sub-frame buffer memories 45 to 48 shown in FIG. (The four image data displaced by one pixel in the horizontal and vertical directions like the pixels S11 to S22 shown) are temporarily stored and the sub-frame buffer is selected by the selection unit 49 based on the signal SEL from the liquid crystal panel drive control unit 44. Each image data from the memories 45 to 48 may be sequentially selected.
In the fifth and sixth embodiments, the number of times of light path deflection by the light path shift unit 55 and the number of times of time division may be the same. In this case, for example, in the fifth and sixth embodiments, a plurality of image data (for example, a plurality of image data displaced by a set amount in the horizontal and vertical directions from the image processing devices 32 to 34 in the subframe buffer memories 45 to 48 shown in FIG. The four image data displaced by one pixel in the horizontal direction and the vertical direction like the pixels S11 to S22 shown in FIG. 2) are temporarily stored, and are selected by the selection unit 49 based on the signal SEL from the liquid crystal panel drive control unit 44. Each image data from the sub-frame buffer memories 45 to 48 may be sequentially selected. In this way, the apparent number of pixels of the spatial light modulator 49 or 49R, 49G, 49B is multiplied by the optical path deflection by the optical path shifting means 55, so that the spatial light modulator having a smaller number of pixels is used. Therefore, the cost can be reduced, and a high-resolution and high-quality image can be displayed on an inexpensive image display device.
[0082]
【The invention's effect】
As described above, according to the present invention, image processing including not only pixels in the horizontal direction but also pixels in the vertical direction can be performed, and any image processing can be performed. High quality can be achieved.
Further, it is possible to display images of various resolutions at the same resolution and with high quality.
Also, high-quality image processing can be easily performed on original image data input from the outside.
[0083]
Further, even when the original image data is not input at a time as much as necessary for the processing, the image processing can be performed, the load of data transfer can be reduced, and the design can be simplified.
Also, high-quality image processing can be realized for input of an original image of any resolution.
[0084]
Further, the image processing apparatus can be realized with an easy configuration.
In addition, even when various controls are simultaneously performed by the coordinate data generation means, the load of image processing can be reduced, and an image processing apparatus having more functions and highly reliable operation performance can be realized.
[0085]
Further, it is possible to realize an image processing apparatus capable of performing higher-speed processing.
Further, the original image can be processed at high speed and high quality by the image processing device to generate high-resolution display image data, and an image display device capable of displaying a high-resolution moving image with high quality can be realized.
Further, a high-resolution and high-quality image display device can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 2 is a diagram schematically illustrating a relationship between a display pixel and an original image pixel adjacent thereto in the first embodiment.
FIG. 3 is a diagram illustrating an example of coordinate data according to the first embodiment.
FIG. 4 is a block diagram schematically illustrating a configuration example of an image processing unit according to the first embodiment.
FIG. 5 is a block diagram schematically illustrating a configuration example of a selection unit in the image processing unit.
FIG. 6 is a block diagram schematically showing a second embodiment of the present invention.
FIG. 7 is a diagram illustrating a configuration example of an image processing unit in the image processing unit 2.
FIG. 8 is a block diagram schematically showing a third embodiment of the present invention.
FIG. 9 is a block diagram schematically showing a fourth embodiment of the present invention.
FIG. 10 is a block diagram illustrating a configuration example of an image switching unit according to the fourth embodiment.
FIG. 11 is a schematic diagram schematically showing a fifth embodiment of the present invention.
FIG. 12 is a schematic view showing a part of Embodiment 6 of the present invention.
[Explanation of symbols]
1-4, 13-26 Image processing unit
5 Video amplifier
6. Synchronous clock recovery circuit
7 A / D conversion circuit
8 Original image size detection means
9 Write control circuit
10 frame memory
11, 27 Read control circuit
12, 28 coordinate data generating means
13 Shift register
14, 15 line buffer
16 Selection means
17 Resolution conversion processing unit
18 Output address generator
29 Write / read control circuit
30 Coordinate data storage unit
31 Comparison section
32-34 Image processing device
35-37 Image synthesis means
38 LCD panel
39, 44 LCD panel drive control unit
40 D / A converter
41-43 image switching means
49, 49R, 49G, 49B spatial light modulator
50 Integrator optical system
51 light source
52 Condenser lens
53 Polarizing beam splitter
54 display control means
55 Optical path shift means
56 Driving means
57 Projection lens
58 screen
59 dichroic mirror

Claims (16)

In an image processing apparatus for processing original image data to generate display image data, a plurality of images for dividing one frame of the display image data into a plurality of subframes and generating display image data corresponding to each subframe An image processing apparatus comprising a processing unit, wherein the display image data is generated by simultaneously inputting the original image data for a plurality of lines to the plurality of image processing units and performing parallel processing. 2. The image processing apparatus according to claim 1, wherein the image processing unit includes a resolution conversion processing unit that enlarges or reduces an original image. 3. The image processing apparatus according to claim 1, further comprising a frame memory for storing the original image data, wherein the original image data is read from the frame memory and input to the plurality of image processing units simultaneously. Image processing device. The image processing apparatus according to claim 1, wherein the image processing unit includes an original image data holding unit that holds a part or all of the input original image data. Image processing device. 5. The image processing apparatus according to claim 1, wherein each pixel of the display image is inversely mapped on coordinates of the original image to generate coordinate data of each display pixel on the original image. An image processing apparatus, comprising: generating means for outputting coordinate data from the coordinate data generating means to the plurality of image processing units corresponding to the sub-frames. 6. The image processing apparatus according to claim 5, further comprising: an original image size detecting unit that detects an original image size from a synchronization signal input from the outside together with the original image data, wherein the coordinate data generating unit includes the original image size. An image processing apparatus, wherein the coordinate data is generated based on an original image size detected by a detection unit. The image processing apparatus according to claim 4, wherein the coordinate data includes, for each pixel of the display image, address information of a plurality of adjacent original image pixels on the coordinates of the original image; An image processing apparatus, wherein the image processing unit selects and processes the corresponding original image data in the original image data holding unit based on the address information. 8. The image processing device according to claim 4, wherein the coordinate data is, for each pixel of the display image, a relative value between a plurality of adjacent original image pixels on the coordinates of the original image and the display pixel. 9. Including position information, the image processing unit generates the display pixel data by processing the original image data selected from the original image data holding unit based on the address information based on the relative position information. Image processing device. The image processing apparatus according to claim 5, wherein the image processing unit has a coordinate data storage unit that stores the coordinate data, and reads out the image processing from the coordinate data storage unit. An image processing apparatus characterized in that the image processing is performed based on coordinate data obtained. 10. The image processing apparatus according to claim 7, wherein the image processing unit simultaneously selects and processes the corresponding original image data from the original image data holding unit based on the address information. Characteristic image processing device. 11. The image processing device according to claim 10, wherein the original image data holding unit has a line buffer, and the image processing unit receives the original image data from the line buffer and converts the corresponding original image data according to the address information. An image processing apparatus comprising a selection unit for outputting at the same time. An image processing apparatus according to claim 1, wherein display image data of a plurality of sub-frames generated by the plurality of image processing units are combined to display image data of one frame. An image display device that generates and displays an image of one frame using the display image data. An image processing apparatus according to any one of claims 1 to 11, wherein an image is displayed in a time-division manner on a display screen using display image data of a plurality of sub-frames generated by the plurality of image processing units. An image display device for generating an image for one frame. 14. The image display device according to claim 13, wherein an image for one frame is displayed in a time-division manner at a plurality of different positions in a horizontal direction and a vertical direction on a display screen by the display image data of the plurality of sub-frames. An image display device characterized by generating. The image display device according to claim 13, wherein a plurality of pixels capable of controlling light in accordance with display image data are two-dimensionally arranged, a spatial light modulator, and a lighting device that illuminates the spatial light modulator with light. An optical device for observing an image pattern displayed on the spatial light modulator, the image processing device according to any one of claims 1 to 11, and the plurality of image processing units of the image processing device. Driving means for displaying an image on the spatial light modulator in a time-division manner based on the generated display image data of the plurality of sub-frames, and deflecting an optical path of light emitted from each pixel of the spatial light modulator to the optical device. Optical path shifting means, and by displaying an image pattern in which the display position is shifted according to the deflection state of the optical path for each sub-frame, the apparent number of pixels of the spatial light modulator can be reduced. The image display apparatus characterized by multiplying and displayed. 16. The image display device according to claim 15, wherein the number of times of light path deflection of the light path shifting means is equal to the number of times of time division.

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