JP4919121B2 - Modulation apparatus, modulation method, and recording medium - Google Patents

Description

The present invention relates to a modulation device, a modulation method , and a recording medium , and in particular, a modulation device suitable for recording data on a recording medium at a high density or reproducing from a recording medium on which data is recorded at a high density, The present invention relates to a modulation method and a recording medium.

  When data is transmitted to a predetermined transmission path or recorded on a recording medium such as a magnetic disk, an optical disk, or a magneto-optical disk, the data is modulated so as to be suitable for the transmission path or the recording medium. A block code is known as one of such modulation methods. The block code is to block a data string into units of m × i bits (hereinafter referred to as data words) and convert the data words into code words of n × i bits according to an appropriate coding rule. This code becomes a fixed length code when i = 1, and when a plurality of i can be selected, that is, when a predetermined i in the range of 1 to imax (maximum i) is selected and converted, Become. The block-coded code is represented as a variable length code (d, k; m, n; r).

  Here, i is referred to as a constraint length, and imax is r (maximum constraint length). The minimum run d indicates the minimum number of consecutive “0” s that enter between consecutive “1” s in the code sequence, and the maximum run k indicates “0” that enters between consecutive “1” s in the code sequence. The maximum continuous number is shown.

  By the way, when the variable length code obtained as described above is recorded on an optical disc or a magneto-optical disc such as a compact disc (CD) or a mini disc (MD) (trademark), the variable length code obtained as described above is used. On the other hand, NRZI (Non Return to Zero Inverted) modulation, which is inverted by “1” and non-inverted by “0”, is recorded, and an NRZI-modulated variable length code (hereinafter referred to as a recording waveform sequence) is recorded. ing. This is also called mark edge recording. On the other hand, on an ISO standard 3.5-inch / 230 MB capacity magneto-optical disk or the like, the recording-modulated code string is recorded as it is without being subjected to NRZI modulation. This is called mark position recording. Mark edge recording is often used in recording media with high recording density as at present.

  When the minimum inversion interval of the recording waveform sequence is Tmin and the maximum inversion interval is Tmax, in order to perform high density recording in the linear velocity direction, the minimum inversion interval Tmin is better, in other words, the minimum run d is The bigger one is better. Further, from the viewpoint of clock regeneration, it is better that the maximum inversion interval Tmax is short, in other words, the maximum run k is preferably small. In consideration of overwrite characteristics, it is desirable that Tmax / Tmin is small. Furthermore, from the viewpoint of Jitter and S / N, it is important that the detection window width Tw = m / n is large, and various modulation methods have been proposed and put into practical use against the conditions of the media (recording medium). ing.

  Here, a modulation scheme that is proposed or actually used in an optical disc, a magnetic disc, a magneto-optical disc, or the like will be described. EFM (Eight to Fourteen Modulation) code (also expressed as (2,10; 8,17; 1)) used in CD and MD, 8-16 code ((2,10) used in DVD (Digital Video Disc) ; 1, 2; 1)), or RLL (Run Length Limited code) (2,7) ((2,7; m, n) used in PD (Phase Change Optical Disk; 120 mm, 650 MB capacity) ;) is also an RLL code with a minimum run d = 2.

  RLL (1,7) (also expressed as (1,7; 2,3; r)) used in ISO standard 3.5inchMO (Magneto Optical; 640MB capacity) is an RLL code with minimum run d = 1. In addition, recording / reproducing disk devices such as optical disks and magneto-optical disks with high recording density use RLL codes with a minimum run d = 1 that balances the minimum mark size and conversion efficiency. Yes.

The conversion table of the variable length RLL (1-7) code is, for example, the following table.
<Table 1> RLL (1,7; 2,3; 2)
Data code i = 1 1 1 1 00x
10 010
01 10x
i = 2 0011 000 00x
0010 000 010
0001 100 00x
0000 100 010

  Here, the symbol x in the conversion table is “1” when the next channel bit is “0”, and is “0” when the next channel bit is “1” (hereinafter, “0”). The same). The maximum constraint length r is 2.

  The parameter of the variable length RLL (1,7) is (1,7; 2,3,2), and the minimum inversion interval Tmin represented by (d + 1) T is 2 when the bit interval of the recording waveform sequence is T. (= 1 + 1) T. When the bit interval of the data string is Tdata, the minimum inversion interval Tmin represented by (m / n) × 2 is 1.33 (= (2/3) × 2) Tdata. The maximum inversion interval Tmax represented by (k + 1) T is 8 (= 7 + 1) T (= (m / n) × 8Tdata = (2/3) × 8Tdata = 5.33Tdata). Further, the detection window width Tw is expressed by (m / n) × Tdata, and its value is 0.67 (= 2/3) Tdata.

  By the way, in the channel bit string modulated by RLL (1,7) in Table 1, the frequency of occurrence is 2T, which is Tmin, and is followed by 3T, 4T. The occurrence of a large amount of edge information such as 2T or 3T at an early cycle is often advantageous for clock recovery.

  However, when the linear recording density is further increased, a short mark becomes a problem on the contrary. That is, if 2T, which is the minimum run, continues to be generated, the recording waveform is likely to be distorted. This is because the 2T waveform output is smaller than other waveform outputs, and is easily affected by, for example, defocusing, tangential tilt, and the like. Further, at a high recording density, continuous recording of the minimum mark (2T) is easily affected by disturbances such as noise. Therefore, such a pattern string is likely to cause an error during data reproduction. In this case, as the data reproduction error pattern, there are many cases in which the beginning and end of consecutive minimum marks are shifted and erroneous, and the error propagation length becomes long.

  On the other hand, when recording data on a recording medium or transmitting data, encoding modulation suitable for the recording medium or transmission path is performed. If these modulation codes include a low-frequency component, For example, various error signals such as tracking errors in servo control of the disk device are likely to fluctuate or jitter is likely to occur. Therefore, it is desirable for the modulation code to suppress the low frequency component as much as possible.

  There is a DSV (Digital Sum Value) control as a method for suppressing the low frequency component. DSV is a recording code string obtained by converting the channel bit string to NRZI (level coding), adding “1” to “+1” and “0” to “−1” of the bit string (data symbol) and adding the code. It means the sum total when you do it. DSV is a measure of the low frequency component of the recording code string, and reducing the absolute value of the DSV fluctuation, that is, DSV control, suppresses the low frequency component except for the DC component of the recording code string. It will be.

  The modulation codes according to the variable length RLL (1,7) table shown in Table 1 are not subjected to DSV control. In such a case, DSV control is realized by performing DSV calculation at a predetermined interval in the encoded sequence (channel bit sequence) after modulation, and inserting the predetermined DSV control bit into the encoded sequence (channel bit sequence). Is done.

  However, since the DSV control bits are redundant bits, the DSV control bits should be as small as possible from the viewpoint of code conversion efficiency, and the minimum run d and the maximum run k vary depending on the inserted DSV control bits. It is better not to. This is because if (d, k) changes, the recording / reproducing characteristics are affected.

Therefore, the present applicant, for example, in Japanese Patent Application No. 10-15280 filed earlier, (d, k) = (1,7), and as a modulation method corresponding to a higher recording density, 7PP code is proposed.
<Table 2> 1,7PP (1,7; 2,3; 4)
Data sign
11 * 0 *
10 001
01 010
0011 010 100
0010 010 000
0001 000 100
000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000
"110111 001 000 000 (next 010)
00001000 000 100 100 100
00000000 010 100 100 100
if xx1 then * 0 * = 000
xx0 then * 0 * = 101
_____________________
Sync & Termination
# 01 000 000 001 (12 channtl bits)
or
# 01 001 000 000 001 000 000 001 (24 channel bits)
# = 0 not terminate case
# = 1 terminate case
_____________________
Termination table
00 000
0000 010 100
"110111 001 000 000 (next010):
When next channel bits are '010',
convert '11 01 11 'to' 001 000 000 'after
using main table and termination table.
_____________________

  The conversion table in Table 2 is a basic code that cannot be converted without it as a conversion code (codes from the data string (11) to (000000)), but conversion processing is possible without it. If there is a replacement code (data string (110111), (00001000), (00000000) code) that enables more effective conversion processing, and a termination code (data for terminating the code at an arbitrary position) Column (00), (0000) code).

  In Table 2, the minimum run d = 1 and the maximum run k = 7, and an indeterminate code (a code including *) is included in the elements of the basic code. The indeterminate code is determined to be “0” or “1” so as to protect the minimum run d and the maximum run k, regardless of the codeword string immediately before and after. That is, in Table 2, when the 2-bit data string to be converted is (11), “000” or “101” is selected depending on the code word string immediately before it, and converted to either one. For example, when one channel bit of the immediately preceding code word string is “1”, in order to keep the minimum run d, the 2-bit data (11) is converted into the code word “000” and the immediately preceding code word string is When one channel bit is “0”, it is converted to a code word “101” so that the maximum run k is protected.

  The basic code of the conversion table in Table 2 has a variable length structure. That is, the basic code in the constraint length i = 1 is composed of three (* 0 *, 001, 010) which is smaller than the required number of four (2 ^ m = 2 ^ 2 = 4). As a result, there is a data string that cannot be converted only with the constraint length i = 1 when the data string is converted. After all, in Table 2, it is necessary to refer to the basic code up to the constraint length i = 3 in order to convert all data strings (in order to hold as a conversion table).

  In addition, since the conversion table of Table 2 has a replacement code that restricts the continuation of the minimum run d, when the data string is (110111), the code word string that follows is referred to, which is “010”. ", The data string is replaced with the code word" 001 000 000 ". This data string is converted into a code word in units of 2 bits ((11), (01), (11)) when the code word string that follows is other than “010”. * 0 * 010 * 0 * ". As a result, the code word string obtained by converting the data is limited to the minimum run continuation, and the maximum run repeats up to 6 times at the maximum.

  Furthermore, the conversion table of Table 2 has a maximum constraint length r = 4. The code having the constraint length i = 4 is composed of a replacement code (maximum run compensation code) for realizing the maximum run k = 7. That is, the data (00001000) is converted into the code word “000100100100”, and the data (00000000) is converted into the codeword “010100100100”. Also in this case, the minimum run d = 1 is maintained.

  By the way, the conversion code in Table 2 is obtained by dividing the remainder of dividing the number of “1” s in the elements of the data string by 2 and the number of “1s” in the elements of the codeword string to be converted by 2. The remainder of the time has a conversion rule such that both are 1 or 0 (the number of “1” is odd or even in all corresponding elements). For example, the element (000001) of the data string in the conversion code corresponds to the element of the code word string “010 100 100”, but the number of “1” of each element is one in the data string. In the corresponding code word string, there are three, and the remainder when divided by 2 is equal to 1 (odd number). Similarly, the element (000000) of the data string in the conversion code corresponds to the element of the code word string “010 100 000”, but the number of “1” corresponds to 0 in the data string. There are two codeword strings, and when both are divided by 2, the remainder is equal to 0 (even).

  Next, a method for performing DSV control will be described. As an example of a conventional DSV control method in the case where DSV control is not performed on the conversion table, such as the RLL (1,7) code in Table 1, after modulating a data string, a channel bit string after modulation In addition, at least (d + 1) bits of DSV control bits are added at predetermined intervals.

  In the conversion table as shown in Table 2, DSV control can be performed efficiently by making use of the relationship between the data string and the codeword string to be converted. That is, when the conversion table divides the number of “1” in the element of the data string and the number of “1” in the element of the codeword string to be converted by 2, both are 1 or 0. When the same conversion rule is used, insert a DSV control bit of “1” indicating “inverted” or “0” indicating “non-inverted” into the channel bit string as described above. Is equivalent to inserting DSV control bits of (1) if “inverted” and (0) if “not inverted” in the data bit string.

For example, in Table 2, when 3 bits for data conversion are followed by (001) and the DSV control bit is included after that, the data is (001-x) (x is 1 bit and “0”). Or “1”). Here, if “0” is given to x, the conversion table of Table 2
Data string Codeword string
0010 010 000
Is converted, and if "1" is given,
Data string Codeword string
0011 010 100
Conversion is performed. When a codeword string is converted to NRZI and level coded, these are a data string, a codeword string, and a level code string.
0010 010 000 011111
0011 010 100 011000
Thus, the last 3 bits of the level code string are mutually inverted. This means that the DSV control can be performed in the data string by selecting (1) and (0) of the DSV control bit x.

  Considering the redundancy by DSV control, DSV control with 1 bit in the data string is 1.5 channel bits from the conversion rate (m / n = 2/3) in Table 2 when expressed in channel bit string. This is equivalent to performing DSV control. On the other hand, in order to perform DSV control in the RLL (1,7) table as shown in Table 1, it is necessary to perform DSV control in the channel bit string. At this time, in order to keep the minimum run, at least 2 channel bits are required. Therefore, when compared with the DSV control of Table 2, the redundancy becomes larger. In other words, when the table structure of Table 2 is used, DSV control can be performed efficiently by performing DSV control within the data string.

  In general, as the maximum constraint length r increases, the propagation characteristic of a demodulation error during bit shift (an error caused by shifting the position of the edge bit by one bit forward or backward from the normal position) is worse. Become.

  When Table 1 and Table 2 are compared, the maximum constraint length r is 2 in the RLL (1,7) code in Table 1, whereas the maximum constraint length r is as large as 4 in the 1,7PP code in Table 2. The worst propagation length of demodulation error propagation for bit shift is 2 bytes in Table 1, but 3 bytes in Table 2. The 1,7PP code is a (d, k) = (1,7) code corresponding to a high recording density and has a compact configuration, but the error propagation characteristics are still better than the conventional RLL (1,7) code. It was disadvantageous.

Japanese Patent Laid-Open No. 11-346154

  As described above, when the RLL code is recorded / reproduced to / from the disk at a high linear density, if there is a continuous pattern of the minimum run d, a long error is likely to occur. Further, in order to perform DSV control in the (1,7; 2,3) code, it is necessary to sandwich redundant bits, but it is necessary to reduce the redundant bits as much as possible. Based on this situation, the number of consecutive minimum runs is limited in the RLL code (d, k; m, n) = (1,7; 2,3) where the minimum run d = 1 as described above. In addition, a 1,7PP code that can perform DSV control with efficient control bits while protecting the minimum and maximum runs has been developed, but the 1,7PP code has a simple structure conversion table. Nevertheless, it has a longer error propagation characteristic than the conventional RLL (1,7) code.

  The present invention has been made in view of such a situation, and uses a table for limiting the number of occurrences of conversion codes that are likely to cause long error propagation, and the number of times a pattern that is likely to cause longer error propagation is generated. By using a table that limits the error, long error propagation is prevented from occurring.

A modulation device according to one aspect of the present invention is a modulation device that converts an m-bit data string into an n-bit code word string at a ratio of 2 to 3, and divides the input data string into m-bit data strings. When converting the segmented m-bit data string into an n-bit code word string based on the first table, with the classification means and the minimum run d being 1 or more, When the run d continues for a predetermined number of times, if the code word string immediately before and immediately after one code word string among the plurality of code word strings is a predetermined code word string, it is converted to the first code word string. , If the codeword string immediately before and immediately after one codeword string is not the predetermined codeword string among the plurality of codeword strings, the plurality of codeword strings are based on the second table converted to the second codeword string. The code word sequence of the limit code that limits the number of consecutive minimum runs d And a converting means for converting.

  The second table may be a table in which the last bit of the immediately preceding codeword string is 0 or 1.

  The restriction code may be generated by a code other than the restriction code or a combination of a part of the codes.

A modulation method according to one aspect of the present invention is a modulation method of a modulation apparatus that converts an m-bit data string into an n-bit code word string at a ratio of 2 to 3, and the input data string is a data string for each m bits. When the minimum run d is set to 1 or more and the divided m-bit data string is converted into an n-bit code word string based on the first table, When the run d continues for a predetermined number of times, if the code word string immediately before and immediately after one code word string among the plurality of code word strings is a predetermined code word string, it is converted to the first code word string. , If the codeword string immediately before and immediately after one codeword string is not the predetermined codeword string among the plurality of codeword strings, the plurality of codeword strings are based on the second table converted to the second codeword string. A limit code that limits the number of consecutive minimum runs d Comprising the step of converting.

In the modulation apparatus and method of one aspect of the present invention, an m-bit data string is converted into an n-bit code word string at a ratio of 2 to 3, and an input data string is divided into m-bit data strings. The minimum run d is a predetermined number of times in a plurality of codeword strings when the segmented m-bit data string is converted into an n-bit codeword string based on the first table, with the minimum run d being 1 or more. When the code word string immediately before and immediately after one code word string is a predetermined code word string among a plurality of code word strings, the code word string is converted into a first code word string If the codeword string immediately before and immediately after one codeword string is not a predetermined codeword string, a plurality of codeword strings are determined based on the second table converted to the second codeword string. It is converted into a limit code that limits the number of times d continues.

A recording medium according to one aspect of the present invention is a data string created by a modulation method that converts an m-bit data string into an n-bit code word string at a ratio of 2 to 3, and the input data string is m When the divided m-bit data string is converted into an n-bit code word string based on the first table with a minimum run d set to 1 or more, the data is divided into bit-by-bit data strings. In the code word string, when the minimum run d continues for a predetermined number of times, if the code word string immediately before and immediately after one code word string among the plurality of code word strings is a predetermined code word string, A second codeword string that is converted into a second codeword string when the codeword string immediately before and immediately after one of the plurality of codeword strings is not the predetermined codeword string . Based on the table, the plurality of codeword strings are obtained by calculating the number of consecutive minimum runs d. It records the data sequence with the converted data structure to the restriction code to limit.

The recording medium according to one aspect of the present invention is a data sequence created by a modulation method that converts an m-bit data sequence into an n-bit codeword sequence at a ratio of 2 to 3, and the input data sequence is When the divided m-bit data string is converted into an n-bit code word string based on the first table with the minimum run d set to 1 or more and divided into m-bit data strings, In the code word string, when the minimum run d continues for a predetermined number of times, the code word string immediately before and immediately after one code word string among the plurality of code word strings is a predetermined code word string. When the codeword string immediately before and immediately after one codeword string is not a predetermined codeword string, the second codeword string is converted to the second codeword string . Based on the table, multiple codeword strings limit the number of consecutive minimum runs d Data string having the converted data structure to limit code is recorded that.

  According to the present invention, it is possible to record and reproduce a code word string having a high linear density and few errors.

It is a block diagram which shows the structure of one Embodiment of the modulation apparatus to which this invention is applied. It is a block diagram which shows the other structure of a modulation apparatus. It is a block diagram which shows the structure of a modulation part. It is a block diagram which shows the other structure of a modulation | alteration part. It is a figure explaining a modulation | alteration. It is a block diagram which shows the structure of a demodulation apparatus. It is a block diagram which shows the structure of a demodulation part. It is a figure explaining a demodulation. It is a flowchart explaining the removal process of a DSV control bit. It is a block diagram which shows the other structure of a modulation apparatus. It is a block diagram which shows the further another structure of a modulation apparatus. It is a block diagram which shows the other structure of a demodulation apparatus.

  An embodiment of the present invention will be described. In the following, for convenience of explanation, the arrangement of data “0” and “1” before conversion (data string before conversion) is expressed as (000011). , (), And a sequence (codeword string) of “0” and “1” after conversion is delimited by “” like “000100100”.

The following table shows an example of a conversion table for converting data of the present invention into codes.
<Table 3> 1,7PP-32 (plus pre0)
Data string Code string
11 * 0 *
10 001
01 010
0011 010 100
0010 010 000
0001 000 100
000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000
___________________
# 110111 (pre0) 001 000 000 (next010)
# 00001000 000 100 100 100
# 00000000 010 100 100 100
___________________
if xx1 then * 0 * = 000
xx0 then * 0 * = 101
___________________
* 1. # "0" +110111 + 01/001/00000 → 001 000 000
# "0" + 110111 + "010" → 001 000 000
# "101-010-101" + "010" → 001 000 000

  The conversion table in Table 3 is a 1,7PP code, and in addition, refer to the immediately preceding and immediately following codeword strings so as to suppress the number of conversion codes that limit the continuation of the minimum run compared to Table 2. The replacement restriction is performed.

  Table 3 has a minimum run d = 1 and a maximum run k = 7, and has an indeterminate code (a code including *) as an element of the basic code. The indeterminate code is determined to be “0” or “1” so as to protect the minimum run d and the maximum run k, regardless of the codeword string immediately before and after. That is, in Table 3, when the 2-bit data string to be converted is (11), “000” or “101” is selected according to the codeword string immediately before it and converted into either one. For example, when one channel bit of the immediately preceding code word string is “1”, in order to keep the minimum run d, the 2-bit data (11) is converted into the code word “000” and the immediately preceding code word string is When one channel bit is “0”, it is converted to a code word “101” so that the maximum run k is protected.

  The conversion table of Table 3 has a variable length structure, and its basic code has i = 1 to 3. Further, since the conversion table of Table 3 has a replacement code that restricts the continuation of the minimum run d, when the data string is (110111), the codeword immediately before and after is further referred to. When the immediately preceding code word is “0” and the code word string that follows is “010”, this data string is replaced with the code word “001 000 000”. Further, this data string is converted into a code word in units of 2 bits ((11), (01), (11)) when the code word string immediately before and immediately after is not shown above, and the code word "* 0 * 010 * 0 * ". As a result, the code word string obtained by converting the data is limited to the minimum run, and the maximum run is repeated up to six times.

  The replacement code that limits the continuation of the minimum run d in Table 3 is determined with reference to both the immediately preceding codeword string and the immediately following codeword string. Of these, even if the immediately preceding code word string is not referred to at the time of conversion, the continuation of the minimum run d is limited to 6 times. However, as shown in Table 3, the number of occurrences of replacement codes can be reduced. Can be reduced.

  In the conversion code shown in Table 3, the maximum constraint length r = 4. The code having the constraint length i = 4 is composed of a replacement code (maximum run compensation code) for realizing the maximum run k = 7. That is, the data (00001000) is converted to the code word “000100100100”, and the data (00000000) is converted to the codeword “010100100100”. In this case as well, the minimum run d = 1 is maintained.

  The conversion code in Table 3 is obtained by dividing the remainder when the number of “1” s in the elements of the data string is divided by 2 and the number of “1s” in the elements of the codeword string to be converted by 2. The remainder of the time has a conversion rule such that both are 1 or 0 (the number of “1” is odd or even in all corresponding elements). For example, the element (000001) of the data string in the conversion code corresponds to the element of the code word string “010 100 100”, but the number of “1” of each element is one in the data string. In the corresponding code word string, there are three, and the remainder when divided by 2 is equal to 1 (odd number). Similarly, the element (000000) of the data string in the conversion code corresponds to the element of the code word string “010 100 000”, but the number of “1” is 0 in the data string, In the corresponding codeword string, there are two, and the remainder when divided by 2 matches with 0 (even number).

<Table 4> 1,7PP-32 (plus i = 4)
Data string Code string
11 * 0 *
10 001
01 010
0011 010 100
0010 010 000
0001 000 100
000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000
____________________
# 110111 001 000 000 (next010)
# 00001000-x 000 100 100 100
# 00000000-x 010 100 100 100
# x = 01, 001
____________________
if xx1 then * 0 * = 000
xx0 then * 0 * = 101
____________________
* 1. # 110111 + 01/001/00000 → 001 000 000
# 110111 + "010" → 001 000 000
# "* 0 * -010-101" + "010" → 001 000 000
* 2. # 000010 + 0001/00001 → 000 100 100 100
# "000-100-000" + "000" → 000 100 100 100
# 000000 + 0001/00001 → 010 100 100 100
# "010-100-000" + "000" → 010 100 100 100

  The conversion table shown in Table 4 is a 1,7PP code. Further, in comparison with Table 2, the code word string (data string) immediately after is referred so as to suppress the number of generations of conversion codes that compensate for the maximum run. By doing so, the replacement is restricted.

  Table 4 shows that the minimum run d = 1 and the maximum run k = 7, and the elements of the basic code have indeterminate codes (codes including *). Further, since the conversion table of Table 4 has a variable length structure, the basic code has i = 1 to 3. Further, since the conversion table of Table 4 has a replacement code that restricts the continuation of the minimum run d, when the data string is (110111), the code word string that follows is referred to and is “010”. This data string is replaced with the code word “001 000 000”. In addition, this data string is converted into a code word in units of 2 bits ((11), (01), (11)) when the immediately following code word string is not the above, so the code word “* 0 * 010 * 0”. * "Is converted. As a result, the code word string obtained by converting the data is limited in the minimum run and the maximum run is repeated up to six times.

  In the conversion table of Table 4, the maximum constraint length r = 4. The code having the constraint length i = 4 is composed of a replacement code (maximum run compensation code) for realizing the maximum run k = 7. That is, when the data is (00001000), the data string that follows is further referred to, and when it is (01) or (001), this data string is converted into the code word “000100100100”. . Further, the data (00000000) is further converted into the code word “010100100100” when the subsequent data string is (01) or (001). Also in this case, the minimum run d = 1 is maintained.

  In other words, the code of the constraint length i = 4 is the replacement code (maximum run compensation code) for realizing the maximum run k = 7. The 6 bits of the data is (000010), and the back When the code word string following “000” is “000”, this data string is converted into a code word “000100100100”. If the 6 bits of the data is (000000) and the codeword string that follows is “000”, it is converted to the codeword “010100100100”.

  The replacement code that realizes the maximum run k = 7 in Table 4 is determined by referring to the total data string 11 bits with a maximum of 3 bits in addition to the data string 8 bits. At the time of conversion, the maximum run k = 7 can be realized only by referring to up to 8 bits of the data string. However, by making it as shown in Table 4, it is possible to reduce the number of occurrences of the replacement code.

  Similarly to Table 3, the conversion code in Table 4 is the remainder of dividing the number of “1” s in the data string elements by 2 and “1” in the codeword string elements to be converted. There is a conversion rule in which the remainder when the number is divided by 2 is equal to 1 or 0.

<Table 5> 1,7PP-32 (plus * 0 *)
Data string Code string
11 * 0 *
10 001
01 010
0011 010 100
0010 010 000
0001 000 100
000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000
_____________________
# 110111 001 000 000 (next010 / * 0 *)
# 00001000 000 100 100 100
# 00000000 010 100 100 100
_____________________
if xx1 then * 0 * = 000
xx0 then * 0 * = 101
_____________________
* 1. # 110111 + 01/001/00000 → 001 000 000
# 110111 + "010" → 001 000 000
# "* 0 * -010-101" + "010" → 001 000 000
_____________________
* 2. # 110111 + 11 / not (110111-01 / 00/11) → 001 000 000
# 110111 + "* 0 *" → 001 000 000
# "* 0 * -010-101" + "* 0 *" → 001 000 000

  The conversion table in Table 5 is a 1,7PP code. Further, in comparison with Table 2, two types of codeword sequences are referred to so as to suppress the number of consecutive 6 occurrences that are repeated most frequently in the minimum run. By doing so, replacement restrictions are made.

  Table 5 shows that the minimum run d = 1, the maximum run k = 7, the element of the basic code has an indeterminate code (a code including *), and has a variable length structure. Have up to three. Similarly to Table 3 and Table 4, the conversion table of Table 5 has a replacement code that restricts the continuation of the minimum run d. Therefore, when the data string is (110111), the codeword string that follows it When it is “010” or “* 0 *”, this data string is replaced with the code word “001 000 000”. If this data string is other than the above two conditions, it is converted into a code word in units of 2 bits ((11), (01), (11)), so that the code word “* 0 * 010 *” 0 * ". As a result, the code word string obtained by converting the data is limited in the minimum run and the maximum run is repeated up to six times.

  The replacement code for limiting the continuation of the minimum run d in Table 5 is determined with reference to the two immediately following code word strings. Of the two codeword strings immediately after the reference, one of the codeword strings immediately following the minimum run d is limited to six times even if it is not referred to at the time of conversion. Thus, it is possible to reduce the number of consecutive occurrences of the minimum run six times.

  The change code in Table 5 is the maximum constraint length r = 4, as in Tables 3 and 4. The code having the constraint length i = 4 is composed of a replacement code (maximum run compensation code) for realizing the maximum run k = 7. Similarly to Table 3 and Table 4, the conversion code in Table 5 includes the remainder when the number of “1” in the data string element is divided by 2, and “1” in the element of the codeword string to be converted. There is a conversion rule in which the remainder when dividing the number of "" by 2 is 1 or 0 is the same.

  In general, the larger the maximum constraint length r, the worse the demodulation error propagation characteristics during bit shift (the edge bit position is shifted forward or backward from the normal position by one bit during reproduction). As a result, there may be a case where the data conversion portion having a large constraint length causes a long demodulation error propagation. That is, reducing the number of occurrences of conversion with a large constraint length improves the error propagation characteristics. Therefore, the 1,7PP code shown in Table 2 can be improved in error propagation characteristics by adopting the structure shown in Table 3 or Table 4. Also, as shown in Table 5, by reducing the number of occurrences of the six consecutive minimum runs, it is possible to reduce long error propagation, thereby improving error propagation characteristics.

  Since Tables 3 to 5 are independent of each other, a table in which these are combined can be configured. For example, Table 6 shown below is a combination of Table 3 and Table 4, and has two conversion codes that can further reduce the number of occurrences of replacement codes that are conversions with a large constraint length. It is.

<Table 6> 1,7PP-32 (plus i = 4, pre0)
Data string Code string
11 * 0 *
10 001
01 010
0011 010 100
0010 010 000
0001 000 100
000011 000 100 100
000010 000 100 000
000001 010 100 100
000000 010 100 000
___________________
# 110111 (pre0) 001 000 000 (next010)
# 00001000-x 000 100 100 100
# 00000000-x 010 100 100 100
# x = 01, 001
___________________
if xx1 then * 0 * = 000
xx0 then * 0 * = 101
___________________
* 1. # "0" +110111 + 01/001/00000 → 001 000 000
# "0" + 110111 + "010" → 001 000 000
# "101-010-101" + "010" → 001 000 000
___________________
* 2. # 000010 + 0001/00001 → 000 100 100 100
# "000-100-000" + "000" → 000 100 100 100
# 000000 + 0001/00001 → 010 100 100 100
# "010-100-000" + "000" → 010 100 100 100

  By the way, when a synchronization signal is inserted at an arbitrary position in the codeword string (channel bit string) generated by the conversion tables of Tables 3 to 6, the conversion table has a variable length structure. A termination table is defined to terminate the code at an arbitrary position, and is used as necessary.

Table 7 below shows an example of the synchronization signal and termination table in Tables 3 to 6 of the present invention.
<Table 7> Sync & Termination for Table 3 to Table 6
# 01 000 000 001 (12 channtl bits)
# = 0 not terminate case
# = 1 terminate case
_________________
Termination table
00 000
0000 010 100

  For example, when inserting a synchronization signal at an arbitrary position, first, connection bits are set so that the minimum run d and the maximum run k are protected in the connection with the immediately preceding and immediately following codeword strings, and synchronization is established between the connection bits. A unique pattern for the signal is set. If a pattern that breaks the maximum run k = 7 is given as the synchronization signal pattern, for example, “# 01 000 000 001” is obtained. The leading “#” of the synchronization signal pattern is a connection bit, and is set to either “0” or “1”. The second channel bit next to “#” is set to “0” in order to keep the minimum run. From the third channel bit, a 9T unique pattern in which k = 8 is given as the synchronization signal pattern. That is, eight “0” s are continuously arranged between “1” and “1”.

The termination table applicable to Tables 3 to 6 can be realized in the same manner as Table 2, and the termination table is as shown in Table 7.
00 000
0000 010 100
It becomes. The termination table is required for a basic code having a constraint length i having fewer than four data strings and codeword string pairs (2 ^ m = 2 ^ 2 = 4).

  With this termination table, data (00) is converted to code “000”, and data (0000) is converted to code “010100”. As a result, when the synchronization signal is inserted, it is possible to prevent the data immediately before that from being converted into a code (the code immediately before the synchronization signal cannot be terminated).

  The connection bit “#” of the synchronization signal pattern is used to distinguish between the case where the termination table is used and the case where it is not used. That is, “#” of the first first channel bit given as the synchronization signal is “1” when the termination code is used, and “0” otherwise. By doing so, the difference between the tables (whether or not the termination code is used) can be definitely identified.

  If the termination table is provided as described above, it can be terminated even when a synchronization signal is inserted at an arbitrary position together with the synchronization signal pattern.

  FIG. 1 is a block diagram illustrating a configuration of a modulation apparatus that performs modulation processing using the conversion table described above. Here, a case where the data string is converted into a variable length code (d, k; m, n; r) = (1, 7; 2, 3; 4) according to Table 6 will be described as an example.

  The data string input to the modulation device 1 determines “1” or “0” which is a DSV control bit, and is input to the DSV control bit determination / insertion unit 11 to be inserted at an arbitrary interval. The data output from the DSV bit determination / insertion unit 11 is input to the modulation unit 12, subjected to modulation processing, and output to the NRZI conversion unit 13. The NRZI conversion unit 13 converts the input data into a recording code string. The timing management unit 14 generates a timing signal and supplies it to each unit to manage timing.

  FIG. 2 is a block diagram illustrating another configuration example of the modulation device 1. The data string input to the modulation device 1 is input to a control bit insertion unit 21 that inserts a DSV control bit “1” or “0” at a predetermined position. The data output from the control bit insertion unit 21 is input to the modulation unit 12, subjected to modulation processing, and output to the NRZI conversion unit 13 which performs NRZI conversion and level encoding. The data output from the NRZI conversion unit 13 is input to the DSV bit determination unit 22 that selects a DSV-controlled one from the two input level code sequences and uses this as a recording code sequence. The timing management unit 14 also generates timing signals and supplies them to each unit to manage timing.

  FIG. 3 is a block diagram illustrating a configuration example of the modulation unit 12. The shift register 31 shifts the data by 2 bits while shifting the constraint length determination unit 32, the minimum run continuation restriction code detection unit 33 including replacement restriction, the run length restriction compensation code detection unit 34 including replacement restriction, and the conversion unit 35. -1 to 35-4. At this time, the shift register 31 supplies the number of bits necessary for each unit to perform the processing.

  The constraint length determination unit 32 determines the constraint length i of data and outputs it to the multiplexer 36. The minimum run continuation restriction code detection unit 33 including replacement restriction outputs a detection signal representing the constraint length to the constraint length determination unit 32 when detecting a dedicated code that limits the continuation of the minimum run. When the run length limit compensation code detection unit 34 including the replacement limit detects a dedicated code for compensating the maximum run shown in Table 6, the run length limit compensation code detection unit 34 outputs a detection signal indicating the constraint length to the constraint length determination unit 32. .

  When a dedicated code is detected by the minimum run continuous limit code detection unit 33 including the replacement limit, or when a dedicated code is detected by the run length limit compensation code detection unit 34 including the replacement limit, the constraint length determination unit 32 Outputs the corresponding constraint length to the multiplexer 36. At this time, the constraint length determination unit 32 may determine another constraint length. However, the minimum run continuation limit code detection unit 33 including a replacement limit or the run length limit compensation code detection unit 34 including a replacement limit. If there is a detection output by a dedicated code from, the constraint length determination unit 32 prioritizes the output and determines the constraint length. In other words, the constraint length determination unit 32 selects a larger constraint length.

  The conversion units 35-1 to 35-4 refer to a built-in conversion table to determine whether or not a conversion code corresponding to the supplied data is registered. Are converted into corresponding code words, and the converted code words are output to the multiplexer 36. When the corresponding data is not registered as a conversion code in the conversion table, the conversion units 35-1 to 35-4 discard the input data.

  The multiplexer 36 selects the code converted by the conversion unit 35-i (i = 1 to 4) corresponding to the constraint length i supplied from the constraint length determination unit 32, and uses the code as serial data to store the buffer 37. To be output via.

  The operation timing of each unit is managed in synchronization with the timing signal supplied from the timing management unit 14.

  Next, the operation of the modulation unit 12 will be described. From the shift register 31, a constraint length determination unit 32, a minimum run continuation limit code detection unit 33 including a replacement limit, a run length limit compensation code detection unit 34 including a replacement limit, and conversion units 35-1 to 35-4, The data input to the modulation unit 12 is supplied in units of 3 bits, and each unit is supplied with the number of bits necessary for determination.

  The constraint length determination unit 32 incorporates, for example, the basic code portion of the conversion table shown in Table 6, refers to this conversion table, determines the constraint length i of the data, and multiplexes the determination result (the constraint length i) with the multiplexer. 36.

  The minimum run continuation restriction code detection unit 33 including the replacement restriction replaces the replacement code (in the case of Table 6, data (110111) and the immediately preceding code word) of the conversion table shown in Table 6 that restricts the continuation of the minimum run. 0 ”and the codeword“ 010 ”that follows it are incorporated, and when a code that limits the continuation of the minimum run is detected with reference to this conversion table, the constraint length i = 3 is output to the constraint length determination unit 32.

  In addition, the run length restriction compensation code detection unit 34 including the replacement restriction replaces the replacement code (in the case of Table 6, data (00001000-x) and (00000000-x)) in the conversion table shown in Table 6. x: (01) or (001)) is built in, and when a replacement code that protects the maximum run is detected with reference to this conversion table, a detection signal of constraint length i = 4 is sent to the constraint length determination unit 32. Output.

  When a constraint length i = 3 detection signal is input from the minimum run continuation limitation code detection unit 33 including replacement limitation, the constraint length determination unit 32 may determine another constraint length at that time. Without selecting the length, the constraint length i (i = 3 in the example of Table 6) corresponding to the detection of the minimum run continuation restriction code detection unit 33 including the replacement restriction is selected and output to the multiplexer 36. Similarly, when a constraint length i = 4 detection signal is input from the run length limitation compensation code detection unit 34 including replacement limitation, the constraint length determination unit 32 may determine another constraint length at that time. Without selecting the constraint length, the constraint length i (i = 4 in the case of Table 6) corresponding to the detection of the run length limitation compensation code detection unit 34 including the replacement limitation is selected and output to the multiplexer 36.

  By doing so, the determination result of the constraint length in the minimum run continuation limit code detection unit 33 including the replacement limitation or the run length limitation compensation code detection unit 34 including the replacement limitation and the constraint length determination unit 32 in the end. This means that if the length determination results are different, the larger constraint length may be selected as the final constraint length.

  FIG. 4 is a block diagram illustrating another configuration example of the modulation unit 12. The shift register 31 shifts the data by 2 bits while shifting the constraint length determination unit 32, the minimum run / maximum run compensation code detection unit 41, the minimum run continuous restriction code detection unit 42, the immediately preceding / immediate bit reference unit 43, and The data is output to conversion units 35-1 to 35-4. At this time, the shift register 31 supplies the number of bits necessary for each unit to perform the processing.

  The minimum run continuous restriction code detection unit 42 and the minimum run / maximum run compensation code detection unit 41 detect the first and second replacement codes to which no replacement restriction is added. The immediately preceding / immediate bit reference unit 43 gives a rule for adding the replacement restriction shown in Table 6, and the signal output from the immediately preceding / immediate bit reference unit 43 and input to the constraint length determination unit 32 is: This is the same signal as the signal to the constraint length determination unit 32 shown in FIG. The other parts are the same as in FIG.

  Next, referring to FIG. 5, the operations of the constraint length determination unit 32, the minimum run continuous limit code detection unit 33 including replacement restrictions, and the run length limit compensation code detection unit 34 including replacement restrictions shown in FIG. A specific example will be described.

  The run length limitation compensation code detection unit 34 including the replacement limitation has conversion parts (00001000-x) and (00000000-x) of the conversion table shown in Table 6, and the input 8-bit data is In the case of coincidence, the next data is further referred to, and when the subsequent data is (01) or (001), the detection signal of the constraint length i = 4 is output to the constraint length determination unit 32. In other words, when the input 6-bit data matches (000010) and (000000), the detection signal with constraint length i = 4 is constrained when the code word string immediately following is “000”. The data is output to the length determination unit 32.

  The minimum run continuation restriction code detection unit 33 including the replacement restriction has a conversion part of data (110111), the immediately preceding code “0”, and the immediately following code “010” in the conversion table shown in Table 6 and is input 6 When the bit data is (110111), the codeword immediately before it is “0”, and the codeword immediately after it is “010”, the detection signal of constraint length i = 3 is the constraint length. The data is output to the determination unit 32. If the portion of the three code words “010” is represented by a data string before data conversion, (01), (001), or (00000) is obtained. Therefore, the minimum run continuation restriction code detection unit 33 including the replacement restriction has a conversion part of the immediately preceding code “0” + (110111) + (01/001/00000), and in addition to the input 6-bit data, In addition to the immediately preceding 1 code, further reference is made to the immediately following 5 bits of data, and if they match any of these, a detection signal of constraint length i = 3 is output to the constraint length determination unit 32.

  The constraint length determination unit 32 incorporates the basic code portion of the table shown in Table 6, and the input 6-bit data is either (000011), (000010), (000001), or (000000). If they match, it is determined that the constraint length i = 3. When the input 4-bit data matches any of (0011), (0010), and (0001), the constraint length determination unit 32 determines that the constraint length i = 2. Further, when the input 2-bit data matches any of (11), (10), and (01), the constraint length determination unit 32 determines that the constraint length i = 1.

  By the way, when the input data is, for example, (000010), the constraint length determination unit 32 determines that the constraint length i = 3. However, when the following data is (0001) or (00001) in addition to the above 6 bits, the run length limitation compensation code detection unit 34 including the replacement limitation determines that the constraint length i = 4. In such a case, the output signal from the run length limit compensation code detection unit 34 including the replacement limit is given priority, and the constraint length i = 4 is determined.

  In this way, according to the table of Table 6, the maximum constraint length of 8 bits and, if necessary, the immediately preceding or immediately following codeword string are referred to, and a data string consisting of all (1) and (0) The constraint length is further determined.

  The constraint length determination unit 32 outputs the constraint length i determined in this way to the multiplexer 36.

  The constraint length determination unit 32 determines the constraint length in the order of i = 1, i = 2, i = 3, and i = 4 from the smaller constraint length, in the reverse order of the order shown in FIG. It may be.

  The conversion units 35-1 to 35-4 are tables corresponding to the respective constraint lengths i (the conversion unit 35-1 is a table with i = 1, the conversion unit 35-2 is a table with i = 2, and the conversion unit 35-3 has a table with i = 3, and the conversion unit 35-4 has a table with i = 4), and the conversion rule corresponding to the supplied data is registered in the table, Using the conversion rule, the supplied 2 × i-bit data is converted into a 3 × i-bit code, and the code is output to the multiplexer 36.

  The multiplexer 36 selects a code from the conversion unit 35-i corresponding to the constraint length i supplied from the constraint length determination unit 33, and outputs the code as serial data via the buffer 37.

  Here, for example, in Table 6, it is assumed that there is no replacement code (11 01 11) that limits the repetition of the minimum run with the constraint length i = 3. At this time, if (01 11 01 11 01 11 01 11 01) is input as data, the conversion process is performed in the order of data (01) (11) (01) (11) (01). 010 101 010 101 010 101 010 101 010 "is generated as a code word string (channel bit string).

  When the code generated in this way is converted into a level code, for example, by converting the code to NRZI, the logic is inverted at “1” of the code word string, so that “011 001 100 110 011 001 100. The minimum inversion interval is continuous. Such a recording code string is a pattern in which an error is likely to occur during recording and reproduction at a high linear density.

  Therefore, as shown in Table 6, if the replacement code for limiting the repetition of the minimum run is defined as (11 01 11), the first data (01 11 01 11 11 11 01 11 01) in the data string (01 11 01 11 01 11 01 11 01) ) + (11 01 11) + (01) corresponds to ““ 0 ”+ (11 01 11) +“ 010 ”” and is replaced and converted, and (11 01 11) becomes “001 000 000”. . Further, from the next data (11 01 11) + (01) and the immediately preceding code word string “0”, it corresponds to ““ 0 ”+ (11 01 11) +“ 010 ”” and is replaced and converted (11 01 11) becomes “001 000 000”. Eventually, the code word string becomes “010 001 000 000 010 001 000 000 010...”, And the repetition of the minimum run is prevented from being continued. Therefore, a pattern that is likely to cause an error during recording / reproduction at a high linear density is removed, and even when the replacement conversion described above is performed, the minimum run and the maximum run are protected.

  In the above description, the case where Table 6 is used in the modulation unit 12 has been described, but Table 3 to Table 5 can also be used. In such a case, details of the minimum run continuation limit code detection unit 33 including replacement restrictions and the run length limit compensation code detection unit 34 including replacement restrictions in the modulation unit 12 shown in FIG. Any one of Table 5 may be used.

By the way, the arrangement order may be different within each constraint length of the data string and the code word string in Tables 3 to 6. For example, the constraint length i = 1 part of Table 6
Data sign
i = 1 11 * 0 *
10 001
01 010
May be arranged as follows:
Data sign
i = 1 11 * 0 *
10 010
01 001
Even in this case, the number of “1” of the data string element and the number of “1” of the codeword string element are both equal to 1 or 0 when divided by 2. .

In addition, (1) and (0) of each element of the data string in Tables 3 to 6 may be inverted. That is,
Data string Code string
11 * 0 *
10 001
01 010
0011 010 100
0010 010 000
0001 000 100
However, even in this case, the number of “1” of the data string element and the number of “1” of the codeword string element are each the remainder when divided by 2. Both match with 1 or 0.
Data string Code string
00 * 0 *
01 001
10 010
1100 010 100
1101 010 000
1110 000 100

  FIG. 6 is a block diagram showing a configuration of a demodulator 51 that demodulates data modulated by the above-described processing. The demodulator 51 demodulates the variable length code (d, k; m, n; r) = (1, 7; 2, 3; 4) into a data string using the inverse conversion table of Table 6.

  The demodulator 51 compares the signal transmitted from the transmission path or the signal reproduced from the recording medium, converts it to inverse NRZI, and converts the recording code string into a codeword string. Input to the unit 52. The signal output from the comparator / inverse NRZI conversion unit 52 is input to the demodulation unit 53 that demodulates based on the demodulation table (inverse conversion table). The data string demodulated by the demodulating unit 53 is input to the DSV control bit removing unit 54 which removes the DSV control bits in the data string inserted at an arbitrary interval and restores the original data string. The data string output from the DSV control bit removing unit 54 is input to the buffer 44, where the serial data is temporarily stored, read at a predetermined transfer rate, and output. The timing management unit 56 generates a timing signal and supplies it to each unit to manage timing.

  FIG. 7 is a block diagram illustrating a configuration example of the demodulation unit 53. The constraint length determination unit 61 receives the digitized signal from the comparator / inverse NRZI conversion unit 52 and determines the constraint length i. Further, the minimum run continuation limit code detection unit 62 detects a dedicated code given to limit the continuation of the minimum run from the digitized signal, and sends a corresponding detection signal to the constraint length determination unit 61. . Further, the run length limit compensation code detection unit 63 detects a dedicated code given to compensate for the maximum run from the input signal, and sends a detection signal corresponding to the code to the constraint length determination unit 61.

  The inverse conversion units 64-1 to 64-4 have a table for inversely converting an n × i-bit variable length code into m × i-bit data. The multiplexer 65 selects any one of the outputs from the inverse transform units 64-1 to 64-4 according to the determination result of the constraint length determination unit 61, and outputs it as serial data.

  Next, the operation of the demodulator 53 shown in FIG. 7 will be described. A signal transmitted from the transmission path or a signal reproduced from the recording medium is input to the comparator / inverse NRZI unit 52 and is compared. Further, a digital signal of an inverse NRZI code (“1” is a code indicating an edge) is input to the constraint length determination unit 61, and the constraint length is determined according to the basic code portion of the conversion table (inverse conversion table) shown in Table 6. The determination process is performed. The determination result (constraint length) of the constraint length determination unit 61 is output to the multiplexer 65.

  The digital signal input to the demodulator 53 is also input to the minimum run continuation limit code detector 62. The minimum run continuation restriction code detection unit 62 incorporates a replacement code for restricting continuation of the minimum run in the conversion table shown in Table 6 (in the case of Table 6, a part for converting the code word “001 000 000”). When the code “001 000 000 not100” that limits the continuation of the minimum run is detected with reference to the inverse conversion table, a detection signal with a constraint length i = 3 is output to the constraint length determination unit 61. Here, “not 100” means a code word other than “100”.

  Further, the input digital signal is also input to the run length limit compensation code detection unit 63. The run length restriction compensation code detection unit 63 uses replacement codes (in the case of Table 6, code word strings “000 100 100 100” and “010 100 100 100” in Table 6) that protect the maximum run in the conversion table shown in Table 6. When a replacement code that protects the maximum run is detected with reference to this inverse conversion table, a detection signal with a constraint length i = 4 is output to the constraint length determination unit 61.

  FIG. 8 is a diagram illustrating the determination processing of the constraint length determination unit 61, the minimum run continuous restriction code detection unit 62, and the run length restriction compensation code detection unit 63. That is, the run length limit compensation code detection unit 63 has an inverse conversion portion of “000 100 100 100” or “010 100 100 100” in the table shown in Table 6, and the input 12-bit codeword string is If it coincides with this, a detection signal with a constraint length i = 4 is output to the constraint length determination unit 61.

  The minimum run continuation restriction code detection unit 62 has an inverse conversion portion of “001 000 000” in the table shown in Table 6, and when the input 12-bit codeword string matches “001 000 000 not100”, A detection signal with a constraint length i = 3 is output to the constraint length determination unit 61.

  The constraint length determination unit 61 incorporates an inverse conversion table shown in Table 6, and the input 9-bit or 12-bit code word string is “000 100 100”, “000 100 000 not 100”, “010”. When it matches either “100 100” or “010 100 000 not 100”, it is determined that the constraint length i = 3. If this is not the case, if the input 6-bit or 9-bit code word string matches one of “010 100”, “010 000 not 100”, or “000 100”, the constraint length i = 2. judge. Further, if this is not the case, when the input 3-bit codeword string matches any of “000”, “101”, “001”, or “010”, the constraint length determination unit 61 Then, it is determined that the constraint length i = 1.

  It should be noted that the constraint length determination process of the constraint length determination unit 61, the minimum run continuous limit code detection unit 62, and the run length limit compensation code detection unit 63 is performed with i = 1, i = 2, i from the smaller constraint length. = 3, i = 4 may be performed in this order.

  When the constraint length is determined in the order of i = 1, i = 2, i = 3, i = 4 from the smaller one, the input codeword string is, for example, “000 100 100 100” When the constraint length determination unit 61 determines matching or mismatching in order from the smallest constraint length, the constraint length i = 1, the constraint length i = 2, the constraint length i = 3, or the constraint length i = 4. This applies to all constraint lengths i. In such a case, the maximum one of the determined constraint lengths i may be selected and determined.

  Among the inverse conversion units 64-1 to 64-4, for example, the inverse conversion unit 64-1 has data (11) at addresses “101” and “000”, and data (10) at address “001”. Data (01) is written in the address “010”. Hereinafter, each inverse conversion table of the inverse conversion units 64-2 to 64-4 is similarly written with corresponding data, and the supplied 3 × i-bit codeword string is converted into a 2 × i-bit codeword sequence. The data word is converted into a data string, and the data word is output to the multiplexer 65.

  The multiplexer 65 selects any of the data supplied from the inverse conversion units 64-1 to 64-4 according to the constraint length determination result of the constraint length determination unit 61, and outputs it as serial data.

The inverse conversion table of Table 6 is shown in Table 8 below.
<Table 8> Inverse conversion table (1, 7; 2, 3; 4)
Codeword sequence Demodulated data sequence
i = 4: limits k to 7
000 100 100 100 00001000
010 100 100 100 00000000
i = 3: Prohibit Repeated Minimum Transition Runlength
001 000 000 (not 100) 110111
___________________
i = 3 000 100 100 000011
000 100 000 (not 100) 000010
010 100 100 000001
010 100 000 (not 100) 000000
i = 2 010 100 0011
010 000 (not 100) 0010
000 100 0001
i = 1 101 11
000 11
001 10
010 01

  Next, the operation of the DSV control bit removing unit 54 will be described with reference to the flowchart of FIG. The DSV control bit removing unit 54 has a counter inside, and when the bits of the data string are input from the demodulating unit 53 in step S1, the number is counted. In step S2, it is determined whether or not the count value has reached a predetermined data interval for inserting the DSV control bits. If it is determined that the count value is not an arbitrary data interval, the process proceeds to step S3 and is input from the demodulator 53. The data is output to the buffer 55 as it is. On the other hand, if it is determined in step S2 that the data interval is the predetermined data interval, the bit is a DSV control bit, so the process of step S3 is skipped and the process proceeds to step S4. That is, in such a case, the bit is not output to the buffer 55 but is discarded.

  Next, in step S4, processing for inputting the next data is executed. Then, in step S5, it is determined whether or not the processing for all data has been completed. If there is data that has not been processed yet, the processing returns to step S1 and the subsequent processing is repeatedly executed. If it is determined in step S5 that all data has been processed, the processing of this flowchart is terminated.

  As described above, the data output from the DSV control bit removal unit 54 is data from which the DSV control bits have been removed. This data is output via the buffer 55.

  By the way, FIG. 10 and FIG. 11 show a configuration example of a modulation apparatus when a synchronization signal (Sync) is inserted during data modulation, and FIG. 12 shows a configuration example of a demodulation apparatus. Also in these embodiments, the data string is modulated and demodulated into variable length codes (d, k; m, n; r) = (1, 7; 2, 3; 4) according to Table 6. And

  In modulation apparatus 71 that inserts a synchronization signal at a predetermined interval, the output of DSV control bit determination / insertion section 72 is supplied to modulation section 73 and SYNC determination section 74 as shown in FIG. The output from the modulation unit 73 is also supplied to the SYNC determination unit 74. The SYNC determination unit 74 determines a synchronization signal from these input signals and outputs the output to the SYNC insertion unit 75. The SYNC insertion unit 75 inserts the synchronization signal input from the SYNC determination unit 74 into the modulation signal input from the modulation unit 73 and outputs it to the NRZI conversion unit 76. Since the other configuration is the same as that of the modulation device 1 shown in FIG. 1, the description thereof is omitted.

  The SYNC determination unit 74 determines the synchronization signal as “# 01 000 000 001” when the synchronization signal pattern is 12 codewords. “#” Depends on the immediately preceding data string (which may include the DSV control bit) delimited by the insertion of the synchronization signal. When the delimited data string is modulated according to the conversion table, the termination table is displayed. When used and terminated, “#” = “1”, and when terminated by the table of Table 2 without using the termination table, “#” = “0”.

  The modulation unit 73 outputs “#” = “1” to the SYNC determination unit 74 when the termination table is used, and “#” = “0” when the termination table is not used. When the SYNC determination unit 74 receives an input of the value “#” from the modulation unit 73, the SYNC determination unit 74 inserts the value into the first bit of the synchronization signal. Then, the synchronization signal is output to the SYNC insertion unit 75.

  The SYNC insertion unit 75 inserts the synchronization signal output from the SYNC determination unit 74 into the output from the modulation unit 73 and outputs it to the NRZI conversion unit 76. Other operations are the same as those of the modulation device 1 shown in FIG.

  The first data after the synchronization signal is inserted is converted from the beginning (without considering the data immediately before the synchronization signal). The modulation unit 73 and the SYNC determination unit 74 include a counter for counting a predetermined interval at which the synchronization signal is inserted, and determines the position of the synchronization signal corresponding to the count value.

  FIG. 11 is a block diagram showing a configuration of another modulation device 71. The signal input to the modulation device 71 is input to a control bit insertion unit 81 that inserts a DSV control bit “1” or “0” at a predetermined position in the data string, and further modulates two data strings. The signal is input to the modulation unit 73. An output from the modulation unit 73 is input to a synchronization signal insertion unit 75 that inserts a synchronization signal at a predetermined interval, and is further input to an NRZI conversion unit 76 that performs NRZI conversion and level encoding. The signal output from the NRZI conversion unit 76 is input to a DSV bit / SYNC determination unit 82 that selects a DSV-controlled one from two kinds of level code sequences and uses this as a recording code sequence. The modulation device 71 also includes a timing management unit 77 that generates a timing signal and supplies the timing signal to each unit to manage timing.

  The modulation unit 73 of the modulation device 71 shown in FIG. 10 or FIG. 11 is realized by the same configuration as the modulation unit 12 shown in FIG. 3 or FIG. It is possible.

  FIG. 12 is a block diagram illustrating a configuration example of a demodulating device that demodulates a code modulated and output by the modulating device 71 of FIG. 10 or FIG. The code input to the demodulator 91 via a predetermined transmission path is input to the comparator / inverse NRZI conversion unit 92 to be a codeword string. The codeword string output from the comparator / inverse NRZI conversion unit 92 is input to the demodulation unit 93 and the SYNC identification unit 94. The SYNC identification unit 94 identifies the synchronization signal using the input code, and outputs the identification signal to the demodulation unit 93 and the SYNC removal unit 95. The SYNC removal unit 95 removes the synchronization signal from the demodulated signal input from the demodulation unit 93 in accordance with the output of the SYNC identification unit 94, and outputs the signal from which the synchronization signal has been removed to the DSV control bit removal unit 96.

  The SYNC identification unit 94 counts codewords with a built-in counter, and determines the position of the synchronization signal inserted at a predetermined interval from the count value. When the position of the sync signal pattern is found, the SYNC identifying unit 94 reads the “#” portion determined at the time of modulation. That is, the first bit of the sync signal bit portion is read and output to the demodulator 93. If the first bit is “1”, the demodulator 93 uses the termination table shown in Table 6 for demodulation of the immediately preceding code. If the first bit is “0”, the demodulator 93 uses the table of conversion codes shown in Table 6 for demodulation of the immediately preceding code. The other sync signal bits are unnecessary because they are bits having no information.

  The SYNC identification unit 94 outputs an identification signal for identifying the bits constituting the synchronization signal to the SYNC removal unit 95. The SYNC removal unit 95 removes only the synchronization signal bit designated by the identification signal output from the SYNC identification unit 94 from the data output from the demodulation unit 93 and outputs the data to the DSV control bit removal unit 96.

  The demodulator 93 of the demodulator 91 shown in FIG. 12 can be realized with the same configuration as the demodulator 53 shown in FIG.

  Here, the result of verifying the modulation result using the conversion table described in the embodiment is shown. Table 6 that modulates the data string in which the continuation of Tmin is limited and the DSV control bit is inserted in the data string is a conversion code that further adds a conversion code conversion condition to reduce demodulation error propagation. Yes. In the simulation, the conventional 1,7PP code according to Table 2 was compared with the 1,7PP code according to Table 6 using the present embodiment.

  After random data 13,107,200 bits are created, DSV control is performed by inserting 1 bit of DSV control bits every 56 data-bits, and then a codeword string (channel bit string) is used using the modulation code table of Table 2 or Table 6. The result when converted to is as follows.

The numerical value of each result was calculated as follows.
Ren_cnt [1 to 10]: Number of occurrences of 1 to 10 repetitions of the minimum run.
T_size [2 to 10]: Number of occurrences of each run from 2T to 10T.
Sum: Number of bits.
Total: Number of runlengths. Total number of runs (2T, 3T, ...)
Average Run: (Sum / Total)
Numerical value of run distribution: (T_size [i] * (i)) / (Sum), i = 2,3,4 ,,, 10

  The numerical values shown in the columns 2T to 10T in Table 9 below represent the numerical values of this run distribution.

  Number of continuous distribution of Tmin: (Ren_cnt [i] * (i)) / T_size [2T], i = 1,2,3,4 ... 10

The values shown in the columns of RMTR (1) to RMTR (7) in Table 9 represent the numerical values of the continuous distribution of this minimum run.
max-RMTR: Maximum number of times the minimum run is repeated.
peak DSV: A positive peak and a negative peak of the DSV value when the DSV value is calculated in the process of performing the DSV control of the codeword string. The redundancy rate when DSV control bits are inserted every 56 data strings as DSV control bits is 1 bit of DSV control bits for 56 data strings, so the redundancy is 1.75% (1 / (1 + 56)) It is.

<Table 9> *** 1,7PP comparison ***
<Table 2><Table6>
Conventional 1,7PP New 1,7PP
Average Run 3.3665 3.3723
Sum 20011947 20011947
Total 5944349 5934288

2T 0.2256 0.2293
3T 0.2217 0.2111
4T 0.1948 0.1949
5T 0.1499 0.1515
6T 0.1109 0.1111
7T 0.0579 0.0672
8T 0.0392 0.0349
9T ------ ------

RMTR (1) 0.3837 0.3803
RMTR (2) 0.3107 0.3032
RMTR (3) 0.1738 0.1799
RMTR (4) 0.0938 0.0968
RMTR (5) 0.0299 0.0319
RMTR (6) 0.0081 0.0079
RMTR (7) ------ ------
max-RMTR 6 6
====================================
peak DSV # -36to36 # -36to37
("#": 56data-bit + 1dc-bit, 1.75%)

  From the above results, the 1,7PP code according to the conventional table 2 and the 1,7PP code according to the table 6 of the present embodiment are the minimum run d = 1, the maximum run k = 7, and the minimum run, respectively. Is confirmed to be limited to 6 times, and DSV control can be performed within the data string from the peak DSV result (the value of peak DSV is within the predetermined range) ) Was shown. Further, from Table 9, it was found that there is no difference in characteristics between the run distribution and the minimum run continuation number distribution due to the difference between Table 2 and Table 6.

  Next, a simulation result of demodulation will be described. Demodulation was performed by the same demodulation method in both Table 2 and Table 6 so that comparison was possible. While confirming normal demodulation, a bit shift error was arbitrarily generated in the codeword string, and the demodulation error propagation characteristics at this time were examined. Demodulation error propagation is how many bits of error are propagated at the time of demodulation with respect to a bit shift error at one location in the codeword string.

<Table 10> *** Shift error response ***
<Table 2><Table6>
Conventional 1,7PP New 1,7PP
worst case 3 Bytes 3 Bytes
(dc bit) exclude.exclude
Byte error (0) 0.177 0.183
Byte error (1) 0.673 0.672
Byte error (2) 0.150 0.144
Byte error (3) 0.000 0.000
Average-
Byte error rate 0.973Byte 0.961Byte

  From the results of Table 10, it was confirmed that the worst error propagation of 1,7PP is 3 bytes in both Tables 2 and 6, but there is almost no actual occurrence frequency. Also, by adding the conversion condition of the replacement code according to Table 6 and giving a conversion code that reduces demodulation error propagation, the occurrence rate of long error propagation is reduced from 15.0% to 14.4%, and the average byte error propagation length Could also be reduced.

  As another effect of the present embodiment, consider the case of Table 5. When this table is used, the RMTR characteristic can be changed at the same time as the average error propagation length decreases.

<Table 11> *** 1,7PP comparison ***
<Table 2><Table6><Table5>
Conventional 1,7PP New 1,7PP New 1,7PP
RMTR (1) 0.3837 0.3803 0.3886
RMTR (2) 0.3107 0.3032 0.3099
RMTR (3) 0.1738 0.1799 0.1839
RMTR (4) 0.0938 0.0968 0.0866
RMTR (5) 0.0299 0.0319 0.0261
RMTR (6) 0.0081 0.0079 0.0049
RMTR (7) ------ ------ ------
max-RMTR 6 6 6

  Table 5 can reduce the number of occurrences of long RMTR. Therefore, when a simulation similar to that in Table 9 is performed, RMTR is the same up to 6 times, and RMTR (4), RMTR (5), The occurrence frequency of large number of times such as RMTR (6) decreases. In particular, Table 11 shows that the appearance probability of the maximum RMTR (6) decreases from about 0.008 to about 0.005, and is reduced to about 2/3.

  In this way, by further reducing the large RMTR, it is possible to prevent long error propagation when an error occurs, and therefore it can be expected that the error propagation value is also improved.

Since the 1,7PP code is provided with a replacement code for limiting the number of repetitions of the minimum run length in the conversion table of the minimum run d = 1, the maximum run k = 7, and the conversion rate m / n = 2/3.
(1) The tolerance for recording / reproduction at high linear density and tangential tilt can be improved.
(2) The portion with a low signal level is reduced, the accuracy of waveform processing such as AGC and PLL is improved, and the overall characteristics can be enhanced.
(3) Compared to the conventional case, the path memory length for Viterbi decoding or the like can be designed to be short, and the circuit scale can be reduced.

Also, the remainder of dividing the number of “1” s in the elements of the conversion table by the number of “1s” in the elements of the codeword string to be converted is equal to 1 or 0. Because
(4) Redundant bits for DSV control can be reduced.
(5) In the minimum run d = 1 and (m, n) = (2,3), DSV control can be performed with 1.5 codewords.
(6) The redundancy is low and the minimum and maximum runs can be protected.

In addition, this table has a replacement code that specifically observes the run length limitation.
(7) The table can be made compact.

In the present embodiment, the point that the error propagation length at the time of demodulation becomes longer is a table structure that reduces the number of occurrences of conversion codes that increase error propagation,
(8) Demodulation error propagation during bit shift can be made smaller than the conventional 1,7PP in Table 2.

  In the present specification, as a providing medium for providing a user with a computer program for executing the above processing, an information recording medium such as a magnetic disk or a CD-ROM, or a transmission medium via a network such as the Internet or a digital satellite may be used. included.

  11 DSV bit determination / insertion unit, 12 modulation unit, 13 NRZI conversion unit, 14 timing management unit, 21 control bit insertion unit, 22 DSV bit determination unit, 32 constraint length determination unit, 33 minimum run continuous restriction code including replacement restriction Detection unit, 34 run length limitation compensation code detection unit including replacement limitation, 41 minimum run / maximum run compensation code detection unit, 42 minimum run continuous limit code detection unit, 43 immediately preceding / immediate bit reference unit, 52 compare / inverse NRZI Conversion unit, 53 demodulation unit, 54 DSV control bit removal unit, 61 constraint length determination unit, 62 minimum run continuous limit code detection unit, 63 run length limit compensation code detection unit

Claims (5)

In a modulation device that converts an m-bit data string into an n-bit codeword string at a ratio of 2 to 3,
A classifying means for classifying the input data string into m-bit data strings;
When the minimum run d is set to 1 or more and the segmented m-bit data string is converted into an n-bit code word string based on the first table, the minimum run d is predetermined in the plurality of code word strings. When the code word string immediately before and immediately after one code word string among the plurality of code word strings is a predetermined code word string, the first code word string is converted into the first code word string, When the codeword string immediately before and immediately after one codeword string is not the predetermined codeword string, the plurality of codewords based on a second table to be converted to a second codeword string A modulation device comprising: conversion means for converting the sequence into a limit code that limits the number of consecutive minimum runs d. The modulation apparatus according to claim 1, wherein the second table is a table in which a last bit of the immediately preceding codeword string is 0 or 1. The modulation device according to claim 1, wherein the limit code is generated by a code other than the limit code or a combination of a part of the codes. In a modulation method of a modulation device that converts an m-bit data string into an n-bit code word string at a ratio of 2 to 3,
The input data string is divided into m-bit data strings.
When the minimum run d is set to 1 or more and the segmented m-bit data string is converted into an n-bit code word string based on the first table, the minimum run d is predetermined in the plurality of code word strings. When the code word string immediately before and immediately after one code word string among the plurality of code word strings is a predetermined code word string, the first code word string is converted into the first code word string, When the codeword string immediately before and immediately after one codeword string is not the predetermined codeword string, the plurality of codewords based on a second table to be converted to a second codeword string A modulation method comprising the step of converting a sequence into a limit code that limits the number of consecutive minimum runs d. A data sequence created by a modulation method for converting an m-bit data sequence into an n-bit codeword sequence at a ratio of 2 to 3,
The input data string is divided into m-bit data strings,
When the minimum run d is set to 1 or more and the segmented m-bit data string is converted into an n-bit code word string based on the first table, the minimum run d is predetermined in the plurality of code word strings. When the code word string immediately before and immediately after one code word string among the plurality of code word strings is a predetermined code word string, the first code word string is converted, When the code word string immediately before and immediately after one code word string is not the predetermined code word string, the plurality of the codes based on the second table converted into the second code word string A recording medium on which a data string having a data structure in which a word string is converted into a restriction code that restricts the number of consecutive minimum runs d is recorded.

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