JP4900021B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a capacitor and a method for manufacturing the same.

  A DRAM is a high-speed semiconductor storage device that stores information in the form of electric charges in a capacitor monolithically formed in a semiconductor device, and is widely used as a storage device for an information processing apparatus such as a computer.

  Recently, a semiconductor device in which such a DRAM and an analog circuit device are monolithically formed on the same semiconductor substrate is required. Such analog circuit devices generally include a monolithically formed capacitor.

  FIG. 1 shows a configuration of a conventional DRAM 10.

  Referring to FIG. 1, a DRAM 10 is formed on a Si substrate 11 having a memory cell region 10A and a peripheral region 10B. An active region is defined on each of the memory cell region 10A and the peripheral region 10B. A field oxide film 12 is formed, and in the active region defined by the field oxide film 12 in the cell region 10A, polysilicon gate electrodes 13A to 13C corresponding to the word lines WL are respectively gate-oxidized. Diffusion regions 11a to 11e are formed in the substrate 11 adjacent to the gate electrodes 13A to 13C. Each of the gate electrodes 13A to 13C carries a sidewall insulating film. However, the sidewall insulating film can be omitted.

  Similarly, a gate electrode 13D is formed in the peripheral region 10B via a gate insulating film 13d, and diffusion regions 11f and 11g are formed in the substrate 11 adjacent to the gate electrode 13D. Further, in the peripheral region 10B, a high concentration diffusion region 11h is formed in a region separated by the field oxide film 12, and corresponds to the gate insulating film 13d of the gate electrode 13D on the high concentration diffusion region 11h. A capacitor electrode 13E is formed through the insulating film 13e. As a result, the insulating film 13e forms the capacitor C of the analog circuit device formed in the peripheral region 10B together with the capacitor electrode 13E and the diffusion region 11h.

  The gate electrodes 13A to 13D, the word line WL, and the capacitor electrode 13E are covered with a first interlayer insulating film 14 formed on the substrate 11 so as to continuously cover the regions 10A and 10B. In the insulating film 14, contact holes 14A to 14C exposing the diffusion regions 11b, 11d, and 11f are formed. Side walls of the contact holes 14A to 14C are covered with side wall insulating films 14a to 14c, respectively, and bit line electrodes 15A and 15B are formed on the interlayer insulating film 14 so as to fill the contact holes 14A and 14B. Electrode 15C is formed so as to fill 14C. The sidewall insulating film 14a functions to prevent a short circuit between the electrode 15A and the gate electrode 13A when the position of the contact hole 14A is shifted. The same applies to the sidewall insulating films 14b and 14c.

  Furthermore, the electrodes 15A to 15C are covered with a second interlayer insulating film 16 formed on the interlayer insulating film 14, and the interlayer insulating film 16 includes the diffusion regions 11a and 11c in the memory cell region 10A. Exposed contact holes 16A and 16B are formed. Side wall insulating films 16a and 16b are formed in the contact holes 16A and 16B, respectively, and polysilicon storage electrodes 17A and 17B filling the contact holes 16A and 16B are formed on the interlayer insulating film 16, respectively. The sidewall insulating films 16a and 16b prevent the storage electrodes 17A and 17B from being short-circuited with the adjacent gate electrode 13A or 13B.

  In the memory cell region 10A, the storage electrodes 17A and 17B are covered with a dielectric film 18, and the dielectric film 18 is further covered with a polysilicon counter electrode 19. Further, the polysilicon counter electrode 19 is covered with a third interlayer insulating film 20 that continuously covers the peripheral region 10B. In the interlayer insulating film 20, a contact hole 20A and an electrode 13E that expose the electrode 15C are exposed. Are exposed, and electrodes 21A and 21B are formed on the interlayer insulating film 20 through the contact holes 20A and 20B. Further, wiring patterns 21C and 21D are formed on the interlayer insulating film 20. The storage electrodes 17A and 17B together with the dielectric film 18 and the counter electrode 19 thereon form a memory cell capacitor.

  2A to 2C show in detail a process for forming a memory cell capacitor in the semiconductor device of FIG. However, in FIGS. 2 (A) to 2 (C), the same reference numerals are given to the portions described above, and description thereof is omitted.

  Referring to FIG. 2A, after a contact hole 16B exposing the diffusion region 11c is formed in the second interlayer insulating film 16, the sidewall of the contact hole 16B is covered on the interlayer insulating film 16. The insulating film 16 ′ is deposited as described above, and the insulating film 16 ′ is subjected to anisotropic etching substantially perpendicular to the main surface of the substrate 11 in the step of FIG. The upper insulating film 16 ′ is removed, and the sidewall insulating film 16b is formed.

  Next, in the step of FIG. 2B, a polysilicon film is further deposited on the interlayer insulating film 16 so as to fill the contact hole 16B, and this is patterned by a resist process, whereby the storage electrode 17B. Form.

  Further, in the step of FIG. 2C, the dielectric film 18 and a polysilicon film constituting the counter electrode 19 are sequentially deposited on the structure of FIG. 2B, and further patterned by a resist process. As a result, a memory cell capacitor is formed.

  2A to 2C, the dry etching process is performed twice in the process of FIG. 2B, and the dry etching process is performed again in the process of FIG. 2C. At that time, since the selection ratio is not ideal in each dry etching, as shown in FIGS. 2B and 2C, some steps are generated at the edge of the storage electrode 17B and the edge of the counter electrode 19. Is inevitable. When these steps are accumulated, as shown in FIG. 2C, the step at the edge of the counter electrode 19 is substantially lower than the surface of the original interlayer insulating film 16, and the memory cell region 10A and the peripheral region 10B. The step formed on the surface of the interlayer insulating film 20 is enlarged. Further, as a result of etching of the surface of the interlayer insulating film 16, there is a possibility that the electrode 15C formed on the interlayer insulating film 14 is exposed in the peripheral region 10B.

  Accordingly, it is a general object of the present invention to provide a new and useful semiconductor device that solves the above-described problems and a method for manufacturing the same.

  A more specific object of the present invention is to minimize a step between a memory cell region and a peripheral circuit region in a semiconductor device having a memory cell region including a memory cell capacitor and a peripheral circuit region not including the memory cell capacitor. It is to become.

  Another object of the present invention is to form a step portion between a memory cell region and a peripheral circuit region in a semiconductor device having a memory cell region including a memory cell capacitor and a peripheral circuit region not including the memory cell capacitor. Another object of the present invention is to provide a semiconductor device from which irregular residual polysilicon patterns are removed.

  Still another object of the present invention is to form a capacitor in a peripheral circuit region without increasing a mask process in a semiconductor device having a memory cell region including a memory cell capacitor and a peripheral circuit region not including the memory cell capacitor. There is to do.

A method for manufacturing a semiconductor device includes a method of manufacturing a semiconductor device including a memory cell region and a peripheral circuit region on a substrate, and a dummy cell region disposed between the memory cell region and the peripheral circuit region. Forming an interlayer insulating film so as to cover the memory cell region, the peripheral circuit region, and the dummy cell region; forming a contact hole in the memory cell region and the dummy cell region in the interlayer insulating film; and Forming an insulating film on the insulating film and in the contact hole; forming a mask pattern on the insulating film to cover the peripheral circuit region and the dummy cell region; and using the mask pattern as a mask, the insulating film and patterning the interlayer insulating film, the height of the surface of the interlayer insulating film, the peripheral circuit region and the dummy territory in the memory cell region To form a boundary consisting of the step to be lower than the height, the side wall surface and the bottom surface of the contact hole of the dummy cell region leaving the insulating film, only the further contact hole inner wall of the memory cell region side walls in A step of forming an insulating film; and a memory cell capacitor on the interlayer insulating film in the memory cell region and the dummy cell region, and the memory cell capacitor in the memory cell region through the contact hole only in the memory cell region. A step of forming the memory cell capacitor in contact with the diffusion region, and a step of covering a boundary portion between the memory cell region and the dummy cell region with a conductor pattern. After the film patterning step, depositing a first conductor film on the interlayer insulating film; By patterning the serial first conductive film to form a storage electrode to cover the contact hole in the memory cell region and the dummy region, depositing a capacitor dielectric film on the storage electrode, the capacitor Depositing a second conductor film on the dielectric film so as to include a portion covering the storage electrode; and patterning the second conductor film to form counter electrodes in the memory cell region and the dummy cell region step and a step to further patterning the second conductive film, the conductor pattern covering a boundary portion between the memory cell region and the dummy cell region is performed so as to form at the same time as the counter electrode .

[Action]
According to the first aspect of the present invention, in the manufacture of a semiconductor device having a memory cell region and a peripheral region on a substrate, an interlayer insulating film on the substrate is formed before forming a memory cell capacitor in the memory cell region. By making the thickness thinner than the peripheral region in the memory cell region, the dry etching process accompanying the formation of the memory cell capacitor reduces the thickness of the interlayer insulating film in the peripheral circuit region. The problem that a large step is generated at the boundary between the peripheral circuit area and the peripheral circuit area is reduced.

  According to the second feature of the present invention, when a capacitor is included in the peripheral circuit, the capacitor is formed without increasing the mask process simultaneously with the electrode pattern filling the contact hole formed in the interlayer insulating film. it can. At this time, the capacitor insulating film is formed simultaneously with the sidewall insulating film formed for protecting the sidewall of the contact hole. By forming such a capacitor on a field insulating film, for example, an increase in the area of the semiconductor device can be avoided.

  Furthermore, according to the third feature of the present invention, in a semiconductor device having a memory cell region and a peripheral region on a substrate, the memory cell capacitor is formed so as to cover a step portion between the memory cell region and the peripheral region. At the same time, by forming the conductor pattern, it is possible to suppress an undesirable effect such as a short circuit due to an irregular conductor residue remaining in the step portion due to the patterning of the memory cell capacitor. By forming such a conductor pattern, it is possible to increase an allowable error in mask alignment when defining the memory cell region and the peripheral region.

  According to a fourth aspect of the present invention, in a semiconductor device having a memory cell region and a peripheral region on a substrate, a dummy cell formed around the memory cell array is provided at a boundary portion between the memory cell region and the peripheral region. By forming on the field oxide film, an increase in the area of the semiconductor device due to the dummy cell can be avoided.

  According to a fifth aspect of the present invention, in a semiconductor device in which two or more types of integrated circuits such as a DRAM and an analog circuit are formed on a substrate, a capacitor insulating film of a capacitor included in the analog circuit is protected with a conductor film. Thus, the natural oxide film can be removed from the substrate surface in the contact hole in the DRAM without reducing the thickness of the capacitor insulating film, and the contact resistance can be reduced.

  According to a sixth aspect of the present invention, in a semiconductor device in which two or more types of integrated circuits such as a DRAM and an analog circuit are formed on a substrate, the capacitor of the analog circuit and the bit line contact or bit line pattern of the DRAM are simultaneously applied. Thus, it is possible to form without increasing the number of mask processes.

  According to a feature of the present invention, in a semiconductor device including a first region or memory cell region having a capacitor and a second region or a peripheral region, the second region is protected when the capacitor is formed. By doing so, the etching of the second region accompanying the patterning of the capacitor is avoided, and the step caused by the presence of the capacitor between the first region and the second region can be reduced. it can. Further, by covering the stepped portion between the first region and the second region with the conductor pattern, the problem of peeling and scattering of the residual conductor pattern that is likely to be formed on the stepped portion is avoided. Furthermore, when it is necessary to form a capacitor in the peripheral region, by forming the capacitor insulating film simultaneously with the sidewall insulating film of the contact hole formed in the memory cell region, without increasing the area of the semiconductor device, In addition, it is possible to form a capacitor having a large capacity without increasing the number of mask processes compared to the conventional method. Further, the dummy memory cell capacitor formed in the peripheral portion of the memory cell region is formed of the same insulating film as the sidewall insulating film on the field oxide film where the tip of the storage electrode covers the contact hole side wall of another memory cell capacitor. By forming the cover so as to be covered, it is possible to avoid an extra area increase accompanying the formation of the dummy memory cell.

  Hereinafter, the present invention will be described.

  FIGS. 3A to 5F show a manufacturing process of the DRAM according to the first embodiment of the present invention.

  Referring to FIG. 3A, an n-type well 31A is formed on a p-type Si substrate 31, and an initial oxide film (not shown) having a thickness of about 3 nm is formed on the substrate 31. After the formation, a SiN pattern 32 having a thickness of about 115 nm is formed so as to expose the element isolation region.

  Next, in the step of FIG. 3B, field oxide films 33A to 33F are formed on the substrate 31 to a thickness of about 320 nm by a wet oxidation process using the SiN pattern 32 as a mask. Thus, a p-type well 31B is formed in the n-type well 31A corresponding to the memory cell region 30A. Further, in the peripheral circuit region 30B outside the p-type well 31B in the substrate 31, a p-type well 31C is formed across the p-type substrate 31 and the n-type well 31A. Actually, the p-type well 31C is formed first, and then the p-type well 31B is formed. The n-type well may be formed by high energy implantation after the field oxide film is formed.

  Further, in the step of FIG. 3B, a gate oxide film 34 having a thickness of about 8 nm is formed on the surface of the substrate 31 by thermal oxidation, and an amorphous silicon layer doped with P on the gate oxide film 34 is heated. Deposited to a thickness of about 160 nm by CVD. By patterning the formed amorphous silicon layer by a photolithography process, gate electrodes 35A to 35F are formed. As is well known, the gate electrodes 35A to 35F constitute a part of the word line WL, and the word lines WL in other memory cell regions extend on the field oxide films 33A and 33B in the memory cell region.

  Further, P @ + ions are implanted by using the gate electrodes 35A to 35F as a mask, so that n <-> type diffusion regions 31a to 31d are formed in the memory cell region 30A adjacent to the gate electrodes 35A to 35C. In the P-type well 31C of the region 30B, n − -type diffusion regions 31h to 31k constituting LDD regions are formed adjacent to the gate electrodes 35E and 35F. At the same time, in the peripheral region 30B, n − type diffusion regions 31f and 31g are formed in the N type well 31A adjacent to the gate electrode 35D.

  Further, B + ions are implanted into the n-type well region 31A of the peripheral circuit region 31A in a state where the memory cell region 30A and the p-type well 31C are protected by a resist, and are formed adjacent to the gate electrode 35D. The conductivity type of the diffusion regions 31f and 31g is changed to p − type.

  Next, an oxide film is deposited so as to cover the gate electrodes 35A to 35F, and further etched back to form sidewall oxide films on the respective gate electrodes 35A to 35F.

  3B, the n-type well 31A in the memory cell region 30A and the peripheral circuit region 30B is covered with a resist, and the gate electrodes 35E and 35F and side walls on both sides thereof are formed in the p-type well 31C. As + ions are implanted using the oxide film as a mask, n + -type diffusion regions 31l to 31o are formed outside the sidewall oxide film.

3B, the surface of the substrate 31 is covered with a resist so that the portion of the n-type well 31A in the peripheral circuit region 30B is exposed, and BF ₂ + is ion-implanted. The p + -type diffusion regions 31p and 31q are formed outside the sidewall oxide film adjacent to the gate electrode 35D.

  4C, a BPSG film 36 is deposited to a thickness of about 250 nm on the structure of FIG. 3B, and the diffusion regions 31b, 31e, 31p and 31n are further formed in the BPSG film 36. Contact holes 36A to 36D are formed to expose each of. Further, an oxide film is deposited on the BPSG film 36 by a thermal CVD method and etched back on the entire surface, thereby forming side wall oxide films 36a to 36d on the side wall surfaces of the contact holes 36A to 36D. Further, electrodes 37A to 37D made of amorphous silicon doped with P and WSi are formed so as to cover the contact hole bottoms 36A to 36D, respectively. Among these, the electrodes 37A and 37B in the memory cell region 30B form a bit line pattern. By forming the sidewall oxide films 36a to 36d in the contact holes 36A to 36D, even when the position of the contact hole is shifted, a short circuit between the electrode formed in the contact hole and the gate electrode can be avoided. it can.

  In the step of FIG. 4C, another BPSG film 38 having a thickness of about 350 nm is further formed on the BPSG film 36 so that the BPSG film 38 covers the electrodes 37A to 37D.

  Next, in the step of FIG. 4D, contact holes 38A to 38C exposing the diffusion regions 31a, 31c and 31d in the memory cell region 30A are formed in the BPSG film 38 of FIG. In the step of FIG. 5E, a memory cell capacitor is formed so as to cover the contact holes 38A to 38C.

  6 (A) to 7 (D) show in detail a process between the process of FIG. 4 (D) and the process of FIG. 5 (E). However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

Referring to FIG. 6A, an insulating film such as SiO ₂ , SiN, or SiON having an etching rate lower than that of the BPSG film 38 or the BPSG film 36 so as to cover the contact hole 38B on the BPSG film 38. 39 is formed and etched back to form a sidewall insulating film 38b covering the sidewall of the contact hole 38B as shown in FIG. 6B. Even when the etching rate of the insulating film 39 is equal to the etching rate of the BPSG film, the following advantages can be obtained.

6B, a resist pattern 40 covering the peripheral circuit region 30B is formed on the insulating film 39, and the insulating film 39 is etched using the resist pattern 40 as a mask, whereby the BPSG during the memory cell region 30A in the film 38, to form a lower surface than the surface of the BPSG film 38 during the peripheral circuit region 30B in level 38 _1. The surface 38 ₁ forms a step S ₁ at the boundary between the memory cell region 30A and the peripheral circuit region 30B.

Next, in the step of FIG. 7C, the resist pattern 40 of FIG. 6B is removed, and an amorphous silicon layer doped with P is deposited and then patterned, and accumulation of the memory cell capacitor covering the contact hole 38B is performed. The electrode 41 is formed. The storage electrode 41 is patterned using a resist pattern (not shown) as a mask. As a result, the position of the surface of the BPSG film 38 in the memory cell region 30A is lowered to a level 38 ₂ lower than the level 38 _1. To do. Accordingly, step formed between the memory cell region 30A and the peripheral circuit region 30B is increased from the S ₁ to the S _2. During the patterning of the storage electrode 41, the insulating film 39 has a lower etching rate than the BPSG film 38, so that the amount to be etched is small.

7D, a capacitor insulating film 42 having an ONO structure is deposited on the structure of FIG. 7C, and a P-doped amorphous silicon layer is further deposited thereon, followed by patterning using a resist pattern. The counter electrode 43 is formed. At that time, with the patterning of the common electrode 43, the in the memory cell region 30A is BPSG film 38 is etched, the groove 38G having Mizomen 38 ₃ at the boundary between the peripheral region 30B is formed. Wherein for the insulating film 39 has a smaller etching rate than the BPSG film 38, the groove 38G in the boundary portion, to form a larger step S ₃ than the step S _2.

  According to this configuration, the insulating film is formed thicker than the memory cell region in the peripheral circuit region 30B by the thickness of the insulating film 39, and the BPSG film 38 is protected by the insulating film 39 having a low etching rate. When the memory cell capacitor is formed, the height of the BPSG film 16 in the peripheral circuit region as described with reference to FIGS. 2A to 2C is smaller than the height in the memory cell region. The problem that the global level difference between the memory cell region and the peripheral region is enlarged is reduced.

  Further, in the process of FIG. 7D, as a result of forming the memory cell capacitor, the insulating film 39 may be completely removed as shown in FIG. That is, FIG. 8 shows a modification of the structure of FIG.

  The structure shown in FIG. 7D corresponds to the structure shown in FIG.

  Referring back to FIG. 5E, the storage electrode 41 and the capacitor dielectric film 42 are formed in the contact holes 38A, 38B and 38C formed in the BPSG film 38 and exposing the diffusion regions 31a, 31c and 31d, respectively. A memory cell capacitor MC composed of the counter electrode 43 is formed.

  Next, in the step of FIG. 5F, a BPSG film 44 is formed to a thickness of about 350 nm on the structure of FIG. 5E. On the BPSG film 44, the electrode 37C and the film 37 are formed. Wiring electrodes 45A and 45B are formed through contact holes 44A and 44B formed so as to expose diffusion regions 31o, respectively. On the BPSG film 44, wiring patterns 45C and 45D are formed.

  In the present embodiment, since the position of the surface of the BPSG film 38 is maintained at the initial position in the peripheral circuit region 30B, it corresponds to the boundary between the memory cell region 30A and the peripheral circuit region 30B in the BPSG film 44. As a result, the resulting global level difference is reduced, and as a result, the focusing margin of the wiring electrodes 45A and 45B or the wiring patterns 45C and 45D increases.

Meanwhile, the conductor when forming the DRAM according to the previous embodiment, the stepped portion S ₃ between the memory cell region 30A and a peripheral region 30B as shown in FIG. 9, by patterning the storage electrode 41 or counter electrode 43 A part of the layer may remain as the pattern 42X along the stepped portion.

  FIGS. 10A and 10B are plan views showing the formation of the memory cell capacitor in the memory cell region 30A. However, FIG. 10A corresponds to the process of FIG.

Referring to FIG. 10A, a step S ₁ is formed as a result of patterning using the resist pattern 40 outside the memory cell region 30A indicated by a broken line, while a contact hole is formed in the memory cell region 30A. 30A is formed in a matrix.

  On the other hand, FIG. 10B corresponds to the process of FIG. 7D, and shows a state in which the capacitors MC each including the storage electrode 41 are formed in the memory cell region 30A corresponding to the contact hole 30A. .

Referring FIG. 10 (B), wherein the peripheral circuit region 30B is exposed insulating film 39, along the step S ₃ between the peripheral circuit region 30B and the memory cell region 30A, the irregular The conductor pattern 42X extends. Further, a dummy memory cell capacitor MC ′ having the same configuration as that of the memory cell capacitor MC is formed outside the region surrounded by the dotted line in the memory cell region 30A. Since the remaining conductor patterns 42X is extending along the stepped S _3, when the memory cell capacitor MC is formed outside the region surrounded by the dotted lines, the memory cells of the outermost peripheral portion, in particular the memory There is a risk that the memory cell capacitor MC may be short-circuited with the conductor pattern 42X when a positional shift occurs in the mask process when forming the cell region 30A and the peripheral region 30B. Since the pattern is different from the inside, the dummy memory cell capacitor MC ′ is formed on the outermost periphery of the memory cell region 30A so as to surround the memory cell that actually operates. Now, the conductor remains 42X is remaining on the step portion S _3, since this does not have exceptionally controlled, there is a possibility that this residue during such normal cleaning process will be scattered. Once scattered, such a conductor residue is only a foreign substance that causes a pattern defect, and therefore a measure for reliably preventing the residue from scattering is required.

  On the other hand, FIG. 11 shows a plan view of a DRAM 50 according to the second embodiment of the present invention.

Referring to FIG. 11, the DRAM50 according to this embodiment, along the step portion S _3, the storage electrode 41 or the counter electrode of the conductor pattern 42Y of predetermined width which covers the stepped portion S ₃ the memory cell capacitor C 43 is formed simultaneously. Since the conductor pattern 42Y is defined by a linearly extending edge portion and has a predetermined width, it is possible to reliably prevent the problem of peeling and scattering of the residue.

  FIG. 12 shows a configuration of a DRAM 60 similar to the DRAM 10 of FIG. 1, except that the peripheral region 10B includes another capacitor D formed on the field insulating film 12A in addition to the capacitor C. However, in FIG. 12, the same reference numerals are given to the portions described above in FIG. 1, and description thereof is omitted.

  In the DRAM 10 of FIG. 1 described above, the capacitor C in the peripheral region 10B is formed in the active region, which is defined by the field insulating films 12B and 12C. It is necessary to ion-implant the region 11h at a high concentration and thereafter perform an oxidation process of the oxide film 13e. Therefore, an additional mask process is required for the ion implantation process. Further, the conventional configuration of FIG. 1 has a problem in that the withstand voltage of the gate oxide film deteriorates because high concentration ion implantation is performed. Further, since the capacitor C is formed so as to cover the diffusion region 11h defined by the field insulating films 12B and 12C, a region for forming an active element such as a transistor is reduced accordingly. This is disadvantageous for miniaturization of semiconductor devices.

  On the other hand, in the DRAM 60 of FIG. 12, the capacitor D is interposed between the lower capacitor electrode 13F formed on the field oxide film 12A and the upper capacitor electrode 15D formed on the interlayer insulating film 14 such as BPSG. Due to the interlayer insulating film 14, a mask process for high-concentration ion implantation is not required, and there is no problem of deterioration of the withstand voltage of the capacitor oxide film 13e.

  On the other hand, in the DRAM 60 of FIG. 12, since the thickness of the interlayer insulating film 14 on the lower electrode 13F is large, a very large area is required to form the capacitor D with a large capacity, and the chip area is greatly increased. There is a problem.

  Further, it is conceivable to form a capacitor having the same structure as the DRAM memory cell capacitor in the peripheral circuit region 10B. In the case of the DRAM memory cell capacitor, the voltage applied to the counter electrode is set to 1/2 of the power supply voltage. In general, the voltage applied to the capacitor insulating film when the HIGH and LOW levels are accumulated is set to ± 1/2 power supply voltage. Thus, the insulating film of the DRAM memory cell is thinned and the capacitor capacity is increased. On the other hand, in a peripheral circuit, particularly an analog peripheral circuit, it is inevitable that a power supply voltage is applied to both terminals of the capacitor. On the other hand, if the insulating film is thickened to withstand analog operation, the capacity of the DRAM memory cell capacitor will be reduced.

  13A to 13C show a manufacturing process of the DRAM 70 according to the third embodiment of the present invention, which solves the problem of the DRAM 60 of FIG. However, in the figure, the same reference numerals are given to the parts described above with reference to FIG.

  Referring to FIG. 13A, an opening 14D exposing the electrode 13F on the field oxide film 12A is formed in the interlayer insulating film 14 in addition to the contact hole 14B. Further, an insulating film 140 is formed to cover the contact hole 14B and the opening 14D in accordance with the respective cross-sectional shapes. The thickness of the interlayer insulating film 14 is 200 nm, and the size of the contact hole 14B is about 0.3 μm. On the other hand, the size of the opening 14D depends on the required capacitance value, but in any case is much larger than the size of the contact hole 14B. As the degree of integration increases, the size of the contact hole 14B further decreases.

  Next, in the step of FIG. 13B, a portion of the insulating film 140 corresponding to the peripheral region 10B is covered with a resist pattern, the insulating film 140 is etched back in the memory cell region 10A, and the contact hole 14B. A side wall insulating film 14b is formed on the side wall. In the step of FIG. 13B, the insulating film 140 remains as it is in the peripheral region 10B, and therefore the bottom of the opening 14D is covered with the insulating film 140. However, the insulating film 140 is formed to a thickness of about 70 nm by a thermal CVD method. In this case, a side wall insulating film of about 80%, that is, 56 nm (= 70 × 0.8) is formed on the side wall of the contact hole 14B, and the final size of the contact hole 14B is about 0.2 μm (= 0.. 3 μm-56 nm × 2).

  Therefore, when the initial size of the contact hole 14B is, for example, 0.2 μm, the contact size of the final contact hole 14B is reduced to about 0.1 μm by forming the insulating film 140 to a thickness of 70 nm. can do. This size has no particular problem as the contact size of the DRAM memory cell. On the other hand, when the initial size of the contact hole 14B is smaller than 0.2 μm, it is necessary to reduce the thickness of the insulating film 140. However, this is also preferable because the size of the capacitive insulating film in the peripheral circuit region 10B is reduced. Therefore, when importance is attached to the capacitance of the analog peripheral circuit, therefore, the thickness of the insulating film 140 is reduced from the above value.

  Further, in the step of FIG. 13C, the resist pattern is removed, and a conductor layer is uniformly deposited and then patterned, whereby an electrode 15B filling the contact hole 14B and an electrode 150 covering the opening 14D are obtained. It is formed. Of these, the electrode 150 is separated from the electrode 13F by the insulating film 140 in the opening 14D. As a result, the electrode 150 forms a capacitor E corresponding to the capacitor D together with the electrode 13F and the insulating film 140. To do.

  In the DRAM 70 according to the present embodiment, although the capacitor E is formed on the field oxide film 12A, the same insulating film 140 as the side wall insulating film 14b is used as a capacitor insulating film. A thin insulating film with a thickness of 1/3 or less of the insulating film can be formed, and a large capacity can be realized without impairing the integration density.

  Further, when the capacitor E is formed, an additional mask process is required to pattern the insulating film 140. On the other hand, compared with the manufacturing process of the capacitor C of FIG. 12, the diffusion region 11h is formed. Therefore, the number of mask processes does not increase as a whole.

  FIG. 14 is an overall structural view of a DRAM 80 according to the fourth embodiment of the present invention. However, in FIG. 14, the same reference numerals are assigned to the portions corresponding to the portions described above, and the description thereof is omitted.

  Referring to FIG. 14, the DRAM 80 includes a capacitor F formed in the peripheral region 10B corresponding to an opening 16C formed in the interlayer insulating film 16 in addition to the capacitor E, and the interlayer insulating film. 16 and a capacitor G formed corresponding to the opening 16D formed in the capacitor 16. The capacitor F is formed on the field oxide film 12B simultaneously with the gate electrodes 13A to 13C, and the opening 16C. From the lower electrode 13G exposed by the above and the insulating film 160 formed on the interlayer insulating film 16 so as to cover the opening 16C and formed simultaneously with the sidewall oxide film 16a or 16b of the contact hole 16A or 16B. A capacitor insulating film, and an upper electrode formed on the capacitor insulating film 160 so as to fill the opening 16C. 1B to become more. However, the capacitor insulating film 160 corresponds to the insulating film 39 in FIG.

  Similarly, the capacitor G is formed so as to cover the opening 16D on the interlayer insulating film 16 and the diffusion region 11h exposed by the opening 16D. The upper electrode 21C is formed on the capacitor insulating film 160 so as to cover the opening 16D. The capacitor insulating film 160 corresponds to the insulating film 39 in FIG.

  In the DRAM 80 according to this embodiment, the capacitor E or F is formed on the field oxide film 12A or 12B, so that the integration density of the DRAM 80 is not lowered. In the capacitor E, the capacitor insulating film 140 is formed of the same insulating film as the insulating film forming the sidewall insulating film 14a or 14b, and a mask process needs to be added to pattern the capacitor insulating film 140 at that time. However, as compared with the manufacturing process of the capacitor C in FIG. 12, the mask process for forming the diffusion region 11h is not necessary, so that the number of mask processes is not increased as a whole.

  On the other hand, in the capacitor F, the capacitor insulating film 160 is formed of the same insulating film as the insulating film forming the side wall insulating film 16a or 16b, so that it is not necessary to add a mask process, and the manufacturing process of the capacitor C in FIG. Compared to the above, the mask process for forming the diffusion region 11h is not necessary, and the number of mask processes can be reduced as a whole. Further, in the capacitor G, an increase in the number of mask processes is avoided as compared with the capacitor C in FIG.

  Note that FIG. 14 showing the capacitors E, F and G at the same time is for explaining the application of the principle of FIG. 13, and it is needless to say that it is not necessary to use all these capacitors at the same time.

  FIG. 15 shows in detail the vicinity of the memory cell region 10A of the conventional DRAM 10 of FIG. However, in FIG. 15, the same reference numerals are given to the parts described above, and the description thereof is omitted.

  In the configuration of FIG. 15, dummy cells as previously described with reference to FIG. 10B are formed in the periphery of the memory cell region 10A. However, since such dummy cells do not contribute to information storage, a dummy cell region is formed. As a result, the integration density of the DRAM 10 decreases accordingly.

  On the other hand, FIGS. 16A, 16B and 17C show the manufacturing process of the DRAM 90 according to the fifth embodiment of the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 16A, in this embodiment, the contact hole 38C of the dummy cell is formed so as to expose the field oxide film 33B, and after the deposition of the insulating film 39, in the step of FIG. Sidewall oxide films 38a and 38b are formed in the contact holes 38A and 38B by protecting the peripheral area 30B with a resist pattern and etching back the insulating film 39 in the memory cell area 30A. However, in this embodiment, the dummy cell is formed at the boundary with the memory cell region 30A in the peripheral region 30B.

  Further, in the step of FIG. 17C, storage electrodes 41A and 41B are formed so as to fill the contact holes 38A and 38B, and further a storage electrode 41C is formed so as to fill the contact hole 38C. Among these, the storage electrodes 41A and 41B are in contact with the diffusion regions 31a and 31c in the substrate 31, respectively, while the storage electrode 41C of the dummy cell is terminated by the insulating film 39 in the field oxide film 33B. Do not contact

  After the formation of the storage electrodes 41A to 41C, a capacitor dielectric film 42 and a counter electrode 43 are sequentially formed so as to cover the storage electrodes 41A to 41C.

  In this embodiment, since the dummy capacitor is formed on the field oxide film 33, an extra area is avoided and the integration density of the DRAM is improved.

  In this embodiment, since the tip of the dummy storage electrode 41C is covered with the insulating film 39, the contact hole 38C may penetrate the field oxide film 33B. Further, as long as the tip of the dummy storage electrode 41C is covered with the insulating film 39, the contact hole 38C can be formed at an arbitrary position, for example, on the electrode 35C.

  18A to 18C show the manufacturing process of the DRAM 70A according to the sixth embodiment of the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

Referring to FIGS. 18A to 18C, DRAM 70A is a modification of DRAM 70 described with reference to FIGS. 13A to 13C. In the process of FIG. A similar structure is formed, but in this embodiment, a P-doped polysilicon or amorphous silicon film 141 is uniformly formed thereon so as to cover the SiO ₂ film 140. However, in FIGS. 18A to 18C, the left and right sides are displayed opposite to the previous FIGS. 13A to 13C.

Next, in the step of FIG. 18B, after patterning the polysilicon film 141 using the same resist pattern as in FIG. 13B, the SiO ₂ film 140 underneath is patterned with the same resist pattern. Patterning is performed on a mask, and the Si substrate 11 is exposed at the bottom of the contact hole 14B. As can be seen from FIG. 18B, in this embodiment, the SiO ₂ film 140 covering the side wall of the contact hole 14B is further covered with the polysilicon film 141, and the SiO ₂ film constituting the capacitor insulating film of the capacitor E 140 is also covered with the polysilicon film 141.

Next, the structure of FIG. 18B is immersed in an HF aqueous solution, and the natural oxide film formed on the exposed surface of the Si substrate 11 is removed by etching. At this time, since the SiO ₂ film 140 is protected by the polysilicon film 141 in both the contact hole 14B and the capacitor E, a pinhole is formed in the sidewall insulating film 140 of the contact hole 14B or the capacitor insulating film 140 of the capacitor E. Problems such as occurrence do not occur.

  Further, in the process of FIG. 18C, the bit line electrode 15B and the capacitor electrode 150 are formed so as to cover the polysilicon film 141 in the contact hole 14B and the capacitor E, respectively.

  As described above, in such a structure, HF treatment can be performed to remove the natural oxide film on the surface of the substrate 11 on the bottom surface of the contact hole 14B, so that the contact resistance of the bit line is reduced and reliable contact is achieved. Can be realized.

  In this embodiment, the bit line electrode 15B and the capacitor electrode 150 are preferably formed of a conductor such as W, Al, polysilicon, WSi, or a laminate thereof. The sidewall polysilicon film 141 can also be replaced with another conductive film such as W.

  For example, the sidewall conductive film 141 is polysilicon doped with P to a first concentration, and the bit line electrode 15B is a second, higher concentration doped polysilicon and W laminated film with P. Also good. Further, both the sidewall conductive film 141 and the bit line electrode 15B may be formed of W.

  FIGS. 19A to 21D show a manufacturing process of a semiconductor integrated circuit 200 in which an analog integrated circuit and a DRAM are monolithically integrated on a common substrate 101 according to a seventh embodiment of the present invention.

  Referring to FIG. 19A, an n-type well 101A corresponding to an analog integrated circuit is formed on a p-type Si substrate 101, and a gate oxide film 102 is provided on the n-type well 101A. An electrode pattern 103A in which a polysilicon film 103a and a WSi film 103b are stacked is formed. Similarly, a plurality of gate electrodes 103B each having a polysilicon film 103a and a WSi film 103b laminated are formed in the DRAM region of the substrate 101 with the gate oxide film 102 therebetween. Both the electrode pattern 103A and the gate electrode 103B are covered with the SiN film 104 at the top and side walls.

  Next, in the step of FIG. 19B, an interlayer insulating film 105 such as BPSG, PSG, or HSG is deposited on the structure of FIG. 19A and planarized by a chemical mechanical polishing (CMP) method. An opening 105A corresponding to the electrode pattern 103A is formed in the interlayer insulating film 105, and a plurality of bit line contact holes 105B corresponding to diffusion regions (not shown) formed between the plurality of gate electrodes 103B. Then, a memory cell contact hole 105C is formed. However, the opening 105A exposes the SiN film 104 on the electrode pattern 103A, whereas the bit line contact hole 105B or the memory cell contact hole 105C exposes the surface of the Si substrate 101. The interlayer insulating film 105 is preferably formed so that a portion on the electrode pattern 103A has a thickness of at least 50 nm after planarization.

The formation of the opening 105A and the contact holes 105B and 105C selectively acts on a silicon oxide film such as SiO ₂ or BPSG using, for example, a C ₄ F ₈ / Ar / CO / O ₂ mixed gas, It is preferable to carry out by the RIE method having a low etching rate for the SiN film. In this case, the contact holes 105B and 105C are formed using the SiN film 104 as a self-alignment mask. That is, according to the method of this embodiment, no special mask or exposure apparatus is required to form the fine contact hole 105B or 105C, and the contact holes 105B and 105C are formed simultaneously with the formation of the opening 105A. Can do. The etching for forming the opening 105A stops spontaneously when the SiN film 104 on the electrode pattern 103A is exposed.

  Further, in the step of FIG. 20C, a conductive amorphous silicon film (not shown) doped with P on the structure of FIG. 19B is filled with the opening 105A and the contact holes 105B and 105C. , Deposited to a thickness of 200-400 nm. Further, by removing a portion of the amorphous silicon film deposited on the interlayer insulating film 105 by CMP, the conductive amorphous silicon plug 106A and the contact holes 105B and 105C filling the opening 105A are formed. Filling conductive amorphous silicon plugs 106B and 106C are formed. The amorphous silicon plug 106A thus formed constitutes the lower electrode of the capacitor in the analog integrated circuit.

In the step of FIG. 20C, a SiO ₂ film 107 is further deposited on the interlayer insulating film 105 to a thickness of about 30 to 70 nm, and the bit line contact hole 105B is filled in the SiO ₂ film 107. The opening 107A exposing the conductive plug 106B is formed by patterning by the RIE method using, for example, a mixed gas of CF ₄ / CHF ₃ / Ar. Further, a polysilicon film 108a and a WSi film 108b are formed on the SiO ₂ film 107 to a thickness of 50 nm and 100 nm, respectively, and further patterned by an RIE method using a mixed gas of Cl ₂ / O _2. Thus, the capacitor upper electrode 108A is formed corresponding to the capacitor lower electrode 106A, and the bit line electrode 108B is formed corresponding to the conductive plug 106B. Each of the capacitor upper electrode 108A and the bit line electrode 108B has a structure in which the polysilicon film 108a and the WSi film 108b are laminated. The capacitor lower electrode 106A and the capacitor upper electrode 108A together with the SiO ₂ film 107 interposed therebetween constitute a capacitor C of an analog integrated circuit.

Next, in the step of FIG. 21D, another interlayer insulating film 109 such as PSG, BPSG or HSG is deposited on the structure of FIG. 20C so as to cover the upper electrode 108A and the bit line electrode 108B. Then, an opening 109A corresponding to the amorphous silicon plug 106C is formed in the formed interlayer insulating film 109 by the RIE method. Further, an SiO ₂ film is deposited on the interlayer insulating film 109 so as to include the opening 109A, and then anisotropic etching is performed so as to act substantially perpendicularly to the main surface of the substrate 101, thereby the opening 109A. At the same time as forming the SiO ₂ sidewall film 109B on the side wall surface, a corresponding opening is formed in the SiO ₂ film 107 to expose the amorphous silicon plug 106C.

Next, a storage electrode 110 of DRAM made of P-doped amorphous silicon or polysilicon is formed on the interlayer insulating film 109 so as to fill the opening 109A, and the surface of the storage electrode 110 is made of SiO ₂ or SiN. A capacitor dielectric film 111 is formed, and a counter electrode 112 made of P-doped polysilicon is formed thereon.

  19A to 21D, the capacitor lower electrode 106A is formed at the same time as the step of forming the amorphous silicon plugs 106B and 106C, and an extra mask step is not required. . The capacitor upper electrode 108A is also formed at the same time as the bit line electrode 108B, and no extra mask process is required. That is, according to the method of the present embodiment, the analog integrated circuit including the capacitor C and the DRAM can be formed on the same substrate at the same time without extra steps.

  22A to 22B show a manufacturing process of the semiconductor device 220 according to the eighth embodiment of the present invention. However, in FIGS. 22A and 22B, the same reference numerals are given to the portions described above, and the description thereof is omitted.

Referring to FIG. 22A, a semiconductor device 220 is a modification of the semiconductor device 200 according to the previous embodiment. In this embodiment, after the step of FIG. 105B and 105C are filled with P-doped amorphous silicon plugs 106A, 106B and 106C, respectively, and further subjected to a CMP process, and then a P-doped amorphous silicon film 107B separate from the SiO ₂ film 107 is formed on the interlayer insulating film 105. Deposit sequentially. Further, in the step of FIG. 22A, a contact hole 107A exposing the amorphous silicon plug 106B corresponding to the bit line contact is formed in the amorphous silicon film 107B and the SiO ₂ film 107B.

Further, in this embodiment, the structure shown in FIG. 22A is wet-etched in an HF solution to remove the natural oxide film from the exposed surface of the amorphous silicon plug 106B. In this step, since the SiO ₂ film 107 is covered with the P-doped amorphous silicon film 107B, the problem of being eroded by the HF etchant does not substantially occur.

  In this embodiment, next, in the step of FIG. 22B, the upper electrode 108A and the bit of the capacitor C are formed on the structure of FIG. 22A processed in this way as in the step of FIG. The line electrode 108B is formed.

In the semiconductor device 220 according to the present embodiment, the natural oxide film can be removed from the exposed surface of the amorphous silicon plug 106B by HF processing in the step of FIG. 22A, and as a result, the contact resistance of the bit line electrode 108B. Can be reduced. Further, since the SiO ₂ film 107 is protected by the amorphous silicon film 107B, the film thickness of the capacitor insulating film in the analog integrated circuit is not reduced even if such HF treatment is performed.

After the process of FIG. 22B, a process similar to that of FIG. 21D is performed, and a semiconductor device in which an analog integrated circuit having a capacitor C and a DRAM are integrated over the common substrate 101 is formed. .

  23A to 24C show a manufacturing process of the semiconductor device 230 according to the ninth embodiment of the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 23A, a semiconductor device 230 is a modification of the semiconductor device 220 according to the previous embodiment. After the step of FIG. 19B, the opening 105A and the contact hole 105C are respectively formed as P. In this embodiment, the contact hole 105B corresponding to the bit line contact is not formed in the process of FIG. 23A, although the doped amorphous silicon plugs 106A and 106C are filled and CMP processing is performed.

Next, in the step of FIG. 23B, an SiO ₂ film 107 and a P-doped amorphous silicon film 107B are deposited on the structure of FIG. 23A, and an opening 107A penetrating the films 107B and 107 is formed. After forming, the contact hole 105B is formed in the interlayer insulating film 105.

  Further, in the step of FIG. 24C, a P-doped polysilicon film 108a is deposited on the structure of FIG. 23B so as to fill the contact hole 105B, and a WSi film 108b is further deposited thereon, followed by patterning. As a result, the upper electrode 108A corresponding to the lower electrode 106A of the capacitor C and the bit line electrode 108B filling the contact hole 105B are formed.

  Also in the method according to this embodiment, the lower electrode 106A is formed at the same time as the conductive plug 106C, and the upper electrode 108A is also formed at the same time as the conductive plug 106B, so that an unnecessary deposition process or mask process is unnecessary. .

  25 (A) to 28 (G) show a manufacturing process of the semiconductor device 240 according to the tenth embodiment of the present invention.

Referring to FIG. 25A, an element isolation groove 201A is formed on a p-type Si substrate 201 between an analog integrated circuit formation area A and a DRAM formation area B. It is filled with _two films 201B. In the step of FIG. 25A, n-type impurities such as As and P are ion-implanted into the analog integrated circuit formation region A to form an n-type well (not shown).

Next, in the step of FIG. 25B, the thermal oxide film 202A that becomes the gate oxide film of the MOSFET formed in the analog integrated circuit formation region A is uniformly formed on the structure of FIG. A polysilicon film is deposited to a thickness of 100 to 200 nm on the gate oxide film 202A. Further, the polysilicon film thus formed is patterned by a dry etching method using a Cl ₂ / O ₂ mixed gas using the resist pattern R as a mask, so that the gate oxide film 202A is formed in the analog integrated circuit formation region A. A polysilicon pattern 203 is formed thereon. Further, in the step of FIG. 25B, ion implantation of an impurity element such as B is performed using the resist pattern R and the polysilicon pattern 203 as a mask to form a p-type well (not shown) in the DRAM formation region B. To do.

Next, in the step of FIG. 26C, the thermal oxide film 202A exposed from the surface of the Si substrate 201 is removed by wet etching using HF, and a new SiO ₂ film is formed on the surface of the Si substrate 201 in the DRAM region B. The film 202B is formed by thermal oxidation. Accordingly, also in the analog integrated circuit formation region A, a thermal oxide film is formed on the surface of the polysilicon pattern 203 as an extension of the SiO ₂ film 202B.

In the step of FIG. 26C, a P-doped amorphous silicon film 204, a W film 205, and an SiO ₂ film 206 are sequentially deposited on the SiO ₂ film 202B in thicknesses of 70 nm, 100 nm, and 100 nm, respectively. In addition, a plurality of gate electrodes 207 are formed in the DRAM region B by sequentially patterning them in the step of FIG. However, the patterning of the SiO ₂ film 206 is performed by RIE using a mixed gas of CF ₄ / CHF ₃ / Ar, whereas the patterning of the W film 205 and the amorphous silicon film 204 is performed by Cl ₂ and O ₂ . This is performed by RIE using a mixed gas.

  Further, in the step of FIG. 26D, an n-type diffusion region (not shown) is formed adjacent to each gate electrode 207 by performing ion implantation of P or As using the gate electrode 207 as a mask. Is done.

Further, in the step of FIG. 27E, a SiO ₂ film is uniformly deposited on the structure of FIG. 26D, and this is etched back by the RIE method acting in a substantially vertical direction on the substrate 201, An oxide film pattern 208 is formed to cover the top and side surfaces of the gate electrode 207. The oxide film pattern 208 is also formed on the side wall surface of the polysilicon pattern 203. The oxide film pattern 208 forms a self-aligned contact hole that exposes the surface of the substrate 201 between the oxide film pattern 208 on the adjacent gate electrode 207.

Next, in the step of FIG. 27F, a polysilicon film 209 is deposited uniformly on the structure of FIG. 27E so as to cover the self-aligned contact hole, and further, as shown in FIG. In the step, this is patterned by, for example, an RIE method using a mixed gas of Cl ₂ and O ₂ as an etching gas, so that in the DRAM region B, the diffusion region in the substrate 201 is electrically contacted in the self-aligned contact hole. Conductive plug 210B is formed. At the same time, in the analog integrated circuit formation region A, the gate electrode 210 is formed as a result of patterning the polysilicon film 209.

  In the semiconductor device 240 of this embodiment shown in FIG. 28G, the conductive plug 210B is not required to be formed in the fine self-aligned contact hole in the DRAM formation region B, and the analog integrated circuit is formed. It can be formed simultaneously with the formation of the gate electrode in the region A. In addition, since the conductive plug 210B is formed, it is not necessary to form a deep contact hole in the interlayer insulating film covering the structure of FIG. 26G in the step after FIG. Is easy to manufacture.

  29A to 30C show a manufacturing process of the semiconductor device 250 according to the eleventh embodiment of the present invention. However, in the figure, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.

In this embodiment, a SiO ₂ film is deposited on the structure of FIG. 27E by the CVD method in the step of FIG. 29A, and this is etched back to form a SiO ₂ film 211A covering the polysilicon pattern 203. To do. However, the SiO ₂ film 211A extends to cover the SiO ₂ sidewall film 208 that covers the sidewall of the polysilicon pattern 203. At the same time, as a result of the patterning of the CVD-SiO ₂ film, a sidewall film 211B is also formed on the sidewall of the SiO ₂ film 208 covering the gate electrode 207.

  In the example of FIG. 29A, the shallow trench structure 201B in the substrate 201 is replaced by an n-type well 201C.

Next, in the process of FIG. 29B, a P-doped amorphous silicon film 212 is typically deposited to a thickness of 100 to 200 nm on the structure of FIG. 29A, and the process of FIG. Then, the amorphous silicon film 212 is patterned, the amorphous silicon pattern 212A corresponding to the polysilicon pattern 203, and the conductive plug 212B in contact with the surface of the Si substrate 201 between the pair of adjacent gate electrodes 207 are formed. And at the same time. Here, the amorphous silicon pattern 212A together with the underlying SiO ₂ film 211A and the polysilicon pattern 203 forms a capacitor C in the analog integrated circuit formation region A. Further, the conductive plug 212B forms a lead electrode similar to the conductive plug 210B of FIG.

  31A to 32D show a manufacturing process of a semiconductor device 260 according to the twelfth embodiment of the present invention. However, in the figure, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.

Referring to FIG. 31A, in this embodiment, a SiO ₂ film 213 is deposited on the structure of FIG. 26D to a thickness of 30 to 50 nm by the CVD method, and in the step of FIG. 31B. This is etched back to simultaneously form an SiO ₂ film 213A covering the polysilicon pattern 203 and an SiO ₂ film 213B covering the gate electrode 207. However, in this etch back step, the SiO ₂ film 213 is protected in the analog integrated circuit formation region A by a resist pattern (not shown). Further, in FIG. 31A, as in FIG. 29A, the shallow trench structure 201B in FIG. 26D is replaced with an n-type well 201C. In FIG. 31B, the SiO ₂ film 206 constituting the uppermost portion of the gate electrode 207 is shown as a part of the SiO ₂ film 213B.

  Further, in the step of FIG. 32C, a P-doped amorphous silicon film 214 is deposited on the structure of FIG. 31B to a thickness of 100 to 200 nm, and this is further patterned, so that FIG. As shown, the upper electrode 214A of the capacitor C and the conductive plug 214B of the DRAM are formed.

  FIG. 33 shows a configuration according to the thirteenth embodiment of the present invention for electrically contacting the capacitor C in the analog integrated circuit formation region in the semiconductor device 200 of FIG. However, in FIG. 33, the same reference numerals are given to the parts described above, and the description thereof is omitted.

Referring to FIG. 33, a contact hole 109C exposing the upper electrode 108A of the capacitor C is formed in the upper interlayer insulating film 109, and an electrode 113A is formed on the interlayer insulating film 109 so as to fill the contact hole 109C. Is formed. Further, another contact hole 109D is formed in the interlayer insulating film 109 so as to penetrate the SiO ₂ film 107 and expose the lower electrode 106A, and the contact hole 109D is formed on the interlayer insulating film 109. An electrode 113B is formed so as to fill the gap.

  FIG. 34 shows a configuration according to the fourteenth embodiment of the present invention for electrically contacting the capacitor C in the analog integrated circuit formation region in the semiconductor device 250 of FIG. 30C described above.

Referring to FIG. 34, in this embodiment forming the extending portion 212A _ex extends to form regions outside part the capacitor C of the upper electrode 212A, an interlayer insulating so as to cover the capacitor C A film 213 is formed. The interlayer contact hole 213A to further expose the extending portion 213A _ex is in the insulating film 213 is formed, on the interlayer insulating film 213 is electrode 214A to fill the contact hole 213A is formed. Further, a contact hole 213B exposing the lower electrode 203 of the capacitor C is formed in the interlayer insulating film 213, and a contact with the lower electrode 203 is made on the interlayer insulating film 213 via the contact hole 213B. An electrode 214B is formed.

  In the above description, the configuration using a field oxide film for element isolation has been described. However, the present invention is not limited to such a specific element isolation structure. For example, an element isolation structure having a shallow isolation trench (STI) structure is used. The same applies to the semiconductor device used.

  Further, the contact hole does not necessarily have to expose the substrate, and may have a configuration in which a conductor plug is formed in the contact hole and an electrical contact is made with the substrate through the conductor plug.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the claims.

It is a figure which shows the structure of the conventional DRAM. (A)-(C) are the figures explaining the problem of DRAM of FIG. (A), (B) is a figure (the 1) explaining the manufacturing process of the semiconductor device by 1st Example of this invention. (C), (D) is a figure (the 2) explaining the manufacturing process of the semiconductor device by 1st Example of this invention. (E), (F) is a figure (the 3) explaining the manufacturing process of the semiconductor device by 1st Example of this invention. (A), (B) is the figure (the 1) which shows the process between FIG.4 (D)-FIG.5 (E) in detail. (C), (D) is a figure (the 2) which shows in detail the process between Drawing 4 (D)-Drawing 5 (E). It is a figure which shows one modification of the structure of FIG.7 (D). It is a figure which shows the conductor pattern which remains in the level | step-difference part between the memory cell area | region and peripheral area | region of DRAM. (A), (B) is a top view explaining formation of the residual conductor pattern of FIG. It is a top view which shows the structure of the semiconductor device by 2nd Example of this invention. It is a figure which shows the structure of the semiconductor device which has a capacitor in the peripheral region adjacent to a memory cell area | region. (A)-(C) are figures which show the structure of the semiconductor device by 3rd Example of this invention. It is a figure which shows the structure of the semiconductor device by 4th Example of this invention. It is a figure which shows the conventional dummy cell. (A), (B) is a figure (the 1) which shows the structure of the semiconductor device by 5th Example of this invention. (C) is a figure (the 2) which shows the structure of the semiconductor device by 5th Example of this invention. (A)-(C) are figures which show the structure of the semiconductor device by 6th Example of this invention. (A), (B) is a figure (the 1) which shows the structure of the semiconductor device by 7th Example of this invention. (C) is a figure (the 2) which shows the structure of the semiconductor device by 7th Example of this invention. (D) is a figure (the 3) which shows the structure of the semiconductor device by 7th Example of this invention. (A) and (B) are diagrams showing a configuration of a semiconductor device according to an eighth embodiment of the present invention. (A), (B) is a figure (the 1) which shows the structure of the semiconductor device by 9th Example of this invention. (C) is a figure (the 2) which shows the structure of the semiconductor device by 9th Example of this invention. (A), (B) is a figure (the 1) which shows the structure of the semiconductor device by 10th Example of this invention. (C), (D) is a figure (the 2) which shows the structure of the semiconductor device by 10th Example of this invention. (E) and (F) are views (No. 3) showing the configuration of the semiconductor device according to the tenth embodiment of the present invention. (G) is a figure (4) which shows the structure of the semiconductor device by 10th Example of this invention. (A), (B) is a figure (the 1) which shows the structure of the semiconductor device by 11th Example of this invention. (C) is a figure (the 2) which shows the structure of the semiconductor device by 11th Example of this invention. (A), (B) is a figure (the 1) which shows the structure of the semiconductor device by 12th Example of this invention. (C), (D) is a figure (the 2) which shows the structure of the semiconductor device by 12th Example of this invention. It is a figure which shows the structure of the semiconductor device by 13th Example of this invention. It is a figure which shows the structure of the semiconductor device by 14th Example of this invention.

Explanation of symbols

10, 30, 50, 60, 70, 70A, 80, 90 DRAM
10A, 30A Memory cell region 10B, 30B Peripheral region 11, 31 Substrate 11a-11h, 31a-31o Diffusion region 12, 12A-12C, 33A-33F Field oxide film 13A-13D, 35A-35F Gate electrodes 13E-13G, 15D , 150 Capacitor electrodes 13a-13d, 34 Gate insulating film 13e Capacitor insulating films 14, 16, 20, 36, 38, 44 Interlayer insulating films 14A-14C, 16A, 16B, 20A, 20B, 36A-36D, 38A-38C, 44A, 44B Contact hole 14D Opening 14a-14c, 16a, 16b, 36a-36d, 38a-38c Side wall insulating film 15A, 15B, 37A, 37B Bit line electrode 15C, 37C, 37D electrode 17A, 17B, 41 Storage electrode 18 42 capacity Dielectric films 19,43 counter electrode 21A, 21B, 45A, 45B wiring electrodes 21C, 21D, 45C, 45D wiring pattern 31A~31C well 38G groove 38 _{1-38 3} interlayer insulating film main face 39,140,160 insulating film 40 Resist 42X Residual conductor pattern 42Y Conductor pattern 141 Amorphous silicon film 101 Substrate 101A, 201C Well 102 Gate oxide film 103a, 108a Polysilicon film 103b, 108b W film 103A, 106A Lower electrode 104 Insulating film 105, 109 Interlayer insulating film 105A Opening Part 105B, 105C Self-aligned contact hole 107 Capacitor insulating film 107A, 109A Contact hole 107B Amorphous silicon film 108A Upper electrode 108B Bit line electrode 109B Side wall isolation Film 200, 220, 230, 240, 250, 260 Semiconductor device 201A Element isolation trench 201B Element isolation insulator 202A Gate oxide film 202B Thermal oxide film 203 Polysilicon pattern 204 Amorphous silicon film 205 W film 206 Insulating film 207, 210A Gate electrode 208, 211B Side wall oxide film 209 Polysilicon film 210B, 212B Lead electrode 211A Insulating film 212A, 214A Upper electrode 213, 213A Insulating film

Claims (1)

In a method of manufacturing a semiconductor device comprising a memory cell region and a peripheral circuit region on a substrate, and a dummy cell region disposed between the memory cell region and the peripheral circuit region,
Forming an interlayer insulating film on the substrate so as to cover the memory cell region, the peripheral circuit region, and the dummy cell region;
Forming contact holes in the memory cell region and the dummy cell region in the interlayer insulating film;
Forming an insulating film on the interlayer insulating film and in the contact hole;
Forming a mask pattern covering the peripheral circuit region and the dummy cell region on the insulating film;
The insulating film and the interlayer insulating film are patterned using the mask pattern as a mask, and the height of the surface of the interlayer insulating film is lower than the heights of the peripheral circuit region and the dummy cell region in the memory cell region, thereby forming a boundary consisting of steps. Forming a portion, leaving the insulating film on the side wall surface and bottom surface of the contact hole in the dummy cell region, and further forming a side wall insulating film only on the inner wall of the contact hole in the memory cell region;
In the memory cell region and the dummy cell region, a memory cell capacitor is formed on the interlayer insulating film so that the memory cell capacitor contacts a diffusion region in the memory cell region only through the contact hole in the memory cell region. And a process of
Covering the boundary between the memory cell region and the dummy cell region with a conductor pattern,
The step of forming the memory cell capacitor, after the step of patterning the interlayer insulating film, depositing a first conductive film on the interlayer insulating film, by patterning the first conductive film, wherein Forming a storage electrode covering the contact hole in the memory cell region and the dummy cell region ; depositing a capacitor dielectric film on the storage electrode; and a portion covering the storage electrode on the capacitor dielectric film Depositing the second conductor film, and patterning the second conductor film to form counter electrodes in the memory cell region and the dummy cell region, and further including the second conductor film patterning the the conductor pattern covering a boundary portion between the memory cell region and the dummy cell region, the counter electrode and simultaneously Method of manufacturing a semiconductor device, characterized in that it is performed as formed.

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